Particle counting apparatus and method
The real number augmentation information processing device addresses counting inaccuracies in high-frequency particle incidence by using analog signals and logical operations, achieving accurate and fast particle counting beyond conventional limits.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- RIKKYO EDUCATIONAL
- Filing Date
- 2022-08-31
- Publication Date
- 2026-07-24
AI Technical Summary
Conventional particle counting devices face limitations in processing high-frequency particle incidence due to information loss, pile-up errors, and dead time, leading to counting inaccuracies and frequency limits that exceed the technically achievable upper limits.
The apparatus and method utilize real number augmentation information processing by acquiring time-series data with analog signals and performing information processing without binarization, employing AND and OR circuits for analog voltage signals to enhance counting accuracy and speed.
This approach allows for accurate particle counting at ultra-high frequencies without pile-up errors or dead time, enabling processing speeds beyond conventional limits, such as up to 1 GHz in particle counting devices.
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Abstract
Description
Technical Field
[0001] The present invention relates to Particle counting devices and methods.
Background Art
[0002] In digital information and signal processing, information takes only two values, either 1 or 0. The unit for recording one piece of this information is 1 bit. To transmit this binary 1-bit information, a serialization method of arranging binary digits in the time direction (see Fig. 13(A)) and a parallelization method of arranging binary digits in the space direction (Fig. 13(B)) have been adopted. In Figs. 13(A) and (B), an example of transmitting the number 3 (011 in binary) is described.
[0003] Also, bit information can be realized by logical sum and logical product in an electronic circuit, and they are respectively called AND circuits and OR circuits. These circuits are elements of large-scale digital circuits. Conventional AND circuits and OR circuits perform the following operations on two binary signals (0 or 1) composed of logical bits of 1 or 0, as shown in Figs. 13(C) and 13(D).
[0004]
Equation
[0005] However, as shown in Fig. 14, problems such as information loss during digitization by using binary signals, limitations in bus density due to parallelization, and processing delays due to serialization can occur.
[0006] Hereinafter, the information loss during digitization will be described by taking a particle counting device as an example (see Non-Patent Document 1). Conventional particle counting devices that utilize the above-described calculations include a sensor that outputs a signal upon particle incidence, a comparator circuit that compares the sensor's output signal with a reference threshold signal to output a binary signal (0 or 1) pulse indicating the presence or absence of particle incidence, and a determination circuit that determines whether or not one particle has been incident within each pulse width from each pulse of the output binary signal (0 or 1).
[0007] In conventional particle counting devices, the comparator circuit requires a certain processing time to process pulses. During this processing time, if the next signal arrives, it cannot be processed and is discarded. This is known as a dead time (see Figure 15). For example, if the processing time is 100 ns, the repetition frequency that can be processed is 1 / 100 ns to 10 MHz, and input information with a higher repetition period than this cannot be handled.
[0008] Furthermore, in conventional particle counting devices, when multiple particles are incident on the sensor at a high frequency within an extremely short time frame, less than the signal pulse width of the comparator circuit, the counting method based on logical OR cannot distinguish between cases where one particle is incident within one pulse width and cases where two or more particles are incident (pile-up), resulting in "counting errors" where only one particle is counted in each case (see Figure 15). At such high frequencies that this occurs, it is no longer possible to acquire information on the number of incident pulses using a digital circuit with a comparator circuit, and in the example of a signal pulse width of 10 ns, the limit is a particle incident frequency of 1 / 10 ns = 100 MHz, as shown in Figure 16(A). As shown in Figures 16(B) and (C), the amount of pile-up increases as the frequency further increases to 1 GHz, 10 GHz, etc.
[0009] On the other hand, there are many cases where ultra-high frequency measurements well exceeding 1 GHz, as illustrated in Figures 16(B) and (C), are required. Overcoming this with existing technology requires reducing the sensor area to lower the incidence frequency, using devices that produce smaller pulse widths, and constructing high-speed signal processing systems with minimal dead time. All of these would result in large-scale systems, and the needs have already far exceeded the technically achievable upper limits. In other words, existing counting circuits using digital circuits have frequency limits that do not meet the needs at all. [Prior art documents] [Non-patent literature]
[0010] [Non-Patent Document 1] KM Kojima et al 2014 J. Phys.: Conf. Ser. 551 012063 [Overview of the project] [Problems that the invention aims to solve]
[0011] The present invention has been made in view of the above facts, and aims to provide an apparatus and method for reducing or eliminating information loss caused by information processing based on digital information consisting of logical bits of 1 or 0.
[0012] Furthermore, the present invention aims to provide a device and method that exceeds the information transmission speed of general digital circuits. [Means for solving the problem]
[0013] To solve the above problems, the real number augmentation information processing device of the present invention comprises a time series data acquisition unit that acquires at least one time series data having an amplitude value of an analog signal or a value obtained by converting the amplitude value to base n (n>2) in the amplitude direction, and an information processing unit that performs at least one information processing on the acquired time series data without binarizing the amplitude value of the time series data.
[0014] Preferably, the time-series data is an analog voltage signal. For example, the analog voltage signal is output from a particle detection sensor, and the information processing of the information processing unit is a counting process that counts the number of particles detected by the particle detection sensor based on the time-series data.
[0015] Preferably, the time-series data acquisition unit includes a digitizer that performs AD conversion on the analog voltage signal and outputs it to the information processing unit. In another aspect of the present invention, the time-series data is at least two analog voltage signals, and the information processing unit comprises at least one AND circuit that multiplies the at least two analog voltage signals as information processing, at least one OR circuit that adds the at least two analog voltage signals as information processing, and a combination of the at least one AND circuit and the at least one OR circuit.
[0016] For example, the at least two analog voltage signals are signals output from at least two sensors, respectively. The time-series data acquisition unit may include a transmission line for transmitting the analog signals output from the sensors as the time-series data.
[0017] The time-series data acquisition unit according to another embodiment includes a DA converter that converts digital information into an analog signal, and outputs the analog signal converted by the DA converter as time-series data to the information processing unit.
[0018] For example, the AND circuit can be an analog multiplier, and the OR circuit can be an analog adder. In one application example of the present invention, the time series data are two analog voltage signals respectively output from two particle detection sensors, the logical product circuit multiplies the two analog voltage signals, and the information processing unit calculates the simultaneous counting probability of two particles simultaneously detected by the two particle detection sensors based on the multiplication result of the logical product circuit.
[0019] Preferably, when the amplitude value exceeds the maximum voltage that can be processed, the time series data acquisition unit represents the time series data in at least one of serialization and parallelization. In this case, the information processing unit converts the time series data represented in at least one of serialization and parallelization into the original amplitude value, and executes the information processing using the converted data.
[0020] A real number extended information processing method according to another aspect of the present invention includes steps of acquiring at least one time series data having an amplitude value of an analog signal or a value obtained by converting the amplitude value into an n -ary number (n>2) in the amplitude direction, and performing at least one information processing on the time series data without binarizing the amplitude value of the acquired time series data.
Brief Description of Drawings
[0021] [Figure 1] FIG. 1 is a schematic diagram of a real number extended information processing apparatus according to the basic configuration of the present invention. [Figure 2] FIG. 2 is a diagram for explaining the time series data of the real number extended information processing apparatus of the present invention. FIG. 2(A) is time series data whose amplitude direction is an analog real value, FIG. 2(B) is time series data whose amplitude direction is a value obtained by converting into an n -ary number (n>2), and FIG. 2(C) shows the outline of the time series data of the present invention in comparison with the prior art. [Figure 3] FIG. 3 is a schematic diagram of a real number extended information processing apparatus according to the first embodiment of the present invention applied to a particle counting device. [Figure 4] FIG. 4 is a schematic diagram of a real number extended information processing apparatus according to the second embodiment of the present invention that performs a logical product operation as information processing. [Figure 5] Figure 5 is a schematic diagram of a real number extension information processing device according to a third embodiment of the present invention, which performs a logical OR operation as information processing. [Figure 6] Figure 6 is a schematic diagram of an analog multiplier that performs a logical AND operation in the second embodiment shown in Figure 4. [Figure 7] Figure 7 is a schematic diagram of an analog adder that performs a logical OR operation in the third embodiment shown in Figure 5. [Figure 8] Figure 8 is a schematic diagram of a real number extended information processing device according to a fourth embodiment of the present invention, which performs logical AND and logical OR operations as information processing that extends the second and third embodiments. [Figure 9] Figure 9 is a schematic diagram of a real number augmentation information processing device according to a fifth embodiment of the present invention, in which the input information of the real number augmentation information processing device according to each of the above embodiments has been changed. [Figure 10] Figure 10 is an example of time-series data (actual data) showing the voltage change over time measured at a counting rate of 10 MHz in the real number augmented information processing device (particle counting device) according to the first embodiment shown in Figure 3. [Figure 11] Figure 11 is a graph of the decay curve showing the decay of muons, acquired at a counting rate of 10 MHz in the real number augmented information processing device (particle counting device) according to the first embodiment shown in Figure 3. [Figure 12] Figure 12 is a graph showing the result of a logical AND operation of the real number extension information processing device according to the second embodiment shown in Figure 4. [Figure 13] Figure 13 illustrates a conventional binary signal, where Figure 13(A) shows a serialized signal, Figure 13(B) shows a parallelized signal, Figure 13(C) shows the input and output signals of an AND gate with a binary signal, and Figure 13(D) shows the input and output signals of an OR gate with a binary signal. [Figure 14] Figure 14 is a schematic diagram showing a conventional analog information processing circuit. [Figure 15]Figure 15 illustrates the pile-up of analog information output from sensors and the dead time in digital logic signals, which are problems in conventional technology. [Figure 16] Figure 16 is a graph showing the results of signal simulations at high frequencies to illustrate pile-ups. Figure 16(A) shows the results at a frequency of 100 MHz, Figure 16(B) shows the results at a frequency of 1 GHz, and Figure 16(C) shows the results at a frequency of 10 GHz. [Modes for carrying out the invention]
[0022] The present invention will be described below with reference to the drawings. <Basic Configuration of the Invention> Figure 1 shows a real number augmentation information processing device 1 according to the basic configuration of the present invention. The real number augmentation information processing device 1 comprises a time series data acquisition unit 2 that acquires at least one time series data 10, and an information processing unit 20 that performs at least one information processing on the time series data 10. The time series data acquisition unit 2 acquires time series data from an analog signal output from a sensor 50, but the present invention is not limited to a sensor as the source of the analog signal.
[0023] Next, the contents of the time-series data 10 acquired by the time-series data acquisition unit 2 will be explained using Figure 2. Figure 2(A) shows an example of time-series data 10. The time-series data 10 in Figure 2(A) is time-series data having amplitude values of an analog signal, i.e., real values in the amplitude direction. This analog signal may be the analog voltage signal directly output from the sensor 50, or it may be an analog signal whose voltage has been increased, decreased, or filtered. Therefore, while in the conventional technology the pulse of a logic bit is an amplitude value of 1 (e.g., a reference voltage of 5V) or 0 (0V), the amplitude value of the time-series data 10 in Figure 2(A) can take values such as 3.2V or 0.5V.
[0024] The information processing unit 20 performs at least one information processing operation on the time-series data 10 without binarizing the amplitude values of the time-series data 10. For this information processing, the information processing unit 20 may be equipped with an AD converter (ADC) (not shown) that performs multi-bit AD conversion of the analog voltage signal of the time-series data 10 in the final stage. The amount of information stored in the amplitude voltage of the time-series data 10 can be increased according to the number of bits of this AD converter (ADC). As a result, even if a pileup occurs due to a large number of particles incident on the sensor 50 in a very short time, binarization is not performed, so the number of particles is not lost in the voltage amplitude values of the time-series data 10, and the information processing unit 20 can accurately detect the number of incident particles without missing any.
[0025] Figure 2(B) shows another example of time-series data 10. The time-series data 10 in Figure 2(B) is time-series data that has values in the amplitude direction obtained by converting the amplitude value of the analog signal to a base-n number (n>2). This time-series data 10 is, for example, the amplitude of the analog voltage signal output from the sensor 50, represented as an integer value in base-n number (n>2), for example, 3(V). The time-series data 10 in Figure 2(B) can be generated using a digitizer (Figure 3) as described later if the original information is an analog voltage signal, and if the original information is n-bit (binary) digital information, it can be obtained by performing a DA conversion (see Figure 9).
[0026] If the amplitude value of the time-series data 10 exceeds the maximum voltage that can be processed, the system can predict this overflow and, if necessary, prepare multiple information units to represent a single voltage amplitude (one amplitude in Figure 2(B)) from these multiple information units. The time-series data acquisition unit 2 can arrange the multiple information units either in the time direction (serialization) or in the space direction (parallelization), similar to the conventional technology shown in Figure 2(C). Both serialization and parallelization can also be used. The information processing unit 2 can convert the serialized or parallelized time-series data back to its original amplitude value and perform information processing using the converted data.
[0027] Even with the analog voltage signal shown in Figure 2(A), it is possible to apply at least one of serialization or parallelization. For example, by using multiple divider resistors connected in series to which the entire voltage of the analog voltage signal is applied, and representing one voltage amplitude of the analog voltage signal with a set of voltages across each divider resistor, and arranging these voltage sets in the time and space directions, both serialization and parallelization become possible.
[0028] Figure 2(C) shows a comparison between the time-series data 10 of the present invention and a binary-bit pulse train of the prior art. As shown in Figure 2(C), the prior art uses logical bits of either 1 or 0. Therefore, to increase the communication speed, methods such as increasing the clock frequency to compress the pulse width in the time direction or expanding the bus to multiple transmission lines in the spatial direction and parallelizing it were employed. However, this resulted in problems such as limitations in bus density due to parallelization and processing delays due to serialization.
[0029] In contrast, the present invention extends the voltage to a real number or a base-n number (n>2) to carry information in the amplitude direction, thus not only virtually eliminating information loss but also improving the information transmission speed. Furthermore, as mentioned above, the present invention also allows for at least one of serialization and parallelization, but since information is also extended in the amplitude direction, it is not as problematic as in the conventional technology, and large amounts of data can be processed at high speed without causing limitations in bus density or processing delays.
[0030] As described above, in this invention, time-series data, which is the input signal (voltage), is used as information directly without binarizing the information. If there is any input to the sensor, an output current is generated. In other words, the output current contains information about the input to the sensor. In conventional technology, a comparator circuit is used to determine whether a particle has definitely entered the sensor, and then the arrival time and number are measured. In contrast, in this invention, a comparator circuit is not used, and the input voltage is recorded directly, and it is determined that there is a high probability that there was some kind of input to the sensor at the time when a high voltage value is observed. That is to say, in this invention, voltage is treated as information with trueness.
[0031] Information with accuracy extends the space of 1 or 0 in the conventional technology to a real number space (including integers of 2 or more). The information processing unit 20 of the real number extended information processing device 1 of the present invention makes a determination, for example, if the time series data extended to the real number space has a value of 1V or more, it determines with what percentage of confidence that some input has been received by the sensor (in the case of a particle detection sensor, that a particle has entered the sensor), and how many particles were entered. For this reason, the information processing unit 20 may be equipped with a database for making accurate quantitative decisions based on the time series data (for example, a table showing the relationship between voltage and the number of particles, or statistical data for calculating the confidence level).
[0032] The present invention is characterized by the combination of the following (1) and (2). (1) The input signal (voltage) carrying the information is acquired as time-series data. (2) Interpret the acquired time-series data as accurate information and analyze it appropriately. Feature (1) is that high-speed phenomena require hardware with a high sampling rate. <First Embodiment of the Invention> Figure 3 shows a real number augmentation information processing device 1a according to a first embodiment, in which the real number augmentation information processing device 1 shown in Figure 1 is applied to a particle counting device.
[0033] The real number augmentation information processing device 1a includes a time-series data acquisition unit 2a that acquires time-series data 10 from an analog voltage signal output by a particle detection sensor 51, and an information processing unit 20a that performs at least one information processing on the time-series data 10.
[0034] The particle detection sensor 51 includes a scintillator 52 that emits fluorescence when particles generated from a particle source such as a radioactive isotope collide with it, and a photomultiplier tube 53 that converts the light emitted by the scintillator 52 into electrons by the photoelectric effect and amplifies them.
[0035] The time-series data acquisition unit 2a includes a transmission line 3 that converts the current pulse output from the photomultiplier tube 53 by particle injection into the scintillator 52 into an analog voltage signal and transmits it, and a digitizer 4 that digitizes the analog voltage signal sent from the transmission line 3. The digitizer 4 includes, for example, a multi-stage divided resistor and a number of parallel-arranged comparator circuits installed at each stage to compare the voltage across each of the divided resistors with a reference voltage using the analog voltage signal. The digitizer 4 samples the analog voltage signal at the sampling frequency and, using the comparator circuits at each stage, simultaneously compares the voltage across the divided resistor at each stage with the reference voltage in a short time within the sampling period, thereby sequentially converting the analog voltage signal to an integer multiple of the reference voltage (see Figure 2(B)). The data converted at each sampling constitutes the time-series data 10. The principle of the digitizer is the same as that of a flash AD converter, and a sampling frequency of nearly 1 GHz is possible.
[0036] The information processing unit 20a can be implemented by a personal computer (PC) 21. If the personal computer (PC) 21 is a typical PC that performs arithmetic operations on a binary bit basis, then in order to process the time-series data 10, which is an integer value obtained by converting the amplitude value to a number of bits greater than 1 bit (binary), for example, 14-bit or 16-bit binary time-series data, the amplitude value is converted to a number of bits greater than 1 bit (binary), for example. This conversion may be performed by an encoder provided inside the digitizer 4, or it may be performed by the personal computer (PC) 21 itself. In any case, since the time-series data is not a binary pulse train of 0 or 1, the loss of information can be virtually eliminated or mitigated.
[0037] Figure 10 shows an example of time-series data 10 actually acquired by the apparatus 1a in Figure 3. According to the figure, the decay time of the scintillator 53's luminescence is the dominant factor, and it takes approximately 10 ns for the signal to disappear. Currently, processing circuits in practical use have a dead time of approximately 100 ns. This dead time cannot be reduced further, even with analog waveform processing using custom ICs (ASICs (Application Specific Integrated Circuits)) or hardware digital processing using programmable logic circuit devices (FPGAs (Field Programmable Gate Arrays)). Therefore, in conventional techniques that determine particle incidence using a single comparator circuit with a dead time, the events in Figure 10 are not recorded, and information overlapping with the dead time is simply discarded.
[0038] Furthermore, if the frequency of particle incidence increases, pile-ups occur as shown in Figures 16(A) to (C). In conventional technology, only one pulse is generated from the comparator circuit for the portion where a pile-up occurs, so information from the second and subsequent overlapping inputs is discarded. In particular, in situations where many pile-ups overlap and a sensor output voltage that is not always zero is generated, a serious situation occurs where no digital pulses are issued at all. As described above, pile-ups and dead time impose a technical upper limit on the counting rate.
[0039] According to the real number augmented information processing device 1a of the first embodiment, the information processing unit 20a counts particles based on time-series data (example in Figure 10) acquired from an analog voltage signal, without requiring a comparator circuit to determine the arrival of particles as a binary value of 1 or 0. In other words, the time-series data is reinterpreted as information with accuracy. Since the voltage amplitude value of the time-series data increases in accordance with the number of arriving particles in a short period of time, accurate counting can be performed without being affected by pile-up or dead time.
[0040] As another application example, consider a phenomenon where the frequency of particle arrivals decreases exponentially. For example, consider a radioactive isotope that decays with a short lifetime as the radiation source shown in Figure 3. In conventional measurement techniques, the radiation emitted during decay is determined by a comparator circuit, and its arrival time is recorded as digitized time information using a time digitizer (TDC: Time to Digital Converter). The time digitizer record is data where the arrival time is arranged for each event. For example, if we want to obtain information about the lifetime from this data, we can divide this data into time segments and create a frequency distribution table, and then create a frequency distribution graph, or histogram. Since this is an exponential function proportional to the decay frequency, the lifetime can be determined from its shape.
[0041] However, the conventional method described above has an upper limit on the frequency at which it can be applied due to the aforementioned dead time and pile-up. As in the example above, anything above approximately 10 MHz is impossible, which means that, in terms of radioactivity, it is impossible to measure strong radiation sources of 10 MBq or more. In terms of information and communication, this means that it is not possible to handle more than 1 M pulse per second, so the upper limit of the information rate is 1 Mbit / s = 1 / 8 Mbyte / s. Of course, actual information and communication equipment has much faster transfer speeds, but this is due to the ability to make the width of the original digital pulse extremely narrow, the effect of busing multiple transmission lines in parallel, and pipeline processing that sequentially accepts and processes the next signal without waiting for processing. A digitizer is a product that is the result of doing exactly this to a flash AD converter (FADC). However, it is more common for the width of the digital pulse to be unable to be narrowed, such as in the processing of sensor output. Even if this can be achieved to some extent with scintillators that emit light for short periods or with fast-operating optical sensors such as MCPs, there is a limit to this. Currently, the only way to increase data communication speed is to narrow the pulse width, that is, to increase the clock frequency in synchronous circuits or increase the number of parallel connections, which is not only costly but also approaching technical impossibility.
[0042] The key point of this invention is the technical idea that if the ultimate goal is to obtain statistical information such as lifetime, then the arrival time of each individual particle is considered unnecessary information used only in the intermediate stages, and if the information is ultimately to be organized into a histogram, then it is sufficient to obtain histogram information from the beginning. If the information to be ultimately obtained is a histogram of "decay rate against time," then since the decay rate is proportional to the number of signals, i.e., the sensor output, it is sufficient to record a histogram of "voltage against time," i.e., time-series data 10. The horizontal axis can simply be time, and there is no need to determine pulses.
[0043] Figure 11 shows a graph of time-series data 10 obtained by measuring muons that decay by emitting a positron with a lifetime of approximately 2 μs using the apparatus 1a in Figure 3. The integrated voltage value decays exponentially as a function of time, indicating that the measurement was accurate. Therefore, the information processing unit 20a (PC21) shown in Figure 3 can output the lifetime of the muon as a calculation result from the shape of the time-series data in Figure 11.
[0044] In the measurement shown in Figure 11, the maximum count rate was approximately 11 MHz. This is a high frequency that is approaching the limits of conventional technology, but the results of the present invention show no pile-up whatsoever, and since there is no dead time, it is still possible to process up to about 100 times that frequency, i.e., about 1 GHz. If a pile-up were occurring, the voltage value in the high-frequency region of Figure 11 should deviate from the linear relationship and saturation should be observed.
[0045] The aforementioned upper limit of around 1 GHz is not a theoretical limit, but rather a consequence of the signal voltage exceeding the maximum voltage observed by the digitizer due to pile-up. This can be solved by lowering the voltage, and can be easily overcome by lowering the applied voltage of the sensor, dividing the short-circuit resistance to reduce the voltage, using an attenuator to reduce the voltage, or using a differentiating circuit to suppress lifetime components and extract the frequency component of interest (for example, in measurements where the signal oscillates). <Second Embodiment of the Present Invention> Figure 4 shows a real number extension information processing device 1b according to the second embodiment. In the second embodiment, one of the information processing operations performed by the information processing unit is a logical AND operation. Note that configurations similar to those in the above embodiment are given the same reference numerals and detailed descriptions are omitted.
[0046] The real number extended information processing device 1b includes a time-series data acquisition unit 2b that acquires analog voltage signals V1 and V2 output from two sensors 54 and 55, respectively, as time-series data 10, and an information processing unit 20b that performs at least one information processing on the two time-series data 10 (V1 and V2).
[0047] The time-series data acquisition unit 2b is equipped with two transmission lines 3b, 3b that transmit the analog voltage signals V1 and V2 output from the two sensors 54 and 55, respectively, as time-series data 10.
[0048] The information processing unit 20b includes two transmission lines 3b, a logical AND circuit 5 that performs a logical AND operation (V1 × V2) on two analog voltage signals V1 and V2 transmitted from 3b, an AD converter 22 that performs an A / D conversion on the analog operation result of the logical AND circuit 5, and a personal computer (PC) 21 that performs predetermined information processing based on the time-series data converted into digital data.
[0049] As shown in Figure 6, the AND gate 5 can be implemented as an analog multiplier that multiplies two analog voltage signals V1 and V2, which are extended to real numbers. The multiplication by the AND gate 5 is as follows:
[0050] V1 × V2 = V1V2, V1 × 0 = 0 In contrast, conventional logical AND circuits perform the following operation: 1 × 1 = 1, 1 × 0 = 0 Conventional logical AND operations can only take the value 1 or 0. In the real number extended information processing device 1b according to the second embodiment, the result of the logical AND circuit 5 is also analog information extended to a real number with accuracy, making it possible to perform information processing with reduced information loss.
[0051] The second embodiment shown in Figure 4 included one AND circuit 5, but the present invention is not limited to this example, and may include multiple AND circuits 5. This allows for the execution of various arithmetic operations. Furthermore, the number of sensors is not limited to two, and three or more sensors may be used. Moreover, even one sensor may be used, and two or more different analog voltage signals can be generated from the analog voltage signal output from one sensor, and these analog voltage signals can be input to the AND circuit 5. <Third Embodiment of the Present Invention> Figure 5 shows a real number extension information processing device 1c according to the third embodiment. In the third embodiment, one of the information processing operations performed by the information processing unit is a logical OR operation. Note that configurations similar to those in the above embodiments are given the same reference numerals and detailed descriptions are omitted.
[0052] The real number extended information processing device 1c includes a time-series data acquisition unit 2c that acquires analog voltage signals V1 and V2 output from two sensors 54 and 55, respectively, as time-series data 10, and an information processing unit 20c that performs at least one information processing operation on the two time-series data 10 (V1 and V2).
[0053] The time-series data acquisition unit 2c is equipped with two transmission lines 3c, 3c that transmit the analog voltage signals V1 and V2 output from the two sensors 54 and 55, respectively, as time-series data 10.
[0054] The information processing unit 20c includes two transmission lines 3c, a logical OR circuit 6 that performs a logical OR operation (V1+V2) on two analog voltage signals V1 and V2 transmitted from 3c, an AD converter 22 that performs an A / D conversion on the analog operation result of the logical OR circuit 6, and a personal computer (PC) 21 that performs predetermined information processing based on the time-series data converted into digital data.
[0055] As shown in Figure 7, the OR circuit 6 can be implemented as an analog adder that adds two analog voltage signals V1 and V2, which are extended to real numbers. The addition performed by the OR circuit 6 is as follows:
[0056] V1+V2=V1+V2, V1+0=V1 In contrast, conventional OR circuits perform the following operation: 1+1=1, 1+0=1 Conventional logical AND operations can only take the value 1 or 0. The fact that 1+1=1 and 1+0=1 result the same is the reason why pile-ups become a problem.
[0057] In the real number extended information processing device 1c according to the third embodiment, the result of the OR operation of the logical OR circuit 6 is also analog information extended to a real number with accuracy, making it possible to perform information processing with reduced information loss.
[0058] The third embodiment shown in Figure 5 includes one OR circuit 6, but the present invention is not limited to this example, and may include multiple OR circuits 6. This allows for the execution of various arithmetic operations. Furthermore, the number of sensors is not limited to two, and three or more sensors may be used. Moreover, even with just one sensor, two or more different analog voltage signals can be generated from the analog voltage signal output from one sensor, and these analog voltage signals can be input to the OR circuit 6. <Fourth Embodiment of the Present Invention> Figure 8 shows a real number extension information processing device 1d according to the fourth embodiment. In the fourth embodiment, one of the information processing operations performed by the information processing unit is a combination of logical AND and logical OR operations. Note that configurations similar to those in the above embodiments are given the same reference numerals and detailed descriptions are omitted.
[0059] The real number extended information processing device 1c includes a time series data acquisition unit 2d that acquires analog voltage signals V1, V2, ... output from two or more sensors 54, 55, ... as time series data 10, and an information processing unit 20d that performs at least one information processing on two or more time series data 10 (V1, V2, ...).
[0060] The time-series data acquisition unit 2d is equipped with two or more transmission lines 3d that transmit analog voltage signals V1, V2, ... output from two or more sensors 54, 55, ... as time-series data 10.
[0061] The information processing unit 20d includes two or more transmission lines 3d, an arithmetic unit 7 that performs analog calculations on two or more analog voltage signals transmitted from 3d, an AD converter 22 that performs A / D conversion of the analog calculation results of the arithmetic unit 7, and a personal computer (PC) 21 that performs predetermined information processing based on the time-series data converted into digital data. The arithmetic unit 7 includes at least one logical AND circuit 5 shown in Figure 6 and at least one logical AND circuit 6 shown in Figure 7, and performs analog calculations that combine logical AND and logical OR operations.
[0062] In the real number extended information processing device 1d according to the fourth embodiment, the calculation result of the arithmetic unit 7 is also analog information extended to a real number having accuracy, making it possible to perform information processing with reduced information loss.
[0063] The fourth embodiment shown in Figure 8 included two or more sensors, but the present invention is not limited to this example. It may also use one sensor, and two or more different analog voltage signals can be generated from the analog voltage signal output from one sensor, and these analog voltage signals can be input to the calculation unit 7. <Fifth Embodiment of the Invention> In the embodiments described above, time-series data 10 was obtained from analog voltage signals output from the sensor, but the present invention is not limited to these examples. Figure 9 shows a real number augmentation information processing device 1e according to a fifth embodiment, which does not directly use the sensor output. Note that configurations similar to those in the embodiments described above are given the same reference numerals and detailed descriptions are omitted.
[0064] The real number augmentation information processing device 1e comprises a time-series data acquisition unit 2e and an information processing unit 20e that performs at least one information processing operation on the time-series data 10. The time-series data acquisition unit 2e comprises a DA converter 61 that performs DA conversion of digital information 60 to an analog signal, and a transmission line 3e that transmits the DA-converted analog signal as time-series data 10. When the digital information 60 is represented by n bits (binary), time-series data 10 having an integer voltage amplitude as shown in Figure 2(B) can be generated as an analog signal obtained by DA conversion of this digital information 60.
[0065] Multiple DA converters 61 and transmission lines 3e can be provided to send multiple different time-series data 10 to the information processing unit 20e. The information processing unit 20e can be the information processing unit of each of the above embodiments.
[0066] The above describes the embodiments of the present invention, including its basic configuration. However, the present invention is not limited to the above examples and can be arbitrarily and suitably modified within the scope of the present invention. [Examples]
[0067] This embodiment is a configuration in which the real number augmentation information processing device 1b according to the second embodiment shown in Figure 4 is used to measure muons. As two sensors 54 and 55 of the real number augmentation information processing device 1b, sensors equipped with a scintillator 52 and a photomultiplier tube 53 as shown in Figure 3 were selected, and muons were measured.
[0068] The frequencies N1 and N2 of muons arriving at the two sensors 54 and 55 both decay exponentially with respect to the muon lifetime T = 2 μs. That is, the frequencies N1 and N2 are expressed by the following equations.
[0069]
number
[0070]
number
[0071] Here, t is time, N1 0 , N2 0 This represents the initial frequency at t=0. As shown in Figure 11 above, the voltage of the time-series data acquired from the output signals of sensors 54 and 55 decreases exponentially over time, supporting equations (1) and (2). In other words, the voltage of the time-series data corresponds to frequencies N1 and N2.
[0072] Since the event of the same single particle passing through two sensors 54 and 55 simultaneously can be ignored, the probability of coincident simultaneous counting, in which two sensors 54 and 55 coincidentally count different particles at the same time, is the product of N1 in equation (1) and N2 in equation (2), and is expressed by the following equation.
[0073]
number
[0074] According to equation (3), the probability of simultaneous counting by chance decreases exponentially at T / 2 = 1 μs. Therefore, it is expected that the voltage of the multiplication result of the AND circuit 5 will also decrease exponentially at T / 2 = 1 μs, corresponding to equation (3).
[0075] Figure 12 shows the result of the logical AND operation performed by the logical AND circuit 5 on the time-series data acquired from the output signals of the two sensors 54 and 55. As shown in Figure 12, the voltage resulting from the logical AND operation decreases exponentially at approximately T / 2 = 1 μs, supporting the prediction given by equation (3).
[0076] As described above, it was confirmed that the probability of simultaneous counting by chance can be correctly measured by performing a real-number extended logical AND, i.e., multiplying by voltage. Therefore, the PC21 of the information processing unit 20b in this embodiment can calculate and output the probability of coincidence based on the results in Figure 12. [Explanation of symbols]
[0077] 1,1a,1b,1c,1d,1e Real Number Extension Information Processing Unit 2,2a,2b,2c,2d,2e Time series data acquisition part 3,3b,3c,3d,3e transmission line 4 Digitizer 5. AND gate 6 OR circuit 7 Arithmetic section 10. Time series data 20, 20a, 20b, 20c, 20d, 20e Information Processing Unit 21. Personal Computer (PC) 22 AD Converters 50 sensors 51 Particle detection sensor 52 Scintillator 53 Photomultiplier tube 54,55 Sensors 60 Digital Information 61 DA Converter
Claims
1. A particle counting device, A time-series data acquisition unit that acquires at least one time-series data having the amplitude value of an analog signal or the value obtained by converting the amplitude value to base n (n > 2) in the amplitude direction, An information processing unit that performs at least one information processing on the acquired time series data without binarizing the amplitude values of the time series data, Equipped with, The aforementioned time-series data consists of two analog voltage signals output from two particle detection sensors, respectively. The information processing unit includes at least one logical AND circuit that multiplies the two analog voltage signals as part of the information processing, The information processing unit calculates the probability of simultaneous counting of two particles detected by the two particle detection sensors based on the multiplication result of the logical AND circuit. Particle counting device.
2. A particle counting device, A time-series data acquisition unit that acquires at least one time-series data having the amplitude value of an analog signal or the value obtained by converting the amplitude value to base n (n > 2) in the amplitude direction, An information processing unit that performs at least one information processing on the acquired time series data without binarizing the amplitude values of the time series data, Equipped with, If the amplitude value exceeds the maximum voltage that can be processed, the time-series data acquisition unit represents the time-series data in at least one of serialization and parallelization. Particle counting device.
3. The particle counting apparatus according to claim 2, wherein the information processing unit converts the time-series data, which is expressed in at least one of serialization and parallelization, back into the original amplitude values, and performs the information processing using the converted data.
4. The information processing unit is: The particle counting device according to claim 1, further comprising at least one logical OR circuit for adding the two analog voltage signals as the information processing.
5. The particle counting apparatus according to claim 1, wherein the time-series data acquisition unit includes a digitizer that performs AD conversion on the analog voltage signal and outputs it to the information processing unit.
6. The particle counting device according to claim 1, wherein the time-series data acquisition unit includes a transmission line for transmitting the analog voltage signal output from the particle detection sensor as the time-series data.
7. The aforementioned time-series data acquisition unit includes a DA converter that converts digital information into analog signals. The particle counting apparatus according to claim 1, wherein the analog signal converted by the DA converter is output to the information processing unit as time-series data.
8. The particle counting device according to claim 4, wherein the AND circuit is an analog multiplier and the OR circuit is an analog adder.
9. A particle counting method, A step of acquiring at least one time-series data having the amplitude value of an analog signal or the value obtained by converting the amplitude value to base n (n > 2) in the amplitude direction, A step of performing at least one information processing on the acquired time-series data without binarizing the amplitude values of the time-series data, wherein the time-series data consists of two analog voltage signals output from two particle detection sensors, and the information processing involves multiplying the two analog voltage signals by a logical AND circuit. The process involves calculating the simultaneous counting probability of two particles detected simultaneously by the two particle detection sensors based on the multiplication result of the aforementioned AND circuit, A particle counting method comprising:
10. A particle counting method, A step of acquiring at least one time-series data having the amplitude value of an analog signal or the value obtained by converting the amplitude value to base n (n > 2) in the amplitude direction, If the amplitude value exceeds the maximum voltage that can be processed, the process of representing the time series data by serialization and parallelization, A step of performing at least one information processing on the acquired time series data without binarizing the amplitude values of the time series data, A particle counting method comprising each of the following steps.
11. The particle counting method according to claim 10, wherein in the step of performing the information processing, if the time series data is represented in serialization or parallelization, the time series data is converted to the original amplitude values, and the information processing is performed using the converted data.