Delta-sigma modulator
The delta-sigma modulator addresses ISI-induced distortion and complexity by using an integrating circuit and quantizer to generate PDM signals, enhancing accuracy and simplifying the circuit, suitable for IC implementation and circuit boards.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- OSAKA SANGYO UNIVERSITY
- Filing Date
- 2022-11-10
- Publication Date
- 2026-07-24
Smart Images
Figure 0007894639000001 
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Abstract
Description
Technical Field
[0006] ,
[0001] The present invention relates to a delta-sigma modulator.
Background Art
[0002] An oversampling analog-to-digital converter (A / D converter) is used, for example, to read out various sensor outputs and incorporated into various products. The A / D converter is composed of a delta-sigma modulator which is an analog part and a digital filter (see Non-Patent Document 1).
[0003] International Publication No. 2008 / 023710 discloses a delta-sigma modulator. This delta-sigma modulator includes a loop filter that inputs a continuous-time signal from an input terminal, a quantizer that outputs a digital signal quantized in response to a clock from the output of the loop filter, and a DA converter that feeds back an analog signal corresponding to the digital signal to the loop filter.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Non-Patent Documents
[0005] Schreier, Richard / Temes, Gabor C., translated by Yasutaka Waho / Akira Yasuda, "Introduction to ΔΣ-Type Analog / Digital Converters, 2nd Edition", published by Maruzen Publishing Co., Ltd., December 2019
Summary of the Invention
Problems to be Solved by the Invention
[0006] In the feedback signal of a delta-sigma modulator, waveform distortion can occur due to inter-symbol interference (ISI). This distortion can lead to a decrease in accuracy. On the other hand, the analog circuit configuration of delta-sigma modulators has become increasingly complex in recent years. A simpler circuit configuration is preferable for delta-sigma modulators. Simplifying the configuration makes it easier to verify the operation of the delta-sigma modulator, to implement it as an IC, or to mount it on a circuit board.
[0007] Therefore, the present disclosure aims to provide a delta-sigma modulator that can suppress accuracy degradation due to distortion of the feedback signal with a simple configuration. [Means for solving the problem]
[0008] The delta-sigma modulator in an embodiment of the present invention comprises an integrating circuit that integrates the difference between an input signal and a feedback signal, and a quantizer connected downstream of the integrating circuit. The quantizer generates a pulse density modulation signal (PDM signal) by sequentially outputting a high-level or low-level voltage based on the output of the integrating circuit and a middle-level voltage between the high-level and low-level at each clock cycle, and outputs this as the feedback signal. [Brief explanation of the drawing]
[0009] [Figure 1] A diagram showing an example configuration of the delta-sigma modulator in this embodiment. [Figure 2] A diagram showing examples of the NRZ waveform W1 and its corresponding RTM waveform W2. [Figure 3] Figure 1 shows an example of the circuit configuration of a delta-sigma modulator. [Figure 4] An example of a CMOS inverter circuit diagram. [Figure 5] A graph showing an example of the input / output characteristics of a CMOS inverter. [Figure 6] The timing chart in Figure 3 shows an example of the operation of the delta-sigma modulator. [Figure 7] Figure showing a circuit configuration example of an integration circuit. [Figure 8] Figure showing a circuit configuration example of an integration circuit. [Figure 9] Figure showing a circuit configuration example of an integration circuit. [Figure 10] Figure showing a circuit configuration example of an integration circuit. [Figure 11] Figure showing a circuit configuration example of an integration circuit. [Figure 12] Figure showing a configuration example of the D-latch circuit of a quantizer. [Figure 13] Figure showing a configuration example of the D-latch circuit of quantizer 3. <OO00072> [Figure 14] Figure showing a configuration example of RTM circuit 32. <OO00074> [Figure 15] Figure showing a configuration example of RTM circuit 32. [Figure 16] Figure showing a circuit configuration example of a switch. [[ID=3o]] [Figure 17] Figure showing another configuration example of a CMOS inverter. [Figure 18] Figure showing another configuration example of a CMOS inverter. <OO00082> [Figure 19] Graph showing the analysis results by simulation of the input / output characteristics of each CMOS inverter in FIGS. 4, 17, and 18. [Figure 20] [[ID=4l]]Frequency spectrum showing the simulation results of the operation of the delta-sigma modulator with the circuit configuration shown in FIG. 3. [[ID=A3]] [Figure 21] Figure showing the operation waveforms of each part in a prototype of a delta-sigma modulator. [Figure 22] Output spectrum of the prototype.
Embodiments for Carrying Out the Invention
[0010] (Configuration 1) The delta-sigma modulator in the embodiment of the present invention includes an integrating circuit that integrates the difference between an input signal and a feedback signal, and a quantizer connected to the subsequent stage of the integrating circuit. The quantizer sequentially outputs a high-level or low-level voltage based on the output of the integrating circuit and a middle-level voltage between the high level and the low level in each cycle of the clock to generate a pulse density modulation signal (PDM signal), and outputs it as the feedback signal.
[0011] In the above Configuration 1, the PDM signal, which is the feedback signal, returns to the middle level between the high level and the low level in each cycle of the clock. As a result, inter-symbol interference is suppressed in the feedback signal. Therefore, the distortion of the feedback signal can be suppressed. In addition, since the output signal of the quantizer only takes the form of returning to the middle level, the complexity of the circuit configuration can be avoided. As a result, with a simple configuration, the reduction in accuracy due to the distortion of the feedback signal can be suppressed.
[0012] (Configuration 2) In the above Configuration 1, the quantizer may include a D flip-flop circuit (DFF circuit) that holds a high-level or low-level voltage based on the output of the integrating circuit for each clock cycle, and a middle-level return circuit (RTM circuit) that sequentially outputs the high-level or low-level voltage held by the DFF circuit and the middle-level voltage in each cycle of the clock. Thereby, the quantizer has a simple configuration with an RTM circuit added to the DFF circuit.
[0013] (Configuration 3) In the above configuration 2, the RTM circuit may include a CMOS inverter and a switch that turns on / off the short circuit between the input and output of the CMOS inverter according to the clock signal. The middle level voltage is the output voltage of the CMOS inverter when the input and output of the CMOS inverter of the RTM circuit are short-circuited. In this configuration, the short-circuit and open-circuit between the input and output of the CMOS inverter of the RTM circuit are switched on and off with each clock cycle. Therefore, the feedback signal can be periodically returned to the middle level with a simpler configuration.
[0014] (Composition 4) In the above configuration 2 or 3, the DFF circuit may be formed using a CMOS inverter. This makes the configuration of the quantizer simpler.
[0015] (Composition 5) In any of the above configurations 1 to 4, the integrating circuit may include an amplifier and a capacitor connected between the input and output of the amplifier. The amplifier may be a CMOS inverter. This simplifies the configuration of the integrating circuit.
[0016] (Composition 6) In any of the above configurations 2 to 4, the RTM circuit may include a CMOS inverter and a switch that turns on / off the short circuit between the input and output of the CMOS inverter according to the clock signal. The DFF circuit may be formed using a CMOS inverter. The integrating circuit may include a CMOS inverter and a capacitor connected in parallel with the CMOS inverter. In this case, the CMOS inverters of the RTM circuit, the DFF circuit and the integrating circuit may be configured to be the same size and shape. As a result, the middle-level voltage from each CMOS inverter in the integrating circuit, the DFF circuit and the RTM circuit will be the same. Therefore, the entire modulator can be made simpler in configuration while the feedback signal can be made into a middle-return type.
[0017] In any of the above configurations 1 to 6, the high-level voltage may be the power supply voltage, and the low-level voltage may be the ground level. As a result, the high level of the feedback signal output from the quantizer becomes the power supply voltage, and the low level becomes the ground level. Therefore, the quantizer operates as a feedback analog-to-digital converter (FBADC). In any of the above configurations 1 to 6, each of the integrating circuit, the DFF circuit, and the RTM circuit may include at least one CMOS inverter. In this case, at least one CMOS inverter of the integrating circuit, at least one CMOS inverter of the DFF circuit, and at least one CMOS inverter of the RTM circuit may be connected in series, i.e., in cascade configuration. This makes the circuit configuration of the delta-sigma modulator simpler.
[0018] In any of the above configurations 1 to 6, the DLL circuit may include at least two D-latch circuits connected in series. Each D-latch circuit may include a first CMOS inverter and a second CMOS inverter connected in series, and a switch. The switch switches between a first state, where the signal input to the first CMOS inverter is turned on to disconnect the output of the second CMOS inverter from the input of the first CMOS inverter, and a second state, where the signal input to the first CMOS inverter is turned off to connect the output of the second CMOS inverter from the input of the first CMOS inverter, at the clock cycle. The two D-latch circuits are switched by the switch such that when one is in the first state, the other is in the second state. This allows a quantizer to be constructed with a simple configuration.
[0019] The output node of the D-latch circuit can be either the node between the two CMOS inverters or the output node of the second-stage CMOS inverter.
[0020] In any of the above configurations 1 to 6, the integrating circuit may include an amplifier and a capacitor connected between the input and output of the amplifier. The input side of the amplifier may be connected to the feedback signal line and the input signal line. A resistor may be connected in series to the feedback signal line and the input signal line, respectively.
[0021] In addition to the resistor connected in series, a capacitor may be connected in parallel to the feedback signal line. In addition to the resistor connected in series, a capacitor may be connected in parallel to the input signal line. The amplifier in the integrating circuit can be an operational amplifier or a CMOS inverter.
[0022] (Embodiment) Figure 1 shows an example configuration of a delta-sigma modulator in this embodiment. The delta-sigma modulator comprises an integrator 2 and a quantizer 3. The integrator 2 integrates the difference between the input signal and the feedback signal. The integrator 2 has a terminal to which an analog input signal is input and a terminal to which a feedback signal is input. The integrator 2 may include, for example, an arithmetic unit that extracts the difference between the input signal and the feedback signal, and an integrator that integrates the output signal of the arithmetic unit. The integrator 2 operates in synchronization with a clock signal. As a result, the integrated value is output at the clock period.
[0023] Quantizer 3 is connected downstream of integrator 2. Quantizer 3 quantizes the output of integrator 2, i.e., the integral signal, and outputs a high-level or low-level value. In this embodiment, quantizer 3 is a 1-bit quantizer. Quantizer 3 operates in synchronization with the clock signal. As a result, a high-level or low-level signal is output at the clock cycle. The signal output from quantizer 3 is a PDM signal. The pulse density of the PDM signal output from quantizer 3 corresponds to the voltage amplitude of the analog input signal input to integrator 2. The output of quantizer 3 is connected to the input of integrator 2. The PDM signal output by quantizer 3 is fed back to integrator 2 as a feedback signal.
[0024] The quantizer 3 is configured to sequentially output a high-level or low-level voltage (H or L) and a middle-level voltage Vb based on the output of the integrator 2 during each clock cycle. The middle-level voltage Vb is the voltage between the high-level H and the low-level L. The quantizer 3 outputs a high-level or low-level voltage (H or L) for half of each clock cycle and a middle-level voltage Vb for the remaining half-cycle. This results in the output of a PDM signal that returns to the middle level in each cycle.
[0025] In the example shown in Figure 1, the quantizer 3 includes a D flip-flop circuit (DFF circuit) 31 and a subsequent middle-level return circuit (RTM circuit) 32. The DFF circuit 31 holds the signal output from the integrator 2 as 1-bit information, represented by a high-level or low-level voltage, during each clock cycle. The RTM circuit 32 outputs the high-level or low-level voltage held by the DFF circuit 31 for half a cycle and a middle-level voltage for the remaining half a cycle. The non-zero return (NRZ) signal output from the DFF circuit 31 is converted into a middle-level return signal (RTM (Return to Middle) signal) by the RTM circuit 32. This RTM signal is fed back to the integrator 2 as a feedback signal.
[0026] Thus, by using an RTM waveform for the feedback signal, distortion due to intersymbol interference (ISI) is suppressed compared to an NRZ waveform. Figure 2 shows an example of an NRZ waveform W1 and its corresponding RTM waveform W2. As shown in Figure 2, the same value (for example, "1" = high level) may occur consecutively in a PDM signal. In this case, the RTM waveform W2 produces rising and falling edges of pulses for each consecutive "1", while the NRZ waveform W1 has a rising edge at the beginning of the TA period of consecutive "1"s and a falling edge at the end of this TA period. Therefore, if there is a distortion in the rising and falling edges of the pulses, the NRZ waveform is more prone to distortion than the RTM waveform. In other words, distortion can be suppressed by using an RTM waveform. For example, when the load capacitance increases and the waveform becomes distorted, the distortion suppression effect of the RTM waveform becomes more pronounced.
[0027] Figure 3 shows an example of the circuit configuration of the delta-sigma modulator shown in Figure 1. The NOT gate in Figure 3 is composed of a CMOS inverter. Figure 4 shows an example of the circuit diagram of the NOT gate and the CMOS inverter that constitutes the NOT gate. As shown in Figure 4, the CMOS inverter is a circuit that combines a p-channel MOSFET (pMOS) and an n-channel MOSFET (nMOS). The gate of the pMOS is connected to the gate of the nMOS, and the drain of the pMOS is connected to the drain of the nMOS. The gate becomes the input (input terminal) of the CMOS, and the drain becomes the output (output terminal).
[0028] Figure 5 is a graph showing an example of the input / output characteristics of a CMOS inverter. In the graph in Figure 5, the horizontal axis represents the input voltage Vin, and the vertical axis represents the output voltage Vout. As shown in Figure 5, there is a transition region Sa in which the output voltage Vout changes rapidly in the region between the high and low levels of the input voltage Vin. In this transition region Sa, both the pMOS and nMOS of the CMOS operate in the saturation region. In this transition region Sa, the ratio of the change in output voltage Vout to the change in input voltage Vin becomes large. By setting the input voltage Vin of the CMOS inverter near the transition region Sa, the CMOS inverter can be operated as an amplifier. Also, when the input and output of the CMOS inverter are short-circuited (Vin = Vout), a voltage Vb with a high gain is obtained from the CMOS inverter. This voltage Vb can be used as the middle level voltage of the RTM circuit 32.
[0029] In the example shown in Figure 3, the integrating circuit 2, the DFF circuit 31, and the RTM circuit 32 each have at least one CMOS inverter. In the delta-sigma modulator of Figure 3, the CMOS inverter IV1 of the integrating circuit 2, the CMOS inverters IV3 and IV5 of the DFF circuit 31, and the CMOS inverter IV7 of the RTM circuit 32 are connected in series, i.e., cascaded. These cascaded CMOS inverters IV1, IV3, IV5, and IV7 may all be configured to operate in the transition region Sa. This simplifies the circuit configuration of the delta-sigma modulator. Furthermore, the cascaded CMOS inverters IV1, IV3, IV5, and IV7 can all be the same size and shape so that the high-gain voltage Vb during a short circuit is the same.
[0030] The integrating circuit 2 in Figure 3 is a two-input integrating circuit having a terminal for inputting an analog input signal and a terminal for inputting a feedback signal. The preceding section of the integrating circuit 2 includes a resistor R1 on the input signal line, a resistor R2 on the feedback signal line, and an adder 21. The adder 21 receives the input signal and the feedback signal and outputs the difference signal between them. In this example, the integrating circuit 2 and quantizer 3 are configured such that the output of adder 21 is the difference signal between the input signal and the feedback signal, and the feedback signal is an inverted signal. In Figure 3, the number of cascaded CMOS inverters from the integrating circuit 2 to the output of quantizer 3 is odd. This allows for the feedback of the inverted signal. Note that if the feedback signal input to the integrating circuit 2 is a non-inverting signal, adder 21 may be replaced with a subtractor, or an inverting circuit may be provided before adder 21 to invert the feedback signal. Note that resistors R1, R2, and adder 21 may be provided outside the integrating circuit 2.
[0031] The integrating circuit 2 includes an amplifier that amplifies the difference signal between the input signal and the feedback signal, and a feedback circuit that feeds the output of the amplifier back to the input of the amplifier. In the example in Figure 3, the amplifier is a CMOS inverter IV1, and the feedback circuit includes capacitors C1 and C2 connected in series between the input and output of the amplifier, and R3 connected in parallel. In Figure 3, the feedback circuit is, as an example, a second-order T-type feedback circuit, but it may be first-order or third-order or higher. Also, the amplifier may be an operational amplifier instead of a CMOS inverter. In the example in Figure 3, a CMOS inverter IV2 is further provided on the output side of the amplifier. The CMOS inverter IV2 can suppress the influence of the DFF circuit 31 on the integrating circuit 2.
[0032] The DFF circuit 31 operates as a 1-bit quantizer. It has two stages of D latch circuits DL1, DL2. In the example in Figure 3, each of the two stages of D latch circuits DL1 and DL2 has two CMOS inverters (IV3, IV4 and IV5, IV6) and two switches (S1, S2 and S3, S4). Switches S1 to S4 are turned on / off in response to a clock signal (Φ or its inverted signal). The on / off switching of switches S1, S2 (or S3, S4) switches between a through phase that outputs a voltage corresponding to the input voltage of the CMOS inverter and a holding phase that holds the output voltage of the CMOS inverter, with a period based on the clock.
[0033] Specifically, the D-latch circuit DL1 has two CMOS inverters IV3 and IV4 connected in series (an example of first and second CMOS inverters). Switch S1 turns the input of CMOS inverter IV3 on / off. Switch S2 turns the connection between the input of CMOS inverter IV3 and the output of CMOS inverter V4 on / off. The on / off of switch S1 and switch S2 in response to a crack signal are opposite. When S1 is on and S2 is off, it is the through phase. When S1 is off and S2 is on, it is the hold phase. The second-stage D-latch circuit DL2 is configured similarly. Switch S3, which turns the input of the second-stage D-latch circuit DL2 on / off, has the opposite on / off behavior to switch S1 of the first-stage D-latch circuit DL1. Therefore, when DL1 is in the through phase, DL2 is in the hold phase, and when DL1 is in the hold phase, DL2 is in the through phase.
[0034] In the first-stage D-latch circuit DL1, the CMOS inverter IV3 functions as an amplifier circuit during the through-phase. For example, by configuring the CMOS inverter IV3 of the D-latch circuit DL1 to match the voltage Vb of the CMOS inverters IV1 and IV2 of the integrating circuit 2, it can function as an amplifier circuit during the through-phase.
[0035] In the second-stage D-latch circuit DL2, the high-level output voltages of the CMOS inverters IV4 and IV5 can be used as the power supply voltage VDD, and the low-level output voltages can be used as the ground level. As a result, the second-stage latch circuit DL2 and the RTM circuit 32 operate as an FBDAC (Feedback Digital to Analog Converter).
[0036] The RTM circuit 32 includes CMOS inverters IV7 and IV8, and switches S5 and S6. Switches S5 and S6 switch between a first state, where the signal input to CMOS inverter IV7 is turned on and the input and output of CMOS inverter IV7 are disconnected, and a second state, where the signal input to CMOS inverter IV7 is turned off and the input and output of CMOS inverter IV7 are short-circuited, at a frequency based on the clock signal. Specifically, switch S5 turns the input of CMOS inverter IV7 on / off. Switch S6 turns the short-circuit between the input and output of CMOS inverter IV7 on / off. Switches S5 and S6 are turned on / off at a frequency based on the clock signal. The on / off state of switch S5 is controlled to be opposite to the on / off state of S6. When S5 is on and S6 is off, the RTM circuit 32 is in the first state, and when S5 is off and S6 is on, the RTM circuit 32 is in the second state. In the example shown in Figure 3, the output of CMOS inverter IV7 is connected to the input of CMOS inverter IV8, and the output of CMOS inverter IV8 is connected to the input of CMOS inverter IV7. Note that the RTM circuit 32 may also be configured without CMOS inverter IV8 (see Figure 14).
[0037] Figure 6 is a timing chart showing an example of the operation of the delta-sigma modulator shown in Figure 3. In the example in Figure 6, at each clock cycle, the integrating circuit 2 outputs a signal obtained by integrating the signal obtained by subtracting the feedback signal from the input signal. The first-stage D-latch circuit DL1 outputs a signal obtained by converting the output signal of the integrating circuit 2 at each clock cycle into a high-level or low-level voltage. The second-stage D-latch circuit DL2 outputs the output voltage of the first-stage D-latch circuit DL1 at each clock cycle with a half-cycle clock delay. The RTM circuit 32 inverts the high-level or low-level voltage output in the holding phase of the D-latch circuit DL2 using the CMOS inverter IV7 and outputs it, and outputs a middle-level voltage Vb obtained by short-circuiting the input and output of the CMOS inverter IV7 during the through phase of the D-latch circuit DL2. As a result, at each clock cycle, the high-level or low-level voltage, which is the signal voltage, and the middle-level voltage Vb are output as feedback signals. In other words, the feedback signal is reset to the middle level at each clock cycle.
[0038] In the timing chart shown in Figure 6, the signals output from the D latch circuits DL1 and DL2 are NRZ signals. Therefore, when the sign (high or low, 1 or 0) of the signals output from DL1 and DL2 is the same for multiple clock cycles, the weight of 1 changes compared to when the sign changes with each clock cycle (see A1 in Figure 6). In other words, intersymbol interference (ISI) occurs. ISI is suppressed by resetting the RTM circuit 32 to a middle-level voltage Vb with each clock cycle. Thus, in this embodiment, ISI can be suppressed and accuracy degradation due to distortion of the feedback signal can be reduced with a simple configuration of providing the RTM circuit 32.
[0039] In the example configuration shown in Figure 3, the integrating circuit 2, DFF circuit 31, and RTM circuit 32 each include CMOS inverters IV1 to IV7. This simplifies the configuration of the delta-sigma modulator. Furthermore, in the integrating circuit 2 and DFF circuit 31, CMOS inverters IV1 and IV3 can be operated as amplifiers. This further simplifies the configuration. For example, when implementing a delta-sigma modulator on a breadboard, it is possible to implement it using a combination of CMOS inverter ICs, switch ICs, resistors, capacitors, and other components, without using general-purpose logic ICs.
[0040] It is preferable that the CMOS inverters IV1 to IV7 included in the integrating circuit 2, DFF circuit 31, and RTM circuit 32, respectively, are configured such that the high-gain voltage Vb is the same when the input and output are short-circuited. For this purpose, for example, the CMOS inverters IV1 to IV7 may be configured with the same size and shape. A configuration in which multiple CMOS inverters are configured with the same size and shape is, for example, a configuration in which the pMOSFETs and nMOSFETs constituting each CMOS inverter are the same size and shape. In this case, it is sufficient that the sizes and shapes of the pMOSFETs and nMOSFETs constituting each of the multiple CMOS inverters are similar enough that the voltage Vb of the multiple CMOS inverters is the same.
[0041] Note that the circuit configuration of the delta-sigma modulator is not limited to the example shown in Figure 3. For example, the integrating circuit 2 may have the circuit configuration shown in any of Figures 7 to 11. As shown in Figures 7 and 8, an operational amplifier Ap may be used as the amplifier instead of a CMOS inverter. In this case, the difference signal between the input signal and the feedback signal is input to the operational amplifier Ap. The integrating circuit 2 has a feedback circuit that connects the terminal to which the difference signal of the operational amplifier Ap is input to the output terminal. In the example in Figure 7, the feedback circuit is a first-order feedback circuit consisting of one capacitor C1. In the example in Figure 8, the feedback circuit is a second-order T-type feedback circuit having two capacitors C1 and C2 in series and a resistor R3 connected in parallel between them. Figure 9 shows an example configuration when the feedback circuit of the integrating circuit 2 shown in Figure 3 is a first-order feedback circuit.
[0042] As shown in Figures 10 and 11, low-pass filters may be provided on both the input signal line and the feedback signal line in the preceding stage of the integrating circuit 2. The low-pass filter can be, for example, an RC filter including two resistors R21 and R22 connected in series and a capacitor C21 connected in parallel between them. Figure 10 shows an example where the feedback circuit is first-order, and Figure 11 shows an example where the feedback circuit is second-order.
[0043] Figures 12 and 13 show examples of the configuration of the D-latch circuit of the quantizer 3. Figure 12 has a configuration similar to the D-latch circuits DL1 and DL2 in Figure 3. In the examples of Figures 12 and 13, the D-latch circuit DL1 has two CMOS inverters IV3 and IV4 connected in series. The output of CMOS inverter IV3 is connected to the input of CMOS inverter IV4, and the output of CMOS inverter IV4 is connected to the input of CMOS inverter IV3 via switch S2. In Figure 12, the node between the two CMOS inverters IV3 and IV4 is the output node of the D-latch circuit DL. In Figure 13, the output node of CMOS inverter IV4 is the output node of the D-latch circuit DL. Figure 12 is an example of a D-latch circuit that inverts the input signal before outputting it, and Figure 13 is an example of a D-latch circuit that outputs the input signal without inverting it.
[0044] Figures 14 and 15 show examples of the configuration of the RTM circuit 32. Figure 12 has the same configuration as the RTM circuit 32 in Figure 3. Figure 15 has the same configuration as in Figure 14, but with the CMOS inverter IV8 omitted. Figure 14 is a latch type, and Figure 15 is an inverter type.
[0045] Figure 16 shows an example of the circuit configuration of the switches in the DFF circuit 31 and the RTM circuit 32. In the example in Figure 16, the switch has a p-type MOSFET (pMOS) and an n-type MOSFET (nMOS). The drains of the pMOS and the nMOS are connected, and the sources of the pMOS and nMOS are connected. The drain is terminal a of the switch, and the source is terminal b of the switch. An inverted signal of the clock signal Φ is input to one of the gates of the pMOS and the nMOS, and a non-inverted signal of the clock signal Φ is input to the other. The threshold voltage of the gate is set to a voltage between the high level and the low level of the clock signal. This controls the switch to be on / off in response to the clock signal.
[0046] Figures 17 and 18 show other configuration examples of a CMOS inverter. The example in Figure 17 is a configuration in which voltage sources P1 and P2 are added to the CMOS inverter shown in Figure 4. Voltage source P1 is connected between the input terminal Tin of the CMOS inverter and the gate of the pMOS. Voltage source P1 causes the voltage at the gate of the pMOS to be higher than that at the input terminal Tin. Voltage source P2 is connected between the input terminal Tin of the CMOS inverter and the gate of the nMOS. Voltage source P2 causes the voltage at the input terminal Tin to be higher than that at the gate of the nMOS.
[0047] The example in Figure 18 is a configuration in which resistors R41 to R44 and diodes D1 and D2 are added to the CMOS inverter shown in Figure 4. Resistor R41 is connected between the gate and source terminal T1 of the pMOS. For example, the power supply voltage VDD is input to the source terminal T1 of the pMOS. Resistor R42 and diode D1 are connected between the gate and input terminal Tin of the pMOS. The forward direction of diode D1 is from the gate of the pMOS to the input terminal Tin. Resistor R43 and diode D2 are connected between the input terminal Tin and the gate of the nMOS. The forward direction of diode D2 is from the input terminal Tin to the gate of the nMOS. Resistor R44 is connected between the gate and source terminal T2 of the nMOS. For example, the source terminal T2 of the nMOS is connected to ground.
[0048] As shown in Figures 17 and 18, the characteristics of a CMOS inverter can be adjusted by adding components in addition to nMOS and pMOS. Figure 19 is a graph showing the simulation analysis results of the input / output characteristics of the CMOS inverters in Figures 4, 17, and 18. In Figure 19, W1 represents the analysis results for the CMOS inverter in Figure 4, W2 for Figure 17, and W3 for Figure 18.
[0049] In this embodiment, by introducing the RTM circuit 32 in the delta-sigma modulator, accuracy degradation can be suppressed with a simple configuration. Furthermore, by operating the CMOS inverter as an amplifier, the delta-sigma modulator can be made even simpler in configuration. In the above example, the delta-sigma modulator can be configured with a combination of a CMOS inverter, a switch, a resistor, and a capacitor. For example, the delta-sigma modulator can be configured without using complex analog circuits such as operational amplifiers. For example, the delta-sigma modulator of this embodiment may be configured as an IC. In this case, the delta-sigma modulator becomes easier to implement as an IC because the circuit configuration is simpler. Alternatively, the delta-sigma modulator of this embodiment may be configured by mounting a CMOS inverter IC, a switch IC, a resistor, and a capacitor on a breadboard.
[0050] A delta-sigma modulator may be used as the analog portion of an A / D converter. In this case, the A / D converter includes a delta-sigma modulator and a digital filter that processes the output signal of the delta-sigma modulator. In this case, the delta-sigma modulator has a simple configuration, which allows the analog portion of the A / D converter to be made smaller. The delta-sigma modulator of the present invention is not limited to these examples, but can be used, for example, in a column A / D converter of an image sensor, or in an A / D converter that converts the analog output of other sensors to digital. In this case, the accuracy of the A / D conversion can be ensured while keeping the analog circuit of the sensor small.
[0051] (Simulation results) Figure 20 shows the frequency spectrum of the operation of the delta-sigma modulator with the circuit configuration shown in Figure 3, based on a simulation. Figure 20 also shows the frequency spectrum of the digital output of the delta-sigma modulator. LTSPICE was used as the simulator. From the results shown in Figure 20, it was found that an accuracy of approximately 45 dB can be achieved with the delta-sigma modulator with the circuit configuration shown in Figure 3.
[0052] (Measurement results) A delta-sigma modulator with the circuit configuration shown in Figure 3 was prototyped and measured. Figure 21 shows the operating waveforms of each part of the prototype delta-sigma modulator. The left side of Figure 21 shows the waveform with a horizontal axis scale of 2ms, and the right side shows the waveform with a horizontal axis scale of 2μm. From top to bottom, the waveforms are shown for the clock signal, input signal, RTM, and regenerated signal. RTM is the output waveform of the RTM circuit. The regenerated signal is the signal obtained by taking the output of the delta-sigma modulator through an analog low-pass filter. In the results shown in Figure 20, the output waveform of the 1-bit quantized RTM returns to the middle-level voltage Vb at each period of the clock.
[0053] Figure 22(a) shows the output spectrum of a prototype with an RTM circuit (circuit configuration shown in Figure 3). Figure 22(b) shows the output spectrum of a prototype without an RTM (the circuit configuration shown in Figure 3 with the RTM removed). When the RTM circuit was introduced, an improvement in accuracy was observed compared to when the RTM circuit was not introduced.
[0054] Although one embodiment of the present invention has been described above, the above-described embodiments are merely illustrative examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiments, and it is possible to carry out the above-described embodiments by appropriately modifying them without departing from the spirit of the present invention. [Explanation of symbols]
[0055] 2: Integrator circuit, 3: Quantizer, 31: DFF circuit, 31: RTM circuit
Claims
1. An integrating circuit that integrates the difference between an input signal and a feedback signal, The circuit comprises a quantizer connected to the subsequent stage of the integrating circuit, The quantizer generates a pulse density modulation (PDM) signal by sequentially outputting a high-level or low-level voltage based on the output of the integrating circuit and a middle-level voltage between the high-level and low-level voltages at each clock cycle, and outputs this as the feedback signal. The quantizer includes a D flip-prop circuit (DFF circuit) that holds a high-level or low-level voltage based on the output of the integrating circuit for each clock period, and a middle-level return circuit (RTM circuit) that sequentially outputs the high-level or low-level voltage held by the DFF circuit and a middle-level voltage for each clock period. The RTM circuit includes a CMOS inverter and a switch that turns on / off the short circuit between the input and output of the CMOS inverter according to a clock signal. The middle-level voltage is the output voltage of the CMOS inverter when the input and output of the RTM circuit of the CMOS inverter are short-circuited, and this is a delta-sigma modulator.
2. An integration circuit that integrates the difference between an input signal and a feedback signal, The circuit comprises a quantizer connected to the subsequent stage of the integrating circuit, The quantizer generates a pulse density modulation (PDM) signal by sequentially outputting a high-level or low-level voltage based on the output of the integrating circuit and a middle-level voltage between the high-level and low-level voltages at each clock cycle, and outputs this as the feedback signal. The quantizer includes a D flip-prop circuit (DFF circuit) that holds a high-level or low-level voltage based on the output of the integrating circuit for each clock period, and a middle-level return circuit (RTM circuit) that sequentially outputs the high-level or low-level voltage held by the DFF circuit and a middle-level voltage for each clock period. The DFF circuit is a delta-sigma modulator formed using a CMOS inverter.
3. An integration circuit that integrates the difference between an input signal and a feedback signal, The circuit comprises a quantizer connected to the subsequent stage of the integrating circuit, The quantizer generates a pulse density modulation (PDM) signal by sequentially outputting a high-level or low-level voltage based on the output of the integrating circuit and a middle-level voltage between the high-level and low-level voltages at each clock cycle, and outputs this as the feedback signal. The integrating circuit includes an amplifier and a capacitor connected between the input and output of the amplifier. The aforementioned amplifier is a delta-sigma modulator composed of a CMOS inverter.
4. An integration circuit that integrates the difference between an input signal and a feedback signal, The circuit comprises a quantizer connected to the subsequent stage of the integrating circuit, The quantizer generates a pulse density modulation (PDM) signal by sequentially outputting a high-level or low-level voltage based on the output of the integrating circuit and a middle-level voltage between the high-level and low-level voltages at each clock cycle, and outputs this as the feedback signal. The quantizer includes a D flip-prop circuit (DFF circuit) that holds a high-level or low-level voltage based on the output of the integrating circuit for each clock period, and a middle-level return circuit (RTM circuit) that sequentially outputs the high-level or low-level voltage held by the DFF circuit and a middle-level voltage for each clock period. The RTM circuit includes a CMOS inverter and a switch that turns on / off the short circuit between the input and output of the CMOS inverter according to a clock signal. The DFF circuit is formed using a CMOS inverter. The integrating circuit includes a CMOS inverter and a capacitor connected in parallel to the CMOS inverter. The CMOS inverters of the RTM circuit, the DFF circuit, and the integrating circuit are delta-sigma modulators configured to be the same size and shape.