Digit recurrence selection constant

Abstract

To provide a data processing apparatus, method and computer-readable medium to perform a digit-recurrence operation on an input value.SOLUTION: A data processing apparatus 2 receives a remainder value of a previous iteration of the digit-recurrence operation, performs comparisons of most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of multiple selection constants associated with available digits of a next digit of a result of the digit-recurrence operation, and outputs the next digit of the result of the digit-recurrence operation based on the comparisons. Each of the selection constants is associated with one of the available digits and an input parameter. Storage circuitry configured to store a subset of the selection constants excludes the selection constants associated with a digit excluded from the available digits.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This technology relates to the field of data processing.

[0002] Digit recurrence algorithms can be used to perform operations such as division or square root. Digit recurrence performs calculations using an iterative algorithm. In each iteration, the next digit of the result value is generated. Each digit is represented using several bits. In the radix r embodiment of the digit recurrence algorithm, each digit has log2(r) bits. For example, an implementation using radix 4 represents each digit with 2 bits, and therefore, in each iteration, two more bits of the result are generated, and thus, generating a result value with a certain number of bits may require a certain number of iterations. Implementations using higher radixes can improve performance by generating results of a given size in fewer iterations, but the circuit for performing a single iteration becomes more complex. When designing a circuit to perform such a digit recurrence method, there may be challenges in meeting the competing requirements of performance, circuit area, and power consumption.

[0003] In at least some examples, a data processing device is provided for performing a digit recurrence operation on an input value, comprising: a receiving circuit configured to receive the remainder of a previous iteration of the digit recurrence operation; a comparing circuit configured to perform a comparison between each of a plurality of selection constants associated with the available digits of the next digit of the result of the digit recurrence operation, each of which is associated with one of the available digits and an input parameter, and the most significant bit of the remainder of a previous iteration of the digit recurrence operation, and output the next digit of the result of the digit recurrence operation based on the comparison; and a storage circuit configured to store a subset of the selection constants, the subset of which excludes the selection constants associated with the digits excluded from the available digits.

[0004] In at least some examples, a data processing method is provided for performing a digit recurrence operation on an input value, the method comprising: receiving the remainder of a previous iteration of the digit recurrence operation; each of a plurality of selection constants associated with the available digits of the next digit of the result of the digit recurrence operation, each of which performs a comparison between one of the available digits and each of the plurality of selection constants associated with an input parameter and the most significant bit of the remainder of a previous iteration of the digit recurrence operation, and outputs the next digit of the result of the digit recurrence operation based on the comparison; and storing a subset of the selection constants, the subset of selection constants excludes selection constants that are excluded from the selection constants, which are associated with digits excluded from the available digits.

[0005] In at least some examples, a computer-readable medium is provided for storing computer-readable code for manufacturing a data processing device for performing a digit recurrence operation on input values, the medium comprising: a receiving circuit configured to receive the remainder of a previous iteration of a digit recurrence operation; each of a plurality of selection constants associated with the available digits of the next digit of the result of the digit recurrence operation, each of which selection constants is configured to perform a comparison between each of a plurality of selection constants associated with one of the available digits and an input parameter and the most significant bit of the remainder of a previous iteration of a digit recurrence operation, and output the next digit of the result of the digit recurrence operation based on the comparison; and a storage circuit configured to store a subset of the selection constants, the subset of selection constants being configured to store a subset of selection constants, excluding selection constants that are excluded from the selection constants, which are associated with digits excluded from the available digits. [Brief explanation of the drawing]

[0006] Further aspects, features, and advantages of this technology will become apparent from the following example description, which should be read in conjunction with the attached drawings. [Figure 1]This diagram schematically shows an example of a data processing operation that includes a division / square root processing circuit. [Figure 2] This diagram schematically illustrates an example of splitting a higher-radix digit recursive square root or division operation, performed within the same processing cycle, into multiple lower-radix partial iterations. [Figure 3] This diagram shows a circuit for performing iterative square root operations for a given base r. [Figure 4] This diagram shows the remainder update circuit. [Figure 5] This is a diagram showing the remainder estimation circuit. [Figure 6] This diagram shows a digit selection circuit. [Figure 7-1] This diagram shows in more detail a square root processing circuit for performing a given base 64 iteration of the square root operation by executing two base 8 partial iterations in the same processing cycle. [Figure 7-2] This diagram shows in more detail a square root processing circuit for performing a given base 64 iteration of the square root operation by executing two base 8 partial iterations in the same processing cycle. [Figure 8-1] This demonstrates a combined division / square root processing circuit capable of performing both division and square root operations, where the shared circuit generates at least one output value on the same data path used for both the division and square root operations. [Figure 8-2] This demonstrates a combined division / square root processing circuit capable of performing both division and square root operations, where the shared circuit generates at least one output value on the same data path used for both the division and square root operations. [Figure 9-1] This figure shows an example of a division / square root pipeline. [Figure 9-2] This figure shows an example of a division / square root pipeline. [Figure 10] This figure illustrates the pipelined operation of consecutive division or square root operations, where the second operation is prohibited from starting a predetermined number of cycles after the first operation if the second operation uses a lower-precision floating-point representation than the first operation. [Figure 11] This is a diagram showing the on-the-fly transformation. [Figure 12] This figure shows an example of an on-the-fly conversion. [Figure 13] This is a diagram showing the on-the-fly transformation of 3X digits. [Figure 14] This figure shows an example of a 3X on-the-fly conversion. [Figure 15-1] This diagram shows a circuit for performing a 3x on-the-fly conversion. [Figure 15-2] This diagram shows a circuit for performing a 3x on-the-fly conversion. [Figure 16] This diagram shows the selection for reconstructing the partial root value. [Figure 17] This figure shows the comparison constants for partial iterations of the division operation with base 8. [Figure 18] This figure shows the comparison constants for partial iterations of the square root operation with base 8. [Figure 19] This figure shows the offset representing the offset of the square root comparison constant to the division comparison constant. [Figure 20-1] This figure shows division and offset lookup tables for determining comparison constants in division and square root operations. [Figure 20-2] This figure shows division and offset lookup tables for determining comparison constants in division and square root operations. [Figure 21-1] This shows a circuit for obtaining a set of comparison constants for division and square root operations. [Figure 21-2] This shows a circuit for obtaining a set of comparison constants for division and square root operations.

[0007] Square root treatment The square root processing circuit may perform a given radix-r iteration of the square root operation of radix r by performing two or more radix-n partial iterations in the same processing cycle, where n < r. This can provide a better compromise between performance and circuit overhead compared to an implementation form that does not subdivide the radix-r iteration into lower-radix partial iterations. Since the overall operation executed in one cycle is a higher-radix operation of radix r, this means that log2(r) bits of the result can be generated per processing cycle, which can provide higher performance than when a smaller radix is used. However, the radix-r iteration is divided into several radix-n partial iterations in the same processing cycle, where for each partial iteration, n is smaller than r. As a result, the overall size of the circuit can be smaller than when the radix-r iteration is executed as a single operation. This is because the number of alternative options available for selection as the next digit for each partial iteration using radix n is less than the number of alternative options for the radix-r digits required when the radix-r iteration of the square root operation is executed as a single operation. However, dividing the radix-r iteration into smaller-radix partial iterations may pose a timing challenge in that those radix-n partial iterations may not be able to fit into a single processing cycle.

[0008] For a given radix n partial iteration, the square root processing circuit may include: a digit selection circuit that selects the next radix n result digit of the square root result based on the previous remainder estimate; a remainder update circuit that adjusts the previous remainder based on a remainder adjustment value corresponding to the next radix n result digit selected by the digit selection circuit to generate an updated remainder value; a remainder estimate circuit that generates an updated remainder estimate showing an estimate of a portion of the updated remainder value; and an output signal path for supplying the updated remainder value and updated remainder estimate for use as the previous remainder value and previous remainder estimate in a subsequent radix n partial iteration of a given radix r iteration, or in the first radix n partial iteration of a further radix r iteration of the radix r square root operation. Since multiple partial iterations are performed per cycle, multiple instances of the digit selection circuit, remainder update circuit, remainder estimate circuit, and output signal path may be provided for each radix n partial iteration within the same radix r iteration of the square root operation.

[0009] In the last sub-iteration of radix n of an iteration of radix r, the remainder estimator circuit may generate an updated remainder estimator in parallel with the remainder update circuit that generates the updated remainder value. This is counterintuitive, as one might expect the remainder value to be available first, and then the remainder estimator to be calculated sequentially, since the updated remainder estimator represents a portion of the updated remainder value. However, the inventors have recognized that in embodiments where an iteration of a higher radix is ​​divided into a sub-iteration of a smaller radix, it is possible to generate the updated remainder estimator for the last sub-iteration in parallel with the remainder update circuit that generates the updated remainder value for that last sub-iteration of the given radix r iteration. This means that the delay associated with calculating the remainder estimator for the last sub-iteration of radix n can be at least partially removed from the critical timing path through the square root processing circuit, reducing the overall time it takes to perform the square root operation for the given radix r iteration and thus improving overall performance.

[0010] A remainder update circuit may generate the updated remainder value in a redundant representation. For example, the remainder value may be represented as two terms that together represent the numerical value of the updated remainder value, or there may be two or more combinations of values ​​for the first and second terms that can represent the same numerical value. Generating the updated remainder value in a redundant representation can be useful because it avoids the calculation of the updated remainder value which would require propagating the carry from one bit to another. Therefore, the remainder update circuit may include a carry-hold adder circuit.

[0011] However, for the purpose of selecting the next radix n result digit of the square root result, the digit selection circuit can perform digit selection using a non-redundant representation of the remainder, and thus the remainder estimation circuit can generate an updated remainder estimate in a non-redundant representation that shows an estimate of at least a portion of the updated remainder value (a non-redundant representation means that the estimate can be represented in a single term, and for any given number in the updated remainder estimate, there is a single bit pattern (and no other) of the non-redundant representation corresponding to that number). Since the full precision of the updated remainder value may not be required for digit selection, the updated remainder estimate can have fewer bits than the updated remainder value (more specifically, the updated remainder estimate can have fewer bits than the number of bits in a single term of the redundantly represented remainder value, which can contain two redundant terms), and by limiting the number of bits in the estimate, the delay in calculating the non-redundant remainder estimate is reduced. For example, the updated remainder estimate can represent an estimate of the most important portion of the updated remainder value, since fewer bits may not significantly affect the precision of digit selection.

[0012] Therefore, the calculation of the remainder estimate in a non-redundant representation can use a carry-propagating adder circuit, which may be slower than a carry-suspended adder, as the carry can be propagated from one bit position to another bit position digit. Thus, in a typical method, the carry-propagating adder circuit used for the remainder estimate can significantly slow down the overall processing of a particular iteration of the square root operation.

[0013] However, the inventors recognize that in a method in which a square root iteration of radix r is divided into multiple smaller sub-iterations of radix n performed within the same processing cycle, the updated remainder estimate of the last sub-iteration of radix n can be computed in parallel with the computation of the updated remainder value, which can be computed using information provided as input to the remainder update circuit in the last sub-iteration of radix n and / or other information from previous sub-iterations in a given iteration of radix r, thus avoiding the need to wait for the updated remainder value in the last sub-iteration of radix n to become available before starting the computation of the updated remainder estimate of the last sub-iteration of radix n. This provides a relatively significant gain in performance due to the removal of the relatively slow carry propagation sum from the critical timing path for computed the updated remainder estimate in the last sub-iteration of radix n of a given iteration of radix r.

[0014] In the remainder update, the previous remainder value is updated based on a remainder adjustment value that takes a value dependent on the next result digit selected by the digit selection circuit. The remainder estimation circuit in the last radix n partial iteration can use this remainder adjustment value and the previous remainder estimation value to generate an updated remainder estimation value for the last radix n partial iteration. Since the remainder adjustment value is used as input to the remainder estimation circuit in the last radix n partial iteration, this eliminates the need to wait for the updated remainder value and allows for faster utilization of the updated remainder estimation.

[0015] The remainder estimator circuit can take advantage of the fact that the last radix n partial iteration is followed by at least one previous partial iteration that is executed within the same cycle, and as a result some information computed in that previous partial iteration can be used by the remainder estimator circuit in the last partial iteration to compute the updated remainder estimator faster than if the remainder estimator were computed sequentially after the updated remainder value was obtained.

[0016] For example, in a preceding radix-n partial iteration of a given radix-r partial iteration, other than the last radix-n partial iteration, the remainder estimator may compute at least one additional bit of the updated remainder estimator that is not needed to select the next radix-n result digit in the last radix-n partial iteration of the given radix-r partial iteration, and in the last radix-n partial iteration of a given radix-r partial iteration, the remainder estimator may use the at least one additional bit determined in the preceding radix-n partial iteration to determine the updated remainder estimator. By computing more bits than required for the updated remainder estimator in the preceding radix-n partial iteration, the additional bits can be used to compute the updated remainder estimator earlier in the last radix-n partial iteration, because the additional bits computed in the preceding partial iteration allow the computed updated remainder estimator in the last partial iteration to be computed without waiting for the updated remainder value to become available.

[0017] In the first sub-iteration of base n of a given sub-iteration of base r, the remainder estimator can determine the updated remainder estimator based on the updated remainder value generated by the remainder update circuit in the first sub-iteration of base n. Therefore, it is not necessary for the updated remainder estimator to be computed in parallel with the updated remainder value in all sub-iterations. In the first sub-iteration of a given sub-iteration of base r, there may not be enough information available to compute the remainder estimator until the updated remainder value is available in redundant form. However, because multiple sub-iterations of base n overlap within the same processing cycle, the circuit designer has the freedom to change the relative timing at which parts of subsequent sub-iterations start relative to parts of previous sub-iterations, and can compute parameters in later sub-iterations using information from previous sub-iterations, making it possible to parallelize the computation of updated remainder values ​​and updated remainder estimators, at least for the final sub-iteration.

[0018] In implementations where at least three partial iterations are performed within the same cycle to perform the square root operation for a given base r, the updated remainder estimate may also be computed in parallel with the updated remainders from one or more intermediate partial iterations between the first and last partial iterations.

[0019] The square root processing circuit comprises one or more instances of a replication circuit for a given radix n partial iteration, each instance of the replication circuit comprising two or more replication circuit units for determining two or more candidate output values ​​corresponding to different result digits that can be selected as the next radix n result digit by the digit selection circuit, in parallel with the selection of the next radix n result digit by the digit selection circuit, and a selection circuit for selecting one of several candidate output values ​​in response to the digit selection circuit indicating which of the different result digits will be selected as the next radix n result digit, the several candidate output values ​​comprising at least two or more candidate output values ​​generated by the two or more replication circuit units. This method can be faster in performance because it does not require waiting for the next radix n result digit to actually be selected by the digit selection circuit before starting the computation to generate candidate output values.

[0020] It should be noted that the number of candidate output values ​​available for selection by the selection circuit may be greater than the number of candidate output values ​​generated by two or more replica circuit units. For example, one of the result digits available for selection may be equal to 0, and in some cases, the candidate output value selected when the next result digit is 0 may be the same as the input value provided to the partial iteration, so it may not be necessary to explicitly calculate the candidate output value for result digit 0. Thus, the selection circuit can take as input candidate output values ​​that are not explicitly generated by one of the replica circuit units, as well as candidate output values ​​generated by two or more replica circuit units.

[0021] Providing a replication circuit unit to predictively calculate multiple candidate output values ​​before the next result digit is known may offer superior performance, but the number of replication circuit units required increases with increasing radix, potentially increasing circuit area costs and power consumption to support higher radix arithmetic.

[0022] One technique for limiting circuit area and power costs may be to provide at least one of two or more duplicate circuit units as a shared circuit unit shared between a positive result digit of a given magnitude and a negative result digit of the same given magnitude. The shared circuit unit is configured to output a shared candidate output value to a selection circuit on a shared signal path, which may select the shared candidate output value from the shared signal path when the next radix n result digit is either a positive or negative result digit of a given magnitude. This eliminates the need to provide two separate duplicate circuit units for each of the positive and negative result digits that share the same magnitude. This reduces the total number of duplicate circuit units required, thus saving circuit area and reducing power consumption.

[0023] For at least one instance of the replication circuit, a shared circuit unit that provides an output shared between positive and negative result digits of the same magnitude can select a value to be output as a shared candidate output value on the shared signal path, based on the sign of the previous remainder estimate. Thus, a common signal path is shared between two result digit values ​​of the same magnitude but different signs, but the actual numerical values ​​output on that shared signal path may differ depending on the sign of the previous remainder estimate.

[0024] For at least one instance of the replication circuit, the shared circuit unit may include a shared add-on circuit for determining shared candidate output values ​​for positive and negative result digits of a given magnitude. The technique of providing a shared circuit unit for generating shared candidate output values ​​for both positive and negative digits of the same magnitude may be particularly useful if the circuit unit includes an adder circuit, as adders are relatively expensive in terms of circuit area.

[0025] For a radix n partial iteration, it is usually expected that the number of candidate output values ​​available for selection by the selection circuit must be n+1. However, by sharing a shared circuit unit between positive and negative result digits of the same magnitude, the total number of candidate output values ​​available for selection by the selection circuit can be reduced to n / 2+1, which means that the number of duplicate circuit units provided can be reduced, and thus the circuit area can be significantly reduced.

[0026] Several instances of the replication circuit may exist within the square root processing circuit. Different parts of the square root processing circuit can each use this technique, with the replication circuit unit predictively determining candidate output values ​​for multiple possible result digits, and then, once the next result digit is selected, the correct candidate output value can be selected by the selection circuit.

[0027] For example, a remainder update circuit may comprise one such instance of a replication circuit. If the remainder update circuit uses a predictive replication and selection technique, the candidate output value selected by the selection circuit may be the updated remainder value of the candidate.

[0028] Similarly, a remainder estimator circuit may use this inferential replication and may include one of the instances of the replication circuit described above. If the remainder estimator circuit includes a replication circuit, the candidate output value may be the updated remainder estimator of the candidate.

[0029] Another part of the digit recurrence method may involve performing on-the-fly transformations. In the case of square root operations, the adjustment of the previous remainder to produce the updated remainder may depend not only on a remainder adjustment value (selected based on the next result digit) but also on a subroot value, which is a numerical value corresponding to the previously selected set of result digits. Since the result digit may be selected by a digit selection circuit as a signed digit, then an on-the-fly transformation circuit may be provided to transform the subroot value into a non-redundant representation so that the subroot value can be used by a remainder update circuit to adjust the previous remainder to produce the updated remainder. It is possible to perform on-the-fly transformations in a way that does not require addition, but can be done simply by concatenating the previous subroot value with some additional bits selected based on the latest radix n result digit, as described below.

[0030] Therefore, the on-the-fly transform circuit (for generating a subroot value that represents a numerical value corresponding to a previously selected series of radix n result digits in a non-redundant representation) may also include an instance of the replica circuit described above, and as a result, the replica circuit unit generates several candidate subroot values, and the candidate output values ​​available for selection by the select circuit include several candidate values ​​of the subroot value.

[0031] Therefore, regardless of which part of the square root processing circuit performs the replication, replication can help improve performance, and if implemented, sharing replication circuit units for positive and negative result digits of the same size can help reduce the overall circuit size.

[0032] In some implementations, the replicated circuit can be implemented using only one or a subset of the above components of the square root processing circuit, and the other components do not use the replicated technique, with the remainder update circuit, remainder estimation circuit, and on-the-fly transform circuit each providing an instance of the replicated circuit, which may result in maximum performance.

[0033] In general, when an iteration of a given base r is divided into several back-to-back or overlapping sub-iterations of base n within the same processing cycle, the value of r can correspond to the product of the respective values ​​of n for each sub-iteration used in one cycle.

[0034] In the specific example described below, r=64 and n=8 are set for each sub-iteration, such that each radix 64 iteration has two radix 8 sub-iterations. This approach can offer a good balance between performance (radix 64 means that 6 bits can be generated per processing cycle) and circuit area and timing complexity (using radix 8 for sub-iterations means that only two sub-iterations are required, which imposes lower timing pressure compared to implementations using three or more sub-iterations, but increasing the radix beyond 64 can make it impossible to manage circuit size while satisfying timing requirements). Therefore, r=64 and n=8 can be a particularly useful combination.

[0035] Nevertheless, other options are possible. For example, the 64-base iteration of the square root operation can be performed as three partial iterations, each with a base of 4 (since 64 = 4 × 4 × 4).

[0036] Performing each partial iteration with the same radix n can be useful because it is more efficient in terms of the overall circuit area and can be simpler in terms of design complexity, as each partial iteration uses the same radix.

[0037] Nevertheless, different sub-iterations within the same radix r iteration can use different radixes. For example, a radix 64 iteration of digit recurrence square root operation can be divided into one radix 4 sub-iteration, one radix 8 sub-iteration, and one radix 2 sub-iteration. Thus, it is not necessary for n to be equal for each sub-iteration.

[0038] The techniques described above can be implemented in square root processing circuits of different designs. For example, the square root processing circuit may be an iterative square root processing circuit, and the output signal path may feed the updated remainder and updated remainder estimate generated in the last radix n partial iteration from the output of the iterative square root processing circuit to the input of the same iterative square root processing circuit, to be used as the previous remainder and previous remainder estimate in the first radix n partial iteration of further radix r iterations of the square root operation. Thus, to perform the square root operation as a whole, multiple paths through the iterative square root processing circuit are executed over multiple processing cycles, and the output of the iterative square root processing circuit in one cycle is fed back as input to the same unit in subsequent cycles.

[0039] However, as will be explained in more detail below, the square root processing circuit may also be part of a pipelined square root processing unit that includes several square root iteration pipeline stages, each stage containing an instance of the square root processing circuit described above. In this case, the output signal path of a given pipeline stage can supply the updated remainder and updated remainder estimate generated in the last sub-iteration of base n of a given base r iteration from the output of the square root processing circuit in one square root iteration pipeline stage to the input of the square root processing circuit (a different instance of the square root processing circuit) in a subsequent square root iteration pipeline stage for processing of subsequent iterations of base r in the next processing cycle. This technique makes it possible to pipeline multiple square root operations with respect to each other, and as a result, while the previous square root operation is being processed in a later stage of the pipelined square root processing unit, the subsequent square root operation may be in an earlier pipeline stage where the previous base r iteration is being executed, which can help improve the overall throughput of the square root operations.

[0040] Combined division / square root processing circuit Commercial processor microarchitectures typically provide separate circuit logic for division and square root operations, so these operations are performed in completely separate circuit logic units, with no sharing of data paths used to calculate the division result compared to the data path used to calculate the square root result. This can make construction simpler because it does not require extra complexity in the square root operation to affect the timing of the division operation. However, it may be desirable to increase the radix used for division and square root operations to improve performance by enabling the calculation of division or square root results with more bits per cycle. For example, it is possible to calculate 6-bit results per cycle using radix 64 division or square root operations, which are not currently available in commercial processors. However, increasing the radix means that more complex circuitry is required compared to embodiments that require lower radix. Therefore, having separate division and square root processing circuits when operating at higher radix can increase circuit size and, consequently, processor power consumption.

[0041] The example described below provides a combined division / square root processing circuit for performing a given base 64 iteration of a base 64 division operation in response to a division instruction, and for performing a given base 64 iteration of a base 64 square root operation in response to a square root instruction. The combined division / square root processing circuit has a shared circuit for generating at least one output value for a given base 64 iteration on the same data path used for both the base 64 division and base 64 square root operations. For example, the at least one output value may include any one or more of the updated remainder value, selected result digit, updated remainder estimate, and / or on-the-fly transformed partial result value. By using a shared circuit where the same data path is used for the outputs of both the division and square root operations, the total amount of circuitry can be reduced compared to implementations with separate division and square root units. This is particularly useful for radix 64 arithmetic, given the increased circuit size required for radix 64 compared to lower radix arithmetic supported by commercially available processor microarchitectures.

[0042] A combined division / square root processing circuit can perform the same number of base 64 iterations per processing cycle for both base 64 division and base 64 square root operations. This can increase the degree to which circuitry can be shared between square root and division operations, helping to limit the overall circuit area of ​​the combined division / square root processing circuit.

[0043] For both base 64 division and base 64 square root operations, a combined division / square root processing circuit can perform a given base 64 iteration by performing one or more base m partial iterations in the same processing cycle, provided m ≤ 64.

[0044] In some examples, m=64, in which case the radix 64 iteration may be performed as a single unified operation that generates 6 bits of the next result digit at once, without splitting the radix 64 iteration into separate sub-iterations. While this technique may be faster, if the radix 64 iteration is performed as a single operation, the possible result digits can expand from -32 to +32, which may require additional circuit logic to accommodate a larger number of candidate result digits.

[0045] However, in some examples, since m < 64, a combined division / square root processing circuit can perform a given base 64 iteration by performing multiple base m partial iterations in the same processing cycle. For example, in the specific example shown below, m is equal to 8, so each base 64 iteration has two base 8 partial iterations. Another option is that m = 4, so that each base 64 iteration has three base 4 partial iterations per processing cycle. The partial iteration base m can take different values ​​between different partial iterations, as mentioned above for the example of the square root processing circuit, but it may be more efficient from a circuit implementation standpoint if m is the same in each partial iteration.

[0046] Therefore, the term “partial iteration of cardinal m” is used to refer to the entire iteration of cardinal 64 if there is no subdivision into multiple partial iterations of smaller cardinalities, or to the individual partial iterations of smaller cardinalities if such subdivision is performed.

[0047] There may be different parts of the combined division / square root processing circuit, which may function as the shared circuit described above.

[0048] In one example, the shared circuit comprises a shared digit selection circuit that, in a partial iteration of a given base m, selects the next base m digit of the division or square root result based on a comparison between the previous remainder estimate and a set of comparison constants. In implementations where m=64 and therefore the base 64 iteration is not divided into multiple partial iterations, the previous remainder estimate used for digit selection may come from the previous base 64 iteration. On the other hand, if m<64 such that the base 64 iteration is divided into multiple partial iterations of base m, then in the first partial iteration of a given base 64 iteration of base m, the previous remainder estimate may come from the last partial iteration of base m of the previous base 64 iteration, and in subsequent partial iterations of base m other than the first partial iteration of base m of the given base 64 iteration, the shared digit selection circuit may select the next base m digit based on the previous remainder estimate calculated in the previous partial iteration of base m of the given base 64 iteration.

[0049] Therefore, a shared digit selection circuit can be provided to save circuit area compared to separate circuits for selecting the result digits of division and square root operations, respectively. For example, the shared digit selection circuit may comprise the same set of comparator circuits used to perform comparisons between the previous remainder estimate and a comparison constant for both division and square root operations.

[0050] The comparator circuit used when performing both division and square root operations may be the same, but the shared digit selection circuit may use different sets of comparison constants for base 64 division and base 64 square root operations, respectively. The set of comparison constants can be selected based on the type of operation.

[0051] However, one problem is that the comparison constant for division may not be the same size as the comparison constant for square root. Error analysis has shown that division may not require as many bits in the comparison constant as the comparison constant used for square root to provide sufficiently accurate digit selection. Therefore, it can be expected that the division comparison constant will have fewer bits than the square root comparison constant. However, to facilitate circuit sharing, the comparison constant compared to the remainder estimate before a base 64 division operation may have at least one least significant bit set to 0 to pad it to the same width as the comparison constant compared to the remainder estimate before a base 64 square root operation. By placing at least one 0 at the least significant bit position, the comparison constant for division is extended to the same bit width as that used for square root operations, which allows the same comparator and the same data path for the remainder estimate in the digit selection circuit to be used for both square root and division operations, thus reducing circuit area.

[0052] Another example of a shared circuit may be a shared remainder update circuit that adjusts the previous remainder value based on a remainder adjustment value in a partial iteration of a given base m in order to generate an updated remainder value in a redundant representation. By using a redundant representation, remainder updates can be performed using carry-delayed addition to avoid the increased delay of carry-propagated addition. Thus, the shared circuit may comprise a shared carry-delayed adder circuit that performs carry-delayed addition to generate an updated remainder value. Since the data path of the remainder value is shared between the division and square root operations, this eliminates the need for two separate carry-delayed adders for the division and square root operations, respectively.

[0053] However, the remainder adjustment value may differ for division operations compared to square root operations. Therefore, a shared remainder update circuit may include a selection circuit that selects, as the remainder adjustment value, a value derived from the divisor when performing a partial iteration of a given base m as part of a base 64 division operation, and a value derived from the partial root value depending on the previously selected root digit of base m when performing a partial iteration of a given base m as part of a base 64 square root operation. Thus, with a small amount of additional logic in the selection circuit, a shared data path can be used for both square root and division operations when generating remainder updates.

[0054] Another example of a shared circuit may be a shared remainder estimator for generating an updated remainder estimator that shows a portion of the updated remainder values ​​generated in a redundant representation in a partial iteration of a base 64 division operation or a base 64 square root operation of a given base m, in a partial iteration of a base 64 division operation. For example, the shared remainder estimator may include a carry-propagated adder for performing carry-propagated adder to generate the non-redundant estimator, so that by sharing it between the division and square root operations, there is no need to have two separate carry-propagated adders.

[0055] In implementations where m is less than 64, in the last sub-iteration of radix m of a given radix 64 iteration, the shared remainder estimator can generate an updated remainder estimator in parallel with the shared remainder update circuit that generates the updated remainder value. This improves performance by reducing the latency of the critical timing path, for the same reasons as described above for the square root processing circuit.

[0056] Another example of shared circuitry is an on-the-fly transform circuit that, in a partial iteration of a given radix m, may be shared to perform an on-the-fly transform to generate a partial result value in a non-redundant representation. Again, on-the-fly transform circuits can sometimes require relatively complex hardware circuit logic, and therefore, avoiding duplicating it for division and square root operations can save a significant amount of circuit area.

[0057] However, one problem is that, in a typical scheme, the on-the-fly transform circuit behaves differently for division compared to square root. The on-the-fly transform circuit can generate an on-the-fly transformed value that represents the partial result corresponding to the sequence of result digits selected in that cycle and any previous cycle, by inserting a value selected based on the next result digit into the partial result value. However, in a typical scheme, the position where the next digit is inserted into the partial result value during the on-the-fly transform differs between division and square root, as division is performed by inserting the value derived from the next digit into the least significant bit position with a left shift to shift all previously inserted bits up to higher bit positions. In contrast, due to the fact that the partial result value affects digit selection and remainder update operations in square root operations (and therefore it is more convenient if, in each processing cycle, the most significant bit of the partial root result value remains in a consistent bit position within the stored representation of the partial result), in the case of square root operations, the value derived from the next result digit is inserted into a variable bit position within the partial result using a mask used to represent the position within the partial result value where the next square root result digit will be inserted. This mask can be adjusted between iterations or partial iterations to gradually shift the position where the next result digit is inserted toward the lower bits of the partial result value.

[0058] Given these contrasting methods of preserving partial result values, one might think it would be difficult to have shared circuit logic for on-the-fly conversion circuits.

[0059] However, the inventors have recognized that it is possible to provide a shared on-the-fly transform circuit. In a given radix n partial iteration, the shared on-the-fly transform circuit selects a position for inserting the next digit into the partial result value based on a mask value, for both radix 64 division and radix 64 square root operations. Thus, for division operations, the shared on-the-fly transform circuit behaves differently from conventional methods, using a mask for radix 64 division operations to select a position for inserting the next digit into the partial result value for the division operation, instead of shifting all digits up and inserting the next digit into the least significant bit position. This allows the on-the-fly transform for division operations to mirror the transform for square root operations, enabling the use of shared circuit logic and shared data paths. This helps improve overall circuit area efficiency.

[0060] Similar to the various circuit units of the square root processing circuit described above, the shared circuit in the shared division / square root circuit may comprise one or more instances of a replica circuit, each instance of which comprises two or more replica circuit units for determining two or more candidate output values ​​corresponding to different digits that can be selected as the next radix m digit, in parallel with the selection of the next radix m digit of the division or square root result, and a selection circuit for selecting one of several candidate output values ​​in response to an indication of which of the different digits has been selected as the next radix m digit, the several candidate output values ​​comprising at least two or more candidate output values ​​generated by the two or more replica circuit units. This helps to improve performance for the same reasons described above for the square root example. Again, in order to reduce the total number of replica circuit units required to process the partial iteration of radix m, at least one of the replica circuit units may be a shared circuit unit shared between positive and negative digits of equal magnitude. The various components of the combined division / square root circuit can use any one or more of such replication circuits, such as remainder update circuits, remainder estimation circuits, and on-the-fly transformation circuits.

[0061] Similar to the square root processing circuit described above, in the case of a combined division / square root processing circuit, this can be implemented as an iterative division / square root processing circuit in which the output of one radix 64 iteration is input to the same iterative division / square root processing circuit for use in further radix 64 iterations of division or square root operations, or as a pipelined division / square root processing unit having several pipelined stages, each having an instance of the combined division / square root processing circuit, with the signal path providing the output generated in one stage as input to the next stage in the pipeline.

[0062] Division / Square Root Pipeline Many programs typically require arithmetic operations to be performed on operands represented in floating-point format. The IEEE-754 technical standard defines various forms for floating-point representation, such as half-precision (HP), single-precision (SP), and double-precision (DP) (other forms are also available). The specific floating-point precision used for operands and results of division or square root operations can control the number of bits that need to be generated for the result, which can affect the number of iterations required for digit recurrence division or square root operations.

[0063] Traditionally, circuit units for performing digit recurrence division or square root operations that can produce results with floating-point precision are implemented as iterative circuit units. Therefore, the circuit logic provided in hardware corresponds to a single iteration of the digit recurrence division or square root operation, and the output of one iteration is fed back as input to the very same circuit logic unit that performed the previous iteration, ready for that same circuit unit to perform the next iteration.

[0064] In contrast, the example described below provides a division / square root pipeline that includes several division / square root iterative pipeline stages, each capable of performing a separate iteration of digit recurrence division or square root operation. A signal path is provided to supply the output generated by one pipeline stage in a single iteration as input to the subsequent pipeline stages of the division / square root pipeline, in order to perform subsequent iterations of digit recurrence division or square root operation. The division / square root pipeline can perform digit recurrence division or square root operations on floating-point operands to produce floating-point results.

[0065] Therefore, while supporting the precision level required for floating-point format, division or square root operations are performed in a pipelined manner rather than as iterative units. This means that for the processing of a single division or square root operation, each iteration is executed by a different pipeline stage, with the output from one pipeline stage being fed into the next pipeline stage, and so on, allowing the operation to move through the pipeline until it reaches its end and the result to be output.

[0066] This approach can be considered contrary to the straight pipe approach, and while instruction pipeline is generally known, the complexity of division / square root operations is far greater than other forms of arithmetic, meaning that the overall circuit area of ​​a single circuit unit to perform a single iteration of digit recursive division or square root operations is relatively large. Therefore, one might think that extending the iterative unit into a pipeline containing enough stages to produce the result precision required for floating-point operations would increase the overall circuit area required for the division / square root unit by a factor corresponding to the maximum number of iterations required for the division or square root operation.

[0067] However, the inventors have recognized that, in practice, a processor microarchitecture having an iterative division / square root processing circuit can actually provide a large number of parallel division / square root units to increase the total available bandwidth, thereby allowing for, for example, multiple division function units and / or multiple square root function units to be present, and allowing two or more division or square root operations to be processed simultaneously. In a pipelined manner, the need to duplicate the entire division / square root unit is eliminated because the division / square root pipeline can process multiple operations in a pipelined manner, where the division / square root pipeline performs the second digit recurrence division or square root operation in parallel with the division / square root iterative pipeline stage that performs the iterations after the first digit recurrence division or square root operation, and the division / square root iterative pipeline stage that performs the iterations after the first digit recurrence division or square root operation in parallel with the division / square root iterative pipeline stage that performs the iterations before the second digit recurrence division or square root operation.

[0068] Therefore, while pipelines appear to significantly increase circuit logic, in reality, the additional circuitry may not be so significant compared to commercially available processors with multiple parallel division / square root units, and various techniques described in this application for reducing circuit area can be applied, particularly by using shared data paths for division and square root operations and reducing the number of duplicate circuit units by sharing the same duplicate circuit unit for positive and negative digits of the same size as previously described.

[0069] Therefore, the entire pipeline can potentially compete in terms of circuit area and may help improve performance because, by using pipelined processing of operations, the pipelined approach can avoid the iterative circuit unit being blocked for the total number of cycles used to perform digit recurrence division or square root operations, and thus can potentially enable higher throughput by scheduling consecutive division or square root operations with fewer cycles between them.

[0070] Just as a division / square root pipeline can perform either division or square root operations, but not both, a pipeline can perform either division or square root operations, but only one of them.

[0071] However, pipelines can be particularly useful when combined division / square root processing circuits are provided with a shared data path used for both operations. Thus, each division / square root iterative pipeline stage comprises a combined division / square root processing circuit for performing a given iteration of a digit recursive division operation in response to a division instruction and a given iteration of a digit recursive square root operation in response to a square root instruction. The combined division / square root processing circuit comprises a shared circuit for generating at least one output value on the same data path used for both a given iteration of the digit recursive division operation and a given iteration of the digit recursive square root operation. Providing a combined division / square root processing circuit helps limit the overall area cost of extending a single iteration unit into a pipeline (since the area budget previously provided for separate division and square root units is available for the pipeline implementation), and helps pipelines compete with current microarchitectures in terms of circuit area. As mentioned earlier, when a combinational division / square root circuit is used, it can be useful for the division / square root pipeline to perform the same number of iterations per processing cycle on the same base for both digit recursive division and digit recursive square root operations, as this facilitates greater sharing of the shared circuit unit.

[0072] Given a given result precision, the division / square root pipeline can handle digit recursive division operations in the same number of processing cycles as digit recursive square root operations. This helps simplify the control of circuit timing within the pipeline and facilitates the sharing of common circuit logic between division and square root operations.

[0073] A division / square root pipeline can support various floating-point formats for the operand(s) input to a division or square root operation and the floating-point result generated by the division or square root operation. For example, the operand(s) and result may be half-precision (HP), single-precision (SP), or double-precision (DP) floating-point values. A division / square root pipeline can support at least one of these formats, or it may support other types of floating-point formats. However, it is particularly useful when the division / square root pipeline supports at least one of SP and DP floating-point values. Since programs written in DP floating-point precision can be particularly common, a division / square root pipeline that supports operations where the result is a DP floating-point representation may be useful in some cases. The pipeline stage of the division / square root pipeline may be used to process the mantissa of the floating-point operand and generate the mantissa of the floating-point result. Separate circuit logic may exist for processing the exponent of the floating-point value. The exponential processing logic may be simpler than the logic for generating the mantissa, and any known technique for generating the exponent of a division / square root result can be used.

[0074] In some cases, the division / square root pipeline can support at least two different result accuracies for digit recurrence division or square root operations. For example, the division / square root pipeline can support any two or more of the HP, SP, and DP floating-point values.

[0075] For lower-precision floating-point results, the division / square root pipeline can perform the division or square root operation in fewer processing cycles than when producing higher-precision results (because fewer bits need to be generated for the result, requiring fewer iterations of the digit recurrence method). The device may have a control circuit that controls the division / square root pipeline to bypass at least one division / square root iteration pipeline stage that is used to perform at least one iteration of the digit recurrence division or square root operation when producing higher-precision results, when performing the digit recurrence division or square root operation to produce lower-precision results. This improves performance by making the result of the operation available more quickly when fewer bits need to be computed.

[0076] However, allowing some stages of the pipeline to be bypassed in this way could create a potential collision if low-precision calculations are performed after high-precision calculations in a pipelined system, when both calculations reach a post-processing stage where post-processing can be performed on the output of the final iteration of a digit recursive division or square root calculation. For example, the post-processing stage could perform rounding of the result of the division or square root calculation to provide a rounded floating-point result, and / or perform non-normalized (partially normalized) result processing by right-shifting to produce a result in accordance with IEEE standards (if the result of the division or square root calculation is less than the smallest number that can be represented as a normal floating-point number). To ensure that post-processing operations receive only the output of the last iteration of a single operation per cycle, the control circuit can prevent a predetermined number of cycles from starting a lower-precision digit recursive division / square root operation, which is performed to produce a lower-precision result, after a higher-precision digit recursive division / square root operation, which is performed to produce a higher-precision result. This predetermined number of cycles corresponds to the difference between the number of cycles required to reach at least one post-processing stage for the higher-precision digit recursive division / square root operation and the number of cycles required to reach at least one post-processing stage for the lower-precision digit recursive division / square root operation. Thus, depending on the difference in precision between the preceding high-precision operation and the subsequent low-precision operation, there may be a certain number of cycles in which the start of a low-precision operation after a high-precision operation is prohibited to avoid collisions. The predetermined number of cycles may differ for pairs of different precision forms.

[0077] Each division / square root iteration pipeline stage may include a digit selection circuit for selecting the next result digit for a partial result value of a digit recurrence division or square root operation based on a comparison between the previous remainder and a set of comparison constants, and a remainder update circuit updates the previous remainder based on the remainder adjustment value and the next result digit selected by the digit selection circuit. Each pipeline stage may also have other elements, such as a remainder estimate circuit, for generating non-redundant estimates of some of the updated remainder values ​​generated by the remainder update circuit in a redundant representation. Each pipeline stage may also have an on-the-fly transform circuit for maintaining on the fly non-redundant versions of partial result values ​​corresponding to a set of previously selected result digits from all preceding iterations of the digit recurrence method.

[0078] All division / square root iterative pipeline stages in a pipeline can use the same set of comparison constants for each iteration performed within the same digit recursive division or square root operation. While the comparison constants may differ from operation to operation, the same set of comparison constants can be used within each iteration of the same operation. Therefore, a division / square root pipeline can perform a table lookup in a preprocessing stage of the division / square root pipeline to obtain the set of comparison constants before the first division / square root iterative pipeline stage of the division / square root pipeline, and the set of comparison constants is passed from stage to stage to avoid repeating the table lookup in each division / square root iterative pipeline stage within the same digit recursive division or square root operation. This technique reduces the overall amount of circuit logic required at each stage by eliminating the need to perform a table lookup at each stage, thus shortening the timing for each individual pipeline stage. A set of flip-flops may exist at each pipeline stage, which simply take the comparison constants received from the previous pipeline stage without needing to update their own. This significantly simplifies the pipeline and reduces the overall circuit area.

[0079] This approach can be surprising because it might seem that the comparison constants for digit recurrence division or square root operations should not be the same for each iteration, and that a different set of comparison constants may be required compared to the constants used in later stages, especially as in the first iteration of a typical division / square root operation. However, in the example described below, the division / square root pipeline includes at least one preprocessing stage to perform operand preprocessing before the first division / square root iteration pipeline stage of the division / square root pipeline, and the operand preprocessing includes the selection of at least one initial result digit for the result of the digit recurrence division or square root operation. By selecting at least one initial result digit for the result of the division or square root operation in the preprocessing stage so that the initial result digit is not selected within the body of the pipeline, this means that different sets of selection criteria can be used for the result digit to avoid requiring different comparison constants in different stages of the main iteration portion of the pipeline. This means that each of the remaining division / square root iteration pipeline stages can improve circuit timing and reduce circuit area as described above by using the same set of comparison constants within the same division or square root operation.

[0080] However, one problem with implementations of the division / square root pipeline that support both digit recursive division and digit recursive square root operations (where a combination of division / square root circuits is provided as described above) is that the number of initial digits requiring a different set of comparison constants compared to subsequent iterations can differ between division and square root operations. For example, error analysis has shown that if radix 8 is used for digit selection in a given iteration or partial iteration to obtain digit selection with sufficient precision for square root operations, the selection of the first two square root digits may use different comparison constants than the selection of the remaining square root digits. If the radix used is not 8, the number of initial root digits selected using different comparison constants for the remaining iterations may be a number other than 2. Nevertheless, regardless of the radix, in general, square root operations can use different comparison constants to select a particular number of initial root digits and then use the same set of comparison constants for subsequent iterations or partial iterations after those initial root digits have been selected. In contrast, division operations can use the same comparison constants for selecting all resulting digits (regardless of the radix used). However, for performance reasons, it may be desirable to select at least one result digit during the preprocessing stage to reduce the number of subsequent pipeline stages required for the division operation and thus reduce latency. For example, in the radix 8 example described below, the first division digit may be selected in the preprocessing stage.

[0081] Therefore, the number of initial digits selected in the preprocessing stage may differ for square root and division operations. For example, at least one preprocessing stage may generate more initial result digits for a digit recursive square root operation than for a digit recursive division operation. While this obviously could introduce some asymmetry between the two operations, in practice, this means that, in the case of square root operations, the comparison constants for the remaining stages can be easily latched from one stage to the next without requiring separate table lookups at each pipeline stage, thus greatly helping to reduce the overall circuit area and improve pipeline performance.

[0082] However, since square root operations generate more initial result digits than division operations in at least one preprocessing stage, this means that fewer remaining iterations are required after the preprocessing stage of a square root operation compared to a division operation, even when producing results of the same precision. Therefore, the results of a square root operation may be available in an earlier division / square root iteration pipeline stage compared to a division operation. To enable the use of a shared pipeline, the control circuit can control the division / square root pipeline to cause at least one division / square root iteration pipeline stage, which is used to perform at least one iteration when a digit recursive division operation is performed, and when performing a digit recursive square root operation, some bits of the result output are skipped or discarded, either completely or partially. In some cases, an entire pipeline stage of the pipeline may be skipped for a square root operation, while in other cases, depending on the floating-point precision used and the radix used for the digit recursive operation, only some of the bits generated in a given pipeline stage may need to be discarded. For example, as in some of the examples above, if a given iteration of a digit recurrence method is divided into multiple sub-iterations of smaller radixes, it may be possible to skip only the individual sub-iterations within a given division / square root iteration pipeline stage for some result accuracies of the square root operation, rather than skipping the entire stage. Also, in some cases, if the total number of bits required for a given result accuracy of the square root operation is not an exact multiple of the number of bits generated per iteration or sub-iteration, result truncation can be achieved by fully executing the given iteration or sub-iteration, but discarding some bits of the result if other bits of the result digit generated in the last executed iteration or sub-iteration are still needed.

[0083] This means that, considering the main body of the pipeline, the result of a square root operation may be available earlier than the result of a division operation, but the total number of cycles required for both operations can be the same. For example, even if the result of a square root operation is available earlier, there can still be at least one cycle before the value is passed to the next cycle unchanged, allowing the overall timing of the operation to reflect the timing of the division operation. This makes scheduling post-processing operations easier, for example, because they can occur at the same time regardless of the operation being performed.

[0084] Another complexity when using combined division / square root data paths in a pipeline lies in maintaining the sub-result values ​​that provide numerical representations of the previously selected set of result digits. When a shared data path should be used, it may be desirable that, when performing a given iteration of the digit recurrence method at a given pipeline stage of the pipeline, the next result digit can be inserted into the sub-result value at the same bit position for both division and square root operations. However, if the preprocessing stage generates a different number of initial result digits for division and square root operations, this can complicate the use of shared circuit logic in the remaining pipeline stages, as the position where the next result digit is inserted in a given iteration may differ from iteration to iteration.

[0085] Therefore, when performing a digit recurrence division operation, at least one preprocessing stage may provide a first division / square root iterative pipeline stage with a partial result value in which selected bit positions are set to dummy bit values, where those selected bit positions correspond to bit positions in which at least one preprocessing stage inserts at least one additional result digit that is not generated for the digit recurrence division operation when performing the digit recurrence square root operation. This allows a given division / square root iterative pipeline stage of the division / square root pipeline to insert the next result digit into the partial result value at the same bit positions for both digit recurrence division and digit recurrence square root operations. The division / square root pipeline may include a postprocessing stage for removing dummy bit values ​​from the final result value when performing a digit recurrence division operation.

[0086] This recognizes that inserting additional dummy bit values ​​into the partial result for a division operation does not affect the overall result of the division operation because the partial result value is not used in the remainder update or digit selection operation in the division operation. The partial result value is used to control the remainder update and digit selection operation only for square root operations. In the case of division operations, it is not a problem that the partial result value temporarily contains some dummy bit values ​​that will be removed in a post-processing stage, as the partial result value is maintained "on the fly" simply to improve performance by eliminating the need to convert the redundant representation of the result to a non-redundant form at the end of the pipeline. Including dummy bit values ​​in the partial result value used for division operations allows the insertion of the next result digit to be in the same position for both operations, improving the sharing of circuit logic for both operations.

[0087] The division / square root pipeline described above can be used for digit recurrence division or square root operations with any base.

[0088] However, since the extra number of bits of the result generated per cycle in a radix 64 operation, compared to a lower radix, helps reduce the total number of pipeline stages required for the pipeline, using a division / square root pipeline can be particularly useful for radix 64 digit recurrence division or square root operations, and as a result, the pipeline can become competitive with respect to circuit area compared to an iterative implementation.

[0089] In one example, each division / square root iterative pipeline stage is configured to perform each radix r iteration of a radix r digit recurrence division or square root operation by performing multiple radix n partial iterations in the same processing cycle, where n < r. By splitting a higher radix iteration into multiple lower radix partial iterations, the amount of circuitry in each pipeline stage is reduced, and as a result, the overall circuit area of the pipeline can compete with current iterative implementations while improving performance. In a specific example, r = 64 and n = 8, but more generally, a radix r iteration can be split into different combinations of lower radix partial iterations as described above for the example of the square root processing circuit.

[0090] On-the-fly conversion A data processing apparatus for converting a plurality of signed digits representing an input value into a redundant representation, comprising, in each of a plurality of iterations, a receiving circuit that receives signed digits from the plurality of signed digits and previous intermediate data from a previous iteration, a concatenating circuit that performs a concatenation of bits corresponding to the signed digits and bits of the previous intermediate data to generate updated intermediate data, and an output circuit that provides the updated intermediate data as the previous intermediate data for a next iteration, wherein the previous intermediate data includes S3[i] in a non-redundant representation, which is at least a part of the input value multiplied by 3 in a non-redundant representation.

[0091] In these examples, each digit is signed. Thus, the input value (which can be positive or negative) consists of individual digits, each individually signed. In this way, for example, the first digit of the input value could be positive, and the second digit of the input value could be negative. This can be used to provide a representation known as a redundant representation, where a pair of words are used to represent the input value. This is in contrast to a non-redundant representation, where a number is represented using a single word. Both non-redundant and redundant representations are optimized for specific types of operations, and therefore conversions between different representations can be useful. The conversion is performed on the fly as each digit of the input value is received, thereby avoiding the large latency that could occur if all digits were converted at once after all digits have been received. The conversion process is achieved using bit concatenation, which can be performed quickly. The bits to be concatenated are derived from signed digits. A set of intermediate data is maintained between iterations and updated in each iteration. The concatenation performed depends on the newly received current digit. In particular, the intermediate data includes S3[i], which is obtained by multiplying S[i] (partial result) by 3. The value of S3[i] is achieved without simply multiplying S[i] by 3, which is not only energy-intensive but also too time-consuming to keep pace with the arrival of new signed digits. Note that although the term "iteration" is used here, the iteration being referred to can be the aforementioned "partial iteration".

[0092] In some examples, the previous intermediate data includes S3[i-1]. In these examples, S3[i-1], which is the value of S3 from the previous iteration, is also maintained in the intermediate data. This value does not need to be calculated and can be carried over from the previous iteration. By providing such data, it is possible to adjust when carries occur during the transformation process.

[0093] In some examples, the preceding intermediate data includes S3M[i], which is a non-redundant representation of the input values ​​multiplied by 3 and minus 1, at least a portion of the input values. In other words, S3M[i] = (S[i] × 3) - 1. The value of SM3[i] is equivalent to the value of S3[i] minus 1.

[0094] In some examples, the previous intermediate data includes S3M[i-1]. In these examples, the value of S3M from the previous iteration is also maintained in the intermediate data. This value does not need to be calculated and can be carried over from the previous iteration. By providing such data, it is possible to adjust when carries occur during the transformation process.

[0095] In some examples, the concatenation performed by the concatenation circuit includes concatenation to each of S3[i] and S3M[i] to generate updated intermediate data containing S3[i+1] and S3M[i+1]. Thus, each of the four values ​​has a concatenation performed in each iteration (or partial iteration). The concatenation can differ for each of the four values.

[0096] In some examples, the bit corresponding to the unsigned digit is concatenated to one of S3[i] and S3M[i] to generate S3[i+1], and the other of S3[i] and S3M[i] generates S3M[i]. One of S3[i] and S3M[i] is determined based on whether the unsigned digit is greater than or less than 0. In these examples, whether the unsigned digit is greater than 0, 0, or less than 0 affects whether S3[i] or S3M[i] is used to generate S3[i+1], and the other of S3[i] and S3M[i] is used to generate S3M[i+1].

[0097] In some examples, the data processing device includes adjustment circuitry configured to perform selective adjustment on at least one of S3[i] and S3M[i] before concatenation, based on the magnitude of the signed digit and whether the signed digit is positive or negative. Selective adjustment can be used, for example, to achieve carry between columns of output values.

[0098] In some cases, selective adjustment is performed when the magnitude of the signed digit multiplied by 3 exceeds the base to which the signed digit is represented. Selective adjustment can be used to handle situations where the concatenated digit multiplied by 3 is greater than the base being used in the conversion, and therefore the digit needs to be incremented or decremented elsewhere. For example, if we have a partial result S[i]=512, as with base 10, and it is desirable to add a digit to this number (thousands) 6, this can be done to achieve the number S[i+1]=6512. However, if we maintain S3[i]=1536, and it is desirable to add a digit to this number (thousands) 6, 3 * We need to add 6 = 18. However, since the base is 10 and 18 is greater than 10, this cannot be done by simply changing the position. Instead, we add 8 to the number of thousands to get 9536, and then carry "1" as the number of 10,000 to get 19536.

[0099] In some examples, data processing devices are configured to convert multiple signed digits representing input values ​​in redundant representations without using an adder. In particular, the value of S3M[i] is not derived simply by taking S3[i] and subtracting 1 (e.g., using an adder). Instead, it is possible to determine these numbers with lower latency than would be achieved by using an adder to perform the subtraction of 1 by calculating these values ​​using concatenation over i iterations (concatenating different numbers for each of S3[i] and SM3[i]).

[0100] In some examples, a data processing unit includes a digit recurrence circuit for performing a digit recurrence operation to generate multiple signed digits, where in each of multiple iterations one of multiple signed digits is provided to a receiving circuit. The digit recurrence circuit can be used to provide a set of digits that make up the input value, and a subset of the digits is provided in iterations (or partial iterations), e.g., each clock cycle.

[0101] In some examples, digit recurrence circuits are configured to operate in square root mode, where the digit recurrence operation is a square root operation. The digit recurrence algorithm for calculating the square root performs multiplication by a subroot S, the multiplication depending on the digit being added. Since the subroot S changes in each iteration, this multiplication is performed in each iteration. Multiplying by 0 always results in 0. Multiplying by 1 is simply the identity function. On the other hand, multiplication by powers of 2 (e.g., 2 or 4) can be performed by performing bit shifts. Similarly, multiplication by -1, -2, and -4 can be performed by negate the multiplications of 1, 2, and 4, respectively. However, multiplication by 3 is significantly more complex. A multiplication circuit that performs an actual multiplication by 3 may require several processor cycles that are too slow. Even the addition of X and 2X to determine 3X requires additional circuitry, which may also be too time-consuming to perform. Therefore, square root digit recurrence can be performed efficiently by maintaining the value of S3 achieved through concatenation.

[0102] In some examples, a digit recurrence circuit is configured to operate in division mode, where the digit recurrence operation is a division operation, and the previous intermediate data includes S[i] which is at least a portion of the input value in its non-redundant representation and SM[i] which is at least a portion of the input value in its non-redundant representation minus 1, and after multiple iterations, the output circuit is further configured to output S[i], so the same data processing device that performs the input-to-output conversion can be used for both square root and division operations. The calculation may also include generating S[i] which is at least a portion of the input value converted to its non-redundant representation, as well as SM[i] which is that value minus 1.

[0103] In some examples, the coupling circuit is configured to suppress the generation of S3[i] in division mode. As explained earlier, the value of S3 (and, more broadly, S3M) is particularly relevant when performing square root digit recurrence division. Furthermore, when performing digit recurrence division, it is not necessary to multiply by the subroot in each iteration, so the generation of S3 and S3M is unnecessary. Therefore, by suppressing the generation of S3 and S3M in division mode, power consumption can be reduced.

[0104] In some cases, digit recurrence operations have a base of at least 8. For a base of at least 8, the available digits include at least one, if not both, +3 and -3. Therefore, during square root digit recurrence algorithms, it may be necessary to multiply the subroot by either 3 or -3 depending on the latest digit. As mentioned earlier, multiplication by 3 can be time-consuming, so maintaining S3 and S3M via concatenation allows for efficient execution of square root digit recurrence for base 8 while satisfying circuit timing constraints.

[0105] In some examples, the possible values ​​of a signed digit include at least one of +3 and -3. As mentioned earlier, the use of signed digits may require multiplication by 3, which is more difficult to perform than multiplication with powers of 2.

[0106] Selection constant In some examples, a data processing device is provided for performing a digit recurrence operation on an input value, comprising: a receiving circuit configured to receive the remainder of a previous iteration of the digit recurrence operation; a comparing circuit configured to perform a comparison between each of a plurality of selection constants associated with the available digits of the next digit of the result of the digit recurrence operation and the most significant bit of the remainder of a previous iteration of the digit recurrence operation, and outputting the next digit of the result of the digit recurrence operation based on the comparison, each of which selection constants is associated with one of the available digits and an input parameter; and a storage circuit configured to store a subset of the selection constants, the subset of selection constants being associated with digits excluded from the available digits, and excluding the selection constants excluded from the selection constants.

[0107] During the digit recurrence process, a comparison is made between the most significant bit of the remainder of the previous iteration and several selection constants to determine the next digit of the digit iteration, i.e., the next output digit. The number of selection constants corresponds to the product of the number of possible values ​​of the most significant bit of the remainder and the number of possible values ​​that the output digit may have. For example, if six most significant bits of the remainder are considered and there are eight possible values ​​for each output digit, the selection constant table will hold 8 × 32 = 256 values. Each value may also occupy several bits. Furthermore, usually multiple tables are required to accommodate both square root digit recurrence and division digit recurrence. Therefore, the number of values ​​stored is large. In the example above, at least some of the required selection constants are not stored. That is, for the range of supported digit recurrence operations (based on the radix and number of most significant bits considered), at least some of the selection constants required for digit selection processing are not stored anywhere in the data processing unit. This reduces the amount of memory space required. This results in smaller and lower-power circuits.

[0108] In some examples, the data processing unit includes a conversion circuit configured to generate selection constants that have been excluded from the selection constants stored in the memory circuit. In these embodiments, missing or omitted selection constants that are not stored in the data processing unit are instead inferred or generated from other selection constants stored in the data processing unit.

[0109] In some examples, the conversion circuit is configured to generate the selection constants to be excluded by performing a selective inversion on the sign of one of the selection constants stored in the memory circuit. In these embodiments, some of the omitted selection constants may be generated by taking another selection constant and inverting its sign. Since the sign inversion of a number (e.g., by taking two's complement) can be performed efficiently, it does not need to affect the time it takes to perform the selection operation.

[0110] In some examples, one of the selection constants is associated with the same input parameter and a different digit among those available as excluded selection constants. Thus, the two columns of the selection constant table can be "merged". That is, for a given set of the most significant bits of the remainder value, the selection constants for two different digits are the same (the sign changes according to the number from which the selection constant is generated). For example, the selection constant for remainder bit 0.100010 can be "2" for possible output digits +4 and -3. However, for digit +4, the selection constant can be negative (-2), and for digit -3, the selection constant can be negative (+2). Thus, these two columns can be merged into one using a rule regarding whether the constant is positive or negative.

[0111] In some examples, the memory circuit is configured to store an exception flag for a selection constant, indicating whether a selective inversion should be performed to generate a selection constant that is excluded. In these examples, whether or not to invert depends on the value of the exception flag. Inversion may also depend on other factors, for example, depending on the digit from which the selection constant is being generated. For example, considering the above example for the remainder bit 0.100010, the selection constant could be positive (+2) for one digit (+4) and negative (-2) for another digit (-3). However, the exception flag overrides this (so that both digits have the same selection constant) or inverts it (-2 for digit +4, and +2 for digit +3).

[0112] In some examples, the digit recurrence operation is the square root digit recurrence operation. The input parameter is the subroot.

[0113] In some examples, the digit recurrence operation is a division digit recurrence operation, where the input parameter is the divisor.

[0114] In some examples, in division mode, the digit recurrence operation is a division-digit recurrence operation, and the input parameter is the divisor; in square root mode, the digit recurrence operation is a square root-digit recurrence operation, and the input parameter is the subroot. Therefore, in these examples, depending on the operation mode, a device can be used that performs both division-digit recurrence and square root-digit recurrence.

[0115] In some examples, in division mode, the digit recurrence operation is a division-digit recurrence operation, and the input parameter is the divisor. In square root mode, the digit recurrence operation is a square root-digit recurrence operation, and the input parameter is the subroot, with each selection constant being either a division-digit recurrence operation selection constant or a square root-digit digit recurrence operation selection constant. Such a data processing device can perform both division and square root digit recurrence, but the selection constants stored are specific to one of these two operation modes (division or square root). By storing selection constants specific to only one of the two operation modes, the storage requirements of the data processing device can be reduced.

[0116] In some examples, each of the selection constants is a division-digit recurrence operation selection constant. This does not mean that all selection constants for division-digit recurrence are stored, but simply that the stored constants are division-digit recurrence selection constants that can be used as part of the process of generating square root-digit recurrence selection constants.

[0117] In some examples, the conversion circuit is configured to generate an exclusion selection constant in the division operation mode by performing a selective sign inversion of one of the division digit recurrence selection constants. That is, one of the division digit recurrence constants is used and inverted based on some criterion (e.g., the value of the digit to which the constant is associated).

[0118] In some examples, the conversion circuit is configured to generate a selection constant to be excluded in the square root mode operation by referencing one of the division digit recurrence operation selection constants.

[0119] In some examples, the memory circuit is configured to store multiple mappings between the excluded selection constants in square root operation mode and one of the division digit recurrence operation selection constants. The mappings are used to indicate which division digit recurrence operation selection constant to use as the basis for creating the square root digit recurrence operation selection constant, and / or how to modify one of the division digit recurrence operation selection constants to generate the corresponding square root digit recurrence operation selection constant.

[0120] In some examples, the memory circuit is configured to store exception flags for a selection constant, indicating whether selective inversion should occur to generate an excluded selection constant. The exception flags may be part of (or stored as part of a larger value) a set of flags indicating the circumstances under which inversion occurs to generate an excluded selection constant.

[0121] In some examples, digit recurrence operations use base 8. For instance, the available digits may be limited to {-4,-3,-2,-1,0,1,2,3,4}.

[0122] Examples of data processing devices Figure 1 shows an example of a data processing device 2, such as a processor, that supports the execution of instructions defined according to a specific instruction set architecture (ISA). The device has an instruction fetch circuit 4 for fetching program instructions defined according to the architecture from an instruction cache or memory (not shown in Figure 1). The fetched instructions are decoded by a decoding circuit 6 to identify the operation to be executed. In response to a given instruction, the decoding circuit 6 generates a control signal that controls the execution unit 8 to execute the processing operation represented by that instruction. The operands of a given processing operation can be read from a register 10, and the result of the operation can be written back to the register 10. The execution unit 8 may include various execution units, including arithmetic units such as an adder 20, a multiplier 22, and a division / square root unit 24. The execution unit may also include other types of functional units, such as a branch unit 26 for determining the result of a branch instruction that may trigger a discontinuous change in the program flow within the program being executed, and a load / storage unit 28 for executing a load instruction to load data from the cache or memory into the register 10, or a storage instruction to store data from the register 10 into the cache or memory.

[0123] The following examples show the circuit logic design of the division / square root execution unit 24 of the processing unit 2. When a division instruction is decoded by the decoding stage 6, the decoding stage 6 controls the division / square root execution unit 24 to perform a digit recurrence method division operation. When a square root instruction is decoded by the decoding stage 6, the decoding stage 6 controls the division / square root execution unit 24 to perform a square root operation using the digit recurrence method.

[0124] While the subsequent examples focus on the division / square root execution unit 24, it will be understood that the rest of the processing unit 2 may be constructed according to any known processor design techniques. Figure 1 is a simplified representation of the components of the data processor, and it will be understood that many other components not shown in Figure 1 may also be provided.

[0125] Theoretical foundations of digit recurrence division and square roots Digit recurrence is performed by obtaining the result digit p for each iteration of cardin r. (i+1) This is a class of iterative algorithms for calculating division (x / d) and the remainder rem[i]. The remainder is used to obtain the next radix r digit. Radix r is a power of 2, and each radix r digit represents log2(r) bits of the result.

number

[0126] The partial result before iteration i is defined as follows:

number

number

number

number

number

[0127] For fast iterations, the remainder is held in a carry hold or signed digit redundant representation. In the implementations described below, known techniques are used to represent the remainder using a carry hold-like representation, where the remainder is represented by a positive word and a negative word (the non-redundant binary value corresponding to the remainder can be obtained by subtracting the negative word from the positive word).

[0128] On the other hand, for the algorithm convergence condition and multiplication time r of equation (3), the remainder has several bits in the integer part. The number of integer bits depends on the radix, digit set, and operation.

[0129] Next, in each iteration, the result's base r digit is obtained from the current remainder, a new remainder is calculated for the next iteration, and the partial result is updated.

[0130] The selection function for selecting the next result digit is the remainder estimator.

number

number

number

number

[0131] The partial result is a redundant representation of the signed digit in radix r, generated in top-level digit-first (MSDF) format. This is converted to the non-redundant representation in each iteration. The most efficient conversion technique is the well-known on-the-fly conversion. Essentially, the on-the-fly conversion is performed using digit p. i+1 This is added to the partial result P[i] (see equation (1)). However, since the digit can be negative, this addition can generate carry propagation. To prevent this slow carry propagation, another form of the result is maintained, and PM[i] has the following values: PM[i]=P[i]-r -i (6) Using this second form, the transformation algorithm for concatenation is as follows:

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[0132] In this way, there are no arithmetic operations involved in the conversion; only the concatenation of values ​​to P[i] and PM[i] is performed, and the value to be concatenated is the selected digit p i+1 It depends on.

[0133] The number of iterations for the digit recurrence algorithm is: it=[n / log2(r)] (9) n is the number of bits in the result, including the bits needed for rounding. [...] is the ceiling function, so [n / (log2(r)] is the smallest integer greater than or equal to n / (log2(r)).

[0134] The number of cycles is directly related to the number of iterations and the number of iterations performed within each cycle. Next, considering m iterations per cycle, the number of cycles is as follows: cycles=[it / m] (10)

[0135] Equations (1) to (10) can be subdivided for any base. In the following two sections, these equations are specialized for r=8, division, and square roots. A higher base r=64 is obtained by superimposing two partial iterations of base 8. The partial iteration base is 8.

[0136] Division by base 8 Floating-point division of dividend x and divisor d produces a quotient q = x / d. In the case of base 8, the partial quotient (partial result) before iteration i and the digit obtained in iteration i are Q[i] and q, respectively. i+1 It is called and equation (1) can be rewritten as follows.

number

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[0137] Regarding the selection function, it was found that only the most significant bit of the remainder (10) needs to be assimilated in order to obtain a remainder estimate with sufficient accuracy for digit selection. As mentioned earlier, the selection constant also depends on the divisor. The six most significant bits of the divisor are used to retrieve a set of eight selection constants for every iteration of the current division. Different divisors can yield different sets. Note that the most significant bit of the divisor is always 1 because the operands are normalized before the constants are selected. The selection constants are stored in a lookup table (LUT).

[0138] In this implementation, it is determined that only the 10 most significant bits (MSB), 3 integer bits, and 7 fractional bits of the remainder are needed to select the next quotient digit in equation (12).

[0139] base 8 square root The floating-point square root of operand x is the square root. [Number] Generate. The partial root before iteration i and the digit obtained in iteration i are S[i] and s, respectively i+1 Called (these correspond to P[i] and p in the general formula shown above, respectively), in the case of base 8, equation (1) can be rewritten as follows. i+1 [Number] [Number] The square root iteration is defined by the following equation [Number] And d[i + 1]=F[i + 1]=2×S[i]+s i+1 ×8 -(i+1) (17) Next rem[i + 1]=8×rem[i]-s i+1 ×F[i + 1] (18) (The notation d[i + 1] is used in some of the following examples and is the same value as F[i + 1]).

[0140] The initial values of the remainder and the partial root are rem[0]=x - 1 and S[0]=1.0, respectively.

[0141] The selection function involves comparing the remainder estimate with a set of eight partial root-dependent selection constants that are constants for each digit value. Thus [Number] cte(k) and cte(k + 1) are the selection constants for digit values k and k + 1, respectively, where k ∈{-3,-2,-1,0,+1,+2,+3,+4}. Note that there is no need to maintain a selection constant for digit value -4. It has been found that only the 11 most significant bits of the remainder need to be assimilated to obtain a remainder estimate of sufficient accuracy for digit selection.

[0142] The selection constants depend on the subroot. The seven most significant bits of the subroot are used to retrieve a set of eight 11-bit selection constants. Different subroot values ​​can select different sets. The subroot lies in the interval [0.5,1]; note that the value S[i]=1 is possible until a non-zero digit is generated. Thus, taking into account that the subroot has 1 integer bit (which is 0 after the first non-zero and negative digits have been generated) and 6 fractional bits, and the minimum value of the subroot is 0.5, the selection constants can be stored in a 33 × 88 bit lookup table (LUT) with 32 entries for S[i] ∈ [0.5,1] and 1 entry for S[i]=1 (however, the size of the storage device for the square root comparison constants can be reduced using offset LUTs, as described below in several techniques).

[0143] A simple implementation of the square root of radix 64 with two radix 8 iterations. Each iteration in base 8 generates a 3-bit result. Then, by superimposing two base 8 iterations, 6 result bits per cycle, corresponding to the square root of base 64, can be obtained. A simplified embodiment is shown in Figure 2. Two identical base 8 partial iterations are connected to obtain a base 64 iteration. Note that only the most significant bit of the remainder is used to select the quotient digit. 11-bit remainder estimate

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[0144] Therefore, in each partial iteration, ● The carry propagating adder 30 receives the remainder value rem[i]31 generated in the previous partial iteration, which is represented in a redundant representation. The carry suspending adder 30 generates a non-redundant remainder estimate of some of the most significant bits of the remainder value 31 by performing a carry propagating sum of the most significant bits of two words of the remainder value 31 (for example, if the representation with positive and negative words described above is used, the negative word is subtracted from the positive word). ● The digit selection comparator 32 compares the remainder estimate with each of the set of comparison constants 34 to determine the next root digit 33. ● The remainder adjustment value generation circuit 36 ​​generates a remainder adjustment value 39 corresponding to the “d vector” or d[i+1] term shown in Equation 17 above. Therefore, in the case of square root operations, the remainder adjustment value depends on the partial root value 37 received from the previous partial iteration and the next root digit 33 selected by the digit selection comparator 32. The term “d vector” is used simply as a label for the term d[i+1] because the number of bits in the value corresponds to the number of bits used in vector operands in some implementations. However, it should be noted that this term does not mean that “d vector” is a single-instruction multiple data (SIMD) vector operand containing multiple independent data elements. Rather, “d vector” is a single data value, not a vector of multiple independent data values. ● The remainder update circuit 38 (including a 3:2 carry-held adder) updates the previous remainder 31 received from the previous partial iteration based on the remainder adjustment value 39 by adding the positive and negative words of the previous remainder 31 with the remainder adjustment value 39 to generate an updated remainder 40 (still in redundant representation) that is supplied to the next partial iteration so that it becomes the previous remainder 31 of that partial iteration. In the path between outputting the updated remainder 40 in one partial iteration and inputting the previous remainder 31 into the carry-held adder in the remainder update circuit 38 of the next partial iteration, a 3-bit left shift is applied to represent the 8 × rem[i] term in equation 18 above. ● The on-the-fly conversion circuit 42 inserts the value determined based on the selected root digit 33 into the partial root value 37, generating an updated partial root value 43 that will be output in subsequent partial iterations so as to be the partial root value 37. The on-the-fly conversion can be performed according to equations 6 to 8 above. Therefore, although not shown in Figure 2 for the sake of brevity, the partial root value can be represented as two separate forms P and PM, as described earlier, in order to simplify the on-the-fly conversion which can later be performed as concatenation.

[0145] The updated remainder 40 and updated subroot value 43 from a partial iteration become the remainder 31 and subroot value 37 from the previous partial iteration. Similarly, the updated remainder 40 and updated subroot value 43 from the last partial iteration in a given iteration become the remainder 31 and subroot value 37 from the previous partial iteration in the next iteration.

[0146] However, this simple implementation is too slow. To speed up the cycle, several techniques described in the next section are used.

[0147] Square root iteration with base 64 Figure 3 shows a square root processing circuit for performing a digit iteration cycle corresponding to a single radix 64 square root iteration. In this example, the square root processing circuit is an iteration unit in which the output of one iteration is fed back as input to the same unit in subsequent iterations, and the flip-flop 50 latches the value passed each cycle. However, as will be further explained below with respect to Figure 9, the square root processing circuit can also be used in a pipelined implementation.

[0148] The square root processing circuit includes several parts, namely (1) a remainder update circuit 34, (2) a digit selection circuit (root digit calculation) 32, and (3) a remainder estimation circuit 30. The connections between these components are also shown. These parts will be described in detail below. The square root processing circuit also includes an on-the-fly transform circuit 42, which will be described in more detail later. The on-the-fly partial root transform holds two partial root forms S[i] and SM[i], where SM[i] is the partial root S[i] minus 1. SM[i]=S[i]-8 -i (20) These two forms are used in some parts of the cardinal 64 iteration. In addition, S3[i] = 3 × S[i] S3M[i]=S3[i]-8 -i As will be explained in more detail below regarding Figures 13 to 16, these are also required for on-the-fly partial root transformations. Using S3[i] and S3M[i] simplifies the processing of ±3 root digit multiplication.

[0149] As shown in Figure 3, when a radix 64 iteration is divided into two radix 8 sub-iterations, there are two instances each of the remainder estimation circuit 30, digit selection circuit 32, and remainder update circuit 34 corresponding to each radix 8 sub-iteration, although there may be some overlap between the circuits used for each sub-iteration, as will be further explained below. There may also be two instances of the on-the-fly transform circuit 42 for performing an on-the-fly transform using the radix 8 root digit obtained in each radix 8 sub-iteration, but for simplicity in Figure 3, this is shown as a single block.

[0150] Remainder update Figure 4 shows in more detail the remainder update circuit 30 for performing remainder updates in a single radix 8 partial iteration (which may be either the first or second radix 8 partial iteration within a radix 64 iteration). The remainder update for each iteration of the cycle (see Equation 16) is performed speculatively. That is, the updated remainder value rem[i+1] for all possible values ​​of the root digit is calculated, and the root digit s i+1 Once the root digit s is known, the correct remainder is selected. Therefore, the remainder update circuit 30 selects the next root digit s. i+1 It has several replica circuit units 60, each generating an updated remainder candidate output value corresponding to a different option. i+1 For =0, no duplicate circuit unit 60 is provided, because equation 18 above means that the updated remainder rem[i+1] can be obtained directly from the previous remainder value rem[i] without addition. The sign of the previous remainder estimate is used to reduce the number of inferred remainders. If the remainder estimate is positive, the root digit can only be {+4,+3,+2,+1,0}. On the other hand, if the remainder estimate is negative, the root digit can only be {-4,-3,-2,-1,0}.

[0151] Accordingly, each replica circuit unit 60 has a carry-hold adder 38 and a selection multiplexer 62 for selecting between alternative values ​​calculated within the logic block 64 for positive and negative root digits of equivalent magnitude, depending on the sign of the previous remainder estimate received from a previous partial iteration or iteration. This reduces the number of replica units required (four replica circuit units 60 are sufficient to handle digits ±1, ±2, ±3, and ±4 respectively, instead of requiring 8 to process each positive / negative digit separately).

[0152] The replication circuit unit 60 constructs a vector d[i+1] (sometimes called F[i+1]) for all non-zero root digit values, both positive and negative.

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[0153] Therefore, Figure 4 shows the bits of the digits concatenated in the on-the-fly calculation for each possible d[i+1] vector. The mask[i] signals where the root digits must be concatenated (the mask is shifted by 3 bits between partial iterations so that each consecutive radix 8 root digit is concatenated 3 bits lower than where the previous radix 8 root digit was inserted).

[0154] Blocks 64 labeled fda_pos and fda_neg, where x=1, 2, 3, 4, are |s i+1 2 have values ​​corresponding to the positive or negative digit = a| * S[i] or 2 * By concatenating SM[i], we can express the vector d[i+1] according to equation 21, and also -a × d[i+1] (the term -s in equation 18 above). i+1 Evaluate the ×F[i+1] (corresponding to F[i+1]) to generate d vectors fd1, fd2, fd3, and fd4.

[0155] In the recurrence relation, d[i+1] is s i+1 Multiply by . To prevent 3X multiplication, s i+1 The case of =±3 is handled differently, and 3×d[i+1] is constructed by the block fd3_pos or fd3_neg using 3×S[i] directly, as follows: 3×d[i+1]=2×(3×S[i])+(3×s i+1 ) × 8 -(i+1) (twenty two)

[0156] In this case, |3 × s i+1Concatenating |=9, this requires 4 bits for display. This is not a problem as a 1-bit left shift of 3 × S[i] leaves room for an additional bit. Then,

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[0157] The remainder estimation sign is used to select a positive or negative d[i+1] set before the 3-to-2 carry-retained adder 38. In this way, as a result, only five estimated remainders are calculated instead of nine.

[0158] The reciprocal of the remainder estimate code is placed in the least significant bit of the inferred remainder carry word; therefore, if the remainder estimate code is 1, the least significant bit of the inferred remainder carry word is 0, and if the remainder estimate code is 0, the least significant bit of the inferred remainder carry word is 1. This is because, as shown in equation (18), when the digit is positive (the remainder estimate code is 0), the term s i+1 This is because we need to subtract ×F[i+1]. Subtraction is performed by s i+1 This means we must calculate the two's complement of ×F[i+1]. The two's complement is the term s i+1×F[i+1] is obtained by taking the bitwise complement and adding 1. For example, the two's complement of 11100010 is 00011101+1=00011110. Therefore, in the fd1_pos, fd2_pos, fd3_pos, and fd4_pos modules of Figure 4, the bitwise complement is taken for this term, and the "+1" is added by changing the least significant bit of the carry word, which is 0 by definition, to 1. In this way, no additional adder is required to complete the two's complement calculation. When the digit is negative (the remainder estimate code is 1), the operation in equation (18) is addition, so there is no need to perform two's complement, and the least significant bit of the carry word is kept at 0. Thus, in summary, the reciprocal of the remainder estimate code is placed in the least significant bit of the carry word.

[0159] Among these speculative surpluses provided by the replication circuit unit 60, since no additional hardware is required, digits i+1 There are no equivalents to the blocks fda_pos and fda_neg with =0, and the next root digit is s i+1 When this is determined by the digit selection circuit 68, the only additional input is to the multiplexer 32, which functions as a selection circuit for selecting the correct candidate output value.

[0160] Each carry-hold adder 38 consists of two terms, the positive and negative words of the redundantly expressed previous remainder rem[i], and the -s of equation (18) represented by fd1-fd4. i+1 Perform a carry-reserve sum of the three terms, including the third term which is the term ×F[i+1]. The output of each carry-reserve adder 38 is a candidate value to be selected as the updated remainder rem[i+1], which is still in redundant representation and therefore contains two terms, positive and negative. If the candidate value is simply 8, as in the case of root digit = 0 * Since there is no carry-hold adder 38, as in the case where it is equal to rem[i], no addition is necessary. The 5:1 multiplexer 68, which functions as a selection circuit, selects the root digit s selected by the root digit selection circuit 32. i+1Select from among the candidate output values ​​accordingly and provide an updated remainder rem[i+1].

[0161] Remainder estimate Figure 5 shows the remainder estimation circuit 30 for the first and second partial iterations. Remainder estimation is an early, speculative calculation of the 11 most significant bits of the remainder for use in root digit selection. This allows for better timing because the remainder estimation is removed from the critical path through the root digit calculation.

[0162] Two different situations are shown. 1. The remainder estimate from the first partial iteration to generate the remainder estimate used for digit selection in the second partial iteration within the cycle. This is done during the first iteration based on the estimated remainder obtained by the remainder update circuit 34 of the first partial iteration, as shown in Figure 4. Thus, the five carry propagating adders 70 take the most significant bit of the sum and the estimated remainder (rem) obtained by the remainder update circuit 34 of the first partial iteration. d4 [i+1] to rem d1 Add the carry words [i+1] and rem[i]). Root digit s i+1 If is known, a suitable remainder estimate for root digit selection in the second partial iteration of the cycle is selected by the multiplexer 72. Thus, this is another example of a replication circuit including a replication circuit unit 70 and a selection circuit 72. 2. A remainder estimate in the second partial iteration to generate a remainder estimate to be used for digit selection in the first partial iteration of the next cycle (the value output by the remainder estimator circuit 30 in the second iteration can be flipped on the flip-flop 50, which is ready for use in the next cycle, as shown in Figure 3). The remainder estimate generated by the remainder estimator circuit 30 in the second partial iteration is the assimilation of the most significant bit of 8 × rem[i+2], which can be derived from rem[i] input as the previous remainder value in the first partial iteration as follows (based on replacing rem[i+1] in the relationship from rem[i+2] to rem[i+1] using equation 18 with another instance of equation 18 relating rem[i+1] to rem[i]).

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[0163] This is calculated during the first and second iterations of the cycle as follows: msb_first=64×(8×rem[i]-s i+1 ×d[i+1]) (25) and msb_rem[i+2]=msb_first-8×s i+2 ×d[i+2] (26) In the equation, equation (25) is evaluated during the first partial iteration, and equation (26) is evaluated during the second partial iteration. Both equations are evaluated predictively for five remainder candidates.

[0164] Note that the difference between equation (18) and equation (25) is a factor of 64X, which is a 6-bit left shift. Next, if a 17-bit adder is used instead of two 12-bit adders, both equations can be evaluated with the same logic, where the most significant bit of 11 is the remainder estimate calculated in the first partial iteration to be used for digit selection in the second partial iteration of the cycle, and the least significant bit of 13 is used to complete the remainder estimate calculation during the second partial iteration to obtain the remainder estimate that will be used for digit selection in the first partial iteration of the next cycle of equation (26).

[0165] Therefore, in this method, the adder 70 in the first partial iteration calculates some additional (least significant) bits that are not actually needed in the remainder estimate used for digit selection in the second partial iteration. However, by calculating these additional bits, it is possible that the term msb_first shown above is calculated in the first partial iteration, reducing the overall circuit area compared to if a separate adder calculated these bits in the second partial iteration.

[0166] The adder 74 in the remainder estimation circuit for the second partial iteration evaluates equation 26, which depends on msb_first and d-vectors 0,fd1[i+2]~fd4[i+2], and this is s i+2 =0,s i+2 = ±1~s i+2 The term 8×s in the equation = ±4 i+2 These correspond to ×d[i+2] respectively. These vectors are generated as part of the remainder update circuit 34 in the second partial iteration of the cycle (see fd1-fd4 in Figure 4). This technique means that the carry-reserve adder 38 in the remainder update circuit 30 of the second partial iteration does not need to wait for the carry-propagating adder 74 in the remainder estimator 34 in the remainder estimator 34 to perform those additions before starting the additions for the second partial iteration. Instead, the calculation of the updated remainder estimator in the second partial iteration can be performed in parallel with the remainder update in the second partial iteration to remove latency from the critical timing path. This improves performance.

[0167] Root digit selection Figure 6 shows the root digit calculation performed by the digit selection circuit 32 (which may be either the first or second radix 8 partial iteration within a radix 64 iteration). The calculation of the root digit has been outlined previously, and the remainder estimate is compared with each of the eight comparison constants, and the digit is selected according to equation (19). The root digit is stored as a 1-hot 9-bit vector s[i], i=8,...,0, where if the digit=i-4, then s[i]=1, for example, if the root digit is -1, then s[3]=1, and the 9-bit vector is s={0,0,0,0,0,1,0,0,0}.

[0168] This is shown in Figure 6. There is a set of 80 11-bit comparators for comparing the remainder estimate with each comparison constant. The carry output ge-output of each comparator is set to 1 if the remainder estimate is greater than the comparison constant. The ge-output and sign of the remainder estimate are then input to a set of NAND and OR gates to generate each bit of a 1-hot 9-bit vector.

[0169] The selection constants required for root selection are derived from values ​​stored in a lookup table (LUT). The selection constant for each radix 8 iteration depends on the subroot value preceding that subiteration, so that each subiteration uses a different set of comparison constants. However, it has been derived that the same set of selection constants can be used for all subiterations except the first two. As will be further explained below with respect to the pipelined example in Figure 9, the selection of the first few root digits can be performed in a preprocessing stage, which allows the same selection constants to be used for each iteration, thus avoiding the need for a separate LUT lookup in the main iteration cycle.

[0170] Integrate Figure 7 shows a block diagram of the digit recurrence square root processing cycle. Different parts (remainder update circuit 34, remainder estimation circuit 30, root digit selection circuit 32, and on-the-fly root transformation 42) are identified by dotted lines. The relationships between these parts are also illustrated.

[0171] As shown in more detail earlier, some parts of the cycle logic use guesswork and replication to satisfy timing constraints. Therefore, replication is used in several places to obtain a guessable result for each digit value. In most cases, replication is reduced by using the sign of the remainder so that the same logic exists for positive digit values ​​and their negative counterparts. In this way, the logic is replicated 5 times instead of 9, resulting in a significant area reduction. Once the root digit is known, the correct value is selected from the 9 or 5 guessable values.

[0172] In some parts, the logic is duplicated only four times, as is the remainder update in the first and second partial iterations and the remainder estimate in the second partial iteration, but the selection is made in a 5:1 mux. This is because one of the inputs to the mux is one of the inputs to the duplicated logic (and therefore no duplication circuit unit is needed to compute new values ​​for the inferred candidate values).

[0173] Accordingly, Figure 7 shows an example of a square root processing circuit that can be used in the division / square root unit 24 of Figure 1. In some examples, the division / square root unit 24 may also include a separate instance of a division processing circuit that performs a division operation in response to a division instruction without sharing circuit and data paths between the square root processing circuit and the division processing circuit.

[0174] However, as will be further explained below with respect to Figure 8, in some examples the techniques described above for square root processing circuits can be used in combined division / square root processing circuits that can also perform division operations, in which case the combined division / square root processing circuit also functions as the aforementioned "square root processing circuit".

[0175] A base-64 combined division / square root processing circuit for shared division and square root iterations. Figure 8 shows an example of a combined division / square root processing circuit for performing radix 64 division / square root iterations, which can be provided as part of the division / square root unit 24 in Figure 1. The combined division / square root processing circuit uses shared circuitry and a shared data path to perform both division and square root operations on the same radix 64. For both division and square root operations, the same number of radix 64 iterations are performed per cycle (in this example, for both division and square root operations, a single radix 64 iteration of the digit recurrence method is performed per cycle). With respect to the square root example above, in this example, the radix 64 iterations are divided into two overlapping radix 8 sub-iterations. The combined division / square root processing circuit receives a signal "div / sqrt" as input, indicating whether the current operation is a division or square root operation. This signal can be controlled by the instruction decoder 6 based on whether the instruction being processed is a division instruction or a square root instruction.

[0176] The combined division / square root processing circuit includes all the components described above with respect to Figures 3-7 for the square root example, and therefore performs the square root operation in the same manner as described above. Since much of this circuit can also be reused for division operations, the data paths for generating the updated remainders rem[i+1], rem[i+2], remainder estimates rem_est[i+1], rem_est[i+2], and partial result values ​​S[i], SM[i] for square root operations are also used to generate the corresponding values ​​for division operations (the partial result values ​​are denoted as Q[i], QM[i] when division operations are performed, but these are on the same data path as the partial root values ​​S[i], SM[i] generated for square root operations).

[0177] Figure 8 shows the microarchitecture of a radix 64 division / square root iteration. The two radix 8 sub-iterations that form the radix 64 iteration are separated into the topmost first sub-iteration and the bottommost second sub-iteration. The two iterations are very similar, but there are some differences that will be addressed later.

[0178] As described in equations (1) and (3) above, the result after iteration i is defined by a partial result P[i] (which may be a partial quotient Q[i] or a partial root S[i]) and a remainder rem[i]. Each iteration then consists of several steps.

[0179] 1. Digit Selection A new result digit is generated from the remainder and divisor (in division) or partial root (in square root) using a lower-precision estimate instead of a full-precision value (see equation (2)). Thus, the combined division / square root unit 24 includes a shared digit selection circuit 32 that, for each radix 8 partial iteration, selects the next radix 8 digit of the division / square root result based on a comparison between the previous remainder estimates rem_est[i], rem_est[i+1] and a set of comparison constants. The remainder estimate word length differs for division and square root.

[0180] As already mentioned regarding the square root example in Figure 6, digit selection is performed by comparing the remainder estimate with a set of eight selection constants. This set depends on the most significant bit of the divisor or subroot. The set of comparison constants is stored in a lookup table (LUT) addressed by the most significant bit of the divisor or subroot (as will be further explained below). Error analysis of the radix 8 division and square root algorithms shows that the number of bits of the comparison constants and the remainder estimates differ in the two operations, namely 11 bits for the square root and 10 bits for the division. However, if an 11-bit remainder estimate is used for both division and the square root, both operations can be placed in the same logic. In this case, the comparison constant for division is extended to 11 bits by placing 0 in the least significant bit position. In this way, the remainder estimation logic 30 and the digit selection circuit 32 in the first and second partial iterations are shared between division and the square root.

[0181] Therefore, the comparison for digit selection is performed using the same set of comparators 80 for both division and square root operations. The operations of the digit selection circuit 32 are the same for both division and square root operations (as previously mentioned with respect to Figure 6), except that it receives a different set of comparison constants to compare with an 11-bit remainder estimate.

[0182] 2. Remainder update The resulting digit thus generated is used to update the remainder and partial results (Equations (1) and (3)). Thus, the shared remainder update circuit 34 is provided in each partial iteration to adjust the previous remainder values ​​rem[i], rem[i+1] based on the remainder adjustment value in a given base 8 partial iteration to generate updated remainder values ​​rem[i+1], rem[i+2] in the redundant representation.

[0183] In the square root example described in Figure 4, the duplication circuit unit is provided to generate candidate remainders of different possible values ​​for the selected result digit (sharing the circuit between positive / negative digits of the same magnitude as described above to reduce the amount of duplication required), and then the 5:1 multiplexer 68 selects one of the candidate values ​​according to the next result digit selected by the digit selection circuit 32. The carry-hold adder 38 and fd calculation unit 64 are the same as in Figure 4.

[0184] However, as shown in equation (4), the remainder adjustment value (F[i+1] term) used in remainder updating differs between division and square roots. In the case of square roots, F[i+1] is the root digit s i+1 This is obtained by concatenating to the shifted subroot. This means that F[i+1] is computed in each iteration by the fd computation unit 64. However, in the case of division F[i+1], the divisor d does not change between iterations.

[0185] Therefore, by adding the XOR gate 90, the -p in equation (3) that occurs when performing a division operation (when F[i+1]=d as shown in equation 4) i+1The ×d term is generated. One XOR gate XORs the divisor d with the inverse sign of the previous remainder estimate rem_est[i], rem_est[i+1] to provide multiplication by -1. In other words, as with division, the remainder update uses multiples of +d or -d. For positive remainders, the divisor is given its complement to obtain negative multiples of the divisor. For the replicated units that compute candidate remainder values ​​corresponding to the root digits of ±2 and ±4, a 1-bit or 2-bit left shift is applied to the path from the XOR gate to obtain the p required in equation (3). i+1 This represents multiplication by . For square roots, a separate representation of 3xd is used to avoid the need to perform 3x (the 3xd multiplication is pre-calculated before the iteration in order to have fast iterations), and so the second XOR gate XORs 3xd with the opposite sign of the previous remainder estimate to provide input to a replica circuit unit which is similarly calculating candidate remainders of ±3 square digits.

[0186] For the square root example, the 2:1 multiplexer 62 shown in Figure 4 is replaced by a set of 3:1 multiplexers 62 in Figure 8 to select the appropriate F[i+1] value for division or square root. Each 3:1 multiplexer 62 selects the corresponding value received from the XOR gate 90 based on its divisor if the operation type signal div / sqrt indicates that a division operation is to be performed. If the operation type signal div / sqrt indicates that a square root operation is to be performed, then, as previously described in Figure 4, the relevant d-vector values ​​generated by the fd1-fd4 calculation blocks 64 are selected based on the sign of the previous remainder estimate. Therefore, the 3:1 multiplexer 62 functions as a select circuit that selects as the remainder adjustment value either a value derived from the divisor value d when performing a partial iteration of a given base 8 as part of a base 64 division operation, or a value derived from a partial root value that depends on a previously selected set of base 8 root digits when performing a partial iteration of a given base 8 as part of a base 64 square root operation. The sharing of the carry-retained adder 38 and the 5:1 multiplexer 68 between both operations provides a circuit area saving.

[0187] 3. Remainder Estimation Value The remainder estimation value is obtained for use in digit calculations in the next partial iteration. Thus, in a given radix-8 partial iteration, there is a shared remainder estimation circuit 34 that generates updated remainder estimation values rem_est[i+1], rem_est[i+2], which are partial non-redundant estimation values of the updated remainder values rem[i+1], rem[i+2] generated in redundant representation by the remainder update circuit 30 in the given radix-8 partial iteration. The remainder estimation circuit 30 is the same as that described above in FIG. 5 for the square root operation. Again, in the second radix-8 partial iteration, the remainder estimation circuit 30 determines the updated remainder estimation value rem_est[i+2] in parallel with the remainder update circuit 34 that generates the updated remainder value rem[i+2].

[0188] 4. On-the-Fly Conversion The partial result P[i] (quotient Q or root S) is converted from a signed-digit redundant representation to a conventional binary non-redundant representation using on-the-fly conversion (Equations (7) and (8)). In a typical on-the-fly conversion method, the fact that the partial root is used in the next digit selection and remainder update for the square root operation, while the partial quotient is not for the division operation, leads to different partial quotient update and partial root update methods. This difference is shown below (digit

Number

[0189]

Table 1

[0190] In the case of division, each time a new digit (3 bits in radix 8) is generated, in a typical scheme, the actual subquotient is left-shifted, and the new digit is placed as the three least significant bits. In this way, the actual subquotient is always in the left significant part. Previously inserted bits are shifted left to higher bit positions. On the other hand, in the case of square roots, the new root digit is concatenated to the actual subroot so that the most significant bit of the subroot is always in the most significant part of the stored data value, and masks mask[i] and mask[i+1] are used to hold a record of where the next digit must be concatenated, as described above for square root operations.

[0191] To share on-the-fly transformation logic between division and square root, it is determined that a partial quotient update should be performed, similar to how it is done for partial root updates. That is, a mask is used to concatenate the new quotient digits, indicating where the digits must be concatenated. This is unconventional but means that increased sharing of data paths and circuit logic is possible.

[0192] Therefore, in the first partial iteration, the shared on-the-fly transform circuit 42 selects a position for inserting the next digit into the partial result values ​​Q[i], QM[i], S[i], SM[i] based on the mask[i] for both division and square root operations. Similarly, in the second partial iteration, the shared on-the-fly transform circuit 42 selects a position for inserting the next digit into the partial result values ​​Q[i+1], QM[i+1], S[i+1], SM[i+1] based on the mask[i+1] for both division and square root operations. The mask is shifted to the right by 3 bits for each partial iteration such that each result digit is inserted 3 bits to the right of the previous one.

[0193] With respect to the square root example mentioned earlier in Figure 7, the combined division / square root processing circuit can be used in either an iterative unit where the output labeled "i+2" generated in one iteration is fed back as an input labeled "i" for the next iteration of the square root or division operation, or in a pipeline unit as further described below with respect to Figure 9.

[0194] Division / Square Root Pipeline The long latency of traditional division and square root implementations, as well as the complexity of each stage with its separate logic for division and square root, hinder the use of pipelining floating-point division and square root units in commercial processors. Instead, commercial processors have iterative units where part of the logic is used over several cycles, resulting in low-bandwidth designs. In a typical scheme, the iterative logic consists of two separate parts: division iterations and square root iterations, with very little logic shared between the two operations, if any. To increase bandwidth, several iterative div / sqrt units operating in parallel are arranged. For example, one design has two iterative floating-point div / sqrt units performing double-precision, single-precision, and half-precision operations, and two other smaller iterative units performing single-precision and half-precision operations. In this way, the double-precision div / sqrt bandwidth is doubled, while the bandwidth for single-precision and half-precision division and square root is four times that of a configuration with only div / sqrt iterative units.

[0195] The method shown in Figure 9 instead provides a single pipelined div / sqrt unit 24. To overcome the drawbacks that hinder the use of such a unit, the inventors developed a low-latency division and square root implementation and a common stage for division and square root, in addition to several other logics shared between both operations. Low latency is achieved by implementing a radix 64 digit recursive division and square root algorithm with radix 8 iterations per cycle. Such an algorithm produces a 6-bit result per cycle, as previously described. Meanwhile, having the same algorithm for division and square root, along with a flawless stage design, makes it possible to reduce area requirements. As a result, we were able to design double-precision, single-precision, and half-precision pipelined floating-point div / sqrt units in a relatively small area. Compared to the alternative configuration described above using two double-precision / single-precision / half-precision units and two single-precision / half-precision units, bandwidth is significantly improved for double-precision and single-precision units, and more gradually for half-precision units, while the circuit area of ​​the pipelined unit can be smaller than the total area of ​​the alternative configuration. Thus, the pipelined unit makes it possible to obtain a high-performance div / sqrt unit 24 by combining low latency and high bandwidth.

[0196] As shown in Figure 9, the pipeline unit 24 includes a pre-processing circuit 100, a pipeline body 102 for performing digit recurrence iterations, and a post-processing circuit 104. The pre-processing and post-processing logic is mostly shared between division and square root, and the iterative portion, the digit iterations, are deployed into several pipelined radix 64 shared stages 110.

[0197] The preprocessing circuit 100 performs various preprocessing operations, including unpacking the operands, normalizing the operands (if necessary), and initialization (for example, searching for comparison constants and selecting one or more initial result digits).

[0198] The pipeline body 102 performs digit iterations, which are the iterative part of the digit recurrence algorithm. The pipeline body 102 comprises several division / square root pipeline stages 100, each containing an instance of the combined division / square root processing circuit shown in Figure 8. Thus, each pipeline stage 110 within the body 102 performs a radix 64 digit recurrence floating-point division operation, q=x / d, or a radix 64 digit recurrence square root operation.

number

[0199] The post-processing circuit 104 includes rounding logic and a right shift in the case of a partially normal result (division only).

[0200] Each pipeline unit handles three different floating-point precisions: double precision, single precision, and half precision (DP, SP, HP), resulting in different latency for division or square root operations for different precisions. Nevertheless, for a given precision, the latency is the same for both division and square roots for the sake of simple scheduling of post-processing stage timings.

[0201] A more detailed explanation of the pipeline focusing on processing the mantissa of the input operands x and d to generate the result is given below. It will be understood that the exponents of the input operands x and d are also processed. This can be done according to any known technique. For example, in the case of division, the resulting exponent may correspond to the difference between the true exponents of the input operands x and d, adjusted for any right shifts in the post-processing stage required for partial regular expression processing. In the case of square root operations, the resulting exponent may correspond to half of the true exponent of the input operand x, which is also adjusted for any normalization applied. Here, "true exponent" refers to the effective power of 2 represented by the floating-point exponent (with the exponential bias applied according to the floating-point precision used removed).

[0202] Preprocessing (V1, V2) The preprocessing circuit 100 performs preprocessing that includes unpacking floating-point operands to extract the sign, mantissa, and exponent, determining special conditions (partially normal, 0,...), normalizing the operands (e.g., processing partially normal), and addressing a lookup table (LUT) to obtain selection constants necessary for digit selection. When dividing by two partially normal operands, both operands are normalized in the same cycle.

[0203] Furthermore, a first radix 8 digit is obtained. In floating-point division, the first digit can only take the values ​​{+1, +2}, and is the integer digit of the quotient. In the square root of a floating-point number, the first radix 8 digit can take the values ​​{-4, -3, -2, -1, 0}, and its calculation is easily integrated with the initialization of the remainder and subroots.

[0204] In the case of a square root, the second digit is also obtained. As described above, the LUT stores the selection constants necessary for digit selection. However, in the case of a square root, the selection constants for each radix-8 iteration depend on the partial root value before that iteration such that each iteration uses a different set of comparison constants. This imposes severe timing and area constraints since the iterative logic should include the LUT and it should be read each time a new iteration starts. However, it has been derived that (by error analysis) for all iterations of the radix-8 square root except the first two, the same set of selection constants can be used (even if the same set of selection constants is used after the first two iterations, sufficient accuracy is given to the result). Thus, at this stage, the second root digit is obtained, then the LUT is read, and the set of selection constants thus obtained is flopped for use in digit selection in the remaining iterations.

[0205] In the case of division, several other operations are performed. To save iterations in single precision, the quotient q is forced to be such that q ∈ [1,2). Note that q < 1 only occurs when x < d. This situation is detected in the preprocessing and the dividend when q is left-shifted by 1 bit such that q = 2×x / d and q ∈ [1,2). Of course, the mantissa is the same as x / d, but the exponent needs to be decremented. Finally, 3×d = 2×d + d is calculated to be used in the radix-8 iteration, avoiding the need for 3x multiples to be calculated in each iteration and saving time.

[0206] The preprocessing stage is divided into two cycles of V1 and V2 such that the unpacking, classification, and normalization of the operands, and the first root digit (square root) is done in V1. On the other hand, in V2, the following operations are performed: calculation of the second root digit (square root), calculation of the first quotient digit (division), comparison and conditional shift of x and d of the quotient (division), calculation of 3×d (division), and LUT addressing to obtain the comparison constants for the remaining iterations (division and square root).

[0207] First Division Digit Selection and First Two Square Root Digit Selections The following provides more information on how the first radix-8 division result digit and the first two radix-8 square root result digits are selected in the preprocessing circuit 100.

[0208] Context ● Division and square root of radix 64 ● Each radix-64 iteration is composed of two radix-8 iterations. ● Division: ○ The first iteration is performed before the iterative part. ○ Reason: ■ Before the iterative part, the constant look-up table (LUT) is addressed to obtain the comparison constants necessary for quotient digit selection for each radix-8 iteration. ● The LUT is addressed with the most significant bit of the divisor. ■ All iterations use the same set of comparison constants. ■ The first radix-8 quotient digit can only take values of +2 or +1. This means that the first iteration is much simpler than the remaining iterations. ■ There is time to execute the first division iteration in the same cycle in which the LUT is addressed. ■ By having the first iteration of the LUT cycle, the final latency could be reduced by one cycle with some accuracy. ● Square root: ○ The LUT is addressed with the most significant bit of the partial root ○ The first and second iterations are performed before the iterative part. ○ Reason: ■ The radix-8 square root algorithm requires different sets of comparison constants for the first iteration, the second iteration, and the remaining iterations. ■ It has been determined to perform the first and second iterations before the iterative part in order to have common square root iterative logic in the iterative part of the square root calculation and to avoid LUT addressing in the iterative logic. ■ The first iteration is performed in the first cycle V1, along with the unpacking of operands and the determination of special operands. ■ The second iteration takes place in the same cycle V2 as the LUT addressing, and obtains the comparison constants for the remaining iterations. This cycle precedes the iterative portion of the algorithm.

[0209] Division: First base 8 digits (in V2) ● The first radix 8 division digit is selected using the same set of constants as the rest of the iteration; therefore, the constants for this first digit selection and for digit selection in subsequent iterations are obtained from the LUT. ● In this cycle ○ LUT is addressed, ○ A constant digit = +2 is used to perform the first iteration. ○ The set of comparison constants is flopped for use in the remaining iterations. ● Next, the first iteration uses the same set of constants as the remaining iterations, but due to the restricted digit value, only the constant with digit = +2 is required.

[0210] Square root: The first base of 8 digits (in V1) ● In the case of repeating a base of 8, the concept is the same, but the logic is not the same as in the case of base 4. ○ The subroot is 1 (initial value) ○ The first radix 8-digit can take the value -4, -3, -2, -1, or 0. Given a partial route, the comparison constants for these five numbers are known and wired to the first digit selection logic (only four values ​​need to be stored). Therefore, LUT addressing is not necessary for this. ○ These four values ​​(comparison cte * 64, that is, the values ​​cited below are 64 times the actual stored constants): Digit constant = 0:-64 Digit constant = -1:-176 Digit constant = -2:-272 The constant for the digit is -3:-352.

[0211] Square root: The second base, 8 digits (in V2) ● The range of subroot values ​​after the first iteration is restricted to only five possible values ​​(a different subroot value for each value of the first digit): ○ First digit = 0 => Next subroot is 1.00_000 ○ First digit = -1 => Next subroot is 0.11_000 ○ First digit = -2 => Next subroot is 0.10_000 ○ First digit = -3 => Next subroot is 0.01_000 ○ First digit = -4 => Next subroot is 0.00_000 ● A small LUT is used to store these five comparison constant sets. ● The size of this LUT is 5 x 88. ○ 5 rows ○ 8 bits / sequence for storing 8 11-bit comparison constants ○ Specify the address using the above partial route ○ Values ​​stored in the LUT (Here again, the constant values ​​shown are 64 times larger than the stored values ​​in the comparison cte) * 64): The subroots of 1.00_000 are 461, 326, 191, 61, -62, -192, -317, and -442.

[0212] The partial roots are 0.11_000 => 406, 281, 171, 61, -62, -172, -277, -377 The partial roots are 0.10_000 => 351, 241, 141, 46, -47, -142, -232, -322 The subroots are 0.01_000 => 291, 206, 121, 41, -42, -122, -192, -267 The subroots are 0.00_000 => 236, 161, 96, 31, -32, -97, -152, -212. The order of the constants above is constant: digit=+4, digit=+3, digit=+2, digit=+1, digit=0, digit=-1, digit=-2, digit=-3.

[0213] This describes the initial digit selection in the preprocessing circuit. The digit selection in subsequent stages is as previously described in Figure 6, with reference to the comparison constants shown in the LUT, which will be further explained below in Figures 17 to 20.

[0214] Pipeline division / square root unit digit iteration For a call n to a general base r and the resulting number of bits, the number of iterations is:

number

[0215] This section provides a detailed explanation of base 64 (r=64), two operations (division and square root), and three floating-point precisions (DS, SP, HP). The number of fractional bits for each precision are 52, 23, and 10, respectively. As mentioned earlier, one base 64 iteration is performed in each cycle. To obtain a simple implementation, a base 64 iteration is obtained by stacking two simpler base 8 iterations in each cycle. However, the number of iterations remains the same as the number of iterations of the base 64 algorithm.

[0216] Floating-point division: The first digit that generates the integer bits of the final quotient is selected in preprocessing. In addition, if the quotient is forced to [1;2), only the guard bit is needed for rounding, and the rounding bit is not used. Next, n=53, 24, and 11 for double precision, single precision, and half precision, respectively. This includes the fraction and the guard bit. Then the number of iterations for the three precisions is:

number

[0217] Floating-point square root: Since the input operand is [0:25;1), the result is [0:5;1), and therefore the result must be left-shifted to obtain the final floating-point result [1;2). As with division, only one extra bit, the guard bit, needs to be rounded. Thus, the number of bits in the root algorithm must be 54, 25, and 12 for DP, SP, and HP, respectively. This includes integer bits, fractional bits, and guard bits.

[0218] On the other hand, the first two radix 8 digits are obtained in preprocessing before iteration. The first digit selection is skipped and integrated into the initialization of the remainder subroot, and the second digit selection is performed in V2 so that there is a single LUT for all iterations of the remainder. These two iterations produce the 6 bits of the final root, and then the number of cycles in the iterative part is,

number

[0219] Therefore, several multiplexers are added to the main body 102 of the pipeline. ● A 2:1 multiplexer 120 in stage D2 is added to select between the outputs of stages D1 and D2, allowing stage D2 to be skipped when the HP square root operation is performed. This reflects the difference between the 2 cycles required for division and the 1 required for the square root, as shown in equations (28) and (29). ● A multiplexer (not shown in Figure 9) is added to the combined division / square root processing circuit to allow the output of the first partial iteration of stage D4 to be selected and output as the iteration result when the SP square root operation is performed (skipping the second partial iteration of stage D4). This avoids the generation of the extra 3 bits from the second partial iteration, and the 2 additional bits generated in the first partial iteration can also be discarded as described above. ● A 2:1 multiplexer 122 is added in stage D9 to select between the outputs of stages D8 and D9, allowing stage D9 to be skipped when a DP square root operation is performed. This reflects the difference between the 9 cycles required for division and the 8 cycles required for the square root. ● In stage 9, the 3:1 multiplexer 124 selects between the outputs received from stages D2, D4, and D9 (with or without the square root skipping described above), and the selection by the multiplexer 124 is based on a control signal indicating the floating-point precision of the current operation, which is controlled by the instruction decoder 6 depending on the type of instruction decoded to control the division / square root operation.

[0220] Therefore, the instruction decoder 6 acts as a control circuit for controlling the pipeline so that at least one division / square root iteration pipeline stage, which is used to perform at least one iteration of the digit recursive division or square root operation when producing a higher-precision result, is bypassed when performing the digit recursive division or square root operation to produce a lower-precision result (by controlling the multiplexer 124 to select the output of an earlier stage when the bypass is applied).

[0221] The instruction decoder 6 can also control the division / square root pipeline to trigger at least one division / square root iteration pipeline stage, which is used to perform at least one iteration when a digit recursive division operation is performed, and when a digit recursive square root operation is performed, it can skip or discard some bits of the result output completely or partially (by controlling multiplexers 120, 122 and an internal multiplexer in stage D4 not shown, it is possible to skip a second partial iteration of stage D4 and discard bits).

[0222] Post-processing (W0) As mentioned above, post-processing in the case of partial normality involves rounding and right-shifting the result. Any known floating-point rounding technique can be used here. Note that the result can only be partial normal in division; there is no partially normal result in square root. Post-processing is performed in one cycle for both division and square root.

[0223] On-the-fly conversion: Integrating two operations and three precisions into the same pipeline. As mentioned above, the number of digit iteration cycles in the square root of DP and HP is one less than that of division (see equations (28) and (29)). An empty cycle is added to the square root to maintain the same latency and collect the results in the same cycle in both operations. That is, the inputs to D2 and D9 are passed to the output without further conversion. Furthermore, in the SP square root, the second radix 8 iteration in the D4 cycle is skipped. Also, the latency differs for each precision. The unrounded result of DP is obtained in D9, while the unrounded results of HP and SP are obtained in cycles D2 and D4, respectively. Next, the operation in the W0 cycle stores the signals coming out of D2, D4, or D9 depending on the precision.

[0224] To achieve an efficient digit iteration cycle, the two operations are: Most of the logic is shared, including an on-the-fly conversion circuit 42 for updating the partial quotient or square root. However, prior to the first digit cycle D1, preprocessing has already generated six fractional bits for the square root and an integer digit for the division. The shared quotient / square root update logic must have the same new fractional digit concatenation position for division and square root.

[0225] Therefore, in the case of division, six zeros are added to the fractional parts of the quotient Q[i], QM[i], in the preprocessing stage V2. Then, the new fractional bits qi generated in each subsequent iteration are concatenated after these zeros (at the same positions where the corresponding bits are concatenated for the square root operation, as indicated by the mask). 1:000 000 q1q2q3 q4q5q6... In the post-processing stage W0, these zeros are removed before rounding, resulting in an unrounded quotient. 1:q1q2q3 q4q5q6... The addition of these zeros does not affect the final quotient precision. This is because the subroot is not used in the digit recurrence division equation, as shown in equation (4).

[0226] Therefore, in the case of a division operation, the preprocessing stage V2 provides the first division / square root iteration pipeline stage D1 with partial result values ​​where selected bit positions are set to dummy bit values ​​(0 in this example), and these selected bit positions correspond to bit positions where at least one preprocessing stage V1, V2 inserts at least one additional result digit that is not generated for a digit recursive division operation when performing a digit recursive square root operation. In the postprocessing stage W0, these dummy bit values ​​are removed.

[0227] Timing control, latency, and throughput The microstructure of the pipeline unit is shown in Figure 9. The unit consists of 12 stages. This represents the latency for slower operations, such as double-precision division, consisting of two pre-processing cycles (V1, V2), nine digit iteration cycles (D1-D9), and one post-processing cycle (W0). For a given floating-point precision, division and square root operations have the same latency. ● Half-precision, 5 cycles: V1-V2-D1-D2-W0 ● Single precision, 7 cycles: V1-V2-D1-D2-D3-D4-W0 ● Double precision, 12 cycles: V1-V2-D1-D2-D3-D4-D5-D6-D7-D8-D9-W0 (Note that even if a cycle is skipped due to the square root in D2 or D9, the latency remains the same as the input to the 3:1 multiplexer 124 that follows the flip-flop at the input to stage D2 or D9.) Having the same latency for both operations simplifies timing control.

[0228] In addition, the waiting time is the same regardless of whether a partially normalized operand or result exists, normalization (if necessary) is performed in V1, and the partially normalized quotient right shift is performed in W0 after rounding.

[0229] The timing control circuit 130 is provided to control the timing at which division and square root operations can be initiated. Although the timing control circuit 130 is shown as a separate unit in Figure 9, in other examples, the decoder 6 can function as the timing control circuit 130.

[0230] The division / square root unit 24 is fully pipelined. This means that a new operation can be started every cycle of throughput 1, provided that all operations have the same precision, which is the most common case. Thus, the control circuit 130 can control the division / square root pipeline to execute the second digit recurrence division or square root operation in a division / square root iterative pipeline stage that executes the iterations after the first digit recurrence division or square root operation, in parallel with the division / square root iterative pipeline stage that executes the iterations before the first digit recurrence division or square root operation and the division / square root iterative pipeline stage that executes the iterations before the second digit recurrence division or square root operation.

[0231] However, when mixed-precision division or square root operations are involved, constraints arise, and it is not possible to have two operations on the same stage simultaneously. As shown in Figure 10, since the latency depends on the precision, there are several prohibited start cycles for SP and HP operations. For example, SP div / sqrt can not be started 5 cycles after DP, because in that case both operations would collide at W0.

[0232] Accordingly, as shown in Figure 10, the timing control circuit 130 can control the circuit to prevent a predetermined number of cycles from starting a lower-precision digit recurrence division / square root operation to produce a lower-precision result after a higher-precision digit recurrence division / square root operation to produce a higher-precision result, the predetermined number of cycles may correspond to the difference between the number of cycles required to reach at least one post-processing stage for the higher-precision digit recurrence division / square root operation and the number of cycles required to reach at least one post-processing stage for the lower-precision digit recurrence division / square root operation.

[0233] The predetermined number of cycles varies depending on the precision used. As shown in Figure 10, the predetermined number is as follows: -When low precision is SP and high precision is DP, 5 cycles, -When low precision is HP and high precision is DP, 7 cycles, -When low precision is HP and high precision is SP, it takes 2 cycles.

[0234] In this case, similar to the case where no collision occurs in the post-processing stage W0, if the number of cycles between operations is greater than a predetermined number, there is no problem in starting a low-precision operation after a high-precision operation.

[0235] This approach can provide significant bandwidth improvements by using shared pipeline division / square root operations, and the area reduction achieved through shared common logic provides a better balance between performance and circuit area.

[0236] Nevertheless, a pipeline approach can also be used for implementations that have separate square root and division units for one or both of the square root and division units.

[0237] Furthermore, while Figure 9 shows the application of the pipeline method to digit recurrence division and square root with a base of 64, the pipeline method can also be used for other base values.

[0238] Furthermore, while Figure 9 shows a pipeline configuration that supports HP, DP, and SP, other examples may support only a subset of these precisions, or other floating-point precisions, and therefore may use a different number of pipeline stages.

[0239] On-the-fly conversion As mentioned earlier, some digit recurrence methods may involve conversion from a redundant representation to a regular binary representation (non-redundant representation). Since the output digits from a digit recurrence method are generated one at a time, it is useful to be able to perform the conversion one digit at a time to avoid the waiting time that may occur if all digits had to be converted at once. This conversion is performed using the on-the-fly conversion circuit 42.

[0240] Simply put, the on-the-fly transformation for the square root holds two subroot words, S[i] and SM[i] (S[0]=1.0 and SM[0]=0.0), and SM[i]=S[i]-r -i Furthermore, using the update rules shown below,

number

[0241] In the formula, (X, Y) represents the concatenation of X and Y, i.e., XY. In practice, SM[i] (binary) is equivalent to S[i] (binary) obtained by subtracting 1 from the least significant bit position. Therefore, if S[0]=111, then SM[0]=110.

[0242] Figure 11 summarizes how S[i] and SM[i] are updated for each digit in radix 8 operations. Figure {Sx[i], aaa} represents the concatenation of aaa bits to the actual value of S[i] or SM[i]. Note that no arithmetic operations are performed; only concatenation occurs.

[0243] Figure 12 shows an example of an on-the-fly transformation of a square root in base 8. The sequence of digits is -1, 1, -2, -4, 2, 0, -1. Note that the final value of SM[i] is S[i]-1.

[0244] As shown earlier, in the case of square root operations, the calculation of the following remainder rem[i+1] is s i+1 This involves multiplication by ×S[i] (see equation (3)). In the radix 8 embodiment, s i+1 ={+4,+3,+2,+1,0,-1,-2,-3,-4}, and therefore, 2X, 3X, and 4X multiples of S[i] are needed. The 2X and 4X terms can be easily obtained by left-shifting S[i] by 1 or 2 bits, but the calculation of 3×S[i] is far more complex, which has been a limiting factor in the practical use of the radix 8 square root algorithm.

[0245] Note that in other embodiments with smaller bases, term 3X is not necessary due to the digit sets, {+1,0,-1} for base 2 and {+2,+1,0,-1,-2} for base 4.

[0246] The present invention maintains additional partial root words representing S3[i] and S3M[i], thereby preventing the calculation from being performed as 3 × S[i] by multiplying by 3 or by multiplying S by 2 and adding S. For each of S3 and S3M, the concatenation performed is as follows: 3xs i+1 ∈{+12,+9,+6,+3,0,-3,-6,-9,-12}

[0247] Figure 13 shows how the connection is made. Note that 3×s i+1 To represent {+12,+9,-9,-12}, 4 bits are needed. This means that the concatenation of these digit values ​​generates a carry that propagates to the previous digit. Thus, 3 × s of 4 bits. i+1 It can be decomposed into a 3-bit digit (3 × s[i+1]) mod 8, with the values ​​{+6, +4, +3, +1, 0, -1, -3, -4, -6} and a positive or negative carry c. i+1 Take {+1,-1}.

[0248] From Figure 13, s i+1 If the result is {+4,+3,+2,+1,0,-1,-2,-3,-4}, then the 3-bit digits concatenated to obtain 3×S[i] are (3×s{i+1])mod8={+4,+1,+6,+3,0,-3,-6,-1,-4}. Therefore, the concatenation process to obtain S3[i] and S3M[i] is as follows.

[0249] 1. |s i+1 If |={4,3}, the actual subroot is incremented / decremented. The actual 3X multiple of the subroot S3[i] and its decremented corresponding part S3M[i] are obtained by the previous digit s according to the carry. i to s i +1 or s iRebuilt by changing to -1 S3_inc[i]=S3[i]+8 -i S3M_dec[i]=S3M[i]-8 -i Three bits are used to represent each concatenated digit, but the entire range of values ​​that can be represented by these three bits is not used; only the maximum value of +6 is added as a digit, so the carry is the previous digit s i Please note that it does not need to propagate beyond a certain point.

[0250] 2. Concatenation of 3-bit digits. Concatenation of 3-bit digits is,

number

[0251] Figure 14 shows an example of an on-the-fly transformation of a 3X square root multiple. The sequence of digits is -1, +1, -2, -4, +2, 0, -1. The final S3[i] result in the table is 3X times the final S[i] result in Figure 12. In the partial iteration i=0, the initial value of S3 is 11 (3 multiplied by the initial value of S[0]=1), and the initial value of S3M is 10 (3-1=2). In the partial iteration i=1, the digit -1 is added. 3 multiplied by -1 is -3, which is equal to the concatenation of the digit -3 in S3 and the digit -2 in S3M. Referring to equations (32) and (33), we can see that the value of S3[i+1] is the concatenation of S3M[i] and 101 (i.e., 5), and the value of S3M[i+1] is the concatenation of S3M[i] and 100 (i.e., 4).

[0252] In the partial iteration i=2, a digit of 1 is added. 3 multiplied by 1 is 3. Referring again to equations (32) and (33), s i+1 When i=1, S3[i+1] is produced by concatenating S3[i] with 011 (i.e., 3), and S3M[i+1] is produced by concatenating S3[i] with 010 (i.e., 2), thereby obtaining S3[2]=10.101011 and S3M[2]=10.101010. In the partial iteration i=3, a digit of -2 is added. Multiplying 3 by -2 gives -6. In the case of S3, the concatenation is performed on the previous value of S3M. Since we are operating in base 8, creating S3[i+1] using S3M[i] means that the value of S3[i+1] is 8 lower than it should be. Since we are trying to subtract 6, this means that we must add +2 here (8-6=+2). Thus, as shown in Figure 14, the concatenation is S3M and 2 (010). Similarly, in the case of S3M, the concatenation is performed on the previous value of S3M. Therefore, as shown in Figure 14, the concatenation is S3 and 1 (001 in binary). In the partial iteration i=4, the digit to be concatenated is -4. Multiplying 3 by -4 gives -12. This is a more complex situation because -12 cannot be represented by only three digits, and therefore a negative carry is performed. After the negative carry, the remaining subtraction to be performed is -4 (-12=-8-4). Therefore, we use the value of S3M_dec, which essentially subtracts 16 (8 is the decremented value, and 8 is derived from S3M). The resulting addition to be performed is 4 (16-12=4), so the concatenation to be performed is on the value of S3M_dec and 100 (which is 4 in binary), resulting in 010 000 100. In the case of the S3M value, the same value is used, but the concatenation is for a value one less (i.e., 4-1=3), so the concatenation is performed between S3M_dec and 011 (which is 3 in binary). The process of digits 2, 0, and -1 used in iterations 5, 6, and 7 should be clear from the above explanation.

[0253] Figure 15 shows an embodiment of a 3X partial root multiple on-the-fly transform that forms part of the on-the-fly transform circuit 42. The circuits for generating the partial root values ​​S[i] and SM[i] are not shown, as this can be achieved by simple modifications of the circuit shown in, for example, U.S. Patent Application Publication No. 2020-0293281 (using the table shown in the figure). In each partial iteration (except the first sub-iteration), the values ​​of S3[i], S3M[i], AUX[i], and AUXM[i] from the previous partial iteration are received by the receiver circuit 202. The implementation has three parts. ● Increment / decrement of the actual 3X partial roots S3[i] and S3M[i] using adjustment circuit 204. ● Calculation of the following 3X subroots S3[i+1] and S3M[i+1], and ● Calculation of new auxiliary 3X partial roots AUX[i+1] and AUXM[i+1].

[0254] The auxiliary 3X subroot is defined as follows:

number

[0255] In other words, there is carry propagation to the actual 3X subroute. According to equations (32) and (33), 3×s i+1The concatenation of these generates the following: S3[i+1]=001 111 010 111 S3M[i+1]=001 111 010 110

[0256] Next, 3 × s i+2 The concatenation of these generates the following:

number

[0257] In other words, a carry is made by digit + 3, so the set of preceding digits is incremented. However, if these digits are already saturated (in this case, the target digit of S3 is 111), a further carry is made to the next bit set. That is, S3[i+2] is incremented to S3[i+1] (3 × s i+2 This is a concatenation of )mod8. However, note that when S3[i+1] is incremented, not only does the last concatenated digit value 111→000 increase, but S3M[i]_dec also needs to be incremented from 001 111 010 to 001 111 011, or equivalently S3M[i] still needs to generate S3[i+2]. Note that in this example, there is no need to carry back any further. This is because 111 is S[i](digit s i+1 Concatenated to (=-3), S[i+1] is obtained, and the next digit s i+2 The conversion of positive carry(s i+2 This is because (=+4,+3) occurs. This carry propagates one digit. Theoretically, if several blocks of "111" exist in a sequence and a subroot must be incremented, the carry propagates beyond two digits. For example, if S3[i] = 0001 011 111 111 and the next digit is +3. In such a case, the carry propagates to the digit three positions back. However, such patterns cannot be generated by the concatenation process described here.

[0258] Therefore, when the carry propagated to the previous digit is carry = +1, S3_inc[i] and S3M_inc[i] are saved for the calculation of S3[i+2] and S3M[i+2], and when carry = -1, S3_dec[i] and S3M_dec[i] are saved. This situation occurs when there is a carry +1 or -1 in the concatenation of two consecutive root digits and for specific values within the 3X partial root.

[0259] Returning to FIG. 15, the adjustment circuit 204 is used to generate S3 inc[i] , S3 dec[i]、 S3M inc[i] , and S3M dec[i] from AUX[i] or AUXM[i]. Whether AUX[i] or AUXM[i] is selected depends on the previous digit s i as shown in FIG. 16. Therefore, the decoding circuit 206 provides signals for multiplexers 208a, 208b, 208c, 208d to select between AUX[i] and AUXM[i] considering the previous digit s i . Next, the value of the previous digit s i is concatenated with the output from the digit x3 circuit to provide correction values for S3_inc[i] and S3M_dec[i]. The digit x3 circuit generates four output values as follows. s i >=0: ● 3s i mod8 + 1 ● 3s i mod8 ● 3s i mod8 - 1 ● 3s i mod8 - 2 And when s i <0: ● 8 - (|3s i | mod8) + 1 ● 8 - (|3s i | mod8) ● 8 - (|3s i | mod8) - 1 ● 8 - (|3s i | mod8) - 2

[0260] For example, s i When = +1, the outputs are 4, 3, 2, and 1, and s i When = -2, the outputs are 3, 2, 1, and 0.

[0261] Next, the new 3X partial routes S3[i + 1] and S3M[i + 1] are generated by concatenating the bits corresponding to the new signed digit s i +1 to S3[i], S3M[i] or S3_inc[i] or S3_dec[i]. This is achieved using the concatenation circuit 210. Note that the remaining sign is used to reduce the number of 2:1 multiplexers whose outputs are fed to the concatenation circuit 210, similar to that described with reference to FIG. 4. That is, the remaining sign is used to select between positive and negative digits. For example, for S[i] within one multiplexer, a selection is made between the digits +3 and -3, and for SM[i] within another multiplexer, a selection is made between the digits +3 and -3. A positive remainder selects a positive or zero root digit, and a negative remainder selects a negative or zero root digit. The digits to be concatenated to each digit are given by equations (32) and (33). For example, for the digit +3, 001 which is (3×3)mod8 is concatenated. On the other hand, for -1, 111 is concatenated, which is 8 - |3×-3| = -1 (or 111 in binary).

[0262] After executing the concatenation circuit, the output circuit 212, in the form of a set of multiplexers, outputs selected values ​​of S3[i+1] and S3M[i+1] along with the updated AUX root values ​​AUX[i+1] and AUXM[i+1], which are generated by the AUX generation circuit 214, which decodes the latest new digit si+1 to determine if there is a carry, and then uses that information to select appropriate values, which are output as AUX[i+1] and AUXM[i+1] as shown in Figure 16. Each of AUX[i+1], AUXM[i+1], S3[i+1], and S3M[i+1] is received back by the receiving circuit 202 in further iterations or partial iterations.

[0263] LUT of selection constants At each stage of the digit recurrence operation, a digit selection operation SEL (see Equation 2) is performed. The digit selection function in the radix 8 division or square root digit recurrence algorithm performs a comparison between the actual remainder (or a portion thereof) and a set of eight selection constants or coefficients. The set of coefficients is selected using the top part of the divisor or partial square root. The eight coefficients in the selected set are compared with the top part of the remainder, and the results of the eight comparisons are used to determine the next quotient or root digit.

[0264] These coefficient sets are stored in a lookup table (LUT) addressed by the most significant bit of the divisor in a division operation or the most significant part of the subroot in a square root operation. The LUT size for radix 8 division is 32 × 72 bits, and the size for radix 8 square root is 33 × 80 bits. A unit that supports both division and square root requires two different LUTs, one for division and one for square root. Therefore, the total LUT size for such a unit is 32 × 72 + 33 × 80 = 4944 bits.

[0265] These examples propose several methods for reducing the size of the entire LUT. Some columns can be merged. Furthermore, the square root coefficient can be calculated by adding a small offset to the division coefficient. As a result, the square root LUT can be replaced by a smaller table and some logic. Additionally, several optimizations are performed to further reduce the division LUT size. Thus, the total LUT size can be reduced to 33 × 42 + 33 × 18 = 1980 bits, which represents a reduction of approximately 60% in the required memory space.

[0266] The selection function is determined by the remainder estimate (the most significant bit of the remainder) and the digit p. i+1 This involves comparison with a set of eight selection constants or coefficients, one constant for each possible value of . Therefore,

number

[0267] In division digit recurrence, the set of selection constants used to obtain the next digit depends on the divisor. In square root, however, it depends on the partial result. The six most significant bits of the divisor or the seven most significant bits of the partial root are used to extract a set of eight selection constants for all iterations of the current division. Different divisor or partial root values ​​extract different sets of constants.

[0268] In the case of division, the selection constant is 10 bits wide, but the most significant bit is 0. On the other hand, note that the most significant bit of the divisor is always 1 because the operands are normalized before the constant is selected. Therefore, the selection constant is stored in a 32 × 72 bit division lookup table (LUT).

[0269] For the square root, the selection constant is 11 bits wide. The subsquare root is [0.5,1]. Therefore, considering that the subroot estimation has one integer bit and six fractional bits, and the minimum value of the subroot is 0.5, the selection constant is stored in a 33 × 80 bit square root LUT with 32 entries for R[i]∈[0.5,1) and 1 entry for R[i]=1.

[0270] Therefore, a unit corresponding to division and square root (fdivsqrt unit) typically uses two LUTs: a 32 × 72 bit division LUT and a 33 × 80 bit square root LUT. The total LUT size is 32 × 72 + 33 × 80 = 4944 bits.

[0271] This technology proposes a method for reducing the total LUT size of an fdivsqrt unit. LUT reduction is based on the following two points:

[0272] 1. It was found that the square root constant sqrt_ct can be obtained from the division constant div_ct by adding a 4-bit offset to the base constant base_ct = [2 × div_ct / 16] × 16. Note that base_ct is div_ct with the four least significant bits set to 0. The 4-bit offset can be negative or positive. In this way, instead of storing the square root constant, it is sufficient to simply store the offset in the offset LUT.

[0273] 2. Some symmetries in division LUTs and offset LUTs allow for further reduction of the total LUT size.

[0274] Figures 17 and 18 show the raw division and square root LUTs. The figures show the constants set for each value of the divisor and partial root estimates. Each set has a digit p i = consists of constants for selecting {+4,+3,+2,+1,0,-1,-2,-3}, and for a total of eight constants in the set, for division, div_ct={md(4),md(3),md(2),md(1),md(0),md(-1),md(-2),md(-3)}, and for the square root, sqrt_ct={ms(4),ms(3),ms(2),ms(1),ms(0),ms(-1),ms(-2),ms(-3)}.

[0275] The values ​​of each comparison constant can be selected from a narrow interval. In these examples, the values ​​have been carefully chosen to be symmetrical across each LUT, meaning that the absolute values ​​of the constants in the columns of digits +4 and -3, +3 and -2, +2 and -1, and +1 and 0 are the same (with a few exceptions). As will be shown later, this selection helps to reduce the LUT size.

[0276] The first two divisor interval constants, md(4) and md(-3), are out of range; that is, the first two digits cannot be 4 or -3. This can be fixed by doubling the number of divisor intervals, but such a technique would mean doubling the LUT size and is therefore very expensive. Instead, the sixth fractional bit of the divisor is used to select a sub-interval and compensate for the two least significant bits of md(4) and md(-3).

[0277] Regarding the size of the LUT, the maximum and minimum values ​​for the division LUT are 222 and -222, respectively. Therefore, the value of the division constant is in the range [222;-222], and 9 bits are needed to represent all values ​​within that range. Similarly, for the square root, the constant is [447;-446], and therefore 10 bits are needed.

[0278] Offset LUT By comparing the division constant and the square root comparison constant shown in Figures 17 and 18, the square root comparison constant can be obtained as follows.

number

[0279] In other words, the division constant md(k) is multiplied by 2, the four least significant bits are cleared to 0, and the 4-bit offset and offset(k) are added.

number

[0280] Note that if the offset has the same sign as the base constant m_base(k), the addition involves replacing the four least significant bits of m_base(k) with the four-bit offset. If the offset does not have the same sign as the base constant, the addition is performed.

[0281] As another example,

number

number

[0282] However, there are cases where the signs of m_base(k) and offset(k) are different. For example,

number

number

[0283] Figure 19 shows the offsets for calculating the square root constant. Cases where the sign of the offset differs from the sign of the division constant are highlighted. The square root and division comparison constants have been carefully selected to make this table symmetrical with respect to the columns, meaning that the absolute values ​​of the constants in columns +4 and -3, +3 and -2, +2 and -1, and +1 and 0 are the same (have opposite signs). There are two cases where this rule is broken: in rows 4 and 13, the offsets for digits +4 and -3 do not have the same absolute value. These cases are handled separately and can be detected, for example, via the offset correction indicator circuit 252.

[0284] Symmetry Using the first division LUT, the result is as follows: 1. The absolute value of a constant can be stored instead of its signed value. This helps reduce the LUT size. 2. Number of digits p i = +1 and p i Since the absolute values ​​of constants = 0 are the same (opposite signs, specifically, digit p), i = +1 is positive, p i (where =0 is negative), these two columns can be replaced by a single column. 3. Number of digits p i = +2 and p i The absolute values ​​of the constants = -1 are the same except for rows 0 and 17 (with opposite signs, specifically digit p). i = +2 is positive, and p i= -1 is negative). These two columns are stored as a single column, and the values ​​in rows 0 and 17 are later corrected, for example, in the division correction instruction circuit 250 and the division constant correction circuit 248. Note that in row 0, m(2) = 50, m(-1) = -48, and in row 17, m(2) = 73, m(-1) = -72. To merge these two columns, the stored values ​​are 48 in row 0 and 72 in row 17, and the final m(2) value is corrected by changing the bit to the left of the least significant bit (row 17) or the least significant bit (row 0). 4. Digit p i = +2 and p i The most significant bit of the absolute value of the constant = -1 is 0. This bit does not need to be stored in the LUT. 5. Digit p i = +1 and p i The two most significant bits of the absolute value of a constant equal to 0 are 0. These bits are not stored in the LUT. 6. Digit p i = +3, p i = +2, p i =+1, p i =0, and p i Since the constant = -1 is an even number, the least significant bit is not stored in the LUT. 7. As a result, the optimized division LUT has only 6 columns for the column fusion described in items 2 and 3 above. The number of bits per column has also been reduced.

[0285] The offset LUT is shown in Figure 19. This table can also be optimized. 1. Digit p i The offset for ={+2,+1,0,-1} has the same sign as m_base. That is, the offset is positive for digits +2 and +1, and negative for digits 0 and -1 (including 0 as negative or positive where appropriate). 2. The LUT is symmetric with respect to the columns, and the absolute offset values ​​for digits +4 and -3, digits +3 and -2, digits +2 and -1, and digits +1 and 0 are the same except in the two cases mentioned above. As a result, only the absolute values ​​of the offsets are stored in the LUT, and when the offsets are used to obtain the square root comparison constant, their sign is set according to the digit value, except when the offset sign differs from the m_base sign (the value highlighted in Figure 19). 3. The signs of these exception values ​​are stored in a new column of the LUT. Next, the offset LUT has only 5 columns, 4 columns, and an additional column for the sign as a result of the column fusion of items 1 and 2.

[0286] Instead of the above, a square root LUT could be provided, and it would be understood that the constants for the division operation could be derived by looking up the values ​​in the division LUT and performing the offset. In such a situation, many of the same techniques described above can be applied to reduce the size of either the floating-point LUT or the division offset table. For example, from Figure 18, it is clear that the constants for digits +4 and -3 are of the same magnitude (the digits have opposite signs, generally the +4 digit is positive and the -3 digit is negative). Similarly, the constants for digits +3 and -2 are of the same magnitude (these are also opposite digits, typically positive for +3 and negative for -2). Similarly, the constants for digits +2 and -1 are of the same magnitude (similarly opposite signs, typically positive for +2 and negative for -1).

[0287] Figure 20 shows the final division and offset tables with the optimizations described in the previous section. The table is divided into two parts: the division LUT on the left and the square root offset LUT on the right. Note that the number of columns is reduced by column fusion. The resulting fused columns are labeled with the corresponding two-digit values. For example, a column labeled (+2, -1) will have the digit p in the raw table. i = +2 and pi =-1 means the merging of the column corresponding to -1.

[0288] On the other hand, note that the last row of the table in Figure 20 contains only square roots (row 32 in Figure 19).

[0289] The address (the leftmost column of the table) is accessed differently for division and square roots. For division, the six most significant bits of the divisor form the address, with the first bit being 1. For square roots, the seven most significant bits of the subroot R[i] are used to address the table with values ​​ranging from 0.5 (0.100000 in binary) to 1.0 (1.000000 in binary). Since the square root LUT has 33 rows, 6 bits are used for the address.

[0290] The contents of the LUT are shown as hexadecimal values. The table specifies the actual number of bits required for each column, and while hexadecimal values ​​are shown, please note that the full range of values ​​may not be possible. For example, the digit p in this division LUT... i The constant value of =+3 requires only 7 bits because its most significant hexadecimal digit can only take the values ​​{2,3,4}, which correspond to the binary values ​​{0010,0011,0100}. Therefore, the most significant bit does not need to be stored. The same applies to the sequences (+2,-1) and (+1,0).

[0291] The offset LUT (right side) in Figure 20 stores the absolute offset values ​​in columns (+4,-3), (+3,-2), (+2,-1), and (+1,0). The two-bit column sign value is the offset sign for columns (+4,-3) and (+3,-2). Note that the offsets for columns (+2,-1) and (+1,0) are positive. The sign bit 1 means that the sign of the offset and its corresponding m_base are different.

[0292] As mentioned earlier, the last row of the table with address 100000 is only meaningful for the square root. Using the same base as row 011111, the comparison constant for this partial root estimation is obtained at the offset shown in the table.

[0293] Consider the following example regarding the calculation of comparison constants for division and square roots. For division, the set of constants is obtained from the LUT by adding leading zeros. For example, in a division operation with divisor = 1.00110x...x, the LUT address is 01_00110, and the LUT returns the following:

number

[0294] Note that the number of bits for each constant in the set depends on how many digits that constant is for. Therefore, considering the rules for reducing the LUT size listed earlier for division, the set of comparison constants for this particular divisor is as follows:

number

[0295] Bits added to obtain the final constants are highlighted. The absolute values ​​of the constants are then calculated from the LUT. In a later step, the signs of m(0), m(-1), m(-2), and m(-3) are taken in two's complement to obtain the final set of constants.

[0296] Note that for the square root constants in this same row, the sign field is 01. This means that the sign of the offset for the calculations of ms(+3) and ms(-2) is different from the sign of the basic constants, and therefore the calculations of these two constants require subtraction. From the table, LUT_offset(01_00110)={1,a,e,2,6} The offsets are as follows. Offsets with a sign different from the basic constant sign are highlighted.

number

[0297] The basic constants are,

number

number

[0298] Since the positive and negative parts of the sqrt LUT are symmetric, the remaining constants can be obtained by taking the two's complement of the above constants. {ms(0),ms(-1),ms(-2),ms(-3)}={-38,-114,-192,-266}

[0299] Figure 21 shows a selection constant generator 238 used to generate selection constants used, for example, by a digit selection comparator 32. The divisor and partial root bits are received by a multiplexer 240. A div / sqrt selection signal is provided to select the divisor when a selection constant for division is required, and to select the partial root when a selection constant for the square root is required. The selected bits are then used to access the corresponding values ​​in a memory circuit 242, which consists of a division LUT and a (square root) offset LUT.

[0300] The output from the division LUT is passed to the padding circuit 246, which pads the bits by adding zeros to the output constant. The padding performed is described, for example, in points 2-6 with respect to the division LUT described above. The resulting constant is sent to the conversion circuit 244, which will be described later, and also to the division constant correction circuit 248. The division constant correction circuit 248 receives the padded (extended) division selection constant, as well as the output from the division correction indicator circuit 250, and the division correction indicator circuit indicates whether the data obtained from the division LUT is one of the exceptional cases where the absolute values ​​of the constants are not the same (point 3 with respect to the division LUT described above). That is, (i) the constants md(4) and md(-3) when the divisor estimate is 0 or 1, and (ii) the digit p when the divisor estimate is 0 or 17 i = +2 and p i The difference in the absolute values ​​of constants equal to -1 is checked. These corrections require setting bits 70, 50, 1, and 0 in the selected set of constants, and clearing bits 71 and 21. The corrections are performed by the division constant correction circuit 248. The output from the offset LUT, along with the output from the offset correction indicator circuit 252, is passed to the conversion circuit 244, which indicates whether the constant being accessed is one of the exceptions where the LUT offset does not have the same value (e.g., lines 4 and 13). If so, the conversion circuit 244 performs the correction to the correct value. The correction circuit 244 also receives a padded (extended) division constant from the padding circuit 246. The substitution circuit 254 is used to add the offset using concatenation or subtraction as described above. In particular, subtraction is performed if the offset sign and the constant base sign are different. Subtraction is made possible by checking the sign field in the offset LUT. Substitution of the four least significant bits of a 4-bit offset is performed only if the signs are equal.

[0301] For both the division constant and the LUT constant, the absolute value is given as digit p. i A signature circuit 256 is provided for converting to signed values ​​=0, -1, -2, and -3.

[0302] Computer-readable code for manufacturing The concepts described herein may be embodied in computer-readable code for the manufacture of devices that embody the described concepts. For example, the computer-readable code may be used in one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to manufacture an integrated circuit comprising a device that embodies the concepts. The computer-readable code described herein may, additionally or alternatively, enable the definition, modeling, simulation, verification, and / or testing of devices that embody the concepts described herein.

[0303] For example, computer-readable code for manufacturing a device that embodies a concept described herein can be embodied in code that defines a hardware description language (HDL) representation of the concept. For example, the code can define register transfer level (RTL) abstractions of one or more logic circuits for defining a device that embodies a concept. The code can define HDL representations of one or more logic circuits that embodied the device in Verilog, SystemVerilog, Chisel, or VHDL (Very High-Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. Computer-readable code can provide definitions that embodied a concept using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of the concept that can be interpreted by a computer to enable simulation of the concept, functional and / or formal verification, and testing of the concept.

[0304] Additionally or alternatively, computer-readable code can embody computer-readable representations of one or more netlists. These netlists can be generated by applying one or more logic synthesis processes to the RTL representations. Alternatively or additionally, one or more logic synthesis processes can generate bitstreams from the computer-readable code that are to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for verification and testing purposes before being manufactured in an integrated circuit, or the FPGA may be deployed directly into a product.

[0305] Computer-readable code may include a mixture of code representations for manufacturing a device, for example, a mixture of one or more RTL representations, netlist representations, or other computer-readable definitions used in semiconductor design and manufacturing processes to manufacture a device that implements the present invention. Alternatively or additionally, the concept may be defined as a combination of computer-readable definitions used in semiconductor design and manufacturing processes to manufacture a device and computer-readable code that defines instructions to be executed by the device that is defined to be manufactured.

[0306] Such computer-readable code can be placed on any known temporary computer-readable medium (such as wired or wireless transmission of code over a network) or on a non-temporary computer-readable medium such as a semiconductor, magnetic disk, or optical disk. An integrated circuit manufactured using computer-readable code may comprise components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or one or more other components that individually or collectively embody a concept.

[0307] In this application, the term "configured to..." is used to mean that an element of the device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to..." does not mean that an element of the device needs to be modified in any way to provide the defined operation.

[0308] While exemplary embodiments of the present invention are described in detail herein with reference to the accompanying drawings, it will be understood that the present invention is not limited to these exact embodiments, and that various changes and modifications can be made to the embodiments without departing from the scope of the present invention as defined by the appended claims.

Claims

1. A data processing device for performing a digit recurrence operation on input values, A receiving circuit configured to receive the remainder of the iteration prior to the digit recurrence operation, Each of a plurality of selection constants associated with a digit available as the next digit of the result of the digit recurrence operation, each of the selection constants is configured to perform a comparison with the higher bits of the remainder of the previous iteration of the digit recurrence operation and output the next digit of the result of the digit recurrence operation based on the comparison, wherein in division operation mode, the digit recurrence operation is a division digit recurrence operation, the input parameter is a divisor, and the selection constants include a division selection constant, and in square root operation mode, the digit recurrence operation is a square root digit recurrence operation, the input parameter is a partial root, and the selection constants include a square root selection constant, A memory circuit configured to store at least a subset of the division selection constant or the square root selection constant, and an offset indicating how to convert between the division selection constant and the square root selection constant, A data processing device equipped with the following features.

2. The data processing apparatus according to claim 1, further comprising a conversion circuit configured to generate selection constants to be excluded from the selection constants stored in the memory circuit.

3. The data processing apparatus according to claim 2, wherein the conversion circuit is configured to generate the excluded selection constant by performing a selective inversion of the sign of one of the selection constants stored in the memory circuit.

4. The data processing apparatus according to claim 3, wherein one of the selection constants is associated with the same input parameter and a different of the available digits as the selection constant to be excluded.

5. The data processing apparatus according to claim 3, wherein the memory circuit is configured to store an exception flag indicating whether the selective inversion should be performed for the selection constant in order to generate the selection constant to be excluded.

6. The aforementioned digit recurrence operation is a square root digit recurrence operation, The data processing apparatus according to any one of claims 1 to 5, wherein the input parameter is a partial root.

7. The aforementioned digit recurrence operation is a division digit recurrence operation, The data processing device according to any one of claims 1 to 5, wherein the input parameter is a divisor.

8. In division operation mode, the digit recurrence operation is a division digit recurrence operation, and the input parameter is the divisor. The data processing device according to any one of claims 1 to 5, wherein in the square root calculation mode, the digit recurrence calculation is a square root digit recurrence calculation, and the input parameter is a partial root.

9. The data processing apparatus according to claim 2, wherein each of the selection constants is a selection constant for the division digit recurrence operation.

10. The data processing apparatus according to claim 9, as dependent on claim 2, wherein the conversion circuit is configured to generate an exclusion selection constant in the division operation mode by performing a selective sign inversion of one of the selection constants of the division digit recurrence operation.

11. The data processing apparatus according to claim 9, as dependent on claim 2, wherein the conversion circuit is configured to generate the excluded selection constant in the square root calculation mode by referring to one of the selection constants of the division digit recurrence calculation.

12. The data processing apparatus according to claim 10, wherein the memory circuit is configured to store an exception flag indicating whether the selective inversion should be performed for the selection constant to generate the selection constant to be excluded.

13. The data processing apparatus according to any one of claims 1 to 5, wherein the digit recurrence operation is base 8.

14. A data processing method for performing a digit recurrence operation on input values, The receiving circuit receives the remainder of the iteration prior to the digit recurrence operation, The comparison circuit outputs the most significant bits of the remainder of the previous iteration of the digit recurrence operation and each of a plurality of selection constants associated with a digit available as the next digit of the result of the digit recurrence operation, each of the selection constants performing a comparison with one of the available digits and each of a plurality of selection constants associated with an input parameter, and outputting the next digit of the result of the digit recurrence operation based on the comparison, wherein in division operation mode, the digit recurrence operation is a division digit recurrence operation, the input parameter is a divisor, and the selection constants include a division selection constant, and in square root operation mode, the digit recurrence operation is a square root digit recurrence operation, the input parameter is a partial root, and the selection constants include a square root selection constant. The memory circuit stores at least a subset of the division selection constant or the square root selection constant, and an offset indicating how to convert between the division selection constant and the square root selection constant. Methods that include...

15. A computer, The steps include receiving the remainder of the previous iteration in the digit recurrence operation, A step of outputting the next digit of the result of the digit recurrence operation, wherein each of the selection constants is associated with a digit available as the next digit of the result of the digit recurrence operation, each of which is associated with one of the available digits and an input parameter, and compares the most significant bits of the remainder of the previous iteration of the digit recurrence operation, and based on the comparison, outputs the next digit of the result of the digit recurrence operation, wherein in division mode, the digit recurrence operation is a division digit recurrence operation, the input parameter is a divisor, and the selection constants include a division selection constant, and in square root mode, the digit recurrence operation is a square root digit recurrence operation, the input parameter is a partial root, and the selection constants include a square root selection constant. The steps include storing at least a subset of the division selection constant or the square root selection constant, and an offset indicating how to convert between the division selection constant and the square root selection constant. A non-temporary computer-readable medium containing computer-readable code for executing a program.

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