Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor suppressed in crack generation.SOLUTION: A multilayer ceramic capacitor 1 is provided, having a laminate 21 in which a plurality of internal electrode layers 5 and a plurality of dielectric layers 4 are alternately laminated. Each of the plurality of internal electrode layers 5 has a plurality of voids 10. Each of the plurality of internal electrode layers 5 has a plurality of inner circumferential portions 12 facing the plurality of voids 10. At least a part of the plurality of inner circumferential portions 12 has a flat inner periphery 11.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This disclosure relates to a multilayer ceramic capacitor.

Background Art

[0002] An example of a conventional multilayer ceramic capacitor is described in, for example, Patent Document 1. In this prior art, a multilayer ceramic capacitor in which internal electrode layers and ceramic dielectric layers are alternately arranged is described. Each of the internal electrode layers has a thickness in the range of 1 μm or more and less than 2 μm and includes a corresponding void. The voids occur more frequently in the outer peripheral portion of the internal electrode layer, and the porosity in the region from the outer peripheral edge of the internal electrode layer to 20 times the thickness of the internal electrode layer is in the range of 5 to 15%.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the prior art of Patent Document 1 described above, cracks are reduced by including voids in the region from the peripheral edge of the internal electrode layer to 20 times the thickness of the internal electrode layer at a total ratio of 5 to 15%. When the internal electrode layer melts during sintering, most of the internal electrode layer tends to become round. Further, since the multilayer ceramic capacitor has a laminated structure using barium titanate (BT) as a dielectric and nickel (Ni) as an internal electrode, internal stress occurs due to the difference in the thermal expansion coefficient and Young's modulus between the two during the cooling process after firing, and cracks are likely to occur. In particular, when the inner peripheral portion of the internal electrode layer is round, the stress at the corners of the internal electrode layer increases, and there is a problem that cracks are likely to occur. Therefore, there is a need for a multilayer ceramic capacitor in which the occurrence of cracks is suppressed.

Means for Solving the Problems

[0005] The multilayer ceramic capacitor of the present disclosure comprises a plurality of internal electrode layers and a plurality of dielectric layers, and includes a laminate in which the internal electrode layers and the dielectric layers are alternately stacked, each of the plurality of internal electrode layers has a plurality of voids that penetrate the thickness of the internal electrode layer, each of the plurality of internal electrode layers has a plurality of inner circumferential portions facing the plurality of voids, and at least a portion of the plurality of inner circumferential portions has a flat inner circumferential surface. [Effects of the Invention]

[0006] According to the multilayer ceramic capacitor of this disclosure, the stress generated in the internal electrode layer is evenly distributed and reduced, and the occurrence of cracks due to internal stress in the internal electrode layer can be suppressed. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 2] Figure 1 is a perspective view showing the basic structure of a multilayer ceramic capacitor. [Figure 3] This is a magnified photograph of a portion of the middle layer of a multilayer ceramic capacitor 1. [Figure 4] This is a magnified photograph of a portion of the surface layer near the first surface 7a of the multilayer ceramic capacitor 1. [Figure 5] This is a schematic cross-sectional view illustrating the relationship between the inner circumference shape and the generated stress. [Figure 6] This is a perspective view illustrating the stress generated in the inner circumference. [Figure 7] This is a magnified photograph showing the occurrence of air gaps and the inner circumference of a multilayer ceramic capacitor. [Figure 8] This graph shows the heating temperature during firing. [Modes for carrying out the invention]

[0008] Embodiments of the multilayer ceramic capacitors of this disclosure will be described below with reference to the drawings. The figures used in the following description are schematic, and the dimensional ratios and other aspects shown in the drawings do not necessarily correspond to those of reality. The number of components shown in each figure (e.g., the number of dielectric layers and internal electrode layers) may not be consistent with each other. For convenience, the Cartesian coordinate system XYZ is defined herein. The X-axis direction is also referred to as the first direction or length direction. The Y-axis direction is also referred to as the second direction or width direction. The Z-axis direction is also referred to as the third direction, height direction, or stacking direction.

[0009] Figure 1 is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present disclosure, and Figure 2 is a perspective view showing the basic structure of the multilayer ceramic capacitor of Figure 1. The multilayer ceramic capacitor 1 of this embodiment includes a laminate 21. The laminate 21 has a substantially rectangular parallelepiped shape. The laminate 21 has a first face 7a and a second face 7b facing each other in a third direction Z, a first end face 8a and a second end face 8b facing each other in a first direction X, and a first side face 9a and a second side face 9b facing each other in a second direction Y. The first face 7a and the second face 7b may be perpendicular to the third direction Z. The first end face 8a and the second end face 8b may be perpendicular to the first direction X. The first side face 9a and the second side face 9b may be perpendicular to the second direction Y. Hereafter, the first surface 7a and the second surface 7b may be referred to as the main surfaces 7a and 7b, the first end surface 8a and the second end surface 8b may be referred to as the end surfaces 8a and 8b, and the first side surface 9a and the second side surface 9b may be referred to as the side surfaces 9a and 9b.

[0010] The laminate 21 is constructed by alternately stacking multiple dielectric layers 4 and multiple internal electrode layers 5 in the third direction (stacking direction) Z. As the material for forming the internal electrode layers 5, base metals such as nickel (Ni) or copper (Cu) may be used because they allow for high stacking while suppressing manufacturing costs. Nickel (Ni) may also be used because it allows for simultaneous firing of the internal electrode layers 5 and the dielectric layers 4. The thickness of the internal electrode layers 5 may be, for example, about 0.1 μm to 1.0 μm, or about 0.4 μm to 0.5 μm.

[0011] The external electrode 3 may be made of a sintered body of metal and glass, for example, a structure in which copper (Cu) powder or an alloy powder of copper and another metal, such as a transition metal such as Ni, is sintered with glass powder.

[0012] The dielectric layer 4 is composed of an insulating material. The dielectric layer 4 may be composed of a ceramic material mainly composed of, for example, barium titanate (BaTiO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), or barium zirconate (BaZrO3). In this specification, "main component" refers to the component with the highest proportion in the material or component of interest. The proportion may be expressed as concentration (mol%).

[0013] The dielectric layer 5 is made of a ceramic composed of crystalline particles in which magnesium oxide, rare earth element (RE) oxides, and manganese oxide are solid-solved in barium titanate (BaTiO3), and a grain boundary phase mainly composed of silicon oxide (SiO2). Note that the type of ceramic is not limited to those mentioned above; other ceramics can also be used. Its average thickness may be 2 μm or less, and in particular, 1 μm or less. This makes it possible to miniaturize and increase the capacitance of the multilayer ceramic capacitor 1. The average thickness of the dielectric layer 5 in the third direction Z may be approximately 0.1 μm to 1.0 μm, or approximately 0.4 μm to 0.5 μm. A thickness of 0.4 μm or more allows for reduced capacitance variation and stabilized capacitance-temperature characteristics.

[0014] The internal electrode layer 5 is exposed on the first side surface 9a and the second side surface 9b. Additionally, the internal electrode layer 5 is exposed on the first end surface 8a and the second end surface 8b, depending on its polarity.

[0015] The multilayer ceramic capacitor 1 includes a protective layer 6 as shown in, for example, FIG. 2. The protective layer 6 is located on the first side surface 9a and the second side surface 9b of the laminate 21. The protective layer 6 electrically insulates between the internal electrode layers 5 with different polarities exposed on the side surfaces 9a and 9b. Also, the protective layer 6 mechanically protects the outer peripheral portions of the internal electrode layers 5 exposed on the side surfaces 9a and 9b. The laminate 21 with the protective layer 6 disposed on the side surfaces 9a and 9b is also referred to as the body 2.

[0016] The protective layer 6 is composed of a material having insulating properties. The protective layer 6 may be composed of, for example, a ceramic material mainly containing barium titanate (BaTiO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), or barium zirconate (BaZrO3). The protective layer 6 may be composed of the same ceramic material as the ceramic material constituting the dielectric layer 4. The protective layer 6 may have a thickness of, for example, about 5 μm to 30 μm in the second direction Y.

[0017] The multilayer ceramic capacitor 1 includes external electrodes 3 that cover the first end face 8a and the second end face 8b and are connected to the internal electrode layers 5 according to polarity. The external electrodes 3 are used for electrical connection to an external substrate or an external device.

[0018] The external electrodes 3 are composed of a first external electrode 31 and a second external electrode 32. The first external electrode 31 is located on the first end face 8a of the laminate 21. The first external electrode 31 is electrically connected to the internal electrode layer 5 exposed on the first end face 8a. The second external electrode 32 is located on the second end face 8b of the laminate 21. The second external electrode 32 is electrically connected to the internal electrode layer 5 exposed on the second end face 8b. The first external electrode 31 and the second external electrode 32 may be located on the main surfaces 7a and 7b as shown in FIGS. 1 and 2, for example. Also, the first external electrode 31 and the second external electrode 32 may be located on the side surfaces 9a and 9b and partially cover the protective layer 6 as shown in FIG. 1, for example.

[0019] The first external electrode 31 and the second external electrode 32 may be composed of a single conductive layer or of multiple conductive layers. In this embodiment, the first external electrode 31 and the second external electrode 32 may be composed of a two-layer structure having a base layer and an outer layer.

[0020] The underlayer is in contact with the laminate 21 and is connected to the internal electrode layer 5 exposed on the first end face 8a and the second end face 8b. The underlayer may be formed using thin-film formation techniques such as plating, sputtering, or vapor deposition, or thick-film formation techniques such as screen printing or gravure printing. The underlayer is composed of a metallic material. The metallic material used for the underlayer may be, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy made of these metals.

[0021] The outer layer covers the base layer. The outer layer may be formed using thin-film formation techniques such as electroless plating or electrolytic plating. The outer layer is made of a metallic material. The metallic material used for the outer layer may be a metal such as Ni, Sn, Cu, or Au, or an alloy made of these metals. The outer layer may consist of a single plating layer or multiple plating layers.

[0022] Figure 3 is a magnified photograph of a portion of the middle layer of the multilayer ceramic capacitor 1, and Figure 4 is a magnified photograph of a portion of the surface layer near the first surface 7a of the multilayer ceramic capacitor 1. The multilayer ceramic capacitor 1 is formed by cutting a sheet laminate, which consists of, for example, 100 to 200 sheets of ceramic green sheet, each laminated with a conductive paste that forms a predetermined internal electrode pattern for the internal electrode layer 5, into a grid shape, thereby forming a capacitor body molded into which the inner circumference of the internal electrode pattern is exposed. After degreasing the capacitor body molded into a state where the oxygen partial pressure is, for example, 1 × 10⁻⁶ -7 Pa~1×10 -9The dielectric layer 4 and the internal electrode layer 5 are integrally sintered by firing in a hydrogen-nitrogen mixed gas of Pa at a temperature of 1100°C to 1200°C for 1 to 4 hours. The internal electrode layer 5 of such a multilayer ceramic capacitor 1 has a plurality of voids 10. Each of the plurality of internal electrode layers 5 has an inner circumference 12 facing the voids 10. At least a portion of the plurality of inner circumferences 12 has a flat inner circumference surface 11. This allows for the distribution of stress in the direction that would cause delamination between the internal electrode layer 5 and the dielectric layer 4, and because the inner circumference surface 11 is flat, the force in the direction that would separate the dielectric layer 4 and the internal electrode layer 5 is reduced, making it difficult for cracks to propagate even if they occur, thereby suppressing the occurrence of cracks.

[0023] The flat inner circumferential surface 11 is more abundant in the end layers at both ends in the thickness direction of the laminate 21 than in the middle layer. Furthermore, the amount of flat inner circumferential surface 11 increases towards the end layers at both ends in the thickness direction of the laminate 21 compared to the middle layer. This configuration makes it possible to suppress the occurrence of cracks originating from the end layers when the internal stress of the laminate 21 increases due to deformation.

[0024] Each inner circumference 12 of the internal electrode layer 5 is tapered towards the void 10. This configuration improves the adhesion between the internal electrode layer 5 and the dielectric layer 4, thereby suppressing the occurrence of cracks.

[0025] A portion of the inner circumference 12 is covered by the adjacent dielectric layer 4. With this configuration, the adhesion between the internal electrode layer 5 and the dielectric layer 4 is improved, and the occurrence of cracks can be suppressed.

[0026] Multiple inner circumferential portions 12, in a cross-sectional view parallel to the thickness direction of the laminate 21, 0.15 The structure includes a curved surface 12a that is convex toward the inside of the void 10 and has a radius of curvature of μm or more. With this configuration, the stress in the direction of delamination between the internal electrode layer 5 and the dielectric layer 4 is distributed, so that the occurrence of cracks can be suppressed.

[0027] The number of inner circumferential portions 12 having a flat inner circumferential surface 11 is 70% or more of the total number of inner circumferential portions 12 facing the multiple voids 10. With this configuration, the stress in the direction of delamination between the internal electrode layer 5 and the dielectric layer 4 is distributed, and the occurrence of cracks can be suppressed.

[0028] The inner circumference 12 is more abundant in the region on the inner circumference side of the thickness direction Z of the laminate 21 than in the middle portion of the thickness direction Z. With this configuration, it is possible to suppress the occurrence of cracks originating from the inner circumference 12, where the internal stress is high due to laminate deformation.

[0029] The inner circumference 12 may be configured to increase from the middle of the thickness direction of the multilayer ceramic capacitor 1 toward both ends in the thickness direction. With such a configuration, it is possible to suppress the occurrence of cracks originating from the inner circumference 12, where the internal stress has increased due to stacking deformation.

[0030] To confirm the crack suppression effect of the inner circumference 12 facing the void 10, the inventors fabricated multilayer ceramic capacitors of samples 1 to 9 by varying the heating rate during firing and the tertiary degreasing temperature, and confirmed the crack occurrence rate and capacitance. The results are shown in Table 1. For the internal electrode layers 5 of samples 1 to 9 when this measurement test was conducted, the tertiary degreasing process was performed by reducing the oxygen concentration at a high temperature. If the degreasing is insufficient, the internal electrode layer 5 melts and the edges become rounded. For example, in the case of a size of 1.0 mm × 0.5 mm, the crack occurrence rate was calculated by observing with a magnifying glass at ×100x and counting how many cracks were present out of 100. Nickel (Ni) with a thickness of 0.5 μm was used as the main material, and barium titanate (BaTiO3) with a thickness of 0.6 μm was used as the material for the dielectric layer 4.

[0031] [Table 1]

[0032] Sample 1 had a void 10 formed in the internal electrode layer 5, but the radius of curvature of the inner surface 11 of the inner circumference 12 was not flat, at 0.04 μm, and it was fired at a heating rate of 300 °C / hr. In this case, the crack occurrence rate was high at 14.1%. The capacitance was low at 1.48 μF.

[0033] When the heating rate of sample 2 was increased to 3000°C / hr and the radius of curvature of the inner surface 11 of the inner circumference 12 was increased to 0.15 μm, the crack occurrence rate decreased to 1.2%, and the capacitance increased to 1.89 μF.

[0034] When sample 3 was heated at a rate of 6000°C / hr and the radius of curvature of the inner surface 11 of the inner circumference 12 was set to 0.17 μm, the crack occurrence rate decreased to 0.3%, and the capacitance increased to 2.06.

[0035] When sample 4 was heated at a rate of 7000°C / hr and the radius of curvature of the inner surface 11 of the inner circumference 12 was set to 0.15 μm, the crack occurrence rate decreased to 0.1%, and the capacitance was 2.05 μF.

[0036] When sample 5 was heated at a rate of 7000°C / hr and the radius of curvature of the inner surface 11 of the inner circumference 12 was set to 0.17 μm, the crack occurrence rate was 2.08% and the capacitance was 2.08 μF.

[0037] When the heating rate of sample 6 was increased to 10,000°C / hr, and the radius of curvature of the inner surface 11 of the inner circumference 12 was increased to 0.22 μm, the crack occurrence rate decreased to 0%, and the capacitance increased to 2.14 μF.

[0038] When the heating rate of sample 7 was further increased to 13000°C / hr, and the radius of curvature of the inner surface 11 of the inner circumference 12 was set to 0.22 μm, the crack occurrence rate remained at 0%, the capacitance was 0.22%, and the capacitance was 2.20 μF.

[0039] When sample 8 was heated at a rate of 13,000°C / hr and the radius of curvature of the inner surface 11 of the inner circumference 12 was set to 0.23 μm, the crack occurrence rate remained at 0%, and the capacitance was 2.11 μF.

[0040] When sample 9 was heated at a rate of 13,000°C / hr and the radius of curvature of the inner surface 11 of the inner circumference 12 was set to 0.24 μm, the crack occurrence rate remained at 0%, and the capacitance was 1.74 μF.

[0041] Figure 5 is a schematic cross-sectional view illustrating the relationship between the inner circumference shape and the generated stress, and Figure 6 is a perspective view illustrating the stress generated in the inner circumference. As shown in Table 1 above, if the tertiary degreasing temperature is too low, as in Sample 1, the amount of binder residue increases, the internal electrode layer 5 melts, the void 10 increases, and the capacitance decreases. When the inner circumference 12 of the internal electrode layer 5 becomes rounded, it is thought that stress is not easily distributed, and crack propagation progresses more easily.

[0042] The tertiary degreasing temperature may be between 800°C and 1100°C. If the tertiary degreasing temperature is lower than 800°C, binder will remain in the internal electrode layer 5, and the internal electrode layer 5 will melt during firing, causing the inner circumferential surface 11 to become rounded. Through this tertiary degreasing process, multiple inner circumferential portions 12, in a cross-sectional view parallel to the thickness direction, 0.15 A curved surface 12a is formed that is convex toward the void 10 and has a radius of curvature of μm or more. If the tertiary degreasing temperature is higher than 1100°C, the amount of binder in the dielectric layer 4 decreases, so the dielectric layer 4 does not shrink, and a void 10 is created in the internal electrode layer 5. In addition, oxidation of the internal electrode layer 5 progresses, so the capacitance decreases.

[0043] The heating rate during firing may be between 3,000 and 13,000°C / hr. If the heating rate during firing is less than 3,000°C / hr, the internal electrode layer 5 will melt, causing the inner circumferential surface 11 to become rounded. If the heating rate is greater than 13,000°C / hr, the setter supporting the laminate 21 in the heating furnace will not heat up. If the setter does not heat up, heat will not be transferred to the laminate 21.

[0044] Since the tertiary degreasing temperature is lower than 1100°C, the binder does not leach out too much from the internal electrode layer 5, and the internal electrode layer 5 melts moderately during sintering, creating voids 10. On the other hand, since the tertiary degreasing temperature is higher than 800°C, the binder in the internal electrode layer 5 is leached out moderately, and the heating rate is faster than 3000°C / hr, so the internal electrode layer 5 does not melt too much during sintering, and the inner circumferential surface 11 tends to become flat after firing.

[0045] In sample 9, the high tertiary degreasing temperature makes it difficult for the dielectric layer 4 to shrink, increasing the voids 10 in the internal electrode layer 5 and reducing the capacitance. This condition is thought to be due to the elimination of the following conditions (1) to (6) which involve a large amount of binder residue.

[0046] (1) The tertiary degreasing temperature is low. (2) Binder residue increases. (3) During firing, the carbon (C) in the binder absorbs the surrounding oxygen (O) and is released as carbon dioxide (CO2). At this time, the oxygen in the dielectric layer 4 (BaCO3) is also absorbed. (4) The number of oxygen vacancies in the dielectric layer 4 increases, making it more prone to shrinkage. (5) When the dielectric layer 4 shrinks, it reduces the air gap 10 in the internal electrode layer 5. (6) The voids 10 in the internal electrode layer 5 are reduced.

[0047] Figure 7 is a magnified photograph showing the occurrence of voids and the inner circumference of a multilayer ceramic capacitor. In Figure 7, a multilayer ceramic capacitor 1 was polished, and a 10 μm area in the center of the polished surface was photographed with an electron microscope at 10,000x magnification. The radius of curvature of the inner circumference 12 was measured, and the number of voids 10 was calculated. The multilayer ceramic capacitor 1 has a multilayer structure using barium titanate (BT) as the dielectric layer 4 and nickel (Ni) as the internal electrode layer 5. The internal electrode layer 5 has voids 10, and the inner surface 11 of the inner circumference 12 facing the voids 10 is flat. Reference numerals a1 to a18 in Figure 7 indicate the measurement target areas of the inner surface 11 where the radius of curvature was measured. The measured values ​​of the radius of curvature for each measurement target area a1 to a18 are shown in Table 2 below.

[0048] [Table 2]

[0049] Since the average value of the radius of curvature measurements for a1 to a18 in Table 2 is 0.25 μm, it can be said that if the inner circumferential surface 11 of the internal electrode layer 5 is flat to the extent that it is equal to or greater than this value, the crack generation suppression effect is high.

[0050] In manufacturing the multilayer ceramic capacitor 1, a conductive paste containing a base metal such as Ni is applied to the surface of a dielectric sheet by a well-known printing method such as screen printing, gravure printing, or offset printing to form an internal electrode pattern. The thickness of the internal electrode pattern may be 2 μm or less, and especially 1 μm or less, from the viewpoint of miniaturizing the capacitor and increasing its reliability. Multiple dielectric sheets with the internal electrode pattern applied to their surfaces are laminated and pressed together. This laminated molded body is degreased in an atmospheric environment for about 19 hours in a primary degreasing process, then degreased in a nitrogen (N2) atmosphere for about 30 minutes in a secondary degreasing process, then degreased in a mixed gas atmosphere of nitrogen (N2) and hydrogen (H2) in a tertiary degreasing process, and finally fired in a mixed gas atmosphere of nitrogen (N2) and hydrogen (H2) for 10 minutes.

[0051] Furthermore, if desired, the oxygen partial pressure can be set to 0.1-10 -4 By performing a re-oxidation treatment for 5 to 15 hours under a low oxygen partial pressure of approximately Pa, the reduced dielectric layer is oxidized, and a laminate 21 is obtained in which dielectric layers 4 and internal electrode layers 5 with good insulating properties are alternately stacked.

[0052] Finally, Cu paste is applied to each end face of the obtained laminated sintered body and baked, Ni / Sn plating is applied, and external electrodes 3 electrically connected to the internal electrode layer 5 are formed to obtain a multilayer ceramic capacitor 1.

[0053] Figure 8 is a graph showing the heating temperature during firing. Increasing the heating rate in the temperature range of 900-1100°C, shown in section W of Figure 8, can suppress the melting of the internal electrode layer 5. If the temperature in this section W is too low, degreasing will be insufficient, and if it is too high, the Ni in the internal electrode layer 5 will oxidize, so the section W is selected to be between 900 and 1100°C.

[0054] In manufacturing the multilayer ceramic capacitor 1, a conductive paste containing a base metal such as Ni can be applied to the surface of a dielectric sheet using well-known printing methods such as screen printing, gravure printing, or offset printing to form an internal electrode pattern. The thickness of the internal electrode pattern is preferably 2 μm or less, and particularly 1 μm or less, from the standpoint of miniaturizing the capacitor and improving its reliability.

[0055] By increasing the heating rate in the temperature range W during firing, the melting of the internal electrode layer 5 can be suppressed.

[0056] Immediately after firing, the multilayer ceramic capacitor 1 is subjected to barrel polishing under predetermined conditions. This process removes the end face of the dielectric layer 4, causing the internal electrode layer 5 to protrude from the end face of the multilayer ceramic capacitor 1, thereby ensuring sufficient electrical connection with the external electrode 3. In this barrel polishing process, the multilayer ceramic capacitor 1 is placed in a ball mill along with ceramic particles and media balls for barrel polishing. The ceramic particles mixed with the media balls help to mitigate the impact of the media balls on the multilayer ceramic capacitor 1 during barrel polishing.

[0057] As described above, according to this embodiment, the stress generated in the internal electrode layer 5 is evenly distributed and reduced, and the occurrence of cracks due to internal stress in the internal electrode layer 5 can be suppressed, thereby improving the manufacturing yield of the multilayer ceramic capacitor 1.

[0058] This disclosure can be implemented in the following configurations (1) to (6).

[0059] (1) A laminate comprising a plurality of internal electrode layers and a plurality of dielectric layers, wherein the internal electrode layers and the dielectric layers are alternately stacked, Each of the aforementioned plurality of internal electrode layers has a plurality of voids that penetrate the thickness of the internal electrode layer, Each of the plurality of internal electrode layers has a plurality of inner circumferential portions facing the plurality of voids, A multilayer ceramic capacitor in which at least a portion of the plurality of inner circumferences has a flat inner circumference surface.

[0060] (2) The multilayer ceramic capacitor according to (1) above, wherein at least a portion of the flat inner surface is covered by two dielectric layers located on both sides in the thickness direction of the internal electrode layer.

[0061] (3) The plurality of inner circumferential portions, in a cross-sectional view parallel to the thickness direction, 0.15 A multilayer ceramic capacitor according to (1) or (2) above, including a curved surface portion that is convex toward the air gap and has a radius of curvature of μm or more.

[0062] (4) The multilayer ceramic capacitor according to any one of (1) to (3) above, wherein the number of inner circumferential portions having a flat inner surface is 70% or more of the total number of the plurality of inner circumferential portions.

[0063] (5) The multilayer ceramic capacitor according to any one of (1) to (4) above, wherein the flat inner surface is more abundant in the end layers on both ends in the thickness direction of the laminate than in the middle layer of the laminate.

[0064] (6) The multilayer ceramic capacitor according to any one of (1) to (5) above, wherein the flat inner surface increases toward the end layers on both ends in the thickness direction of the laminate compared to the middle layer of the laminate.

[0065] Although embodiments of this disclosure have been described in detail above, this disclosure is not limited to the embodiments described above, and various modifications and improvements are possible without departing from the gist of this disclosure. It goes without saying that all or part of each of the above embodiments can be combined as appropriate and in a non-contradictory manner. [Explanation of Symbols]

[0066] 1. Multilayer ceramic capacitor 2. Base body 3 External electrode 3a Base layer 3b outer layer 4. Dielectric layer 5 Internal electrode layer 6 Protective layer 7a 1st page 7b 2nd side 8a 1st end face 8b 2nd end face 9a 1st side 9b Second side 10 void 11 Inner surface 12 Inner circumference 12a Curved surface 13 Page 1 14. Second edge 15 Side 2 21 Laminate 31 1st external electrode 32 2nd external electrode

Claims

1. The laminate comprises a plurality of internal electrode layers and a plurality of dielectric layers, wherein the internal electrode layers and the dielectric layers are alternately stacked. The thickness of the internal electrode layer is in the range of 0.1 to 1.0 μm. Each of the aforementioned plurality of internal electrode layers has a plurality of voids that penetrate the thickness of the internal electrode layer, Each of the plurality of internal electrode layers has a plurality of inner circumferential portions facing the plurality of voids, Each of the aforementioned plurality of inner circumference portions is tapered toward the gap, At least a portion of the plurality of inner circumferential portions has an inner circumferential surface including a curved surface, The curved surface, in a cross-sectional view parallel to the thickness direction, has a radius of curvature of 0.15 μm or more at the tapered tip portion in contact with the void, and is convex toward the void. A multilayer ceramic capacitor in which the number of inner circumferential portions having an inner circumferential surface including the curved surface is 70% or more of the total number of inner circumferential portions facing the plurality of voids.

2. The multilayer ceramic capacitor according to claim 1, wherein at least a portion of the inner circumferential surface including the curved surface is covered by two dielectric layers located on both sides in the thickness direction of the internal electrode layer.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the inner circumferential surface including the curved surface is more abundant in the end layers on both ends in the thickness direction of the laminate than in the middle layer of the laminate.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein the inner circumferential surface including the curved surface increases toward the end layers on both ends in the thickness direction of the laminate compared to the middle layer of the laminate.

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