Clock synchronization system and method

Abstract

The present disclosure provides a clock synchronization system and method, the clock synchronization system including: a pulse generation module configured to receive an input first signal, obtain a second signal by sampling the first signal, and generate a pulse signal based on the second signal; a voltage controlled oscillator configured to output a first output clock to an output divider module, the pulse generation module, and a synchronous output module; an output divider module configured to divide the first output clock and synchronize the divided clock based on the pulse signal to obtain a second output clock; and a synchronous output module configured to receive the first output clock output from the voltage controlled oscillator, the second output clock output from the output divider module, the first signal, and the pulse signal input from the pulse generation module, and obtain a third signal by synchronously processing the first signal based on the first output clock, the second output clock, and the pulse signal.

Description

Technical Field

[0001] This disclosure claims priority to a Chinese patent application filed with the China National Intellectual Property Administration on November 15, 2021, with an application number of 202111350980.4 and an invention title of "Clock Synchronization System and Method", and all the contents of the Chinese patent application are incorporated herein by reference.

[0002] This disclosure mainly relates to the field of communications, and specifically to clock synchronization systems and methods.

Background Art

[0003] The technology of digital-analog / analog-digital converters has become increasingly mature, and the sampling speeds of analog-digital converters and digital-analog converters of semiconductor companies are several orders of magnitude faster than those of products a decade ago. For example, in 2005, the sampling speed of the fastest digital-analog / analog-digital converter with a 12-bit resolution in the world was 250 MS / s, while in 2018, the sampling speed of 12-bit digital-analog / analog-digital converters reached 6.4 GS / s. Due to these performance improvements, digital-analog / analog-digital converters can directly digitize RF (radio frequency) signals while providing a sufficient dynamic range for modern communication and radar systems.

[0004] With the emergence of ultra-high-speed digital-analog / analog-digital converters with higher resolutions, RF input signals can be directly converted into signals in the order of several gigahertz. Due to these conversion speeds, engineers can digitize with very high instantaneous bandwidths in the L-band and S-band. With the continuous development of digital-analog / analog-digital converters, direct RF sampling in other frequency bands (such as the C-band and X-band) has also begun to be realized.

[0005] The main advantage of direct RF sampling is that it simplifies the RF signal chain, reducing the cost of each channel and the density of channels. Equipment based on a direct RF sampling architecture typically has smaller dimensions and higher power efficiency because it uses fewer analog components. When building high-channel systems, direct RF sampling can reduce the system's footprint and cost. In addition to reduced size, weight, and power, the simplified architecture also eliminates noise, image, and other error sources that may be present within the RF equipment itself, such as local oscillator leakage and quadrature defects. Finally, the direct RF sampling architecture also simplifies synchronization. For example, to achieve phase matching in an RF system, the internal clock of the RF equipment and the local oscillator must be synchronized. With direct sampling, where a local oscillator is unnecessary, only the clock synchronization of the components needs to be considered.

[0006] Currently, wireless communication system chips in RF direct sampling transceivers exhibit relatively large delay jitter deviations, with maximum deviations reaching up to 10 ns. The main causes of such large deviations are delay deviations in the interface and clock domain crossing deviations. Furthermore, in order to balance the reliability of the digital chain design with multiple factors such as power consumption, there are multiple clock domain crossing designs in the chain, which naturally creates a contradiction with reducing delay jitter.

[0007] With increasing market demand for positioning, communication systems are required to have higher latency accuracy, and therefore, improvements in the latency performance of hardware systems are being pursued. To meet the system demands, the latency deviation between multiple power-ups to the system chip must be 1 ns or less. On the other hand, the portion of the clock that specifically allocates the system-level clock accuracy of 1 ns or less to the clock's phase-locked loop (PLL) must be controlled within approximately one cycle of a high-frequency clock. In other words, at a sampling clock frequency of 16 GHz, the latency must be less than 62.5 ps, but in related technologies, the latency deviation between multiple power-ups to the system chip is much larger than 62.5 ps.

[0008] No effective technical solutions have yet been proposed to address problems such as large delay deviations between multiple power-on cycles to the system chip caused by related technologies. [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] In embodiments of this disclosure, a clock synchronization system and method are proposed to solve problems such as large delay deviations between multiple power-on cycles to a system chip, at least according to related technologies. [Means for solving the problem]

[0010] Embodiments of the present disclosure include a pulse generation module, a synchronous output module connected to the pulse generation module, an output frequency divider module connected to the pulse generation module and the synchronous output module, and a voltage-controlled oscillator connected to the pulse generation module, the output frequency divider module and the synchronous output module, wherein the voltage-controlled oscillator is configured to output a first output clock to the output frequency divider module, the pulse generation module and the synchronous output module, the pulse generation module is configured to receive a first signal input from an external source and a first output clock input from the voltage-controlled oscillator, obtain a second signal by sampling the first signal, generate a pulse signal based on the second signal and the first output clock, and output the pulse signal to the output frequency divider module and the synchronous output module, respectively, the output frequency divider module is configured to connect to the pulse generation module or A clock synchronization system has been proposed in which a pulse signal output from the pulse generation module and the first output clock output from the voltage-controlled oscillator are received, the first output clock is divided, and a second output clock is obtained by synchronizing the divided clock based on the pulse signal. The synchronization output module is connected to the output terminal of the pulse generation module and the output terminal of the output frequency divider module, and is configured to receive the first output clock output from the voltage-controlled oscillator, the second output clock output from the output frequency divider module, the first signal input from the outside, and the pulse signal input from the pulse generation module, and to obtain a third signal by synchronizing the first signal based on the first output clock, the second output clock, and the pulse signal, with the third signal and the second output clock being synchronization signals output to the digital-to-analog conversion module, respectively.

[0011] In embodiments of the present disclosure, a clock synchronization method is further proposed, which includes the steps of: inputting a first signal and a first output clock to a pulse generation module, obtaining a second signal by sampling the first signal using the pulse generation module, and generating a pulse signal based on the second signal and the first output clock; inputting the pulse signal and the first output clock to an output frequency divider module, dividing the first output clock using the output frequency divider module, and synchronizing the divided clock based on the pulse signal; and inputting the pulse signal, the first output clock, the second output clock, and the first signal to a synchronization output module, and obtaining a third signal which is a synchronization signal with the second output clock by synchronizing the first signal using the synchronization output module based on the first output clock, the second output clock, and the pulse signal.

[0012] Another embodiment of the present disclosure further proposes a computer-readable storage medium on which a computer program is stored, wherein when the computer program is executed, the steps of any one of the method embodiments described above are performed.

[0013] In another embodiment of the present disclosure, an electronic device is proposed comprising memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the above-described method embodiments.

[0014] In the proposed technology described above, the voltage-controlled oscillator is configured to output a first output clock to the output frequency divider module, the pulse generation module, and the synchronous output module. The pulse generation module is configured to receive a first signal input from an external source and a first output clock input from the voltage-controlled oscillator, obtain a second signal by sampling the first signal, generate a pulse signal based on the second signal, and output the pulse signal to the output frequency divider module and the synchronous output module, respectively. The output frequency divider module receives the pulse signal output from the pulse generation module and the first output clock output from the voltage-controlled oscillator. The synchronous output module is configured to receive a clock, divide the first output clock, and synchronize the divided clock based on the pulse signal. The synchronous output module receives the first output clock output from the voltage-controlled oscillator, the second output clock output from the output divider module, the first signal input from the outside, and the pulse signal input from the pulse generation module. It is configured to acquire a third signal by synchronizing the first signal based on the first output clock, the second output clock, and the pulse signal. The third signal and the second output clock are synchronization signals output to the digital-to-analog conversion module, respectively. According to the above-described technical proposal, problems such as large delay deviations between multiple power-on cycles to the system chip due to related technologies are solved. In this disclosure, a first signal is transmitted from the outside, the output clock of the output divider is synchronized by internal phase-locked loop processing, and the first signal is sampled by the synchronized second output clock and output to another subsystem in the chain, such as an analog-to-digital converter or a digital-to-analog converter. This allows the other subsystem to perform the same synchronization operation as the phase-locked loop, thereby achieving accurate delay functionality for the entire chip.

[0015] The drawings described herein provide further understanding of the Disclosure and constitute part of the Application. Exemplary embodiments and descriptions of the Disclosure are for illustrative purposes only and do not unduly limit the Disclosure. The drawings are as follows: [Brief explanation of the drawing]

[0016] [Figure 1] This is a system block diagram of a clock synchronization system according to an embodiment of the present disclosure. [Figure 2] This is a flowchart of a clock synchronization method according to a selective embodiment of the present disclosure. [Figure 3] This is a receiving block diagram of an RF direct sampling system according to a selective embodiment of the present disclosure. [Figure 4] This invention relates to an architecture for a phase-locked loop circuit with clock synchronization functionality, applicable to an RF direct sampling system according to a selective embodiment of the present disclosure. [Figure 5] This is a block diagram of a pulse generation module according to a selective embodiment of the present disclosure. [Figure 6] This is a block diagram of a synchronous output module according to a selective embodiment of the present disclosure. [Figure 7] This is a block diagram of an output frequency divider module according to a selective embodiment of the present disclosure. [Figure 8] This is a sequence diagram of the synchronization function operation according to a selective embodiment of the present disclosure. [Modes for carrying out the invention]

[0017] The embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments and features referred to herein can be combined with each other, as long as they do not contradict each other.

[0018] Note that in the specification, claims, and the above-described drawings of the present disclosure, terms such as "first," "second," etc. do not indicate a specific order or priority, but are for distinguishing similar objects. The data used in this way should be understood as interchangeable when appropriate for the convenience of the embodiments of the present disclosure described in this specification. Further, terms such as "comprising," "having," and any variations thereof are intended to cover those inclusively and non-exclusively. For example, a process, method, system, product, or device including a series of steps or units is not limited to the explicitly listed steps or units, and may include other steps or units specific to these processes, methods, products, or devices that are not explicitly listed.

[0019] All technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the art, unless otherwise defined. The terms used in the specification of the present disclosure are for the purpose of describing the embodiments for implementing the invention and are not intended to limit the present disclosure.

[0020] In this embodiment, a clock synchronization system is proposed. FIG. 1 is a system block diagram of the clock synchronization system according to an embodiment of the present disclosure. As shown in FIG. 1, such a system includes a pulse generation module 10, a synchronization output module 16 connected to the pulse generation module 10, an output frequency divider module 14 connected to the pulse generation module 10 and the synchronization output module 16, and a voltage controlled oscillator 12 connected to the pulse generation module 10, the synchronization output module 16, and the output frequency divider module 14. The voltage controlled oscillator 12 is configured to output a first output clock to the output frequency divider module 14, the pulse generation module 10, and the synchronization output module 16. The pulse generation module 10 receives a first signal input from the outside and a first output clock input from the voltage control oscillator 12, obtains a second signal by sampling the first signal, generates a pulse signal based on the second signal and the first output clock, and is configured to output the pulse signal to the output frequency divider module 14 and the synchronous output module 16 respectively. The output frequency divider module 14 receives the pulse signal output from the pulse generation module 10 and the first output clock output from the voltage control oscillator 12, divides the first output clock, and is configured to synchronize the divided clock based on the pulse signal. The synchronous output module 16 receives the first output clock output from the voltage control oscillator 12, the second output clock output from the output frequency divider module 14, the first signal input from the outside, and the pulse signal input from the pulse generation module 10, and is configured to obtain a third signal by synchronously processing the first signal based on the first output clock, the second output clock, and the pulse signal. The third signal and the second output clock are synchronous signals output to the digital-to-analog conversion module respectively.

[0021] In the steps described above, the voltage-controlled oscillator 12 is configured to output a first output clock to the output frequency divider module 14, the pulse generation module 10, and the synchronous output module 16. The pulse generation module 10 receives the input first signal and the first output clock input from the voltage-controlled oscillator 12, obtains a second signal by sampling the first signal, generates a pulse signal based on the second signal and the first output clock, and outputs the pulse signal to the output frequency divider module 14 and the synchronous output module 16, respectively. The output frequency divider module 14 receives the pulse signal output from the pulse generation module 10 and the output from the voltage-controlled oscillator 12. The synchronization output module 16 is configured to receive the first output clock that has been generated, divide the first output clock, and synchronize the divided clock based on the pulse signal. The synchronization output module 16 receives the first output clock output from the voltage-controlled oscillator 12, the second output clock output from the output frequency divider module 14, the first signal input from the outside, and the pulse signal input from the pulse generation module 10, and is configured to acquire a third signal by synchronizing the first signal based on the first output clock, the second output clock, and the pulse signal. The third signal and the second output clock are synchronization signals output to the digital-to-analog conversion module, respectively. According to the proposed technology described above, problems such as large delay deviations between multiple power-on cycles to the system chip due to related technologies are resolved. In this disclosure, a first signal is transmitted from an external source, the output clock of the output divider is synchronized by internal phase-locked loop processing, and the first signal is sampled by the synchronized second output clock and output to another subsystem in the chain, such as an analog-to-digital converter or a digital-to-analog converter. This allows the other subsystem to perform the same synchronization operation as the phase-locked loop, thereby achieving accurate delay functionality for the entire chip.

[0022] In one exemplary embodiment, the pulse generation module 10 in a clock synchronization system is a module used to generate a pulse width controllable pulse signal based on a first signal input from an external source, the first signal may be a reference signal or a 10ms periodic signal, and the pulse signal is used to synchronize a first output clock from an output frequency divider with a third signal output from an output sampling circuit, and such a pulse generation module, A delay module configured to acquire the second signal by sampling the first signal, A first sampling circuit module connected to the output terminal of the delay module, configured to receive the second signal output from the delay module and to acquire a fourth signal by sampling the second signal on its rising edge, A module connected to the output terminal of the first sampling circuit module, the first high-frequency sampling circuit module is configured to receive the fourth signal output from the first sampling circuit module and to acquire a fifth signal by sampling the fourth signal based on the first output clock, The present invention includes an exclusive OR circuit module connected to the output terminal of the first high-frequency sampling circuit module, which is configured to receive the fifth signal output from the first high-frequency sampling circuit module and to acquire the pulse signal by performing an exclusive OR operation on the fifth signal.

[0023] In embodiments of the present disclosure, a delay module is configured to acquire a corresponding second signal by sampling the first signal in order to solve the problem of a metastable state that may occur due to the asynchronous relationship between the first signal and the output clock of a voltage-controlled oscillator; a first sampling circuit module is designed to remove the falling edge of the second signal, the purpose of which is to allow the pulse generation module to recognize only the rising edge signal throughout the entire process of the synchronization function; a first high-frequency sampling circuit module is configured such that its sampling clock is a first output clock output from a voltage-controlled oscillator, and it acquires a fifth signal with a fixed phase difference by beating a sampled fourth signal with a rising edge based on the first output clock; and an exclusive OR circuit module is configured to generate a pulse signal of a fixed width by performing an exclusive OR operation on the fifth signal in order to implement an exclusive OR function.

[0024] In one exemplary embodiment, the first high-frequency sampling circuit module includes: a second high-frequency sampling circuit module configured to acquire a sixth signal by sampling the fourth signal based on the first output clock; a third high-frequency sampling circuit module connected to the output terminal of the second high-frequency sampling circuit module, configured to receive the sixth signal output from the second high-frequency sampling circuit module and acquire a seventh signal by sampling the sixth signal based on the first output clock; a fourth high-frequency sampling circuit module connected to the output terminal of the third high-frequency sampling circuit module, configured to receive the seventh signal output from the third high-frequency sampling circuit module and acquire an eighth signal by sampling the seventh signal based on the first output clock; and a fifth high-frequency sampling circuit module connected to the output terminal of the fourth high-frequency sampling circuit module, configured to receive the eighth signal output from the fourth high-frequency sampling circuit module and acquire a ninth signal by sampling the eighth signal based on the first output clock, wherein the fifth signal includes the sixth signal, the seventh signal, the eighth signal, and the ninth signal.

[0025] In other words, the first high-frequency sampling circuit module consists of a second high-frequency sampling circuit module, a third high-frequency sampling circuit module, a fourth high-frequency sampling circuit module, and a fifth high-frequency sampling circuit module. Each of the second, third, fourth, and fifth high-frequency sampling circuit modules samples the fourth signal based on the first output clock (or it may be understood as beating the fourth signal based on the first output clock), thereby acquiring the sixth, seventh, eighth, and ninth signals, and the sixth and ninth signals are input to the exclusive OR circuit module. The roles of the second, third, fourth, and fifth high-frequency sampling circuit modules are selectable. This allows for adjustment of the pulse width of the pulse signal.

[0026] In one exemplary embodiment, the exclusive OR circuit module is a module to which the output terminal of the second high-frequency sampling circuit module and the output terminal of the fifth high-frequency sampling circuit module are connected, and is configured to receive a sixth signal output from the second high-frequency sampling circuit module and a ninth signal output from the fifth high-frequency sampling circuit module, and to acquire the pulse signal by performing an exclusive OR operation on the sixth signal and the ninth signal.

[0027] In other words, the exclusive OR circuit module is configured to generate a fixed-width pulse signal by performing an exclusive OR operation on a first beat and a sixth and ninth signal of a selectable number of beats output thereafter, the width of which is an integer multiple of the period of the output frequency corresponding to the first output signal.

[0028] The basic function of an output frequency divider is to divide a first output signal output from a voltage-controlled oscillator by a predetermined frequency division ratio to generate a second output signal that has been divided. The output frequency divider also has a synchronization function, that is, the synchronization function according to this disclosure acts directly on the output frequency divider. In the embodiments of this disclosure, the specific configuration of the output frequency divider module will be described, and it includes an AND gate module configured to receive a pulse signal output from the pulse generation module and an enable control signal for the output frequency divider module, and to obtain a reset signal for the frequency divider module by performing an AND operation on the enable control signal and the pulse signal, and a module connected to the output terminal of the AND gate module, which is configured to receive a reset signal output from the AND gate module and to determine the second output clock based on the reset signal and the first output clock.

[0029] Specifically, the basic function implemented by the AND gate module is to perform an AND operation on the enable control signal and pulse signal of the output frequency divider. However, from the perspective of synchronization requirements, in actual circuit design, it is necessary to beat the reset signal output using the first output signal output from the voltage-controlled oscillator in order to ensure that the output reset signal is synchronized with the first output signal of the output frequency divider itself. Note that if synchronization is not required for the entire system, or if there is no first signal, it will not affect the output frequency divider to output a normal output signal, and the frequency divider module can consist of multiple frequency divider modules to meet the demand for different frequency divisions. However, from the perspective of synchronization requirements, the frequency divider here needs to have a fixed initial operating state when the power is turned on. When the reset signal is "1", the frequency divider module operates normally, when the reset signal is "0", the frequency divider module outputs at a fixed level, and when the reset signal is switched from "0" to "1", the change state of the frequency divider module from non-operating to normal operation is definitive each time.

[0030] In one exemplary embodiment, the synchronous output module includes: a rising edge sampling module configured to acquire a tenth signal by sampling the first signal on its rising edge; a falling edge sampling module configured to acquire an eleventh signal by sampling the first signal on its falling edge; a sixth high-frequency sampling circuit module connected to the output terminals of the rising edge sampling module and the falling edge sampling module, configured to receive the tenth signal output from the rising edge sampling module or the eleventh signal output from the falling edge sampling module, and to acquire a twelfth signal by sampling the tenth signal or the eleventh signal based on the first output signal; and a first low-frequency sampling module connected to the output terminals of the sixth high-frequency sampling circuit module and the pulse generation module, configured to receive the twelfth signal output from the sixth high-frequency sampling circuit module and a pulse signal input from the pulse generation module, and to acquire a fourth signal by sampling the twelfth signal based on the second output clock and the pulse signal.

[0031] The role of the synchronous output module is to sample the first signal using the second output clock and output it to a digital-to-analog / analog-to-digital converter in the RF direct sampling system. The synchronous output module mainly includes a rising edge / falling edge sampling module 1) which samples the first signal on the rising or falling edge, mainly reducing the non-deterministic delay of synchronization to half a period of the second output clock instead of one period; a high-frequency sampling module 2) which uses the first output signal as its clock, and when the sampling delay by the preceding rising edge / falling edge sampling module is subtracted, the number of beats here becomes exactly the same as the number of beats of the pulse signal, and the same high-frequency clock source is used, thereby ensuring synchronization between the first signal and the pulse signal (it can also be understood as the first signal and the pulse signal having a fixed phase difference); and a low-frequency sampling module 3) which resynchronizes the twelfth signal using the second output signal. Here, the low-frequency sampling module ensures that the delay here and the delay of the output frequency divider are the same, thus reducing the non-deterministic delay. Finally, the first output clock of the output divider is transmitted to the next stage of the RF direct sampling system along with the fourth signal that is synchronized with it.

[0032] In one exemplary embodiment, the first low-frequency sampling module includes a second low-frequency sampling module configured to acquire a 13th signal by sampling the 12th signal based on the second output clock and the pulse signal, and a third low-frequency sampling module connected to the output terminal of the second low-frequency sampling module, configured to receive the 13th signal output from the second low-frequency sampling module and to acquire a 4th signal by sampling the 13th signal based on the second output clock.

[0033] In this embodiment, a clock synchronization method is proposed, and Figure 2 is a flowchart of the clock synchronization method according to an embodiment of the present disclosure, which is performed by the clock synchronization system described above, and includes the following steps S202, S204, and S206.

[0034] In step S202, the first signal and the first output clock are input to a pulse generation module, and the pulse generation module samples the first signal to obtain a second signal, and generates a pulse signal based on the second signal and the first output clock.

[0035] In step S204, the pulse signal and the first output clock are input to the output frequency divider module, the output frequency divider module divides the first output clock, and synchronizes the divided clock based on the pulse signal.

[0036] In step S206, the pulse signal, the first output clock, the second output clock, and the first signal are input to the synchronous output module, and the synchronous output module synchronizes the first signal based on the first output clock, the second output clock, and the pulse signal, thereby obtaining a third signal which is a synchronization signal with the second output clock.

[0037] In the above embodiment, a first signal and a first output clock are input to a pulse generation module, and a second signal is obtained by sampling the first signal using the pulse generation module. A pulse signal is generated based on the second signal and the first output clock. The pulse signal and the first output clock are input to an output frequency divider module, and the output frequency divider module divides the first output clock. The divided clock is synchronized based on the pulse signal. The pulse signal, the first output clock, the second output clock, and the first signal are input to a synchronization output module, and the synchronization output module synchronizes the first signal based on the first output clock, the second output clock, and the pulse signal, thereby obtaining a third signal which is a synchronization signal with the second output clock. According to the proposed technology described above, problems such as large delay deviations between multiple power-on cycles to the system chip due to related technologies are resolved. In this disclosure, a first signal is transmitted from an external source, the output clock of the output divider is synchronized by internal phase-locked loop processing, and the first signal is sampled by the synchronized second output clock and output to another subsystem in the chain, such as an analog-to-digital converter or a digital-to-analog converter. This allows the other subsystem to perform the same synchronization operation as the phase-locked loop, thereby achieving accurate delay functionality for the entire chip.

[0038] More specifically, a pulse signal can be generated based on the second signal by means of inputting the first signal to a delay module, obtaining the second signal by sampling the first signal using the delay module, inputting the second signal to a first sampling circuit module, obtaining a fourth signal by sampling the second signal on its rising edge using the first sampling circuit module, inputting the fourth signal to a first high-frequency sampling circuit module, obtaining a fifth signal by sampling the fourth signal based on the first output clock using the first high-frequency sampling circuit module, and inputting the fifth signal to the exclusive OR circuit module, and obtaining the pulse signal by performing an exclusive OR operation on the fifth signal using the exclusive OR circuit module.

[0039] Selectively, inputting the fifth signal to the exclusive OR circuit module involves the steps of: inputting the first output clock to a second high-frequency sampling circuit module and obtaining a sixth signal by sampling the fourth signal based on the first output clock by the second high-frequency sampling circuit module; inputting the sixth signal to a third high-frequency sampling circuit module and obtaining a seventh signal by sampling the sixth signal based on the first output clock by the third high-frequency sampling circuit module; and inputting the seventh signal to a fourth high-frequency sampling circuit module and obtaining a seventh signal by sampling the sixth signal based on the first output clock by the fourth high-frequency sampling circuit module. The procedure includes the steps of: obtaining an eighth signal by sampling the seventh signal; inputting the eighth signal to a fifth high-frequency sampling circuit module and obtaining a ninth signal by sampling the eighth signal based on the first output clock using the fifth high-frequency sampling circuit module; and inputting the sixth signal and the ninth signal to the exclusive OR circuit module, wherein the fifth signal includes the sixth signal, the seventh signal, the eighth signal, and the ninth signal, and the first high-frequency sampling circuit module includes the second high-frequency sampling circuit module, the third high-frequency sampling circuit module, the fourth high-frequency sampling circuit module, and the fifth high-frequency sampling circuit module.

[0040] In order to better understand the operation process and principles of the clock synchronization system described above, several selective embodiments of the parallel decoding flow will be described below, but this does not limit the technical concepts of the embodiments of this disclosure.

[0041] Example 1 This disclosure proposes a clock synchronization system applicable to RF direct sampling technology. Figure 3 is a receiving block diagram of an RF direct sampling system according to a selective embodiment of this disclosure. As shown in Figure 3, the clock synchronization system according to the embodiment of this disclosure can solve the problem of excessive system clock delay. In this disclosure, a reference signal or a 10ms periodic signal (corresponding to the first signal in the above-described embodiment) is transmitted from an external source, and the first output clock of the output frequency divider (corresponding to the first output signal in the above-described embodiment) is synchronized by internal processing of the phase-locked loop circuit. The reference signal or 10ms periodic signal is sampled by the synchronized second output clock, and the synchronized reference signal or 10ms periodic signal is output to another subsystem in the chain, such as an analog-to-digital converter or a digital-to-analog converter. This allows the other subsystem to perform the same synchronization operation as the phase-locked loop, thereby achieving accurate delay functionality across the entire chip.

[0042] The clock synchronization system according to the embodiments of this disclosure is proposed to meet the low-latency requirements of 5G communication systems, solving the problem of excessive clock delay in superheterodyne and zero-intermediate frequency transceiver systems, thereby significantly improving the performance of 5G communication systems and enhancing the user experience.

[0043] As shown in Figure 4, Figure 4 is an architecture of a phase-locked loop circuit with clock synchronization functionality applied to an RF direct sampling system according to a selective embodiment of the present disclosure, the clock synchronization system according to the embodiment of the present disclosure specifically includes several modules.

[0044] 1. Pulse generation module: Generates a pulse signal with controllable pulse width based on an externally input reference signal or a 10ms periodic signal, and this pulse signal is used to synchronize the first output clock of the output frequency divider and the first signal of the output sampling module. As shown in Figure 5, Figure 5 is a block diagram of a pulse generation module according to a selective embodiment of the present disclosure, and includes the following functional parts.

[0045] 1) Delay Module: This delay unit is designed with an adjustable delay to solve the problem of metastable states that may occur due to asynchronous operation between a reference signal or a 10ms periodic signal and a first output clock output from a voltage-controlled oscillator.

[0046] 2) Sampling circuit module (corresponding to the first sampling circuit in the above-described embodiment): This sampling circuit module is designed to remove the falling edge of a reference signal or a 10ms periodic signal, with the purpose being that the pulse generation module recognizes only rising edges throughout the entire synchronization process.

[0047] 3) High-frequency sampling circuit modules (corresponding to the first high-frequency sampling circuit module in the above-described embodiment) (high-frequency sampling circuit modules 1 to 4) (corresponding to the second, third, fourth, and fifth high-frequency sampling circuit modules in the above-described embodiment): The sampling clock of the high-frequency sampling circuit modules is a first output clock output from a voltage-controlled oscillator, and the roles of high-frequency sampling circuit modules 1 to 4 can be selected by logic control of a sampled reference signal or a 10ms periodic signal, and the pulse width of the pulse signal can be adjusted.

[0048] 4) Exclusive OR Circuit Module: The exclusive OR circuit module implements the exclusive OR function and generates a pulse signal of a predetermined width by performing an exclusive OR operation on a synchronized reference signal or a 10ms periodic signal (corresponding to the fifth signal in the above embodiment).

[0049] 2. Output Divider: The basic function of the output divider is to divide the first output clock output from the voltage-controlled oscillator by a predetermined division ratio to generate a divided second output clock. Here, the output divider also has a synchronization function; in other words, the synchronization function proposed in this disclosure acts directly on the output divider. As shown in Figure 7, Figure 7 is a block diagram of an output divider module according to a selective embodiment of this disclosure, and mainly includes the following functional parts.

[0050] 1) Frequency Divider Modules (Frequency Divider Modules 1-3): The frequency divider modules provide the basic frequency division function. However, due to the need for synchronization, the frequency dividers here must have a fixed initial operating state when the power is turned on. When the reset signal is "1", the frequency divider module operates normally. When the reset signal is "0", the frequency divider module outputs a fixed level. When the reset signal is switched from "0" to "1", the change state of the frequency divider module from non-operating to normal operation is always definitive. Note that frequency divider modules 1-3 are set to achieve different frequency division ratios, and during use, the corresponding frequency divider module should be selected according to the required frequency division ratio.

[0051] 2) AND Gate Module: The basic function of this module is to perform an AND operation on the enable control signal and pulse signal of the output frequency divider. However, in terms of synchronization requirements, in actual circuit design, it is necessary to beat the first output clock to ensure that the output reset signal is synchronized with the first output clock itself. Moreover, this module is designed to ensure that it does not affect the normal clock output by the output frequency divider when synchronization is not required for the entire system, or when no reference signal or 10ms periodic signal is input.

[0052] 3. Synchronized Output Module: The role of this module is to sample a reference signal using the output clock from a synchronized output divider and output it to a digital-to-analog / analog-to-digital converter in an RF direct sampling system. As shown in Figure 6, Figure 6 is a block diagram of a synchronous output module according to a selective embodiment of the present disclosure, and mainly includes the following functional parts.

[0053] 1) Rising / Falling Edge Sampling Module: This module samples a reference signal or a 10ms periodic signal at its rising or falling edge, primarily used to reduce the non-deterministic delay of synchronization to half a period, rather than a full period, of the first output clock.

[0054] 2) High-frequency sampling modules (corresponding to the sixth high-frequency sampling circuit module in the above-described embodiment) (high-frequency sampling modules 1-3): In these sampling modules, the clock used is the first output clock, and after subtracting the sampling delay caused by sampling the reference signal or 10ms periodic signal at the rising / falling edge, the number of beats here becomes exactly the same as the number of beats of the pulse signal, and the same high-frequency clock source is used, thereby ensuring synchronization between the reference signal or 10ms periodic signal and the pulse signal.

[0055] 3) Low-frequency sampling modules (corresponding to the first low-frequency sampling module in the above-described embodiment) (low-frequency sampling modules 4-5) (corresponding to the second and third low-frequency sampling modules in the above-described embodiment): The role of the two low-frequency sampling modules here is to resynchronize the synchronized reference signal or 10ms periodic signal using the second output clock. Here, low-frequency sampling module 4 controls the sampling enable of the pulse signal, ensuring that the delay here and the delay of the output divider are the same, thereby reducing non-deterministic delays. Finally, the synchronous output clock of the output divider is transmitted to the next stage of the RF direct sampling system along with the thereby synchronized reference signal or 10ms periodic signal.

[0056] Example 2 The specific implementation of the clock synchronization system described herein will be explained in more detail by combining the following embodiments. The specific steps 1 to 6 are as follows.

[0057] In step 1, an externally input reference signal or 10ms periodic signal is sampled and synchronized. The externally input reference signal or 10ms periodic signal is driven by an internal buffer and processed into two channels. One channel generates a pulse signal via a pulse generation module, while the other channel outputs the synchronized reference signal or 10ms periodic signal via a synchronous communication DFF module with the same beat rate as the pulse generation module, as shown in Figures 5 and 7.

[0058] In step 2, the pulse generation module generates a pulse signal. As shown in Figure 5, the pulse generation module first removes the quasi-stable state between the reference signal and the first output clock output from the voltage-controlled oscillator by performing a certain sampling process on the input reference signal or 10ms periodic signal, and the maximum delay by this delay module is controlled within one period of the output clock. Next, the falling edge introduced into the reference signal or 10ms periodic signal is removed, only the rising edge is taken, and this rising edge signal is beaten. An exclusive OR operation is performed on the first beat and subsequent beats of a selectable number of beats to generate a fixed-width pulse signal, the width of which is an integer multiple of the output frequency of the first output clock.

[0059] Step 3 involves processing the pulse signal in the frequency divider module. The pulse signal is sent to the OUPTUTDIV module, and a control signal for the output frequency divider is generated by constant logic control and high-frequency clock beating to control the normal operation and enable / disable state of the output frequency divider. The off state of the output frequency divider must be fixed at a certain level, and no uncertainty should exist.

[0060] Specifically, after outputting the pulse signal to the frequency divider module, an AND logic is performed with the enable control signal of the frequency divider module, as shown in Figure 7, to ensure that the control signal is limited to both the pulse signal and the enable control signal. However, before performing this logic operation on the pulse signal, it is necessary to increase the number of controls that can be directly raised to a high level, thereby ensuring that if the pulse signal is not functioning, the enable control of the entire frequency divider is not affected and frequency division can be performed normally. In addition, a reset signal is generated because it is necessary to beat the enable signal to the frequency divider in order to ensure that it is a synchronization signal.

[0061] Step 4 involves processing the pulse signal in the synchronous output module. A pulse signal is output to the synchronous output module to reset the low-frequency sampling circuit (as shown in Figure 6), and the low-frequency sampling module 4 remains inactive throughout the entire process while the pulse signal is at a low level. This is to prevent the reference signal from being sampled by the output clock before synchronization by the output divider. To ensure that the synchronized output clock by the output divider can always sample the reference signal, two output sampling circuits are designed (as shown in Figure 6): the low-frequency sampling module 4 and the low-frequency sampling module.

[0062] Step 5 is enable control of the frequency divider module by a reset signal. When the reset signal acts on the frequency divider module, it can output a synchronized second output clock. The design of the core frequency divider in the output frequency divider requires, on the one hand, ensuring accurate frequency division at high frequencies, and more importantly, for this disclosure, the level of each node should be deterministic, either high or low, when the frequency divider enable is turned off, and no non-deterministic levels should exist, preventing non-deterministic initial states from appearing when the frequency divider enable is turned on next.

[0063] In step 6, the synchronized reference signal is sampled using the synchronization clock output from the output frequency divider. The synchronized output clock from the output frequency divider is used as the sampling clock for the low-frequency sampling module 4 and the low-frequency sampling module 5 in Figure 6, and the reference signal is sampled and output, which is then output to the digital-to-analog / analog-to-digital converter.

[0064] This completes the entire clock synchronization function. Example 3 The following example illustrates how to achieve accurate delay functionality in a phase-locked loop, using the case where the output frequency divider operates at a 2-division rate.

[0065] As shown in Figure 8, the first output clock output from the voltage-controlled oscillator functions as the reference clock for the entire synchronization function. When the first reference signal or the first 10ms periodic signal is input, the first output clock asynchronously samples the first reference signal or the first 10ms periodic signal and obtains a synchronized second reference signal or second 10ms periodic signal (corresponding to the second signal in the embodiment described above) by sampling on the next rising edge. A synchronization pulse signal is generated using the second reference signal or the second 10ms periodic signal. A reset signal is generated for the output divider with the pulse width of the pulse signal, turning off the output of the output divider, and when the reset signal is emitted, all output dividers start from a fixed level at the same time. All of these initial operating states are fixed and do not change with the structure of the divider and the clock frequency, and the off time of the divider is controlled only by the pulse width of the pulse signal.

[0066] If the output divided clock turns on at a fixed level and starts at a definite time after the reset signal of the frequency divider is emitted, then the output divided clock and the second reference signal or second 10ms periodic signal have a fixed phase relationship, and the first output clock can be considered to be synchronized with the second reference signal or second 10ms periodic signal, and in this way the second output clock can be obtained.

[0067] As is clear from Figure 8, by sampling a second reference signal or a second 10ms periodic signal based on the second output clock, a third reference signal or a third 10ms periodic signal and a fourth reference signal or a fourth 10ms periodic signal are obtained. A stable synchronization relationship is established between the fourth reference signal or fourth 10ms periodic signal and the second output clock, and the fourth reference signal or fourth 10ms periodic signal and the second output clock are output as a pair to the next-stage subsystem, such as a digital-to-analog / analog-to-digital converter. In the subsystem, such as the digital-to-analog / analog-to-digital converter, the same synchronization function is used, and thus all first-level clocks are synchronized to a precise delay by the reference signal or 10ms periodic signal, enabling accurate delay functionality for the entire RF direct sampling system.

[0068] In the embodiments of this disclosure, the pulse signal generation method by the pulse generation module is realized by a high-frequency clock beat. The advantage of this is that it is possible to obtain pulses with a fixed width and controllable properties, and moreover, the pulse signal and the clock are synchronized. The purpose of generating a pulse signal and a control signal for a frequency divider can also be achieved by performing an exclusive OR operation on different delays of a reference signal or a 10ms periodic signal. However, the delay of the pulse signal itself generated in this way is non-deterministic, and moreover, the non-deterministic delay increases as the process angle, high / low temperature, and power supply voltage conditions change. This disclosure includes an application in which a pulse signal is used to enable the low-frequency sampling module 4 in Figure 6. In practice, it is possible to prevent the sampling phenomenon of the reference signal by the clock before synchronization by using a large number of delay units. However, if a delay exceeding one period of the voltage-controlled oscillator is achieved using a large number of delay units, a non-deterministic delay of the reference signal is introduced, which becomes even more serious under power supply voltage.

[0069] The foregoing are merely preferred embodiments of the Disclosure and do not limit the Disclosure, and those skilled in the art can make various modifications and changes to the Disclosure. Any amendments, equivalent substitutions, improvements, etc., made without departing from the principles of the Disclosure shall be included within the scope of the Disclosure.

Claims

1. It is a clock synchronization system, The system includes a pulse generation module, a synchronous output module connected to the pulse generation module, an output frequency divider module connected to the pulse generation module and the synchronous output module, and a voltage-controlled oscillator connected to the pulse generation module, the output frequency divider module and the synchronous output module. The voltage-controlled oscillator is configured to output a first output clock to the output frequency divider module, the pulse generation module, and the synchronous output module. The pulse generation module is configured to receive a first signal input from an external source and a first output clock input from the voltage-controlled oscillator, obtain a second signal by sampling the first signal, generate a pulse signal based on the second signal and the first output clock, and output the pulse signal to the output frequency divider module and the synchronous output module, respectively, wherein the first signal is a reference signal or a periodic signal. The output frequency divider module is configured to receive the pulse signal output from the pulse generation module and the first output clock output from the voltage-controlled oscillator, divide the first output clock, and obtain a second output clock by synchronizing the divided clock with the pulse signal. The synchronous output module is configured to receive a first output clock output from the voltage-controlled oscillator, a second output clock output from the output frequency divider module, a first signal input from the outside, and a pulse signal input from the pulse generation module, and to obtain a third signal by synchronously processing the first signal with the first output clock, the second output clock, and the pulse signal. The pulse signal and the first output clock are synchronous signals, the first output clock and the second output clock are synchronous signals, the third signal and the second output clock are synchronous signals, and the third signal and the second output clock are output to the digital-to-analog conversion module, respectively. Clock synchronization system.

2. The pulse generation module is A delay module configured to acquire the second signal by sampling the first signal, A first sampling circuit module connected to the output terminal of the delay module, configured to receive the second signal output from the delay module and to acquire a fourth signal by sampling the second signal on its rising edge, A module connected to the output terminal of the first sampling circuit module, the first high-frequency sampling circuit module is configured to receive the fourth signal output from the first sampling circuit module and to acquire a fifth signal by sampling the fourth signal based on the first output clock, A module connected to the output terminal of the first high-frequency sampling circuit module, comprising an exclusive OR circuit module configured to receive the fifth signal output from the first high-frequency sampling circuit module and to acquire the pulse signal by performing an exclusive OR operation on the fifth signal, The clock synchronization system according to claim 1.

3. The first high-frequency sampling circuit module is A second high-frequency sampling circuit module is configured to acquire a sixth signal by sampling the fourth signal based on the first output clock, A third high-frequency sampling circuit module, connected to the output terminal of the second high-frequency sampling circuit module, is configured to receive the sixth signal output from the second high-frequency sampling circuit module and to acquire a seventh signal by sampling the sixth signal based on the first output clock, A fourth high-frequency sampling circuit module, connected to the output terminal of the third high-frequency sampling circuit module, configured to receive the seventh signal output from the third high-frequency sampling circuit module and to acquire an eighth signal by sampling the seventh signal based on the first output clock, The present invention includes a fifth high-frequency sampling circuit module, which is connected to the output terminal of the fourth high-frequency sampling circuit module and is configured to receive the eighth signal output from the fourth high-frequency sampling circuit module and to acquire a ninth signal by sampling the eighth signal based on the first output clock, The fifth signal is the sixth signal and the ninth signal. The clock synchronization system according to claim 2.

4. The exclusive OR circuit module is a module to which the output terminal of the second high-frequency sampling circuit module and the output terminal of the fifth high-frequency sampling circuit module are connected, and is configured to receive the sixth signal output from the second high-frequency sampling circuit module and the ninth signal output from the fifth high-frequency sampling circuit module, and to acquire the pulse signal by performing an exclusive OR operation on the sixth signal and the ninth signal. The clock synchronization system according to claim 3.

5. The output frequency divider module is, An AND gate module is configured to receive a pulse signal output from the pulse generation module and an enable control signal from the output frequency divider module, and to obtain a reset signal from the frequency divider module by performing an AND operation on the enable control signal and the pulse signal. A frequency divider module connected to the output terminal of the AND gate module, which is configured to receive a reset signal output from the AND gate module and to determine a second output clock based on the reset signal and the divided first output clock, The clock synchronization system according to claim 1.

6. The aforementioned synchronous output module is A rising edge sampling module configured to acquire a tenth signal by sampling the first signal at its rising edge, A falling edge sampling module configured to acquire an eleventh signal by sampling the first signal at its falling edge, A sixth high-frequency sampling circuit module connected to the output terminal of the rising edge sampling module and the output terminal of the falling edge sampling module, configured to receive a 10th signal output from the rising edge sampling module or an 11th signal output from the falling edge sampling module, and to acquire a 12th signal by sampling the 10th signal or the 11th signal based on the first output clock, A module connected to the output terminal of a sixth high-frequency sampling circuit module and the output terminal of the pulse generation module, the first low-frequency sampling module is configured to receive the 12th signal output from the sixth high-frequency sampling circuit module and the pulse signal input from the pulse generation module, and to acquire a third signal by sampling the 12th signal based on the second output clock and the pulse signal, The clock synchronization system according to claim 1.

7. The first low-frequency sampling module is, A second low-frequency sampling module is configured to acquire a 13th signal by sampling the 12th signal based on the second output clock and the pulse signal, A third low-frequency sampling module is connected to the output terminal of the second low-frequency sampling module and is configured to receive a 13th signal output from the second low-frequency sampling module and to acquire a third signal by sampling the 13th signal based on the second output clock, The clock synchronization system according to claim 6.

8. A clock synchronization method for a clock synchronization system according to any one of claims 1 to 7, A step of inputting a first signal input from an external source and a first output clock input from a voltage-controlled oscillator to a pulse generation module, obtaining a second signal by sampling the first signal using the pulse generation module, and generating a pulse signal based on the second signal and the first output clock, wherein the first signal is a reference signal or a periodic signal. The steps include: inputting the pulse signal and the first output clock to the output frequency divider module, dividing the first output clock by the output frequency divider module, and obtaining a second output clock by synchronizing the divided clock with the pulse signal; A step of inputting the pulse signal, the first output clock, the second output clock, and the first signal to the synchronous output module, and obtaining a third signal by synchronizing the first signal with the first output clock, the second output clock, and the pulse signal by the synchronous output module, wherein the pulse signal and the first output clock are synchronous signals, the first output clock and the second output clock are synchronous signals, and the third signal and the second output clock are synchronous signals. A clock synchronization method, including...

9. The steps of inputting a first signal to a pulse generation module, obtaining a second signal by sampling the first signal using the pulse generation module, and generating a pulse signal based on the second signal are as follows: The steps include inputting the first signal to a delay module and obtaining the second signal by sampling the first signal using the delay module, The steps include inputting the second signal to a first sampling circuit module and obtaining a fourth signal by sampling the second signal on its rising edge using the first sampling circuit module, The steps include inputting the fourth signal to a first high-frequency sampling circuit module and obtaining a fifth signal by sampling the fourth signal based on the first output clock using the first high-frequency sampling circuit module, The process includes the step of inputting the fifth signal to an exclusive OR circuit module and obtaining the pulse signal by performing an exclusive OR operation on the fifth signal using the exclusive OR circuit module, The clock synchronization method according to claim 8.

10. Inputting the fifth signal to the exclusive OR circuit module means The steps include inputting the first output clock to a second high-frequency sampling circuit module and obtaining a sixth signal by sampling the fourth signal based on the first output clock using the second high-frequency sampling circuit module, The steps include inputting the sixth signal to a third high-frequency sampling circuit module and obtaining a seventh signal by sampling the sixth signal based on the first output clock using the third high-frequency sampling circuit module, The steps include inputting the seventh signal to a fourth high-frequency sampling circuit module and obtaining an eighth signal by sampling the seventh signal based on the first output clock using the fourth high-frequency sampling circuit module, The steps include inputting the eighth signal to a fifth high-frequency sampling circuit module and obtaining a ninth signal by sampling the eighth signal based on the first output clock using the fifth high-frequency sampling circuit module, The steps include inputting the sixth signal and the ninth signal to the exclusive OR circuit module, The fifth signal is the sixth signal and the ninth signal, The first high-frequency sampling circuit module includes the second high-frequency sampling circuit module, the third high-frequency sampling circuit module, the fourth high-frequency sampling circuit module, and the fifth high-frequency sampling circuit module. The clock synchronization method according to claim 9.

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