Semiconductor equipment

Abstract

To provide a novel semiconductor device.SOLUTION: A semiconductor device including an oxide semiconductor which is a first semiconductor, a silicon which is a second semiconductor, and a plurality of memory cells connected in a first direction, in which one memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, and a part of the first semiconductor functions as a channel formation region of the writing transistor, and a part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, method, or method of manufacture. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Therefore, semiconductor elements such as transistors and diodes, as well as circuits containing semiconductor elements, are semiconductor devices. Display devices, light-emitting devices, illumination devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also include semiconductor elements or semiconductor circuits. Display devices, light-emitting devices, illumination devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also be referred to as semiconductor devices. [Background technology]

[0004] In recent years, with the increasing amount of data being handled, there has been a demand for semiconductor devices with larger storage capacities. To increase storage capacity per unit area, three-dimensional memory devices formed by stacking memory cells are known (Patent Document 1). In three-dimensional memory devices, semiconductor layers are often provided extending in the direction of stacking the memory cells. Furthermore, in three-dimensional memory devices, semiconductors containing many grain boundaries, such as polycrystalline silicon, are often used for the semiconductor layers.

[0005] Since polycrystalline silicon has many grain boundaries, it is difficult to improve the operating speed and reduce the variation in characteristics between memory cells. For the purpose of reducing grain boundaries and increasing the grain size, a crystallization technique for producing crystalline silicon using a catalyst element such as nickel (Ni) is known (Patent Document 2). Patent Document 2 also discloses the growth mechanism of crystals using a catalyst element and the technical idea of fixing the catalyst element used for crystallization in a gettering region.

[0006] Patent Document 3 discloses the technical idea of applying a crystallization technique using a catalyst element to a memory device having a three-dimensional structure. In recent years, an oxide semiconductor, which is a kind of metal oxide, has attracted attention. Non-Patent Document 1 discloses CAAC-IGZO as an oxide semiconductor. Non-Patent Document 1 also discloses the growth mechanism of CAAC-IGZO and the like.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0008]

Non-Patent Document 1

Summary of the Invention

[0009] One embodiment of the present invention aims to provide a highly reliable storage device. Alternatively, it aims to provide a storage device with a large storage capacity. Alternatively, it aims to provide a storage device with a small footprint. Alternatively, it aims to provide a storage device with a fast operating speed. Alternatively, it aims to provide a storage device with low manufacturing costs. Alternatively, it aims to provide a novel storage device. Alternatively, it aims to provide a highly reliable semiconductor device. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device with a fast operating speed. Alternatively, it aims to provide a semiconductor device with low manufacturing costs. Alternatively, it aims to provide a novel semiconductor device.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising a first semiconductor extending in a first direction, a second semiconductor extending in a first direction, and a plurality of memory cells connected in a first direction, wherein each memory cell comprises a first transistor and a second transistor, a portion of the first semiconductor functioning as a channel formation region of the first transistor, a portion of the second semiconductor functioning as a channel formation region of the second transistor, the first semiconductor including an oxide semiconductor, the second semiconductor including silicon, the second semiconductor including a region in contact with the first layer, and the first layer including a first metal element.

[0012] Another aspect of the present invention is a semiconductor device comprising a structure extending in a first direction, a plurality of first conductors extending in a second direction intersecting the first direction, and a plurality of second conductors extending in the second direction, wherein the structure comprises a third conductor, a first insulator, a plurality of fourth conductors, a first semiconductor, a second insulator, a second semiconductor, and a third insulator, wherein at each intersection of the plurality of first conductors and the structure, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically on the outside of the third conductor, and at each intersection of the plurality of second conductors and the structure, the first insulator, the fourth conductor, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically on the outside of the third conductor, the first semiconductor includes an oxide semiconductor, the second semiconductor includes silicon, the second semiconductor has a region in contact with the first layer, and the first layer includes a first metal element.

[0013] The first metallic element is an element that functions as a catalytic element. For example, nickel can be used as the first metallic element. The first layer may also contain impurity elements such as phosphorus.

[0014] The oxide semiconductor preferably contains at least one of indium or zinc. In particular, it is preferable that it contains both indium and zinc. Furthermore, various crystalline oxide semiconductors, such as CAAC-OS, nc-OS, and a-like OS, can be used as the oxide semiconductor. [Effects of the Invention]

[0015] One embodiment of the present invention can provide a highly reliable storage device, or a storage device with a large storage capacity, or a storage device with a small footprint, or a storage device with a fast operating speed, or a storage device with a low manufacturing cost, or a novel storage device, or a highly reliable semiconductor device, or a semiconductor device with a small footprint, or a semiconductor device with a fast operating speed, or a semiconductor device with a low manufacturing cost, or a novel semiconductor device.

[0016] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0017] [Figure 1] Figure 1 is a perspective view of the storage device. [Figure 2] Figure 2 is a cross-sectional view of the memory device. [Figure 3] Figure 3 is a cross-sectional view of a memory string. [Figure 4] Figure 4 is a cross-sectional view of a memory string. [Figure 5] Figures 5A and 5B are cross-sectional views of the memory string. [Figure 6] Figures 6A and 6B are cross-sectional views of the memory string. [Figure 7] Figure 7A is a cross-sectional view of the memory element. Figure 7B is a perspective cross-sectional view of the memory element. [Figure 8] Figures 8A and 8B are cross-sectional views of the memory string. [Figure 9]Figures 9A to 9F are cross-sectional views of a memory string. [Figure 10] Figures 10A and 10B are cross-sectional views of the memory string. [Figure 11] Figure 11A illustrates the classification of the crystal structure of oxide semiconductors. Figure 11B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 11C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 12] Figures 12A to 12C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 13] Figures 13A to 13C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 14] Figures 14A to 14C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 15] Figures 15A to 15C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 16] Figures 16A to 16C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 17] Figures 17A to 17C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 18] Figures 18A to 18C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 19] Figures 19A to 19C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 20] Figures 20A to 20C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 21] Figures 21A to 21C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 22] Figures 22A to 22C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 23]Figures 23A to 23C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 24] Figures 24A to 24C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 25] Figures 25A to 25D are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 26] Figures 26A to 26C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 27] Figures 27A to 27C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 28] Figures 28A to 28C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 29] Figures 29A to 29C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 30] Figures 30A to 30C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 31] Figures 31A to 31C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 32] Figures 32A to 32C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 33] Figures 33A to 33C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 34] Figures 34A to 34C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 35] Figure 35 illustrates an example of a memory string circuit configuration. [Figure 36] Figure 36 is an equivalent circuit diagram of the memory element MC. [Figure 37] Figure 37 illustrates an example of a memory string circuit configuration. [Figure 38]Figure 38 illustrates an example of a memory string circuit configuration. [Figure 39] Figure 39 is a timing chart illustrating an example of a memory string write operation. [Figure 40] Figures 40A and 40B are circuit diagrams illustrating an example of memory string writing operation. [Figure 41] Figures 41A and 41B are circuit diagrams illustrating an example of memory string writing operation. [Figure 42] Figures 42A and 42B are circuit diagrams illustrating an example of memory string writing operation. [Figure 43] Figures 43A and 43B are circuit diagrams illustrating an example of memory string writing operation. [Figure 44] Figures 44A and 44B are timing charts illustrating an example of a memory string read operation. [Figure 45] Figures 45A and 45B are circuit diagrams illustrating an example of memory string read operation. [Figure 46] Figures 46A and 46B are circuit diagrams illustrating an example of memory string read operation. [Figure 47] Figures 47A and 47B illustrate the Id-Vg characteristics of a transistor. [Figure 48] Figure 48 is a block diagram illustrating an example configuration of a semiconductor device. [Figure 49] Figures 49A to 49C are perspective views illustrating an example of a semiconductor device configuration. [Figure 50] Figure 50 is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 51] Figures 51A to 51E illustrate an example of a storage device. [Figure 52] Figures 52A to 52G are diagrams illustrating an example of an electronic device. [Modes for carrying out the invention]

[0018] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and the repetition of their descriptions is omitted.

[0019] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings. For example, in the actual manufacturing process, resist masks and other materials may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for the sake of ease of understanding.

[0020] Furthermore, in drawings and other diagrams, some components may be omitted from the description to make the explanation easier to understand.

[0021] Furthermore, the terms "electrode" and "wiring" in this specification do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wiring" are formed as a single unit.

[0022] Furthermore, in this specification, the term "terminal" in an electrical circuit refers to a part where current is input or output, voltage is input or output, or a signal is received or transmitted. Therefore, a part of the wiring or electrode may function as a terminal.

[0023] In this specification, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0024] Furthermore, the functions of source and drain can be interchanged depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to definitively determine which is the source and which is the drain. For this reason, in this specification, the terms source and drain may be used interchangeably.

[0025] Furthermore, in this specification, "electrically connected" includes both direct connections and connections made via "something that has some electrical function." Here, "something that has some electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in a real circuit there may be no physical connection point, and only wiring may extend.

[0026] Furthermore, in this specification, "parallel" refers to a state in which, for example, two straight lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" refer to a state in which, for example, two straight lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0027] In this specification and other documents, when referring to count values ​​and measured values, or to objects, methods, and events that can be converted to count values ​​or measured values, terms such as "identical," "same," "equal," or "uniform" shall include an error margin of plus or minus 20%, unless otherwise explicitly stated.

[0028] Furthermore, in this specification, the terms "adjacent" and "proximity" are not limited to direct contact between components. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B be formed in direct contact, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0029] Furthermore, voltage often refers to the potential difference between a given potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential are considered interchangeable.

[0030] Even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it will possess the properties of an "insulator." Therefore, it is possible to replace "semiconductor" with "insulator." In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and a strict distinction between the two is difficult. Consequently, "semiconductor" and "insulator" as used herein may be interchangeable.

[0031] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently high, it will possess the properties of a "conductor." Therefore, it is possible to replace "semiconductor" with "conductor." In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and a strict distinction between the two is difficult. Consequently, "semiconductor" and "conductor" as used herein may be interchangeable.

[0032] Furthermore, ordinal numbers such as "first," "second," etc., in this specification are added to avoid confusion of constituent elements and do not indicate any order or rank, such as process order or layering order. In addition, even if an ordinal number is not used for a term in this specification, an ordinal number may be used in the claims to avoid confusion of constituent elements. In addition, even if an ordinal number is used for a term in this specification, a different ordinal number may be used in the claims. In addition, even if an ordinal number is used for a term in this specification, the ordinal number may be omitted in the claims, etc.

[0033] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited (also called the "conducting state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically disconnected (also called the "non-conducting state").

[0034] Furthermore, in this specification, "on-current" may refer to the current flowing between the source and drain when the transistor is in the "on" state. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is in the "off" state.

[0035] Furthermore, in this specification, the high power supply potential VDD (hereinafter also simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS," "L potential," or "L"). Also, VSS refers to a power supply potential that is lower than VDD. In addition, the ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, if VDD is the ground potential, then VSS is a potential lower than the ground potential, and if VSS is the ground potential, then VDD is a potential higher than the ground potential.

[0036] Furthermore, unless otherwise specified, the transistors described herein are enhancement-type (normally-off type) n-channel field-effect transistors. Therefore, their threshold voltage (also called "Vth") shall be greater than 0V. Also, unless otherwise specified, "supplying a high potential to the gate of the transistor" may be synonymous with "turning the transistor ON." Also, unless otherwise specified, "supplying a low potential to the gate of the transistor" may be synonymous with "turning the transistor OFF."

[0037] Furthermore, in this specification, "gate" refers to the gate electrode and part or all of the gate wiring. Gate wiring refers to wiring that electrically connects the gate electrode of at least one transistor to another electrode or another wire.

[0038] Furthermore, in this specification, "source" refers to a source region, a source electrode, and part or all of the source wiring. The source region refers to a region of the semiconductor layer whose resistivity is below a certain value. The source electrode refers to the conductive layer in the portion connected to the source region. The source wiring refers to wiring used to electrically connect the source electrode of at least one transistor to another electrode or another wiring.

[0039] Furthermore, in this specification, "drain" refers to a drain region, a drain electrode, and part or all of the drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is below a certain value. The drain electrode refers to the conductive layer in the portion connected to the drain region. The drain wiring refers to wiring used to electrically connect the drain electrode of at least one transistor to another electrode or another wiring.

[0040] Furthermore, in drawings and other diagrams, to make the potential of wiring, electrodes, or conductors easier to understand, a "H" indicating a high potential or a "L" indicating a low potential may be added adjacent to the wiring, electrodes, or conductors. In addition, a "H" or "L" enclosed in a box may be added to wiring, electrodes, or conductors where a potential change has occurred. Also, if a transistor is in the off state, an "×" symbol may be added superimposed on the transistor.

[0041] Furthermore, generally speaking, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitive element" includes the case of the aforementioned "capacitance." That is, in this specification, the term "capacitive element" includes cases in which two electrodes face each other with an insulator in between, cases in which two wires face each other with an insulator in between, or cases in which two wires are arranged with an insulator in between.

[0042] Furthermore, in this specification, when the same reference numeral is used for multiple elements, and it is particularly necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "a", "A", "_1", "_2", "[m,n]", etc. For example, one of two wiring GLs may be described as wiring GLa and the other as wiring GLb.

[0043] (Embodiment 1) Figure 1 shows a perspective view of a memory device 100 according to one aspect of the present invention. The memory device 100 is a memory device having a three-dimensional stacked structure. Figure 2 is a cross-sectional view of the area A1-A2 shown by the dashed line in Figure 1. Note that in Figure 1 and other figures, arrows indicating the X, Y, and Z directions may be added. The X, Y, and Z directions are mutually orthogonal directions. In this specification and other documents, the direction perpendicular to the upper surface of the substrate 121, which will be described later, is defined as the Z direction.

[0044] Furthermore, in this specification and other documents, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0045] Figure 2 shows a cross-section in the XZ plane. As mentioned above, some components may be omitted in Figures 1 and 2, etc., for the sake of clarity.

[0046] <Example of storage device configuration> A memory device 100 according to one aspect of the present invention has a memory cell array 110 (see Figure 1). The memory cell array 110 has a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane. Figure 3 shows an example of the cross-sectional configuration of the memory strings 120.

[0047] The memory string 120 comprises multiple memory elements MC (also called "memory cells") connected in the Z direction. In other words, the memory string 120 comprises multiple memory elements MC connected in series. Figure 3 shows the case where five memory elements MC are connected in series, but the number of memory elements MC in the memory string 120 is not limited to five. If the number of memory elements MC in the memory string 120 is n, then n can be an integer of 2 or greater.

[0048] In Figure 3, the five memory elements MC are shown as memory element MC_1 to memory element MC_5. When describing aspects common to memory elements MC_1 to MC_5, they are simply referred to as "memory element MC." The same applies to other components such as conductor WWL, conductor RWL, and insulator 123.

[0049] The memory string 120 includes a transistor STr1 that is electrically connected to the memory element MC_1, and a transistor STr2 that is electrically connected to the memory element MC_5.

[0050] Furthermore, the memory device 100 has a plurality of conductors WWL, a plurality of conductors RWL, and a conductor SG above the substrate 121. The plurality of conductors WWL, a plurality of conductors RWL, and a conductor SG extend in the X direction (see Figures 1 and 2). The conductors WWL, RWL, and SG also have regions that overlap with the memory cell array 110. The conductors WWL, RWL, and SG are stacked in a stepped manner outside the memory cell array 110.

[0051] The conductor SG is provided in a layer below multiple conductors WWL and multiple conductors RWL. In Figure 3, layer 122 is provided on the substrate 121, insulator 123_1 is provided on layer 122, and conductor SG is provided on insulator 123_1. Furthermore, the conductors WWL and conductors RWL are provided in alternating layers via insulator 123. For example, in Figure 3, insulator 123_2 is provided on conductor SG, conductor RWL_1 is provided on insulator 123_2, insulator 123_3 is provided on conductor RWL_1, conductor WWL_1 is provided on insulator 123_3, and insulator 123_4 is provided on conductor WWL_1. As will be described in detail later, layer 122 functions as a gettering layer.

[0052] The memory string 120 has a structure 160. The structure 160 is provided so as to penetrate the conductor WWL, conductor RWL, conductor SG, and insulator 123. The structure 160 also has a region in contact with layer 122. An example of the cross-sectional configuration of the structure 160 is shown in Figure 4. Note that Figures 4 and 3 are cross-sectional views of the same part. In Figure 4, the conductor WWL, conductor RWL, conductor SG, insulator 123, layer 122, and substrate 121 are shown by dashed lines.

[0053] The structure 160 has a columnar structure including a conductor 130, an insulator 129, a semiconductor 127, an insulator 126, a semiconductor 125, an insulator 124, and a plurality of conductors 128. In Figure 4, the central axis 169 of the memory string 120 extending in the Z direction is shown by a dashed line. More specifically, the conductor 130 extends along the central axis 169, and the insulator 129 is provided adjacent to the side surface of the conductor 130. The semiconductor 127 is provided adjacent to the insulator 129, and the insulator 126 is provided adjacent to the semiconductor 127. The semiconductor 125 is provided adjacent to the insulator 126, and the insulator 124 is provided adjacent to the semiconductor 125. The semiconductor 125 has a region in contact with layer 122. Furthermore, at the intersection of the conductor RWL and the structure 160, a conductor 128 is provided between the insulator 129 and the semiconductor 127.

[0054] Figure 5A shows a cross-sectional view of the area B1-B2, indicated by the dashed line in Figure 3, as seen from the Z direction. Figure 5A is a cross-sectional view of the intersection of the conductor WWL and the structure 160. At this intersection, the insulator 129, semiconductor 127, insulator 126, semiconductor 125, and insulator 124 are each provided concentrically on the outside of the conductor 130.

[0055] Figure 5B shows a cross-sectional view of the area C1-C2, indicated by the dashed line in Figure 3, as seen from the Z direction. Figure 5B is a cross-sectional view of the intersection of the conductor RWL and the structure 160. At this intersection, the insulator 129, conductor 128, semiconductor 127, insulator 126, semiconductor 125, and insulator 124 are each provided concentrically on the outside of the conductor 130.

[0056] Figures 5A and 5B illustrate the cross-section (XY cross-section) of a single memory string 120, while Figures 6A and 6B show examples where multiple memory strings 120 are provided. The multiple memory strings 120 may be arranged side by side in the X direction, side by side in the Y direction, or in a matrix.

[0057] Figure 7A shows an enlarged view of the region 105 indicated by the dashed line in Figure 3. Figure 7A corresponds to a cross-sectional view of the memory element MC. Figure 7B shows a perspective cross-sectional view of the memory element MC. Note that the insulator 123 is omitted in Figure 7B to make the structure of the memory element MC easier to understand.

[0058] The intersection of the conductor WWL and the structure 160 functions as a transistor WTr. Similarly, the intersection of the conductor RWL and the structure 160 functions as a transistor RTr. Specifically, the conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the back gate electrode of the transistor WTr. Furthermore, a portion of the semiconductor 127 functions as the semiconductor layer where the channel of the transistor WTr is formed. The semiconductor layer where the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via portions of the insulator 126, semiconductor 125, and insulator 124. While this embodiment shows an example where a portion of the conductor WWL functions as the gate electrode, the gate electrode and the conductor WWL may be provided independently and electrically connected.

[0059] Conductor 128 functions as the gate electrode of transistor RTr. Conductor RWL functions as the back gate electrode of transistor RTr. A portion of semiconductor 125 functions as the semiconductor layer where the channel of transistor RTr is formed. The semiconductor layer where the channel of transistor RTr is formed overlaps with the gate electrode (conductor 128) via a portion of insulator 126. The semiconductor layer where the channel of transistor RTr is formed also overlaps with the back gate electrode (conductor RWL) via a portion of insulator 124. In this embodiment, an example is shown where a portion of conductor RWL functions as the back gate electrode, but the back gate electrode and conductor RWL may be provided independently and electrically connected to each other.

[0060] Furthermore, dividing the memory string 120 along the Z direction is preferable because it increases the storage capacity per unit area. When dividing the memory string 120 along the Z direction, the conductor WWL and conductor RWL may also be divided.

[0061] Figure 8A shows how the conductor WWL and the memory string 120 are separated by an insulator 153 provided along the XZ plane, and Figure 8B shows how the conductor RWL and the memory string 120 are separated by an insulator 153 provided along the XZ plane. Note that Figure 8A corresponds to a modified example of the cross-section shown in Figure 5A, and Figure 8B corresponds to a modified example of the cross-section shown in Figure 5B. In Figure 8 and other figures, the reference numerals of the separated components are suffixed with a or b.

[0062] As shown in Figure 8A, the region where conductor WWL_a and conductor 130_a overlap functions as transistor WTr_a. Specifically, the region where conductor WWL_a, insulator 124_a, semiconductor 125_a, insulator 126_a, semiconductor 127_a, insulator 129_a, and conductor 130_a overlap functions as transistor WTr_a. Conductor WWL_a functions as the gate electrode of transistor WTr_a, and conductor 130_a functions as the back gate electrode of transistor WTr_a. In addition, a portion of semiconductor 127_a functions as the semiconductor layer where the channel of transistor WTr_a is formed. The semiconductor layer where the channel of transistor WTr_a is formed overlaps with the gate electrode (conductor WWL_a) via a portion of insulator 124_a, a portion of semiconductor 125_a, and a portion of insulator 126_a.

[0063] Furthermore, the region where conductor WWL_b and conductor 130_b overlap functions as transistor WTr_b. Specifically, the region where conductor WWL_b, insulator 124_b, semiconductor 125_b, insulator 126_b, semiconductor 127_b, insulator 129_b, and conductor 130_b overlap functions as transistor WTr_b. Conductor WWL_b functions as the gate electrode of transistor WTr_b, and conductor 130_b functions as the back gate electrode of transistor WTr_b. In addition, a portion of semiconductor 127_b functions as the semiconductor layer where the channel of transistor WTr_b is formed. The semiconductor layer where the channel of transistor WTr_b is formed overlaps with the gate electrode (conductor WWL_a) via a portion of insulator 124_b, a portion of semiconductor 125_b, and a portion of insulator 126_b.

[0064] As shown in Figure 8B, the region where conductor RWL_a and conductor 130_a overlap functions as transistor RTr_a. Specifically, RWL_a, insulator 124_a, semiconductor 125_a, insulator 126_a, semiconductor 127_a, conductor 128_a, insulator 129_a, and conductor 130_a function as transistor RTr_a. Conductor RWL_a functions as the gate electrode of transistor RTr_a. Conductor 130_a also functions as the back gate electrode of transistor RTr_a. A portion of semiconductor 125_a functions as the semiconductor layer where the channel of transistor RTr_a is formed. The semiconductor layer where the channel of transistor RTr_a is formed overlaps with the gate electrode (conductor RWL_a) via insulator 124_a. The semiconductor layer in which the channel of transistor RTr_a is formed overlaps with the back gate electrode (conductor 130_a) via a portion of insulator 126_a, a portion of semiconductor 127_a, a portion of conductor 128_a, and a portion of insulator 129_a.

[0065] Furthermore, the region where the conductor RWL_b and conductor 130_b overlap functions as transistor RTr_b. Specifically, RWL_b, insulator 124_b, semiconductor 125_b, insulator 126_b, semiconductor 127_b, conductor 128_b, insulator 129_b, and conductor 130_b function as transistor RTr_b. Conductor RWL_b functions as the gate electrode of transistor RTr_b. Conductor 130_b also functions as the back gate electrode of transistor RTr_b. A portion of semiconductor 125_b functions as the semiconductor layer where the channel of transistor RTr_b is formed. The semiconductor layer where the channel of transistor RTr_b is formed overlaps with the gate electrode (conductor RWL_b) via insulator 124_b. The semiconductor layer in which the channel of transistor RTr_b is formed overlaps with the back gate electrode (conductor 130_b) via a portion of insulator 126_b, a portion of semiconductor 127_b, a portion of conductor 128_b, and a portion of insulator 129_b.

[0066] As described above, by dividing the conductor WWL, conductor RWL, and memory string 120, the storage capacity per unit area can be doubled. However, the method of dividing the memory string 120 is not limited to the above. In Figures 8A and 8B, the memory string 120 is divided by an insulator 153 extending in the X direction, but as shown in Figures 9A and 9B, the insulator 153 may extend in a direction different from the X direction. Also, as shown in Figures 9C to 9F, the memory string 120 may be divided into three or more parts. Figures 9C and 9D show an example where the memory string 120 is divided into three parts, and Figures 9E and 9F show an example where the memory string 120 is divided into four parts. In this way, the storage capacity per unit area can be increased.

[0067] In Figures 9A to 9F, it is preferable that the insulator 153 is positioned so as not to obstruct the conductivity of the conductor WWL and the conductor RWL in the X direction.

[0068] Here, let's explain the back gate. The gate and back gate are positioned to overlap via the channel formation region of the semiconductor layer. The back gate can function similarly to the gate. Furthermore, the threshold voltage of the transistor can be changed by changing the potential of the back gate. One of the gate or back gate is sometimes referred to as the "first gate" or "first gate," and the other as the "second gate" or "second gate."

[0069] Since the gate and back gate are formed from conductive layers or semiconductor layers with low resistivity, they have the function of preventing electric fields generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly an electrostatic shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of external electric fields such as static electricity.

[0070] Furthermore, the threshold voltage of the transistor can be controlled by controlling the potential of the back gate. The potential of the back gate may be the same as the gate potential, or it may be the ground potential (GND potential) or any other potential.

[0071] The semiconductor layer in which the channels of transistors WTr and RTr are formed can be single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. Examples of semiconductor materials include silicon or germanium. Compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. The same applies to transistors STr1 and STr2.

[0072] Furthermore, the semiconductor layers used in the transistor may be stacked. When stacking semiconductor layers, semiconductors having different crystalline states may be used for each layer, or different semiconductor materials may be used for each layer.

[0073] The transistor RTr turns on when reading data held by the memory device 100. Therefore, it is preferable to use a semiconductor material with high mobility as the semiconductor layer of the transistor RTr. As such a semiconductor, it is preferable to use a semiconductor whose crystallinity has been improved using a catalytic element disclosed in Patent Document 2. A semiconductor whose crystallinity has been improved using a catalytic element has reduced grain boundaries, which can increase the operating speed of the transistor. In addition, since the variation in the characteristics of the transistor is reduced, the operation of the semiconductor device can be made more stable and reliable. Also, since the variation in the characteristics of the transistor is reduced, the number of memory elements MC provided in one memory string can be increased. Therefore, the storage capacity per unit area can be increased. Therefore, the occupied area of ​​the semiconductor device can be reduced.

[0074] In this embodiment, the semiconductor layer of the transistor RTr uses silicon in which crystallinity has been enhanced (grain boundaries have been reduced) using nickel (Ni) as a catalytic element. The manufacturing method will be described later.

[0075] Transistor WTr is a transistor used to write data to the memory device 100 and to retain the written data. Transistor WTr is in the ON state during data writing operations, but is mainly used in the OFF state. Therefore, it is preferable that transistor RTr is a transistor with low off-current. As a semiconductor material used for a transistor with low off-current, it is preferable to use an oxide semiconductor, which is a type of metal oxide.

[0076] Because oxide semiconductors have a bandgap of 2 eV or more, transistors that use oxide semiconductors in the semiconductor layer where the channel is formed (also called "OS transistors") have significantly low off-current. When an OS transistor is used in the transistor WTr, data written to the memory element MC can be retained for a long period of time. When an OS transistor is used in the transistor constituting the memory element MC, the memory element MC can be called an "OS memory". Furthermore, the memory string 120 containing the memory element MC can also be called an "OS memory". Furthermore, the storage device 100 can also be called an "OS memory". Moreover, OS memory is a type of storage device. Therefore, the memory element MC and the memory string 120 are also types of storage devices.

[0077] OS memory can retain written data for more than a year, or even more than 10 years, even when the power supply is cut off. Therefore, OS memory can be considered non-volatile memory.

[0078] Furthermore, because the data (amount of charge) written to OS memory does not change easily over long periods of time, OS memory can store not only binary (1-bit) information, but also multi-bit or analog information.

[0079] Furthermore, because OS memory writes charge to nodes via transistors, it does not require the high voltage necessary for conventional flash memory, enabling high-speed writing operations. Also, the erase operation performed before data rewriting, which is necessary for flash memory, is unnecessary for OS memory. In addition, since no charge injection or extraction is performed to the floating gate or charge trapping layer, OS memory can write and read data virtually an unlimited number of times. Compared to conventional flash memory, OS memory exhibits less degradation and offers high reliability.

[0080] Furthermore, OS memory does not involve structural changes at the atomic level, unlike magnetoresistive memory (MRAM) or resistive random-access memory (ReRAM). Therefore, OS memory has superior rewrite endurance compared to magnetoresistive memory and resistive random-access memory.

[0081] Furthermore, OS transistors exhibit almost no increase in off-current even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Additionally, the on-current does not easily decrease even in high-temperature environments. Memory devices including OS memory operate stably and with high reliability even in high-temperature environments. OS transistors also have high dielectric strength between the source and drain. By using OS transistors in semiconductor devices, stable and highly reliable semiconductor devices can be realized even in high-temperature environments.

[0082] In this embodiment, IGZO (a metal oxide containing In, Ga, and Zn) is used as the oxide semiconductor for the semiconductor layer of the transistor WTr. Various crystalline oxide semiconductors such as CAAC-OS, nc-OS, and a-like OS can be used as the oxide semiconductor for the transistor WTr. Oxide semiconductors will be described in detail later.

[0083] The transistor WTr, which writes and holds data, is preferably an enhancement-type (normally off) transistor to more reliably achieve the off state. The transistor RTr, which reads data, is preferably a depletion-type (normally on) transistor with a low threshold voltage to achieve faster operation. Therefore, the threshold voltage of transistor RTr is preferably lower than the threshold voltage of transistor WTr.

[0084] Depending on the purpose or application, semiconductor 125 and semiconductor 127 may be made of the same material or different materials. For example, semiconductor 125 and semiconductor 127 may each be oxide semiconductors. Alternatively, semiconductor 125 and semiconductor 127 may each be semiconductors in which grain boundaries are reduced using catalytic elements. Alternatively, semiconductor 125 may be an oxide semiconductor and semiconductor 127 may be a semiconductor in which grain boundaries are reduced using catalytic elements.

[0085] Transistors STr1 and STr2 may be OS transistors, or they may be Si transistors (transistors that use silicon in the semiconductor layer where the channel is formed), which are capable of faster operation than OS transistors.

[0086] Figure 5A corresponds to the XY plane at or near the center of transistor WTr, and Figure 5B corresponds to the XY plane at or near the center of transistor RTr. In Figures 5A and 5B, if the cross-sectional shape of the conductor 130 as viewed from the Z direction is circular, the insulator 129 is provided concentrically outside the conductor 130, the semiconductor 127 is provided concentrically outside the insulator 129, the insulator 126 is provided concentrically outside the semiconductor 127, the semiconductor 125 is provided concentrically outside the insulator 126, and the insulator 124 is provided concentrically outside the semiconductor 125. In addition, the conductor 128 is provided concentrically between the insulator 129 and the semiconductor 127.

[0087] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. As shown in Figure 10A, the cross-sectional shape of the conductor 130 may be rectangular. Also, as shown in Figure 10B, the cross-sectional shape of the conductor 130 may be triangular. Therefore, the cross-sectional shape of the structure 160 as viewed from the Z direction is not limited to a circle.

[0088] [Materials used in semiconductor devices] Next, we will describe the constituent materials that can be used in the memory device 100.

[0089] [substrate] The memory device 100 can be mounted on a substrate. The substrate can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0090] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0091] In this specification, "oxide nitride" refers to a material in which the oxygen content is higher than the nitrogen content. For example, "silicon oxide nitride" refers to a silicon material in which the oxygen content is higher than the nitrogen content. Also, in this specification, "nitride oxide" refers to a material in which the nitrogen content is higher than the oxygen content, and "aluminum nitride oxide" refers to an aluminum material in which the nitrogen content is higher than the oxygen content.

[0092] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0093] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0094] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0095] Furthermore, the electrical properties of an OS transistor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride, and silicon nitride can be used.

[0096] Furthermore, when an oxide semiconductor is used for semiconductor 125 and / or semiconductor 127, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by making a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is in contact with semiconductor 125 and / or semiconductor 127, the oxygen vacancies in semiconductor 125 and / or semiconductor 127 can be compensated for.

[0097] [conductor] As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0098] Furthermore, a semiconductor with enhanced electrical conductivity due to the addition of p-type or n-type impurities can be used as the conductor. Additionally, when silicon is used as the conductor, for example, a silicide containing titanium, cobalt, or nickel may be used.

[0099] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0100] Furthermore, when using an oxide semiconductor, a type of metal oxide, in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0101] In particular, it is preferable to use a conductive material containing a metal element in the oxide semiconductor in which the channel is formed, and oxygen, as the conductor functioning as the gate electrode. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the oxide semiconductor in which the channel is formed. Alternatively, it may be possible to capture hydrogen introduced from an external insulator or the like.

[0102] [Oxide Semiconductors] The oxide semiconductor preferably contains at least one of indium or zinc. In particular, it is preferable that it contains both indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0103] Here, we consider the case where the oxide semiconductor is an In-M-Zn oxide containing indium, element M, and zinc. Element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, in some cases, multiple elements from the aforementioned list may be combined as element M.

[0104] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0105] [Classification of crystal structures] First, we will explain the classification of crystal structures in oxide semiconductors using Figure 11A. Figure 11A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO.

[0106] As shown in Figure 11A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0107] The structure within the thick frame shown in Figure 11A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from "Crystal" or the energetically unstable "Amorphous."

[0108] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 11B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 11B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 11B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0109] As shown in Figure 11B, the XRD spectrum of the CAAC-IGZO film shows a clear peak indicating crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 11B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0110] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 11C. Figure 11C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 11C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0111] As shown in Figure 11C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0112] [Structure of oxide semiconductors] Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 11A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0113] Next, we will explain the details of the aforementioned CAAC-OS, nc-OS, and a-like OS.

[0114] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0115] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0116] Furthermore, in In-M-Zn oxides, CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0117] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0118] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0119] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0120] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0121] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0122] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0123] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0124] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0125] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0126] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0127] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0128] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0129] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0130] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0131] When using CAC-OS for a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, thereby enabling the function of switching (On / Off function) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS for a transistor, a high on-current (I ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0132] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0133] [Transistor having an oxide semiconductor] Subsequently, the case of using the above oxide semiconductor for a transistor will be described.

[0134] It is preferable to use an oxide semiconductor having a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 ​​​​​​​​​​​​​​It is even more preferable that the value be less than [value]. When the carrier concentration of an oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film is reduced to lower the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Also, high-purity intrinsic or substantially high-purity intrinsic may be referred to as type i or substantially type i.

[0135] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0136] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0137] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0138] 〔impurities〕 Here, we will explain the effects of various impurities in oxide semiconductors.

[0139] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the concentrations of silicon and carbon near the interface with the channel formation region (concentrations obtained by secondary ion mass spectrometry (SIMS)) are measured in 2 × 10⁻¹⁰ units. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0140] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0141] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17atoms / cm 3 Do the following:

[0142] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these oxygen vacancies, electrons, which act as carriers, may be generated. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0143] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0144] [Other semiconductor materials] The semiconductor materials that can be used for semiconductors 125 and 127 are not limited to the oxide semiconductors described above. Semiconductor materials having a band gap (semiconductor materials that are not zero-gap semiconductors) may be used as semiconductors 125 and 127. For example, semiconductors of single elements such as silicon, compound semiconductors such as gallium arsenide, and layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) may be used as semiconductor materials. In particular, it is preferable to use layered materials that function as semiconductors as semiconductor materials.

[0145] In this specification, "layered material" refers to a general term for materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0146] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0147] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as semiconductor 125 and semiconductor 127. Specific examples of transition metal chalcogenides applicable as semiconductor 125 and semiconductor 127 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0148] <Example of a method for manufacturing a storage device> Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to Figures 12 to 34. In each of Figures 12 to 34, A is a top view seen from the Z direction, and B is a cross-sectional view of the area indicated by the dashed line A1-A2 in A. Also, in each of Figures 12 to 34, C is a cross-sectional view of the area indicated by the dashed line A3-A4 in A. Furthermore, Figure 25D is an enlarged cross-sectional view of the area enclosed by the dashed line in Figure 25B. In this manufacturing method, a single memory string 120 having two memory elements MC (also referred to as "two stages") is illustrated, but this embodiment is not limited to this. The memory string 120 may have three or more stages of memory elements MC. For example, the memory string 120 may have 32 or more stages of memory elements MC, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages of memory elements MC.

[0149] First, a layer 122 is formed on a substrate 121 having an insulating surface, and an insulator 132 is formed around the layer 122 (see Figures 12A to 12C).

[0150] First, a conductive film is formed, and the conductive film is processed using lithography to form layer 122. Next, an insulating film is formed on the substrate 121 so as to cover layer 122. Next, it is preferable to perform a planarization treatment on the insulating film. In this planarization treatment, it is preferable to polish the insulating film until the surface of layer 122 is exposed. An insulator 132 can be formed by the above method, however, the method of forming layer 122 and the insulator 132 is not limited to this. Alternatively, the insulator 132 may be formed on the substrate 121, grooves and openings may be formed by removing unnecessary parts of the insulator 132, and layer 122 may be embedded in the grooves and openings. Such a method of forming a conductor is sometimes called the damascene method (single damascene method, dual damascene method). By the above method, the structure of layer 122 and insulator 132 shown in Figures 12A to 12C can be obtained.

[0151] The layer 122 and the insulator 132 can be formed using methods such as sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD.

[0152] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo-CVD (Photo-CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0153] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0154] Furthermore, the ALD method is a film deposition method that can minimize plasma damage to the workpiece. Also, because the ALD method does not cause plasma damage during film deposition, it can produce films with fewer defects.

[0155] Unlike film deposition methods where particles emitted from a target or other source are deposited, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and offer good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method.

[0156] CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases during film deposition. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be reduced compared to depositing films using multiple deposition chambers, by eliminating the time spent on transport and pressure adjustment. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0157] In lithography, the resist is first exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a photomask is not required. To remove the resist mask, dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching can be performed.

[0158] Alternatively, a hard mask made of an insulator or conductor may be used instead of a resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask material is formed on a conductive film, a resist mask is formed on top of that, and the hard mask material is etched to form a hard mask of the desired shape.

[0159] This process can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication.

[0160] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power supplies of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0161] When a hard mask is used for etching a conductive film, the etching process may be performed either after removing the resist mask used to form the hard mask, or with the resist mask still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching the conductive film. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0162] For layer 122, for example, a conductive film containing a metal element formed by sputtering can be used. Alternatively, this conductive film can be formed using CVD. Layer 122 may also be a semiconductor. For example, when performing a gettering treatment related to the crystallinity improvement treatment using a catalytic element (also called "catalytic crystallization") described later, it is preferable to use a conductive film with many crystal defects as layer 122. Layer 122 can also be called the "gettering layer".

[0163] Furthermore, to perform the gettering process described later more effectively, it is preferable that the layer 122 contains impurity elements. Examples of impurity elements include Group 15 elements such as phosphorus (P), arsenic (As), nitrogen (N), antimony (Sb), and bismuth (Bi). In addition to Group 15 elements, Group 13 elements (typically boron (B), aluminum (Al), gallium (Ga), and indium (In)) may also be used. The concentration of impurities in the layer 122 is 1 × 10⁻⁶. 19 atoms / cm 3 The above 1 x 10 21 atoms / cm 3 The following is recommended. Note that the addition of impurity elements to layer 122 for gettering is not mandatory. Furthermore, group 18 elements (typically helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), etc.) may be used as impurity elements in layer 122. A combination of group 15 elements, group 13 elements, and group 18 elements may also be used as impurity elements in layer 122.

[0164] In this embodiment, amorphous silicon containing phosphorus is used as layer 122. For example, after forming an amorphous silicon film, phosphorus can be introduced into the amorphous silicon film by plasma doping or ion implantation. Also, when forming layer 122 by CVD or the like, a gas containing impurity elements may be mixed into the material gas.

[0165] The surface of the insulator 132 is preferably planarized as needed. Chemical mechanical polishing (CMP) or reflow can be used for the planarization process.

[0166] An insulating film 123A, a conductive film 134A, and a conductive film 136A are alternately laminated on layer 122 and the insulator 132. In this embodiment, an example is shown in which the insulating film 123A is formed on the insulator 132, the conductive film 134A is formed on the insulating film 123A, the insulating film 123A is formed on the conductive film 134A, and the conductive film 136A is formed on the insulating film 123A (see Figures 12A to 12C). CVD can be used to form the conductive film 134A, the conductive film 136A, and the insulating film 123A. Alternatively, sputtering may be used.

[0167] The aforementioned conductors can be used as conductive film 134A and conductive film 136A. Since conductive film 136A needs to be selectively etched against layer 122 and conductive film 134A in a subsequent process, it is preferable that conductive film 136A be made of a different material from layer 122 and conductive film 134A. On the other hand, layer 122 and conductive film 134A may be made of the same material or different materials. Layer 122, conductive film 134A, and conductive film 136A may be conductors having different crystallinity.

[0168] The aforementioned insulators can be used as the insulator 132 and the insulating film 123A. For example, insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, metal nitride oxides, etc., can be used.

[0169] Furthermore, although this embodiment shows an example in which 6 layers of insulating film 123A, 3 layers of conductive film 134A, and 2 layers of conductive film 136A are formed, the number of layers is not limited to this. They can be formed according to the required performance of the semiconductor device. Here, if the number of layers of conductive film 134A is m (where m is an integer of 2 or more), then the number of layers of insulating film 123A is 2 × m, and the number of layers of conductive film 136A is m-1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and even more preferably 257 or more.

[0170] Next, a mask is formed on the insulating film 123A (not shown), and the insulating film 123A, conductive film 134A, and conductive film 136A are processed using lithography to form a first opening 141 that exposes layer 122 (see Figures 13A to 13C).

[0171] Next, isotropic etching is performed on the conductive film 136A to recede the side surface of the conductive film 136A within the first opening 141 compared to the side surfaces of the insulating film 123A and the conductive film 134A (see Figures 14A to 14C). This process makes the diameter of the first opening 141 overlapping with the conductive film 136A in the direction perpendicular to the Z direction larger than the diameter of the first opening 141 overlapping with the insulating film 123A and the diameter of the first opening 141 overlapping with the conductive film 134A in the direction perpendicular to the Z direction. As a result, irregularities are formed on the side surface of the first opening 141. For such processing, isotropic etching by dry etching using gas, radicals, plasma, etc., or isotropic etching by wet etching using a liquid can be used. The liquid used in wet etching is sometimes called an etchant. When performing isotropic etching using dry etching, a gas, radical, plasma, etc. containing at least one of chlorine, bromine, and fluorine can be used. Isotropic etching is preferably performed without removing the mask used to form the first opening 141.

[0172] Next, an insulating film 124A is formed on the insulating film 123A and inside the first opening 141 (see Figures 15A to 15C). Although not shown, the insulating film 124A may have a multilayer structure. The insulating film 124A can be formed using CVD or ALD. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves or openings with a large aspect ratio. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. If the insulating film 124A has a multilayer structure, each insulating film may be formed using the same deposition apparatus or using different deposition apparatuses.

[0173] The insulating film 124A formed by the above method has good coverage and can be formed even on the uneven surface of the first opening 141. That is, the insulating film 124A can be formed so as to be in contact not only with the sides of the insulating film 123A, the conductive film 134A, and the conductive film 136A, but also with a portion of the upper surface and a portion of the lower surface of the insulating film 123A.

[0174] Next, the insulating film 124A formed at the bottom of the first opening 141 is removed to obtain the insulator 124. It is preferable to use anisotropic etching to remove the insulating film 124A. At this time, the insulating film 124A on the insulating film 123A is also removed, so the insulator 124 is provided only on the side wall of the first opening 141 (see Figures 16A to 16C). By removing the insulating film 124A at the bottom of the first opening 141, layer 122 is exposed again.

[0175] Next, a semiconductor film 125A and an insulating film 126A are formed inside the first opening (see Figures 17A to 17C).

[0176] The semiconductor film 125A and the insulating film 126A can be formed using CVD or ALD. In particular, the ALD method is preferred because it allows for the formation of films with uniform thickness even in grooves or openings with large aspect ratios. Alternatively, the semiconductor film 125A and the insulating film 126A may be formed by combining the ALD method and the CVD method. Furthermore, different film deposition methods or different film deposition apparatus may be used for each film to be formed.

[0177] In this embodiment, amorphous silicon is formed as the semiconductor film 125A, and silicon oxide nitride is formed as the insulating film 126A.

[0178] Next, a portion of the insulating film 126A is removed, leaving the region where the insulating film 126A overlaps with the first opening 141 and its vicinity (see Figures 18A to 18C). In this embodiment, a portion of the insulating film 126A is removed such that, when viewed from the Z direction, a region overlapping with the first opening 141 and a portion overlapping with the region that will later function as transistor STr2 remain. In the region where the insulating film 126A has been removed, the semiconductor film 125A is exposed. This region is also called the "catalyst element doped region".

[0179] Next, a catalyst layer 185 containing a catalyst element is formed on the semiconductor film 125A and the insulating film 126A (see Figures 19A to 19C). The catalyst layer 185 may be formed using sputtering, CVD, ALD, or other methods, or it may be formed by coating a solution containing a catalyst element using a spin coating method or the like. The catalyst layer 185 may be, for example, a silicide containing a catalyst element.

[0180] As catalytic elements, any element selected from metallic elements such as nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), and germanium (Ge) can be used.

[0181] In this embodiment, nickel is used as the catalyst element. When forming the catalyst layer 185 by coating, a solution can be used in which nickel salts such as nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, or nickel sulfate are used as the solute, and water, alcohol, acid, or ammonia is used as the solvent. Alternatively, a solution can be used in which nickel is used as the solute, and a solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform, or ether is used. Or, even if nickel is not completely dissolved, a material such as an emulsion in which nickel is dispersed in the medium may be used.

[0182] Next, in order to diffuse the catalytic elements from the catalyst layer 185 containing the catalytic elements to the semiconductor film 125A, a heat treatment is performed at a temperature of 450 to 650°C for 4 to 24 hours. Prior to this heat treatment, a hydrogen removal treatment at 450°C for about 1 hour may be performed. By performing the hydrogen removal treatment, the hydrogen concentration in the semiconductor film 125A is reduced. Reducing the hydrogen concentration through heat treatment makes it easier for silicides to form.

[0183] Silicon in contact with a catalytic element combines with the catalytic element to form a silicide. Catalytic elements tend to combine with areas that have many defects, such as amorphous states. Therefore, the catalytic elements contained in the silicide react with amorphous silicon to form new silicides. In this way, crystallization progresses as the silicides move. This is because the interatomic distance between the catalytic element and silicon is very close to that of single-crystal silicon, with the Ni-Si distance being the closest to the Si-Si distance in single crystals, being about 0.6% shorter. By using a catalytic element to induce crystallization, the grain size increases, and defects within the semiconductor are reduced.

[0184] Figures 20 and 21 show the movement of silicide 188 from the catalyst element doped region to the semiconductor film 125A. Figure 20 shows the initial state of the heat treatment. First, silicide is formed on the semiconductor film 125A in contact with the catalyst element doped region. Since the insulating film 126A acts as a mask, the catalyst element is not added to the semiconductor film 125A in the region overlapping with the insulating film 126A. As the heat treatment progresses, silicide 188 moves away from the catalyst element doped region. In the semiconductor film 125A, the region where catalytic crystallization has occurred (the region where the crystallinity has been enhanced by the catalyst element) is shown as semiconductor film 125Ac. The amorphous semiconductor film 125A changes into a crystalline semiconductor as silicide 188 passes through.

[0185] Figure 21 shows the process during the middle stage of the heat treatment. As the heat treatment progresses, silicide 188 moves toward layer 122. In this embodiment, amorphous silicon containing phosphorus is used as layer 122, so when silicide 188 reaches layer 122 during the heat treatment period, the crystallinity of layer 122 is also promoted.

[0186] Ultimately, the catalytic elements contained in silicide 188 are incorporated into layer 122 (gettering process). By including impurity elements such as group 15 or group 13 elements in layer 122, the re-diffusion of the catalytic elements that have moved to layer 122 can be reduced.

[0187] The concentration of the catalyst element remaining in the semiconductor film 125Ac is 5 × 10⁻⁶. 17 atoms / cm 3 The following is preferable: When impurity elements such as group 15 elements are included in layer 122, by performing a further heat treatment at a higher temperature after the heat treatment of the semiconductor film 125A using the catalyst element, the catalyst elements remaining in the semiconductor film 125Ac can be moved (absorbed) into layer 122. Including impurity elements in layer 122 can enhance the effect of the gettering treatment.

[0188] Next, the catalyst layer 185 is removed (see Figures 22A to 22C), and the semiconductor film 127A and the conductive film 128A are formed inside the first opening 141 (see Figures 23A to 23C).

[0189] The semiconductor film 127A and the conductive film 128A can be formed using CVD or ALD. In particular, the ALD method is preferred because it allows for the formation of films with uniform thickness even in grooves or openings with large aspect ratios. Alternatively, the ALD method and the CVD method may be combined to form the semiconductor film 127A and the conductive film 128A. Furthermore, different film deposition methods or different film deposition apparatus may be used for each film to be formed.

[0190] The conductive film 128A only needs to be formed to fill the recess on the side of the first opening 141 (the intersection of the first opening 141 and the conductive film 136A in a direction perpendicular to the Z direction) via at least the insulator 124, the semiconductor film 125Ac, the insulating film 126A, and the semiconductor film 127A, and it is not necessary to fill the entire interior of the first opening. The conductive film 128A can be formed using the CVD method or the ALD method. In particular, the ALD method is preferred because it can form a film of uniform thickness even for grooves or openings with a large aspect ratio. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0191] The semiconductor film 127A is preferably an oxide semiconductor. As the oxide semiconductor used for the semiconductor film 127A, oxide semiconductors such as CAAC-OS, nc-OS, and a-like OS can be used.

[0192] Next, the conductive film 128A is processed to form the conductor 128 (see Figures 24A to 24C). Isotropic etching or anisotropic etching can be used to process the conductive film 128A. In forming the conductive film 128A, the conductive film 128A fills the recess on the side of the first opening 141, but if the first opening 141 is not completely filled (see Figure 23), it is preferable to use isotropic etching to process the conductive film 128A. On the other hand, if the conductive film 128A is formed so as to completely fill the first opening 141, it is preferable to use anisotropic etching. Through the above processing, the conductor 128 can be formed in the recess on the side of the first opening 141.

[0193] Next, an insulating film 129A is formed inside the semiconductor film 127A and the conductor 128. Subsequently, using the conductor 128 as a mask, a portion of the semiconductor film 127A is made highly resistive to form a high-resistance region (Type I region) (see Figures 25A to 25D). One method for forming the high-resistance region is to irradiate the semiconductor film 127A with microwaves 144 via the insulating film 129A to remove hydrogen contained in the semiconductor film 127A. It is preferable to irradiate with microwaves 144 in an oxygen-containing atmosphere because oxygen is supplied to the semiconductor film 127A. In this embodiment, in an atmosphere containing oxygen and argon, a portion of the semiconductor film 127A is irradiated with microwaves 144 via the insulating film 129A to make a region 146, which is a part of the semiconductor film 127A, highly resistive (see Figure 25D).

[0194] Heat treatment may be performed at this stage. The heat treatment is preferably carried out in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, more preferably 300°C to 400°C. The atmosphere for the heat treatment is not limited to the above, but may be an atmosphere containing at least one of nitrogen, oxygen, and argon. Furthermore, the heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere.

[0195] Heat treatment reduces the resistance of the semiconductor film 127A in contact with the conductor 128, allowing a low-resistance region (N-type region) to be formed in region 148. By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact, a metal compound layer containing the metal elements of the conductor 128 and the components of the semiconductor film 127A may be formed at the interface between the conductor 128 and the semiconductor film 127A. The formation of this metal compound layer is preferable because it reduces the resistance of the semiconductor film 127A in the region in contact with the conductor 128. In addition, the conductor 128 may absorb oxygen contained in the semiconductor film 127A. By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact, the resistance of the semiconductor film 127A is further reduced. This heat treatment may be performed before microwave treatment. The region 148, whose resistance has been reduced by heat treatment, is covered by the conductor 128, and therefore is not affected by the microwaves 144, and can maintain a low resistance value even after microwave treatment.

[0196] The carrier concentration in region 146 after the above microwave treatment and heat treatment is 1 × 10⁻⁶ 18 / cm 3 Less than, preferably 1 × 10 17 / cm 3 More preferably, 1 × 10 16 / cm 3 The following is preferable. Also, the carrier concentration in region 148 is 1 × 10⁻⁶. 18 / cm 3 Preferably, 1 × 10 19 / cm 3 More preferably, 1 × 10 20 / cm 3 It is preferable that the above conditions are met.

[0197] Next, a conductive film 130A is formed (see Figures 26A to 26C). The conductive film 130A can be formed using the CVD method or the ALD method. In particular, the ALD method is preferred because it is possible to form a film of uniform thickness even in grooves or openings with a large aspect ratio. Alternatively, the ALD method and the CVD method may be combined.

[0198] Next, a heat treatment is performed. The heat treatment is preferably carried out in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, or more preferably 300°C to 400°C. The atmosphere for the heat treatment is not limited to the above, but may be an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may also be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere.

[0199] Next, the conductive film 130A is removed using CMP or the like until the surface of the insulating film 129A is exposed to obtain the conductor 130 (see Figures 27A to 27C). Note that the aforementioned heat treatment may also be performed after the formation of the conductor 130.

[0200] Next, the semiconductor film 125A, insulating film 126A, semiconductor film 127A, and insulating film 129A are processed to obtain semiconductor 125, insulator 126, oxide film 127B, and insulating film 129B (see Figures 28A to 28C). This processing can be carried out using either a dry etching method or a wet etching method.

[0201] Next, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form insulators 123B, conductors 134B, and conductors 136B that overlap in a stepped manner at their edges, as shown in Figure 29B (see Figures 29A to 29C). In processing the insulating film 123A, the conductive film 134A, and the conductive film 136A, stepped edges can be formed by alternately etching the insulating film 123A, the conductive film 134A, and the conductive film 136A and slimming the mask.

[0202] Next, the insulator 150 is formed (see Figure 29). The insulator 150 can be formed using the CVD method. Preferably, the surface of the insulator 150 is planarized using the CMP method or the reflow method.

[0203] Next, insulator 150, insulator 123B, conductor 134B, and conductor 136B are processed to form insulator 123, conductor 134, and conductor 136. (See Figures 30A to 30C.)

[0204] Next, an insulator 152 is formed to fill the portions removed during the formation of the insulator 123, conductor 134, and conductor 136 (see Figure 30). The insulator 152 can be formed using CVD or ALD. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves or openings with a large aspect ratio. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. It is preferable that the insulator 152 be planarized using CMP or reflow.

[0205] Next, the oxide film 127B and the insulating film 129B are processed using lithography to obtain the semiconductor 127 and the insulator 129 (see Figures 31A to 31C). This processing can be performed using either dry etching or wet etching. At this time, a portion of the insulator 126 is exposed.

[0206] Next, a conductor 154 is formed so as to overlap a portion of the semiconductor 125 via the insulator 126 (see Figures 32A to 32C). The conductor 154 is obtained by forming a conductive film on the insulators 126, 150, and 152, and then processing the conductive film using lithography. Note that in Figure 32A, the conductor 154 is not located on the dashed line A1-A2, but in Figure 32B, the conductor 154 is shown by a dashed line. The conductor 154 is similarly shown in Figures 33 and 34, which will be described later.

[0207] Next, an insulator 156 is formed to cover the conductor 154, insulator 126, insulator 150, and insulator 152 (see Figures 33A to 33C). The insulator 156 can be formed using methods such as CVD, ALD, or sputtering.

[0208] Next, insulators 156, 126, 129, semiconductor 127, and insulator 150 are processed using lithography to form second openings that expose conductors 134, 136, 130, 154, and semiconductor 125. The second openings are formed for each of the stepped conductors 134 and 136 (see Figure 33).

[0209] Next, conductors 161 that electrically connect to conductor 134, conductor 162 that electrically connects to conductor 136, conductor 163 that electrically connects to conductor 130, conductor 164 that electrically connects to conductor 154, conductor 165 that electrically connects to semiconductor 125, and conductor 166 that electrically connects semiconductor 125 and semiconductor 127 are formed so as to be embedded in the second opening (see Figures 34A to 34C). Conductors 161, 162, 163, 164, 165, and 166 can be formed using CVD or ALD. In particular, the ALD method is preferred because it is possible to form a film of uniform thickness even for grooves or openings with a large aspect ratio. Alternatively, the above conductors may be formed by combining the ALD method and the CVD method. Furthermore, conductors 161, 162, 163, 164, 165, and 166 may have a laminated structure consisting of multiple layers. Conductors 161, 162, 163, 164, 165, and 166 can be formed by forming a conductive film on the insulator 156 and inside the second opening, and then removing the unnecessary conductive film using CMP or the like.

[0210] Next, conductors 171, 172, 173, 174, and 175 are formed to electrically connect to conductor 161, conductor 162, conductor 163, conductor 174, and conductor 165 (see Figure 34). Conductors 171, 172, 173, 174, and 175 can be formed by forming a conductive film on the insulator 156 and processing it using lithography. This processing can be done using either dry etching or wet etching.

[0211] Conductors 171, 161, and 134 function as conductor SG or conductor WWL. Conductors 172, 162, and 136 function as conductor RWL. Conductors 173, 163, and 130 function as conductor BG. Conductors 174, 164, and 154 function as conductor SEL. Conductors 175 and 165 function as BL. A memory device can be manufactured through the above process.

[0212] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0213] (Embodiment 2) In this embodiment, the circuit configuration and operation of the memory string 120, which is a storage device, will be described. Figure 35 shows an example of the circuit configuration of the memory string 120.

[0214] <Example of a memory string circuit configuration> Figure 35 shows an example of a circuit configuration when the number of memory elements MC included in the memory string 120 is 5. As described in the above embodiment, the memory element MC has a transistor WTr and a transistor RTr.

[0215] In equivalent circuit diagrams and other diagrams, the designation "OS" may be added to the transistor's circuit symbol to indicate that it is an OS transistor. Similarly, the designation "Si" may be added to the transistor's circuit symbol to indicate that it is a Si transistor (a transistor that uses silicon in the semiconductor layer where the channel is formed). Figure 35 shows that transistor WTr is an OS transistor and transistor RTr is a Si transistor.

[0216] Figure 36 shows the equivalent circuit diagram of the memory element MC. As shown in Figure 36, the transistor WTr can be represented by replacing it with a capacitor Cs and a transistor Tr. The gate of the transistor Tr is electrically connected to the conductor WWL via the capacitor Cs. The memory element MC illustrated in this embodiment is a "2Tr1C type" memory cell composed of two transistors and one capacitor.

[0217] In Figure 35, the transistor WTr included in the memory element MC_1 is shown as transistor WTr_1, and the transistor RTr included in the memory element MC_1 is shown as transistor RTr_1. Therefore, the memory string 120 shown in Figure 35 has transistors WTr_1 to WTr_5 and transistors RTr_1 to RTr_5. The memory string 120 shown in Figure 35 also has transistors STr1 and STr2. The memory string 120 is a NAND type memory device.

[0218] A NAND-type storage device that includes OS memory is also called an "OS NAND type" or "OS NAND type storage device." Furthermore, an OS NAND type storage device having a configuration in which multiple OS memories are stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0219] One source or drain of transistor RTr_1 is electrically connected to one source or drain of transistor STr1, and the other is electrically connected to one source or drain of transistor RTr_2. One source or drain of transistor WTr_1 is electrically connected to the gate of transistor RTr_1, and the other is electrically connected to one source or drain of transistor WTr_2. The back gate of transistor RTr_1 is electrically connected to conductor RWL_1. The gate of transistor WTr_1 is electrically connected to conductor WWL_1. Also, the back gate of transistor WTr_1 is electrically connected to conductor BG. Furthermore, the other source or drain of transistor STr1 is electrically connected to layer 122, and its gate is electrically connected to conductor SG.

[0220] Furthermore, one source or drain of transistor RTr_5 is electrically connected to the other source or drain of transistor RTr_4, and the other is electrically connected to one source or drain of transistor STr2. The gate of transistor RTr_5 is electrically connected to one source or drain of transistor WTr_5. The other source or drain of transistor WTr_5 is electrically connected to one source or drain of transistor STr2. The back gate of transistor RTr_5 is electrically connected to conductor RWL_5. The gate of transistor WTr_5 is electrically connected to conductor WWL_5. Furthermore, the back gate of transistor WTr_5 is electrically connected to conductor BG. Furthermore, the other source or drain of transistor STr2 is electrically connected to conductor BL, and its gate is electrically connected to conductor SEL.

[0221] If the memory string 120 has n memory elements MC, then in the i-th memory element MC_i (where i is an integer between 1 and n), excluding the 1st and nth memory elements MC, one source or drain of transistor RTr_i is electrically connected to the other source or drain of transistor RTr_i-1, and the other is electrically connected to one source or drain of transistor RTr_i+1. The gate of transistor RTr_i is electrically connected to one source or drain of transistor WTr_i. The other source or drain of transistor WTr_i is electrically connected to one source or drain of transistor WTr_i+1. The back gate of transistor RTr_i is electrically connected to conductor RWL_i. The gate of transistor WTr_i is electrically connected to conductor WWL_i. Also, the back gate of transistor WTr_i is electrically connected to conductor BG.

[0222] Furthermore, the node where the gate of transistor RTr and either the source or drain of transistor WTr are electrically connected is defined as node ND. That is, the node where the gate of transistor RTr_i and either the source or drain of transistor WTr_i are electrically connected is defined as node ND_i. In Figure 35, node ND included in memory element MC_1 is shown as node ND_1.

[0223] Transistors STr1 and STr2 may be, for example, OS transistors or Si transistors. One of transistors STr1 and STr2 may be an OS transistor and the other a Si transistor.

[0224] As shown in Figure 37, depending on the purpose or application, a Si transistor may be used as transistor WTr and an OS transistor as transistor RTr. Figure 37 also shows an example in which OS transistors are used for transistors STr1 and STr2.

[0225] Also, depending on the purpose, application, etc., as shown in FIG. 38, a configuration may be adopted in which the transistor WTr does not have a back gate. Further, in FIG. 38, an example in which OS transistors are used for the transistors STr1 and STr2 is shown.

[0226] <Operation Example of Memory String> Subsequently, an operation example of the memory string 120 shown in FIG. 35 will be described.

[0227] [Write Operation] In the present embodiment, an operation example in the case where an H potential is written to the memory elements MC_1 and MC_3 and an L potential is written to the other memory elements MC will be described. FIG. 39 is a timing chart for explaining the write operation. FIGS. 40A to 43B are circuit diagrams for explaining the write operation. Note that for symbols not shown in FIGS. 40A to 43B, reference may be made to FIG. 35 and the like.

[0228] As an initial state, it is assumed that L potentials are written to the memory elements MC_1 to MC_5. Also, it is assumed that L potentials are supplied to the conductors WWL_1 to WWL_5, the conductors RWL_1 to RWL_5, the conductor SEL, the conductor BG, the conductor BL, the conductor SG, and the layer 122. Note that the threshold value of the transistor RTr can be controlled by adjusting the potential supplied to the conductor BG. The potential supplied to the conductor BG may be appropriately adjusted so that the transistor RTr becomes a desired normally-on type transistor.

[0229] [Period T1] In period T1, H potentials are supplied to the conductors WWL_1 to WWL_5, the conductor BL, and the conductor SEL (see FIG. 40A). Then, the potentials of the nodes ND_1 to ND_5 become H potentials.

[0230] [Period T2] During period T2, an L potential is supplied to the conductor WWL_1 (see Fig. 40B). Then, the transistor WTr_1 turns off, and the charge written to the node ND_1 is retained. Here, the charge corresponding to the H potential is retained.

[0231] [Period T3] During period T3, an L potential is supplied to the conductor BL (see Fig. 40B). Then, the potentials of the nodes ND_2 to ND_5 become the L potential. In this case, although the gates of the transistors RTr_2 to RTr_5 also become the L potential, since the transistor RTr is a normally-on type transistor, the transistors RTr_2 to RTr_5 do not turn off.

[0232] [Period T4] During period T4, an L potential is supplied to the conductor WWL_2 (see Fig. 41A). Then, the transistor WTr_2 turns off, and the charge written to the node ND_2 is retained. Here, the charge corresponding to the L potential is retained.

[0233] [Period T5] During period T5, an H potential is supplied to the conductor BL (see Fig. 41B). Then, the potentials of the nodes _3 to _5 become the H potential.

[0234] [Period T6] During period T6, an L potential is supplied to the conductor WWL_3 (see Fig. 42A). Then, the transistor WTr_3 turns off, and the charge written to the node ND_3 is retained. Here, the charge corresponding to the H potential is retained.

[0235] [Period T7] During period T7, an L potential is supplied to the conductor BL (see Fig. 42B). Then, the potentials of the nodes ND_4 and ND_5 become the L potential.

[0236] [Period T8] During period T8, an L potential is supplied to the conductor WWL_4 (see Figure 43A). This turns off transistor WTr_4, and the charge written to node ND_4 is retained. Here, a charge equivalent to an L potential is retained.

[0237] [Period T9] During period T9, the conductor BL remains at L potential. Therefore, the potential of node ND_5 also remains at L potential.

[0238] [Period T10] During period T10, an L potential is supplied to the conductor WWL_5 (see Figure 43B). This turns off transistor WTr_5, and the charge written to node ND_5 is retained. Here, a charge equivalent to an L potential is retained. Additionally, an L potential is supplied to the conductor SEL.

[0239] In this way, information can be written to the memory element MC.

[0240] Furthermore, when writing information to the i-th memory element MC (excluding i=1) among multiple memory elements MC, the information writing operation to memory elements MC up to i-1 can be omitted. For example, if you want to write information to memory element MC_4, you do not need to perform the information writing operation to memory elements MC_1 through MC_3. In other words, the writing operations from period T1 to period T6 shown in this embodiment can be omitted. Therefore, the time and power consumption related to the writing operation of the storage device can be reduced.

[0241] [Read operation] An example of the read operation of the memory string 120 with the above circuit configuration will be described. As an initial state, it is assumed that memory elements MC_1 and MC_3 hold a high potential, and memory elements MC_2, MC_4, and MC_5 hold a low potential. It is also assumed that conductors WWL_1 to WWL_5, RWL_1 to RWL_5, SEL, BG, BL, SG, and layer 122 are supplied with a low potential. Figures 44A and 44B are timing charts illustrating the read operation. Figures 45A, 45B, and 46 are circuit diagrams illustrating the read operation. For symbols not shown in Figures 45A, 45B, and 46, please refer to Figure 35, etc.

[0242] ≪When the holding potential is H potential≫ First, we will explain the read operation of memory element MC_3, which holds a high potential.

[0243] [Period T11] During period T11, a high potential is supplied to conductors RWL_1 through RWL_5 and conductor SEL (see Figure 45A). This turns on transistor STr2, and semiconductor 125 of transistor RTr and conductor BL become conductive. In this state, conductor BL and semiconductor 125 are precharged with a high potential, putting them into a floating state.

[0244] Here, we will explain the Id-Vg characteristics of transistors. Figures 47A and 47B illustrate the Id-Vg characteristics of transistors. In Figures 47A and 47B, the horizontal axis represents the gate voltage (Vg), and the vertical axis represents the drain current (Id). Figure 47A shows the Id-Vg characteristics of a normally-off type transistor, and Figure 47B shows the Id-Vg characteristics of a normally-on type transistor.

[0245] The H potential is a potential higher than the L potential. If the L potential is set to 0V, the H potential is a positive voltage. In a normally-off transistor, when Vg is at the L potential (0V), the channel resistance value (the resistance value between the source and the drain) is extremely large and almost no Id flows. Also, when Vg reaches the H potential, the channel resistance value decreases and Id increases (see Fig. 47A).

[0246] In a normally-on transistor, even when Vg is at the L potential, the channel resistance value is small and more Id flows compared to a normally-off transistor. Also, when Vg reaches the H potential, the channel resistance value becomes even smaller and Id further increases (see Fig. 47B).

[0247] Since the transistor RTr is a normally-on transistor, precharging to the semiconductor 125 is possible even when the potential of the conductor RWL remains at the L potential. However, by supplying the H potential to the conductor RWL, the channel resistance value of the transistor RTr becomes even smaller. Therefore, the time and power consumption required for precharging can be reduced.

[0248] [Period T12] During period T12, supply the L potential to the conductor RWL_3 (see Fig. 45B). The H potential is held at the node ND_3. Therefore, even when the potential of the conductor RWL_3 becomes the L potential, the channel resistance value of the transistor RTr_3 is smaller than when the L potential is held at the node ND_3.

[0249] [Period T13] During period T13, a high potential is supplied to the conductor SG, turning on transistor STr1 (see Figure 46A). This creates a conductive state between conductor BL and layer 122. At this time, since a high potential is supplied to conductors RWL_1, RWL_2, RWL_4, and RWL_5, the channel resistances of transistors RTr_1, RTr_2, RTr_4, and RTr_5 become small regardless of the potential of node ND. Also, as mentioned above, a low potential is supplied to conductor RWL_3, but since a high potential is maintained at node ND_3, the channel resistance of transistor RTr_3 becomes small. As a result, the potential of conductor BL, which is in a floating state, changes rapidly from a high potential to a low potential (see Figure 44A).

[0250] [Period T14] During period T14, an L potential is supplied to the conductors SEL, RWL, and SG (see Figure 46B).

[0251] ≪When the holding potential is L potential≫ Next, we will explain the read operation of memory element MC_2, which is holding an L potential. When reading the information (potential) held in memory element MC_2, the potential of conductor RWL_2 is set to an L potential during period T12 (see Figure 44B). At this time, since an L potential is held at node ND_2, the channel resistance value of transistor RTr_2 is greater than when an H potential is held at node ND_2.

[0252] Next, during period T13, a high potential is supplied to the conductor SG, making the conductor BL and layer 122 conductive. At this time, because the channel resistance of transistor RTr_2 is large, the potential of the conductor BL changes slowly from high potential to low potential.

[0253] In this way, during period T13, by setting the potential of the conductor RWL corresponding to the memory element MC to be read to a low potential and detecting the change in the potential of the conductor BL, the information held in the memory element MC can be determined.

[0254] Furthermore, during periods other than writing operations, it is preferable to supply a potential lower than the L potential (also called the "LL potential") to the conductor BG. By supplying the LL potential to the conductor BG, the transistor WTr can be more reliably turned off. Therefore, the information written to node ND can be retained for a longer period of time.

[0255] Furthermore, during the writing operation, a potential higher than L potential may be supplied to the conductor BG. For example, an H potential may be supplied to the conductor BG during the writing operation. By supplying an H potential to the conductor BG during the writing operation, the resistance value of semiconductor 127 is reduced, and the writing speed can be increased.

[0256] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0257] (Embodiment 3) In this embodiment, an example configuration of a semiconductor device 200 including a storage device 100 will be described.

[0258] Figure 48 shows a block diagram illustrating an example configuration of a semiconductor device 200 according to one aspect of the present invention. The semiconductor device 200 shown in Figure 48 includes a drive circuit 210 and a memory array 220. The memory array 220 has one or more storage devices 100. Figure 48 shows an example in which the memory array 220 has a plurality of storage devices 100 arranged in a matrix.

[0259] The drive circuit 210 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 includes a peripheral circuit 211 (row decoder), a control circuit 212 (control circuit), and a voltage generation circuit 228. The semiconductor device 200 includes various functional elements or circuits such as a memory array 220, PSWs 241 and 242, peripheral circuit 211, control circuit 212, and voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or subsystem.

[0260] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0261] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may also be generated by the control circuit 212.

[0262] The control circuit 212 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 200 (e.g., write operation, read operation). Alternatively, the control circuit 212 generates control signals for the peripheral circuit 211 so that this operating mode is executed.

[0263] The voltage generation circuit 228 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 228. For example, when a high-level signal is applied to the WAKE signal, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0264] The peripheral circuit 211 is a circuit for writing and reading data to and from the storage device 100. The peripheral circuit 211 includes a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0265] The row decoder 221 and column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying the row to access, and the column decoder 222 is a circuit for specifying the column to access. The row driver 223 has the function of selecting the wiring specified by the row decoder 221. The column driver 224 has the function of writing data to the storage device 100, reading data from the storage device 100, and holding the read data, etc.

[0266] The input circuit 225 has the function of holding the signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is the data (Din) to be written to the storage device 100. The data (Dout) read by the column driver 224 from the storage device 100 is output to the output circuit 226. The output circuit 226 has the function of holding Dout. In addition, the output circuit 226 has the function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is the signal RDA.

[0267] PSW241 controls the supply of VDD to the peripheral circuit 215. PSW242 controls the supply of VHM to the row driver 223. Here, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW241 is controlled by signal PON1, and the on / off state of PSW242 is controlled by signal PON2. In Figure 48, the number of power supply domains to which VDD is supplied in the peripheral circuit 215 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0268] The drive circuit 210 and the memory array 220 may be provided on the same plane. Alternatively, as shown in Figure 49A, the drive circuit 210 and the memory array 220 may be stacked on top of each other. By stacking the drive circuit 210 and the memory array 220, the signal propagation distance can be shortened. Furthermore, as shown in Figure 49B, multiple layers of the memory array 220 may be stacked on top of the drive circuit 210.

[0269] Furthermore, as shown in Figure 49C, memory arrays 220 may be provided on the upper and lower layers of the drive circuit 210. Figure 49C shows an example in which one memory array 220 is provided on both the upper and lower layers of the drive circuit 210. By arranging multiple memory arrays 220 to sandwich the drive circuit 210, the signal propagation distance can be further shortened. Note that the number of memory arrays 220 stacked on the upper layer of the drive circuit 210 and the number of memory arrays 220 stacked on the lower layer of the drive circuit 210 may be one or more. It is preferable that the number of memory arrays 220 stacked on the upper layer of the drive circuit 210 is equal to the number of memory arrays 220 stacked on the lower layer of the drive circuit 210.

[0270] <Example of cross-sectional configuration of a semiconductor device> Figure 50 shows an example of the cross-sectional configuration of the semiconductor device 200 shown in Figure 49A. Figure 50 shows a part of the semiconductor device 200 shown in Figure 49A.

[0271] Figure 50 shows transistors 301, 302, and 303 included in the drive circuit 210. Transistors 301 and 302 function as part of the sense amplifier 304. Transistor 303 functions as a column selection switch. Specifically, the conductor BL included in the memory array 220 is electrically connected to one of the source and drain of transistor 301, the gate of transistor 301 is electrically connected to one of the source and drain of transistor 302, and the gate of transistor 302 is electrically connected to the other of the source and drain of transistor 301. Furthermore, one of the source and drain of transistor 301 and the other of the source and drain of transistor 302 are electrically connected to one of the source and drain of transistor 303, which functions as a column selection switch. This reduces the layout area of ​​the semiconductor device 200. Figure 50 shows an example where seven memory elements MC are provided per memory string. However, the number of memory elements MC provided in a single memory string is not limited to this. For example, the number of memory elements MC provided in a single memory string may be 32, 64, 128, or 200 or more.

[0272] The conductor BL of the memory array 220 is electrically connected to the sense amplifier 304 and the transistor 303, which functions as a row selection switch, via conductors 752, 705, 714, and 715, which are formed to be embedded in the insulators 726 and 722, respectively. Note that the circuit and transistors of the drive circuit 210 are examples and are not limited to its circuit configuration and transistor structure. In addition to the above, appropriate circuits and transistors such as control circuits, row decoders, row drivers, source line drivers, and input / output circuits can be provided depending on the configuration of the semiconductor device 200 and its driving method.

[0273] Transistors 301, 302, and 303 are provided on a substrate 311 and each has a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 311, and low-resistance regions 314a and 314b that function as source or drain regions. As shown in Figure 50, one low-resistance region may be shared by transistors 301 and 302 as one source or drain region and the other source or drain region.

[0274] Transistors 301, 302, and 303 have a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such transistors 301, 302, and 303 are also called FIN type transistors because they utilize the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film with a convex shape may be formed by processing an SOI substrate.

[0275] Transistors 301, 302, and 303 may each be p-channel or n-channel, but it is preferable that transistors 301 and 302 have different polarities.

[0276] In the region where the channel of the semiconductor region 313 is formed, the region near it, the source region, or the low-resistance region 314a and low-resistance region 314b, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, transistors 301, 302, and 303 may be HEMTs (High Electron Mobility Transistors) by using GaAs and GaAlAs, etc.

[0277] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0278] The insulator 315 functions as a gate insulating film for transistors 301, 302, and 303.

[0279] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0280] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use a layer of metallic materials such as tungsten or aluminum as the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0281] Furthermore, it is preferable to provide an insulator 317 above the conductor 316 that functions as an etch stopper. It is also preferable to provide an insulator 318 on the side surface of the insulator 315 that functions as a spacer. By providing insulators 317 and 318, the areas where the low-resistance regions 314a and 314b and the conductor 328 are electrically connected can be self-aligned. Therefore, even if misalignment occurs when forming an opening to expose a part of the low-resistance regions 314a and 314b, an opening can be formed to expose the intended area. By forming the conductor 328 in the opening thus formed, good contact with reduced contact resistance can be obtained between the low-resistance regions 314a and 314b and the conductor 328. The contact between the low-resistance regions 314a and 314b and the conductor 328 formed in this way is sometimes called a self-aligned contact. Furthermore, a conductor 329 may be provided that is electrically connected to the conductor 316 so as to be embedded in the insulators 317 and 322.

[0282] Insulators 320, 322, 324, 326, and 327 are layered in order to cover transistors 301, 302, and 303.

[0283] For insulators 320, 322, 324, 326, and 327, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0284] The insulator 322 may also function as a planarizing film that flattens steps caused by transistors 301 or the like located below it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0285] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent hydrogen and impurities from diffusing from the substrate 311 or the transistor 301, etc., into the region where the memory array 220 is provided.

[0286] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as a memory element MC, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the memory element MC and the transistor 301, etc. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0287] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0288] Furthermore, it is preferable that insulators 326 and 327 have a lower dielectric constant than insulator 324. For example, the relative permittivity of insulators 326 and 327 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of insulators 326 and 327 is preferably 0.7 times or less, and more preferably 0.6 times or less, than the relative permittivity of insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0289] Furthermore, insulators 320, 322, 324, 326, and 327 have embedded conductors 328, 329, and 330, etc., which are electrically connected to the memory array 220. Conductors 328, 329, and 330 function as plugs or wiring. Conductors that function as plugs or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0290] The plugs and wiring (conductors 328, 329, and 330, etc.) can be made from conductive materials such as metals, alloys, metal nitrides, or metal oxides, either in a single layer or in a laminated configuration. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, with tungsten being preferred. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0291] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in Figure 50, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as plugs or wiring. Conductors 356 can be provided using the same material as conductors 328, 329, and 330.

[0292] For example, it is preferable that the insulator 350, like the insulator 324, be an insulator that has barrier properties against hydrogen. It is also preferable that the conductor 356 includes a conductor that has barrier properties against hydrogen. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, the transistor 301 and the memory element MC can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 301 to the memory element MC can be suppressed.

[0293] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from transistors 301 and the like while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0294] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 50, insulators 360, 362, and 364 are stacked in order. Conductors 366 are formed on insulators 360, 362, and 364. Conductors 366 function as a plug or wiring. Conductors 366 can be provided using the same material as conductors 328, 329, and 330.

[0295] For example, it is preferable that the insulator 360, like the insulator 324, be an insulator having barrier properties against hydrogen. It is also preferable that the conductor 366 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 360. With this configuration, the transistor 301 and the memory element MC can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 301 to the memory element MC can be suppressed.

[0296] An insulator 722 is provided on the insulator 364 and the conductor 366, and a memory array 220 is provided above the insulator 722. A barrier film made of the same material as the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0297] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0298] (Embodiment 4) This embodiment describes application examples of a semiconductor device using the storage device shown in the previous embodiment. The storage device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 51A to 51E schematically show some configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memory.

[0299] Figure 51A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. A storage device or semiconductor device as shown in the above embodiment can be incorporated into the memory chip 1105, etc.

[0300] Figure 51B is a schematic diagram of the external appearance of an SD card, and Figure 51C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. The capacity of the SD card 1110 can be increased by also providing a memory chip 1114 on the back side of the circuit board 1113. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The memory chip 1114 and other components can be incorporated into the storage device or semiconductor device shown in the above embodiment.

[0301] Figure 51D is a schematic diagram of the external appearance of the SSD, and Figure 51E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. The storage device or semiconductor device shown in the above embodiment can be incorporated into the memory chip 1154, etc.

[0302] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0303] (Embodiment 5) Figures 52A to 52G show specific examples of electronic devices equipped with a storage device or semiconductor device according to one aspect of the present invention.

[0304] <Electronic Equipment and Systems> A storage device or semiconductor device according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book readers, television equipment, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems, and sound playback devices. Here, "computer" includes not only tablet computers, notebook computers, and desktop computers, but also large computers such as server systems.

[0305] An electronic device according to one aspect of the present invention may have an antenna. By receiving signals with the antenna, the display unit can display images and information. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0306] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0307] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0308] [Information terminal] A memory device or semiconductor device according to one aspect of the present invention can be used to form a memory device for holding the program of a microcontroller. Therefore, according to one aspect of the present invention, the microcontroller chip can be made smaller.

[0309] Figure 52A illustrates a mobile phone (smartphone), a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. A touch panel is provided on the display unit 5102 as an input interface, and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the mobile phone. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0310] Figure 52B illustrates a notebook-type information terminal 5200. The notebook-type information terminal 5200 comprises a terminal body 5201, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the notebook-type information terminal can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the notebook-type information terminal. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0311] In the above, smartphones and notebook computers were used as examples of electronic devices, as illustrated in Figures 52A and 52B, respectively. However, other types of information terminals can also be used. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0312] [Game console] Figure 52C shows a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Housings 5302 and 5303 can be detached from housing 5301. By attaching the connection unit 5305 provided on housing 5301 to another housing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). At this time, housings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. A memory device or semiconductor device according to one aspect of the present invention can be incorporated into chips or the like provided on the circuit boards of housings 5301, 5302, and 5303.

[0313] Figure 52D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection.

[0314] By using a miniaturized microcontroller according to one aspect of the present invention in game consoles such as the portable game console 5300 and the home game console 5400, the limited space inside the game console can be effectively utilized. Furthermore, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the portable game console. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0315] Figures 52C and 52D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the microcontroller according to one aspect of the present invention is applied are not limited to these. Examples of game consoles to which the microcontroller according to one aspect of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0316] [Large computer] A storage device or semiconductor device according to one aspect of the present invention can be applied to a large-scale computer.

[0317] Figure 52E shows the supercomputer 5500, an example of a large-scale computer. Figure 52F shows the rack-mount computer 5502, which is part of the supercomputer 5500.

[0318] The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. Furthermore, each computer 5502 is provided with a plurality of circuit boards 5504, on which a microcontroller according to one aspect of the present invention can be mounted. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space of the large computer can be effectively utilized. Additionally, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the large computer. This increases the storage capacity per unit area of ​​the storage device.

[0319] Figures 52E and 52F illustrate a supercomputer as an example of a large computer, but the large computers to which the microcontroller according to one aspect of the present invention is applied are not limited to this. Examples of large computers to which the microcontroller according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes).

[0320] [electric appliances] Figure 52G shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0321] A storage device or semiconductor device according to one aspect of the present invention can also be applied to an electric refrigerator 5800. For example, by applying a miniaturized microcontroller according to one aspect of the present invention to the electric refrigerator 5800, the limited space of the electric refrigerator can be effectively utilized.

[0322] While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0323] The electronic devices described in this embodiment, their functions, and their effects can be appropriately combined with descriptions of other electronic devices.

[0324] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of Symbols]

[0325] 100: Memory device, 105: Region, 110: Memory cell array, 120: Memory string, 121: Substrate, 122: Layer, 123: Insulator, 124: Insulator, 125: Semiconductor, 126: Insulator, 127: Semiconductor, 128: Conductor, 129: Insulator, 130: Conductor, 132: Insulator, 134: Conductor, 136: Conductor

Claims

1. A structure extending in the first direction, A plurality of first conductors extending in a second direction intersecting the first direction, The invention comprises a plurality of second conductors extending in the second direction, The aforementioned structure comprises a third conductor, a first insulator, a plurality of fourth conductors, a first semiconductor, a second insulator, a second semiconductor, and a third insulator. In the first region corresponding to each intersection of the plurality of first conductors and the structure, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically in this order on the outside of the third conductor. In the first region, a portion of the first conductor functions as the first gate electrode of the first transistor, a channel of the first transistor is formed in the first semiconductor, and a portion of the third conductor functions as the second gate electrode of the first transistor. In the second region corresponding to each intersection of the plurality of second conductors and the structure, the first insulator, one of the plurality of fourth conductors, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically in this order on the outside of the third conductor, and the first semiconductor is in contact with one of the plurality of fourth conductors. In the second region, a portion of the second conductor functions as the first gate electrode of the second transistor, a channel of the second transistor is formed in the second semiconductor, and a portion of any one of the plurality of fourth conductors functions as the second gate electrode of the second transistor. The first semiconductor includes an oxide semiconductor, The second semiconductor includes polycrystalline silicon, The second semiconductor has a region in contact with the first layer, A semiconductor device wherein the first layer contains a first metal element.

2. In claim 1, A semiconductor device wherein the first metallic element is nickel.

3. In claim 1 or claim 2, The first layer comprises silicon and phosphorus in a semiconductor device.

4. In any one of claims 1 to 3, The oxide semiconductor comprises at least one of indium or zinc.

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