Display devices, electronic machines

Abstract

To suppress the deterioration in electric characteristic in a transistor with an oxide semiconductor layer or a semiconductor device including the transistor.SOLUTION: In a transistor including an oxide semiconductor as a channel layer, a silicon layer is provided in contact with a surface of an oxide semiconductor layer. The silicon layer is provided in contact with at least a region where a channel is formed in the oxide semiconductor layer, and a source electrode layer and a drain electrode layer are provided in contact with a region where the silicon layer is not provided in the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a transistor using an oxide semiconductor layer, a semiconductor device including the transistor, and methods for manufacturing them.

Background Art

[0002] Metal oxides exist in various forms and are used in a variety of applications. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

[0003] Some metal oxides exhibit semiconductor characteristics. Generally, metal oxides are insulators. However, depending on the combination of elements constituting the metal oxide, it is known that they can become semiconductors.

[0004] For example, metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors having such metal oxides exhibiting semiconductor characteristics as a channel formation region are already known (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] By the way, metal oxides are known not only as single-component oxides but also as multi-component oxides. For example, InGaO3(ZnO) (m: natural number) having a homologous phase is known as a multi-component oxide semiconductor containing In, Ga, and Zn (Non-Patent Documents 2 to 4). m

[0006] And it has been confirmed that an oxide semiconductor composed of an In-Ga-Zn-based oxide as described above can be applied as a channel layer of a thin film transistor (also referred to as a TFT) (Patent Document 5, Non-Patent Documents 5 and 6). ​​​​​​​​​​​​

[0007] However, oxide semiconductors are susceptible to damage from etching agents and plasma during the device fabrication process. The presence of elements such as hydrogen can easily alter semiconductor properties, which in turn affects the device's characteristics. Variations and degradation in electrical characteristics become a problem. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Japanese Patent Publication No. 2000-150900 [Patent Document 5] Japanese Patent Publication No. 2004-103957 [Non-patent literature]

[0009] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-licensed Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System", J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-licensed Document 4] Masaki Nakamura, Noboru Kimizuka, Naohiko Mori, Mitsumasa Isobe, "The crystal structure of the ホモロガス phase, InFeO3(ZnO)m(m: natural number) and the same type of compound", Solid State Physics, 1993, Vol.28, No.5, p.317-327 [Non-licensed Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-licensed Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, one aspect of the present invention is to suppress variations and deterioration in electrical characteristics in a transistor having an oxide semiconductor layer or a semiconductor device including the transistor. This is one of the problems.

Means for Solving the Problems

[0011] To solve the above problems, one aspect of the present invention is configured such that in a transistor using an oxide semiconductor as a channel layer, a silicon layer is provided in contact with the surface of the oxide semiconductor layer. In this case, the silicon layer functions as a protective film that reduces the incorporation of hydrogen or the like into the oxide semiconductor layer, functions as a protective film for the oxide semiconductor layer in the manufacturing process, and can suppress variations and deterioration in the electrical characteristics of the transistor.

[0012] Also, one aspect of the present invention is configured such that the silicon layer is provided in contact with at least a region where a channel is formed in the oxide semiconductor layer, and in the oxide semiconductor layer, the source electrode layer and the drain electrode layer are provided in contact with at least a part of a portion where the silicon layer is not in contact.

[0013] ​​​​​​​Furthermore, in one aspect of the present invention, in an oxide semiconductor layer, a region in which a silicon layer is not provided A low-resistance region that functions as a source region or drain region is provided in at least a part of the said A configuration can be achieved in which the source electrode layer and the drain electrode layer are placed in contact with each other in the low-resistance region.

[0014] Furthermore, one aspect of the present invention comprises a gate electrode, a gate insulating layer provided on the gate electrode, and An oxide semiconductor layer provided on the insulating layer and overlapping the gate electrode, and the surface of the oxide semiconductor layer A silicon layer provided in contact with the surface, and a source electrode electrically connected to the oxide semiconductor layer. A transistor having a layer and a drain electrode layer is provided. The source electrode layer and the drain electrode layer are in contact with at least a portion of the surface of the oxide semiconductor layer that is not in contact with the surface. It can be provided in the region of the oxide semiconductor layer in contact with the source electrode layer. A first low-resistance region is provided that functions as a zone, and the oxide semiconductor layer in contact with the drain electrode layer is provided. A second low-resistance region that functions as a drain region can be provided in the region.

[0015] Furthermore, one aspect of the present invention comprises a gate electrode, a gate insulating layer provided on the gate electrode, and An oxide semiconductor layer provided on the insulating layer and overlapping the gate electrode, and the oxide semiconductor layer A silicon layer is provided in contact with a portion of the surface, and an oxide semiconductor is provided where the silicon layer is not provided. A first metal oxide layer and a second metal are provided in contact with at least a portion of the surface of the conductive layer. An oxide layer, a source electrode layer electrically connected to the first metal oxide layer, and a second metal oxide layer The present invention provides a transistor having a physical layer and an electrically connected drain electrode layer.

[0016] Furthermore, one aspect of the present invention comprises a gate electrode, a gate insulating layer provided on the gate electrode, and A source electrode layer and a drain electrode layer are provided on a galvanic insulating layer, and the source electrode layer and drain An oxide semiconductor provided on the electrode layer and on the gate electrode via a gate insulating layer A transistor having a layer and a silicon layer provided in contact with the surface of the oxide semiconductor layer. provide.

[0017] Furthermore, in one aspect of the present invention, a gate electrode is formed on a substrate, and a gate insulating layer is formed on the gate electrode. Form an oxide semiconductor layer on the gate insulating layer so as to overlap with the gate electrode, and then form an oxide semiconductor layer on the gate insulating layer. A silicon layer is formed to cover the semiconductor layer, and the silicon layer is etched to form an oxide semiconductor. A portion of the layer is exposed, a conductive film is formed on the silicon layer and the oxide semiconductor layer, and the conductive film is etched. This provides a method for fabricating a transistor by chipping to form a source electrode layer and a drain electrode layer. do.

[0018] Furthermore, in one aspect of the present invention, a gate electrode is formed on a substrate, and a gate insulating layer is formed on the gate electrode. Form an oxide semiconductor layer on the gate insulating layer so as to overlap with the gate electrode, and then form an oxide semiconductor layer on the gate insulating layer. A silicon layer is formed to cover the semiconductor layer, and the silicon layer is etched to form an oxide semiconductor. By exposing a portion of the layer and performing plasma treatment on the exposed portion of the oxide semiconductor layer, low A resistive region is formed, a conductive film is formed on the silicon layer and the oxide semiconductor layer, and the conductive film is etched. This invention provides a method for fabricating a transistor by forming a source electrode layer and a drain electrode layer. ru.

[0019] In this specification, silicon oxidnitride is defined as having a composition in which the oxygen content is greater than the nitrogen content. It is more common, and preferably Rutherford backscattering (RBS) (rd Backscattering Spectrometry) and hydrogen forward scattering method Measurements were taken using (HFS: Hydrogen Forward Scattering). In that case, the concentration range would be 50-70 atomic percent oxygen, 0.5-15 atomic percent nitrogen, and silica This refers to substances containing 25-35 atomic percent of ions and 0.1-10 atomic percent of hydrogen. Silicon nitride is a material whose composition contains more nitrogen than oxygen. Preferably, when measured using RBS and HFS, the oxygen concentration range is 5 to 30 Atomic percent: 20-55 atomic percent nitrogen, 25-35 atomic percent silicon, 10-30 atomic percent hydrogen This refers to substances included within a certain percentage range. However, it does not include silicon oxide nitride or silicon nitride oxide as constituent elements. When the total amount of atoms is set to 100 atomic%, the content ratios of nitrogen, oxygen, silicon, and hydrogen are It shall be included within the above scope.

[0020] In this specification, "semiconductor device" refers to all devices that can function by utilizing semiconductor properties. The term "electronic device" includes all "display devices," "semiconductor circuits," and "electronic devices." In this document, the term "display device" includes light-emitting devices and liquid crystal display devices. Light-emitting devices include light-emitting elements. A liquid crystal display device includes liquid crystal elements. The brightness of the light-emitting element is controlled by current or voltage. This category includes elements such as inorganic EL (Electroluminescent Lumines). This includes elements such as CE elements, organic EL elements, and LED elements.

[0021] In this specification, B is formed on A, or B is formed on A. When explicitly stating this, it is not limited to the case that B is formed in direct contact with A. i. This also includes cases where there is no direct contact, that is, when another object is interposed between A and B. Let's assume that. [Effects of the Invention]

[0022] According to one aspect of the present invention, in a transistor in which the channel layer is made of an oxide semiconductor, By providing a silicon layer in contact with the surface of the semiconductor layer, the electrical characteristics of the transistor are improved. It can suppress the deterioration of sexual function. [Brief explanation of the drawing]

[0023] [Figure 1] A diagram illustrating the configuration of a transistor according to Embodiment 1. [Figure 2] A diagram illustrating an example of a method for fabricating a transistor according to Embodiment 1. [Figure 3] A diagram illustrating the configuration of a transistor according to Embodiment 1. [Figure 4] A diagram illustrating the configuration of a transistor according to Embodiment 1. [Figure 5] A diagram illustrating an example of a method for fabricating a transistor according to Embodiment 2. [Figure 6] A diagram illustrating the configuration of a transistor according to Embodiment 2. [Figure 7] A diagram illustrating the configuration of a transistor according to Embodiment 3. [Figure 8] A diagram illustrating an example of a method for fabricating a transistor according to Embodiment 3. [Figure 9] A diagram illustrating the configuration of a transistor according to Embodiment 3. [Figure 10] A diagram illustrating the configuration of a transistor according to Embodiment 4. [Figure 11] A diagram illustrating an example of a method for fabricating a transistor according to Embodiment 4. [Figure 12] A diagram illustrating the configuration of a transistor according to Embodiment 4. [Figure 13] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 14] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 15] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 16] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 17] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 18] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 19] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 20] A diagram illustrating an example of a semiconductor device according to Embodiment 6. [Figure 21] A diagram illustrating an example of a semiconductor device according to Embodiment 7. [Figure 22] A diagram illustrating an example of a semiconductor device according to Embodiment 8. [Figure 23] External view showing examples of television equipment and digital photo frames. [Figure 24] An external view showing an example of a gaming machine. [Figure 25] A diagram illustrating an example of a method for fabricating a transistor according to Embodiment 1. [Figure 26] A diagram illustrating the configuration of a transistor according to Embodiment 1. [Figure 27] A diagram illustrating the model used in the simulation. [Figure 28] A diagram illustrating the hydrogen diffusion coefficient obtained through simulation. [Modes for carrying out the invention]

[0024] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The invention is not limited to the embodiments described below, and without departing from the spirit of the invention, it may take any form. It is obvious to those skilled in the art that the form and details can be modified in various ways. Therefore, the present invention The following descriptions of embodiments are not to be interpreted as being limited to those described below. The configurations related to the form can be combined as appropriate. Furthermore, the following development In the structure of the light, the same reference numeral is used for identical parts or parts having similar functions, and their repetition I will omit the explanation of the counter-argument.

[0025] (Embodiment 1) In this embodiment, an example of the structure of a transistor constituting a semiconductor device is shown in the drawings. I will explain by referring to it.

[0026] The transistor 120 shown in Figure 1 has a gate (gate wiring and gate) provided on the substrate 100. If a gate electrode is included (hereinafter referred to as "gate electrode 102"), then a gate electrode 102 is provided A gate insulating layer 104 and an oxide semiconductor layer 108 provided on the gate insulating layer 104 And, a silicon layer 112 provided so as to be in contact with the surface of the oxide semiconductor layer 108, and Sources electrically connected to the semiconductor layer 108 (including source wiring and source electrodes) (hereinafter) (Denoted as "source electrode layer 116a") and drain (drain wiring and drain electrode) It includes (hereinafter referred to as "drain electrode layer 116b") (see Figure 1).

[0027] In Figure 1, Figure 1(A) shows a top view, and Figure 1(B) shows A1 in Figure 1(A). Figure 1(C) shows a cross-sectional view between A2 and B1, and Figure 1(A) shows a cross-sectional view between A2 and B2. This indicates that.

[0028] The oxide semiconductor layer 108 is at least partially connected to the gate electrode 10 via the gate insulating layer 104. It is provided so as to overlap with 2, and is a layer (ch) that forms the channel region of transistor 120. It functions as a channel layer.

[0029] As the oxide semiconductor layer 108, any oxide material having semiconductor properties can be used. For example InMO3(ZnO) m It is possible to use oxide semiconductors with a structure represented by (m>0). In particular, it is preferable to use an In-Ga-Zn-O based oxide semiconductor. Note that M is Ga Iron (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co This indicates one or more metallic elements selected from ). For example, if M is Ga, In addition to the above, if Ga and Ni or Ga and Fe are included, In addition, in the above oxide semiconductor, in addition to the metal element contained as M, there are impurity elements. Products containing Fe, Ni, or other transition metal elements, or oxides of said transition metals, as elements. In this specification, InMO3(ZnO) m Acids with a structure represented by (m>0) Among oxide semiconductors, oxide semiconductors with a structure containing at least Ga as M are called In-Ga-Z This is called an nO-based oxide semiconductor, and the thin film is also called an In-Ga-Zn-O non-single crystal film.

[0030] In addition to the above, other oxide semiconductors that can be applied to the oxide semiconductor layer 108 include In-Sn- Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system In-O, Sn-O, and Zn-O oxide semiconductors can be applied.

[0031] The silicon layer 112 is an oxide semiconductor in at least the region overlapping with the gate electrode 102. It is provided so as to be in contact with the surface of layer 108. Furthermore, silicon layer 112 is made of oxide semiconductor It is provided so as to be in contact with a part of the surface of the conductive layer 108, and in the oxide semiconductor layer 108 In the region where the recon layer 112 is not provided, the source electrode layer 116a and the drain electrode layer 11 A structure in which 6b is provided in contact with each other can be provided. Here, the oxide semiconductor layer 108 is Regions where the recon layer 112 is not provided are provided spaced apart from each other, and each of these regions is provided with This diagram shows the case where the drain electrode layer 116a and the drain electrode layer 116b are provided in contact with each other.

[0032] Furthermore, it is preferable that the silicon layer 112 be made of i-type (intrinsic) silicon. In this context, "i-type silicon" refers to silicon containing impurities that impart either p-type or n-type silicon. Each is 1 x 10 17 atoms / cm 3 The concentration is less than 1 unit each of oxygen and nitrogen. ×10 20 atoms / cm 3 This refers to silicon with the following concentrations. Therefore, this silicon The corn contains impurity elements such as phosphorus (P) or boron (B) within the ranges mentioned above. It is also possible that the concentration of these impurities contained in the silicon layer 112 is secondary ions. Secondary Ion Mass Spectrosc (SIMS) Measurements can be taken using opy.

[0033] Furthermore, the crystalline state of the silicon layer 112 can be amorphous silicon or microcrystalline silicon. It can be silicon or polycrystalline (poly)silicon. Note that the silicon layer 112 is Of these crystal structures, two or more crystal structures (for example, amorphous structure and microcrystalline structure (or It may also contain a polycrystalline structure.

[0034] Furthermore, methods for forming the silicon layer 112 include CVD, sputtering, vapor deposition, and coating. It can be used. Also, the thickness of the silicon layer 112 is 1 nm or more and 500 nm or less. Preferably, the wavelength can be between 10 nm and 100 nm.

[0035] For example, in an atmosphere that does not contain hydrogen, such as an argon atmosphere, or an atmosphere with a low hydrogen content. In this process, the silicon layer 112 is formed by sputtering, thereby forming the silicon layer 112 film The hydrogen concentration contained therein is reduced, and the oxide caused by the hydrogen contained in the silicon layer 112 This can reduce fluctuations in the semiconductor properties of the semiconductor layer 108.

[0036] Furthermore, when depositing the silicon layer 112 using the sputtering method, a DC sputtering apparatus is used. It is preferable to use a pulsed DC sputtering device (including a pulsed biasing device). By using a DC sputtering system, compared to using an RF sputtering system, larger size This also makes it possible to use substrates. This is because a silicon oxide layer or silicon nitride layer can be used as a protective layer. This offers a significant advantage compared to using an insulating layer such as a silicon oxide layer. When forming insulating layers such as silicon nitride layers by sputtering (with an insulator as the target) This is because, when using (this method), it is necessary to use RF sputtering, which is difficult to scale up.

[0037] When depositing the silicon layer 112 using a DC sputtering apparatus, the silicon target is used. Alternatively, a silicon target to which impurities such as boron have been added can be used.

[0038] As shown in Figure 1, the back channel side of the oxide semiconductor layer 108 (opposite the gate electrode 102) By providing the silicon layer 112 in contact with the side surface, the silicon layer 112 is maintained It functions as a protective film and can suppress the mixing of hydrogen and other elements into the oxide semiconductor layer 108. As a result, the semiconductor properties of the oxide semiconductor layer 108 are affected by the inclusion of elements such as hydrogen. This suppresses the electrical characteristics of the transistor with the oxide semiconductor layer 108 as the channel layer. This makes it possible to suppress variations and deterioration in sexual characteristics.

[0039] Furthermore, a source electrode layer 116a and a drain electrode layer 116b are provided on the oxide semiconductor layer 108. In this case, the silicon layer 112 functions as a channel protection layer (channel stop layer). This is possible. Therefore, in cases where the silicon layer 112 is not provided in contact with the oxide semiconductor layer 108, Compared to the combined (channel etch) type, the properties change due to the exposure of the oxide semiconductor layer 108. This can suppress the transformation. The silicon layer 112 is actively made to function as a channel protection layer. In such cases, it is preferable to make the silicon layer 112 a dense film. For example, the CVD method By using this to form the silicon layer 112, a dense film can be created.

[0040] The silicon layer 112 has a region where channels are formed in at least the oxide semiconductor layer 108. It should be provided so as to be in contact with the surface of the region. Also, on the silicon layer 112, a silicon oxide film, A silicon oxide-nitride film, a silicon nitride film, or a silicon nitride-oxide film may be formed. The insulating film to be placed on layer 112 is formed by depositing a film using the sputtering method or the CVD method. Alternatively, the surface of the silicon layer 112 may be oxidized (including spontaneous oxidation) or nitrided. It may also be provided. To oxidize or nitride the surface of the silicon layer 112, use an oxygen atmosphere or a nitrogen atmosphere. Plasma treatment should be performed in a plain atmosphere.

[0041] Furthermore, in Figure 1, the source electrode layer 116a functions as the source of the transistor 120. The drain electrode layer 116b functions as the drain of the transistor 120. Depending on the driving method of the inverter 120, the source electrode layer 116a may function as a drain. The drain electrode layer 116b may also function as a source.

[0042] Furthermore, in the configuration shown in Figure 1, the material provided in contact with the surface of the oxide semiconductor layer 108 is In addition to silicon, there is also germanium, and silicon to which germanium is added. Germanium or silicon carbide (SiC) may be used.

[0043] Next, regarding the effect of placing the silicon layer in contact with the oxide semiconductor layer, a computer simulation was performed. This will be explained based on the theory. Note that here, amorphous silicon (a-Si) and We investigated the hydrogen blocking effect of morphous silicon oxide (a-SiO2). Ta.

[0044] <Calculation method> First, using classical molecular dynamics simulations, at a temperature T=27°C and a pressure P=1atm... Then, by numerically solving the equations of motion for each atom, the motion of the atoms was tracked. From the mean squared displacement of H obtained from the calculation results, Einstein's formula (equation (1)) Next, we determine the diffusion coefficient D of H. A larger diffusion coefficient D means that it diffuses more easily. ru.

[0045]

number

[0046] <Calculation Model and Calculation Conditions> a-Si:H model in which 60 atoms (10 atom%) of H are inserted into a-Si with 540 atoms. (See Figure 27(A)) and 60 atoms (10 atom%) of H in 540 atoms of α-SiO2. A model of a-SiO2:H (see Figure 27(B)) was prepared. Here, the three-dimensional periodic boundary This model calculates bulk by imposing boundary conditions.

[0047] The classical molecular dynamics method used in this calculation characterizes the interatomic interactions with empirical potentials. By defining this, we can evaluate the forces acting on each atom. In the a-Si:H model, Tersoff Potential was used. In the a-SiO2:H model, the Born-Maye Using the r-Huggins potential and Morse potential, α-SiO2 and hydrogen In interatomic interactions (between silicon atoms and hydrogen atoms, between oxygen atoms and hydrogen atoms), Lenn The Ard-Jones potential was used. The calculation program was manufactured by Fujitsu Limited. Using the simulation software "Materials Explorer 5.0" .

[0048] In each calculation model, the temperature T=27°C and pressure P=1atm are used for a time step of 1 nsec. A classical molecular dynamics simulation was performed with a width of 0.2 fsec and 5 million steps.

[0049] <Calculation Results and Discussion> The mean squared displacement of H atoms in a-Si and the mean squared displacement of H atoms in a-SiO2, which were obtained from calculations. The squared displacements are shown in Figure 28(A). In Figure 28(A), the slope of the graph is approximately one H atoms in each calculation model obtained from the fixed region (70 psec to 100 psec) The diffusion coefficient D is shown in Figure 28(B). From Figure 28(B), the H atoms in a-Si are more numerous. The diffusion coefficient is smaller than that of H atoms in a-SiO2, and is smaller than that of H atoms in a-Si. However, it was found that it diffuses less easily than H atoms in a-SiO2. In other words, a-Si film This is considered to be more effective in preventing hydrogen contamination compared to an a-SiO2 film.

[0050] Next, regarding the shape of the oxide semiconductor layer 108 and the silicon layer 112 in the configuration shown in Figure 1... This will be explained. In the following explanation, the width (Wb) of the silicon layer 112 and the oxide semiconductor are used. The width (Wc) of layer 108 is the length of silicon layer 112 in the channel width direction, respectively. This refers to the length of the oxide semiconductor layer 108. It also refers to the length (Lb) of the silicon layer 112, and the oxide semiconductor layer... The length (Lc) of the conductor layer 108 is the length of the silicon layer 112 in the channel length direction. Length refers to the length of the oxide semiconductor layer 108. Also, the channel length direction refers to the transistor 1 In 20, the direction in which the carrier moves is roughly parallel to the direction (source electrode layer 116a and the drain The channel width direction refers to the direction connecting the electrode layers 116b, and is roughly perpendicular to the channel length direction. It points in that direction.

[0051] The transistor shown in Figure 1 has a silicon layer 112 width (Wb) and an oxide semiconductor layer 108 width (Wc) is made larger than the silicon layer 112 in the channel width direction, which is an oxide semiconductor. This shows the case where it is installed so as to cross over (over) both ends of the body layer 108. The length (Lb) of the recon layer 112 is made smaller than the length (Lc) of the oxide semiconductor layer 108. Two regions are provided in the channel length direction that are not covered by the silicon layer 112, and these regions are spaced apart. The source electrode layer 116a and the drain electrode layer 116b are electrically connected to the provided region. This shows an example of how it can be provided. By providing it in this way, the oxide semiconductor layer 108 This can reduce leakage current caused by changes in the semiconductor properties of the surface.

[0052] Note that the transistor configuration shown in this embodiment is not limited to that shown in Figure 1.

[0053] In Figure 1, the length (Lc) of the oxide semiconductor layer 108 is increased, and in the channel length direction... The transistor 120 is shown in a configuration that extends over the end of the gate electrode 102. As shown in Figure 3, the length (Lc) of the oxide semiconductor layer 108 is reduced, as in transistor 121. Thus, a configuration in which all of the oxide semiconductor layer 108 is placed on the gate electrode 102 may also be used. Note that in Figure 3, Figure 3(A) shows a top view, and Figure 3(B) is a top view of Figure 3(A). This shows a cross-sectional view of A1-B1.

[0054] Furthermore, in the configurations shown in Figures 1 and 3, in the region overlapping with the oxide semiconductor layer 108, The width (Wd) of the drain electrode layer 116a and the drain electrode layer 116b is set to the width of the oxide semiconductor layer 108. It may be formed to be larger than (Wc) (see Figures 4(A) and (B)). Figure 4(A) The transistors 122 and 123 shown in (B) respectively are located in silicon layer 1 The region of the oxide semiconductor layer 108 that is not in contact with 12 is the source electrode layer 116a and the drain electrode Because it can be covered by the polar layer 116b, the oxide semiconductor layer 108 is protected and reliability is improved. It has the advantage of being able to be raised. Also, the oxide semiconductor layer 108 and the source electrode layer 1 The contact area between 16a and the drain electrode layer 116b is increased, and the oxide semiconductor layer 108 and the saw This reduces the contact resistance between the drain electrode layer 116a and the drain electrode layer 116b. ru.

[0055] Note that the width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is the channel width. This refers to the lengths of the source electrode layer 116a and the drain electrode layer 116b in that direction.

[0056] Furthermore, the width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is set to the silicon layer 11 It may be formed to be larger than the width (Wb) of 2, or the source electrode layer 116a and the drain Only one width (Wd) of the electrode layer 116b is the width (Wc) of the oxide semiconductor layer 108 (and It may be formed to be larger than the width (Wb) of the silicon layer 112.

[0057] Furthermore, in the configuration shown in this embodiment, a bra is placed above and / or below the silicon layer 112. A light-shielding section, such as a black matrix, can be provided to shield the silicon layer 112 from light. By configuring the silicon layer 112 to block light, light is irradiated onto the silicon layer 112. This can suppress variations in the electrical characteristics of transistors caused by this. When a light-shielding material is used for the electrode 102, the top of the silicon layer 112 (gate electrode) A light-shielding section, such as a black matrix, can be provided on the opposite side of 102.

[0058] Next, an example of a method for fabricating the transistor shown in Figure 1 will be explained with reference to Figure 2.

[0059] First, a gate electrode 102 is formed on the substrate 100, and then a gate electrode 102 is formed on the gate electrode 102. An insulating layer 104 is formed, and then an oxide semiconductor layer 106 is formed on the gate insulating layer 104. (See Figure 2(A)).

[0060] The substrate 100 can be any substrate having an insulating surface; for example, a glass substrate can be used. Yes, it is possible. In addition, as substrate 100, there are ceramic substrates, quartz substrates and sapphire substrates, etc. An insulating substrate made of a rim body, or a semiconductor substrate made of a semiconductor material such as silicon, has its surface covered with an insulating material. The covering is a conductive substrate made of a conductive material such as metal or stainless steel, with its surface coated with an insulating material. Materials can be used. Also, if it can withstand the heat treatment in the manufacturing process, plastic A black substrate can also be used.

[0061] The gate electrode 102 is formed by first forming a conductive film over the entire surface of the substrate 100, and then using photolithography. Furthermore, it can be formed by etching a conductive film.

[0062] The gate electrode 102 is made of aluminum (Al), copper (Cu), molybdenum (Mo), and tungsten. It can be formed from conductive materials such as stainless steel (W) and titanium (Ti). Furthermore, wiring and When using aluminum as an electrode, pure aluminum has low heat resistance and is prone to corrosion. Due to the following problems, it is preferable to form it in combination with a heat-resistant conductive material.

[0063] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum. Selected from den (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). Elements, alloys containing the above-mentioned elements, alloys combining the above-mentioned elements, or the above-mentioned It can be formed from nitrides composed of elements. Films made of these heat-resistant conductive materials. By laminating aluminum (or copper), wiring and electrodes can be formed.

[0064] Furthermore, the gate electrode 102 is made of a material that is transparent to visible light and has high conductivity. It may be formed by [doing something]. For example, indium tin oxide (Indiu m Tin Oxide (ITO), indium tin oxide (ITSO) containing silicon dioxide, Organic indium, organotin, zinc oxide (ZnO), etc., can be used.

[0065] The gate insulating layer 104 consists of a silicon oxide film, a silicon oxide nitride film, a silicon nitride film, and an acid nitride film. It can be formed from a silicon oxide film, an aluminum oxide film, or a tantalum oxide film, etc. These films may be layered together. These films may be formed, for example, by sputtering. The film thickness can be formed to be between 10 nm and 500 nm.

[0066] The oxide semiconductor layer 106 can be formed using an In-Ga-Zn-O based oxide semiconductor. Yes, it is possible. In this case, an oxide semiconductor target containing In, Ga, and Zn (for example, In Acids with an amorphous structure obtained by sputtering using 2O3:Ga2O3:ZnO=1:1:1 A synthetic semiconductor layer 106 can be formed.

[0067] For example, the conditions for the sputtering method include a distance of 30 mm or more between the substrate 100 and the target. 00mm or less, pressure between 0.01Pa and 2.0Pa, DC power supply of 0.25kJ Power consumption: W or more, 5.0 kW or less; temperature: 20°C or more, 200°C or less; atmosphere: argon atmosphere, oxygen This can be a neutral atmosphere, or a mixed atmosphere of argon and oxygen.

[0068] Furthermore, in the sputtering method, using a pulsed DC power supply can reduce dust and improve film thickness. The uniform distribution is also preferable. Furthermore, the film thickness of the oxide semiconductor layer 106 is 5 nm or more. It can be reduced to approximately 0 nm or less.

[0069] When forming an In-Ga-Zn-O non-single-crystal film as the oxide semiconductor layer 106, Then, insulating impurities are added to an oxide semiconductor target containing In, Ga, and Zn. It is acceptable if they are present. Examples of such impurities include silicon oxide, germanium oxide, and aluminum oxide. Insulating oxides such as silicon nitride and aluminum nitride are representative of insulating materials. Nitrides, or insulating oxynitrides such as silicon oxynitride or aluminum oxynitride, are applied. These insulating oxides or insulating nitrides do not impair the electrical conductivity of oxide semiconductors. It is added at a concentration that is not present.

[0070] By including insulating impurities in the oxide semiconductor layer 106, the oxide semiconductor layer 106 The crystallization of the oxide semiconductor layer 106 can be suppressed. This makes it possible to stabilize the characteristics of thin-film transistors. Also, In-Ga-Zn-O By incorporating impurities such as silicon oxide into the oxide semiconductor, it becomes possible to operate at temperatures above 200°C and 600°C. Even when heat treatment is performed below °C, it is possible to prevent crystallization of the oxide semiconductor or the formation of microcrystalline grains. Cut.

[0071] In addition to the above, In-Sn-Zn- O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In -O-based, Sn-O-based, and Zn-O-based oxide semiconductors can be applied. By adding impurities to the oxide semiconductor that suppress crystallization and maintain an amorphous state, The characteristics of thin-film transistors can be stabilized. The impurities in question are silicon oxide and acid Insulating oxides such as germanium oxide and aluminum oxide, silicon nitride, nitride Insulating nitrides such as aluminum, or silicon oxynitride, aluminum oxynitride These include insulating oxynitrides such as um.

[0072] Next, the oxide semiconductor layer 106 is etched to form island-shaped oxide semiconductor layers 108. See Figure 2(B). In this case, the island-shaped oxide semiconductor layer 108 is at least connected to the gate electrode 10 The oxide semiconductor layer 106 is etched so that it remains above layer 2.

[0073] Next, a silicon layer 110 is formed to cover the oxide semiconductor layer 108 (see Figure 2(C)). ).

[0074] The silicon layer 110 can be formed by sputtering. In this case, an argon atmosphere DC under gas pressure using a silicon target or a silicon target with boron added. A silicon layer 110 can be formed by sputtering. However, it is not limited to this, and silicon The film layer 110 may be formed using a CVD method or the like. Depending on the film formation conditions, oxide semi-oxides may form. At the interface between the conductive layer 108 and the silicon layer 110, the oxide semiconductor layer 108 and the silicon layer 110 A thin mixed layer (for example, silicon oxide) may be formed.

[0075] Next, the silicon layer 110 is etched to form island-shaped silicon layers 112 (Figure 2(D) (See reference). In this case, the island-shaped silicon layer 112 is placed in a region that overlaps with at least the gate electrode 102. The silicon layer 110 is etched so that it remains in the region. Also, the oxide semiconductor layer 108 The silicon layer 110 is etched to expose at least a portion of it.

[0076] For etching, for example, TMAH (Tetra Methyl Ammonium Wet wipes using Hydroxide (tetramethylammonium hydroxide) Chining can be applied. In this case, the oxide semiconductor layer 108 and the silicon layer 110 A high etching selectivity ratio can be achieved, and the oxide semiconductor layer 108 is almost completely etched. Without doing so, the silicon layer 110 can be etched well. This can reduce damage to the semiconductor layer 108.

[0077] Note that etching selectivity refers to, for example, the etching selectivity of layer A when etching layer A and layer B. This refers to the difference between the etching rate of layer B and the etching rate of layer B. A high selectivity ratio means that there is a sufficient difference in etching rates.

[0078] Next, a conductive film 11 is placed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. Form 4 (see Figure 2(E)).

[0079] The conductive film 114 is made using methods such as sputtering and vacuum deposition, using aluminum (Al) and copper (Cu ), Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), A metal containing elements selected from chromium (Cr), neodymium (Nd), and scandium (Sc). A material consisting of an alloy containing the above-mentioned elements, or a nitride containing the above-mentioned elements. It can be formed.

[0080] For example, the conductive film 114 can be formed as a single-layer structure of a molybdenum film or a titanium film. Furthermore, the conductive film 114 may be formed in a laminated structure, for example, an aluminum film and a titanium film. This can be a layered structure. Furthermore, a titanium film, an aluminum film, and another titanium film can be layered sequentially. A three-layer structure with layers is also possible. Alternatively, a molybdenum film, an aluminum film, and a molybdenum film may be used. A three-layer structure in which these are stacked in order may also be used. Furthermore, the aluminum used in these stacked structures A neodymium-containing aluminum (Al-Nd) film may be used as the film. Furthermore, conductive The film 114 may also be a single-layer structure of an aluminum film containing silicon.

[0081] Furthermore, the conductive film 114 is made of a material that is transparent to visible light and has high conductivity. It may be formed. For example, indium tin oxide (Indium Indium tin oxide (ITSO), containing silicon dioxide, organic Indium, organotin, zinc oxide (ZnO), etc., can be used.

[0082] Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b. A conductive film 114 is formed (see Figure 2(F)). During this process, etching conditions are used to etch the conductive film 114. Simultaneously with etching, the silicon layer 112 may also be etched, resulting in film reduction. Here, conductive This shows a case where the silicon layer 112 is also etched and the film thickness decreases when the film 114 is etched. Yes, they are.

[0083] In the above process, the silicon layer 112 is an oxide semiconductor during the etching of the conductive film 114. It functions as a channel protection layer (channel stop layer) that suppresses etching of layer 108. Furthermore, in the oxide semiconductor layer 108, in the region where the silicon layer 112 is not provided... In some cases, the oxide semiconductor layer 108 may be reduced in thickness at the same time as the conductive film 114 is etched.

[0084] In this way, by providing the silicon layer 112 in contact with the oxide semiconductor layer 108, This suppresses the intrusion of unintended elements such as hydrogen into the oxide semiconductor layer 108 from the outside. It is possible.

[0085] By following the above steps, transistor 120 can be manufactured.

[0086] Furthermore, a protective insulating layer may be formed to cover the transistor 120. For example, using methods such as CVD or sputtering, silicon oxide films, silicon nitride films, and acid Silicon nitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film, acid It may be formed as a single layer or a multilayer of aluminum nitride film or aluminum nitride oxide film. Furthermore, after forming the source electrode layer 116a and the drain electrode layer 116b, the silicon layer 11 By oxidizing (including natural oxidation) or nitriding the exposed portion of 2, the source electrode layer 116a A silicon oxide film is placed on the silicon layer 112 located in the region between the drain electrode layer 116b and the drain electrode layer 116b. A silicon nitride film, a silicon oxide nitride film, or a silicon nitride oxide film may be formed.

[0087] Furthermore, in the process shown in Figure 2, after forming the oxide semiconductor layer 108, the process is carried out under a nitrogen atmosphere or air. Under ambient conditions, temperatures between 100°C and 600°C, typically between 200°C and 400°C. Heat treatment is preferable. For example, heat treatment at 350°C for 1 hour under a nitrogen atmosphere. This heat treatment can be performed to rearrange the island-like oxide semiconductor layer 108 at the atomic level. In that it can release the strain that inhibits carrier movement in the oxide semiconductor layer 108. It is important.

[0088] Furthermore, the timing of the heat treatment is not particularly limited as long as it is performed after the formation of the oxide semiconductor layer 106. First, after forming the silicon layer 110, then forming the island-shaped silicon layer 112, then the conductive film 11 After forming 4, after forming the source electrode layer 116a and the drain electrode layer 116b or after maintaining This may be done after forming the protective insulating layer. Note that depending on the heat treatment conditions, etc., oxide semiconductors may also be affected. A mixture of oxide semiconductor layer 108 and silicon layer 112 is present at the interface between layer 108 and silicon layer 112. A thin layer (for example, silicon oxide) may be formed.

[0089] Subsequently, by forming various electrodes and wiring, the semiconductor device equipped with transistor 120 is completed. To accomplish.

[0090] In Figure 2 above, the silicon layer 110 is formed after the oxide semiconductor layer 108 is formed. As shown in the example, the oxide semiconductor layer 106 and the silicon layer 110 are formed by continuously stacking them. After that, multiple masks are used to apply patterns to the silicon layer 112 and the oxide semiconductor layer 108 respectively. It may be done. The manufacturing method in this case will be explained with reference to Figure 25.

[0091] First, a gate electrode 102 is formed on the substrate 100, and then a gate electrode 102 is formed on the gate electrode 102. A gate insulating layer 104 is formed. Subsequently, an oxide semiconductor layer 106 and a gate insulating layer 104 are formed. After sequentially stacking and forming the recon layers 110, a resist mask 175 is selectively formed. See Figure 25(A). From gate insulating layer 104 to silicon layer 110, or oxide semiconductor It is preferable to continuously deposit the film from layer 106 to silicon layer 110.

[0092] Next, using the resist mask 175, the silicon layer 110 and the oxide semiconductor layer 106 are inspected. The essential parts are etched to form island-shaped oxide semiconductor layers 108 and silicon layers 111. (See Figure 25(B)). Then, remove the resist mask 175.

[0093] Next, a resist mask 176 is formed on the silicon layer 111, and the resist mask 176 By using this method, the exposed silicon layer 111 is etched, thereby creating island-shaped silicon layers 1 Forms 12 (see Figure 25(C)).

[0094] Next, a conductive film 11 is placed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. After forming 4 (see Figure 25(D)), the conductive film 114 is etched to form the source electrode. Layer 116a and drain electrode layer 116b are formed (see Figure 25(E)).

[0095] By following the above steps, a transistor 124 as shown in Figure 26 can be fabricated. The transistor 124 shown in 26 has a silicon layer 112 width (Wb) and an oxide semiconductor layer 10 This shows the case where the width (Wc) of 8 is set to be equal. Note that in Figure 26, Figure 26(A) shows a top view, and Figure 26(B) shows the area between A1 and B1 in Figure 26(A). The diagrams show cross-sectional views, with Figure 26(C) showing a cross-sectional view between A2 and B2 in Figure 26(A). It is.

[0096] In this way, by continuously forming the oxide semiconductor layer 106 and the silicon layer 110, Damage caused by etching agents, plasma, etc., to the surface of the oxide semiconductor layer 106 This can reduce the risk.

[0097] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0098] (Embodiment 2) In this embodiment, a method and configuration for manufacturing a transistor that differs from that of Embodiment 1 described above is described. I will explain this by referring to the drawings.

[0099] First, the method for fabricating the transistor will be explained with reference to Figure 5. The manufacturing process (applicable materials, etc.) shown in the diagram is largely the same as that of Embodiment 1 described above. Therefore, in the following, we will omit explanations of overlapping parts and explain the differences in detail. explain.

[0100] First, a gate electrode 102 is formed on the substrate 100, and then a gate electrode 102 is formed on the gate electrode 102. A gate insulating layer 104 is formed. Subsequently, an oxide semiconductor layer 106 and a gate insulating layer 104 are formed. After sequentially stacking and forming the recon layers 110, a resist mask 171 is selectively formed. See Figure 5(A). From gate insulating layer 104 to silicon layer 110, or oxide semiconductor layer It is preferable to continuously deposit the film from layer 106 to the silicon layer 110.

[0101] Next, the silicon layer 110 is etched using the resist mask 171, creating island-shaped silicon An etching layer 111 is formed (see Figure 5(B)). Here, an alkaline etching solution is used. Wet etching is performed. By using an alkaline etching solution, oxide semi-oxides are removed. The etching selectivity ratio between the conductive layer 106 and the silicon layer 110 can be increased, Layer 110 can be selectively etched. Note that an alkaline etching solution is used. For example, TMAH (Tetra Methyl Ammonium Hydroxide) You can use ide (tetramethylammonium hydroxide).

[0102] Next, the oxide semiconductor layer 106 is etched using the resist mask 171, and island-shaped acid A crystalline semiconductor layer 108 is formed (see Figure 5(C)). Here, an acid-based etching solution is used. Wet etching is performed on the oxide semiconductor. By using an acid-based etching solution, The etching selectivity ratio between layer 106 and silicon layer 111 can be increased, making oxide semiconductors Layer 106 can be selectively etched. Note that the acid-based etching solution is: For example, a mixture of phosphoric acid, acetic acid, nitric acid, and water (also called aluminum mixed acid) can be used. ru.

[0103] Next, the silicon layer 111 is etched using the resist mask 171, creating island-shaped silicon Forming layer 112 (see Figure 5(D)). Here, an alkaline etching solution is applied again. Wet etching is performed using the same method. By using an alkaline etching solution, oxidation occurs. The etching selectivity ratio between the semiconductor layer 108 and the silicon layer 111 can be increased, The cone layer 111 can be selectively etched. Here, the etching is isotropic. As the process progresses, the sides of the silicon layer 111 are etched (side etching). Examples of potassium-based etching solutions include TMAH (Tetra Methyl Ammonia). Using onium hydroxyde (tetramethylammonium hydroxide) It is possible.

[0104] Thus, by etching the silicon layer after etching the oxide semiconductor layer, This allows etching of the oxide semiconductor layer and silicon layer without adding a mask. Therefore, the process can be simplified.

[0105] Next, a conductive film is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. After this, the conductive film is etched to form the source electrode layer 116a and the drain electrode layer 116 b is formed (see Figure 5(E)).

[0106] By following the above steps, a transistor 130 as shown in Figure 6 can be fabricated. In Figure 6, Figure 6(A) shows a top view, and Figure 6(B) shows the same view as in Figure 6(A). Figure 6(C) shows a cross-sectional view between 1 and B1, and Figure 6(A) shows the cross-section between A2 and B2 in Figure 6(A). A diagram is shown.

[0107] When the manufacturing method shown in Figure 5 is used, the width (Wb) of the silicon layer 112 is as shown in Figure 6. ) becomes smaller than the width (Wc) of the oxide semiconductor layer 108, and the length of the silicon layer 112 (Lb) becomes smaller than the length (Lc) of the oxide semiconductor layer 108.

[0108] In the fabrication process shown in Figure 5, the oxide semiconductor layer 106 and the silicon layer 110 are formed in a continuous manner. As a result, damage caused by etching agents, plasma, etc., to the surface of the oxide semiconductor layer 106 The addition of esters can be reduced. By providing a silicon layer that allows for a suitable switching selectivity ratio, the oxide semiconductor layer and the silicon layer can be separated. Even when making adjustments, the process can be simplified without adding a mask. Cut.

[0109] Furthermore, after forming the transistor 130, a protective insulating layer is applied to cover the transistor 130. It may also be formed. In addition, in the process shown in Figure 5, after forming the oxide semiconductor layer 108, nitrogen Heat treatment may be performed under atmospheric conditions or in an air atmosphere.

[0110] Note that the method for fabricating transistor 130 shown in Figure 6 is not limited to the method shown in Figure 5. For example, after proceeding to Figure 5(C), the resist mask 171 is subjected to an oxygen plasma treatment. By performing the scrubbing, the resist mask 171 is isotropically reduced and the silicon layer 11 After exposing a portion of 1, the exposed portion of the silicon layer 111 is etched. A silicon layer 112 may be formed.

[0111] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0112] (Embodiment 3) In this embodiment, a transistor and a method for manufacturing the same that differ from those in embodiments 1 and 2 described above are described. The following will be explained with reference to the drawings. The manufacturing process (applicable materials, etc.) shown in this embodiment is also described. This is in common with Embodiment 1 above in many respects. Therefore, in the following, there will be no overlap. The explanation of the parts that are the same will be omitted, and the differences will be explained in detail.

[0113] The transistor 140 shown in Figure 7 has a gate electrode 102 provided on the substrate 100, and a gate electrode 102. A gate insulating layer 104 provided on the electrode 102, and a gate insulating layer 104 provided on the gate insulating layer 104 An oxide semiconductor layer 108 and a silica provided in contact with the surface of the oxide semiconductor layer 108 A source electrode layer provided so as to be in contact with the surface of the cone layer 112 and the oxide semiconductor layer 108. The oxide semiconductor layer 108 has a drain electrode layer 116a and a drain electrode layer 116b, and the source electrode Low-resistance regions 109a and 109b are located in the regions in contact with the polar layer 116a and the drain electrode layer 116b. A system is in place.

[0114] In other words, the transistor 140 shown in this embodiment has the configuration shown in the above embodiment. Therefore, a low-resistance region is formed in the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided. The configuration includes the addition of 109a and 109b. Note that in Figure 7, Figure 7(A) is the upper The diagram shows a top view, and Figure 7(B) shows a cross-sectional view of A1-B1 in Figure 7(A).

[0115] Low-resistance regions 109a and 109b are created by vaccinating oxygen in the oxide semiconductor layer 108. This can be achieved by creating an oxygen-deficient state compared to the region in contact with the recon layer 112. Oxygen vacancies occur when the silicon layer 112 is not provided in the oxide semiconductor layer 108. If you create it by selectively plasma-treating the region with reducing gases such as hydrogen and argon, good.

[0116] In addition, by selectively adding hydrogen to the oxide semiconductor layer 108, a low-resistance region 109 can be created. a and 109b may also be provided.

[0117] The low-resistance regions 109a and 109b function as source regions or drain regions in the transistor 140. By providing the source electrode layer 116a in contact with the low-resistance region 109a and the drain electrode layer 116b in contact with the low-resistance region 109b, the contact resistance between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b can be reduced. Next, an example of a method for manufacturing the transistor shown in FIG. 7 will be described with reference to FIG. 8. First, the steps shown in FIGS. 2(A) to 2(D) above are performed, and the resist mask 172 used for etching the silicon layer 112 is left intact (see FIG. 8(A)). Next, using the resist mask 172, the oxide semiconductor layer 108 is subjected to plasma treatment with a reducing gas such as hydrogen or argon to form the low-resistance regions 109a and 109b in the oxide semiconductor layer 108 (see FIG. 8(B)). Next, a conductive film 114 is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112 (see FIG. 8(C)). The conductive film 114 is formed so as to be in contact with the low-resistance regions 109a and 109b of the oxide semiconductor layer 108. <000088()Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b (see FIG. 8(D)). Through the above steps, the transistor 140 can be manufactured.

[0119] After the transistor 140 is formed, a protective insulating layer is formed so as to cover the transistor 140.

[0120]

[0121]

[0122]

[0123]

[0124]

[0125]

[0126] It may be formed. Also, in the process of FIG. 8, after forming the oxide semiconductor layer 108, nitrogen heat treatment may be performed in an atmosphere or in an air atmosphere.

[0125] Note that in FIGS. 7 and 8, low resistance regions 109a and 109b are provided in the oxide semiconductor layer 108 to reduce the contact resistance between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b is shown, but it is not limited thereto.

[0126] As in the transistor 141 shown in FIGS. 9(A) and (B), between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b, a first metal oxide layer 11 5a and a second metal oxide layer 115b may be provided respectively. In FIG. 9, FIG. 9(A) shows a top view, and FIG. 9(B) shows a cross-sectional view taken along A1 - B1 in FIG. 9(A). is shown.

[0127] The first metal oxide layer 115a and the second metal oxide layer 115b may be formed of a metal oxide having at least a lower resistance than the oxide semiconductor layer 108.

[0128] Also, the first metal oxide layer 115a and the second metal oxide layer 115b can be formed of the same material as the oxide semiconductor layer 1 08 and under different film formation conditions. For example, as the oxide semiconductor layer 108, the first metal oxide layer 115a, and the second metal oxide layer 115b, an In - Ga - Zn - O - based non - single crystal film is used. In the case of using an In - Ga - Zn - O - based non - single crystal film for the first metal oxide layer 115a and the second metal oxide layer 115b, the ratio of the oxygen gas flow rate to the argon gas flow rate in the film formation conditions of the In - Ga - Zn - O - based non - single crystal film of the first metal oxide layer 115a and the second metal oxide layer 115b is higher than that of the In - Ga - Zn - O - based non - single crystal film of the oxide semiconductor layer 108 ​The conditions for film formation are those in which the oxygen gas flow rate accounts for a large proportion. Specifically, the first gold In-Ga-Zn-O non-single crystal film of the second metal oxide layer 115a and the second metal oxide layer 115b The film deposition conditions are under a rare gas atmosphere (argon or helium, etc.) (or 10% oxygen gas). The following assumes argon gas content of 90% or more, and the oxide semiconductor layer 108 is In-Ga-Zn-O system. The deposition conditions for non-single crystal films are under an oxygen-mixed atmosphere (oxygen gas flow rate is greater than the noble gas flow rate). It is possible.

[0129] Thus, the oxide semiconductor layer 108, the source electrode layer 116a, and the drain electrode layer 116b A first metal oxide layer 115a and a second metal oxide layer 115b are provided between them, respectively. This prevents carrier injection from the source electrode layer 116a and the drain electrode layer 116b. Because the wall can be reduced, the oxide semiconductor layer 108, the source electrode layer 116a and the drain electrode layer This reduces the contact resistance with 116b.

[0130] The first metal oxide layer 115a and the second metal oxide layer 115b are shown in Figure 2(A) above. After completing the steps up to (D), metal oxides are placed on the silicon layer 112 and the oxide semiconductor layer 108. The material layer and the conductive film 114 are sequentially stacked and formed, and then etched in the same manner as the conductive film 114. It can be formed by the etching conditions and the selected material, which can result in a conductive film 11 4 and the metal oxide layer, or the conductive film 114, the metal oxide layer and the oxide semiconductor layer 108 simultaneously It may be checked.

[0131] Furthermore, as shown in Figure 9(C) for transistor 142, a low-resistance region is formed in the oxide semiconductor layer 108. Regions 109a and 109b are provided, along with a first metal oxide layer 115a and a second metal oxide layer It may be configured to include the layer 115b.

[0132] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0133] (Embodiment 4) In this embodiment, a transistor and a method for manufacturing the same, which are different from those in the above Embodiments 1 to 3, will be described with reference to the drawings. Note that many parts of the manufacturing process (applicable materials, etc.) shown in this embodiment are common to Embodiment 1. Therefore, in the following, descriptions of overlapping parts will be omitted, and different points will be described in detail. The transistor 150 shown in FIGS. 10(A) and 10(B) includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, a source electrode layer 116a and a drain electrode layer 116b provided on the gate insulating layer 104, and an oxide semiconductor layer 108 provided on the gate insulating layer 104 above the gate electrode 102 and located in a region between the source electrode layer 116a and the drain electrode layer 116b, and a silicon layer 112 provided to cover the oxide semiconductor layer 108. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical order (stacking order) of the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor layer 108 is reversed from the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a top gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. The description of overlapping parts will be omitted, and different points will be described in detail.

[0134] The transistor 150 shown in FIGS. 10(A) and (B) includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, a source electrode layer 116a and a drain electrode layer 116b provided on the gate insulating layer 104, and an oxide semiconductor layer 108 provided on the gate insulating layer 104 above the gate electrode 10, and located in a region between the source electrode layer 116a and the drain electrode layer 116b, and a silicon layer 112 provided to cover the oxide semiconductor layer 108. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical order (stacking order) of the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor layer 108 is reversed from the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a top gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. The transistor 150 shown in FIGS. 10(A) and (B) includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, a source electrode layer 116a and a drain electrode layer 116b provided on the gate insulating layer 104, and an oxide semiconductor layer 108 provided on the gate insulating layer 104 above the gate electrode 102 and located in a region between the source electrode layer 116a and the drain electrode layer 116b, and a silicon layer ------------- 116a and the drain electrode layer 116b, and is located above the gate electrode 102 and in the region between the source electrode layer 116a and the drain electrode layer 116b. An oxide semiconductor layer 108 is provided on the gate insulating layer 104, and a silicon layer 112 is provided to cover the oxide semiconductor layer 108. That is, the transistors 150 and 151 shown in this embodiment have a structure in which the vertical order (stacking order) of the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor layer 108 is reversed from the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a top gate - bottom contact type. In FIG. 10, FIG. A is a top view of the upper surface. The transistor 150 shown in FIGS. 10(A) and (B) includes a gate electrode 102 provided on a substrate 100, a gate insulating layer 104 provided on the gate electrode 102, a source electrode layer 116a and a drain electrode layer 116b provided on the gate insulating layer 104, and an oxide semiconductor layer 1---------------- 8 provided on the gate insulating layer 104 above the gate electrode 102 and located in a region between the source electrode layer 11--------------

[0135] That is, the transistors 150 and ---- shown in this embodiment have a structure in which the vertical order (stacking order) of the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor layer 108 is reversed from the structure shown in the above embodiment. The structure shown in FIG. 10 is also called a top gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. In the structure shown in the above embodiment, the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor layer 108 have a structure in which their vertical order (stacking order) is reversed. The structure shown in FIG. 10 is also called a top gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. In the structure shown in the above embodiment, the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor layer 108 have a structure in which their vertical order (stacking order) is reversed. The structure shown in FIG. 10 is also called a top gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. In the structure shown in the above embodiment, the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor layer 108 have a structure in which their vertical order (stacking order) is reversed. The structure shown in FIG. 10 is also called a top gate - bottom contact type. In FIG. 10, FIG. 10(A) is a top view. The diagram shows that Figure 10(B) is a cross-sectional view of A1-B1 in Figure 10(A). .

[0136] As shown in Figures 10(A) and (B), the back channel side (gate) of the oxide semiconductor layer 108 By providing the silicon layer 112 so as to be in contact with the surface opposite to the electrode 102, hydrogen This can suppress the incorporation of hydrogen into the oxide semiconductor layer 108. This suppresses the fluctuations in the semiconductor properties of the oxide semiconductor layer 108 caused by this, and consequently the oxide semiconductor layer This makes it possible to suppress variations in the characteristics of transistors with 108 as the channel layer.

[0137] Furthermore, as shown in Figure 10(C), the source electrode layer 116a and the drain Between the in electrode layer 116b and the oxide semiconductor layer 108, metal oxide layers 115a and 115b A configuration with a metal oxide layer 115a, 115b may be provided. Contact resistor between the semiconductor layer 108 and the source electrode layer 116a and drain electrode layer 116b Resistance can be reduced.

[0138] Next, refer to Figure 11 for an example of a transistor fabrication method shown in Figures 10(A) and (B). I will explain it.

[0139] First, a gate electrode 102 is formed on the substrate 100, and then a gate electrode 102 is formed on the gate electrode 102. A gate insulating layer 104 is formed, and then a source electrode layer 116a and a gate insulating layer 104 are formed on top of it. A rain electrode layer 116b is formed (see Figure 11(A)).

[0140] Next, an oxide semiconductor layer 1 covers the source electrode layer 116a and the drain electrode layer 116b. Forms O6 (see Figure 11(B)).

[0141] Next, the oxide semiconductor layer 106 is etched to form island-shaped oxide semiconductor layers 108. See Figure 11(C). In this case, the island-shaped oxide semiconductor layer 108 is at least the gate electrode 1 The oxide semiconductor layer 106 is etched so that it remains above layer 02.

[0142] Next, a silicon layer 110 is formed to cover the oxide semiconductor layer 108 (see Figure 11(D)). (see).

[0143] Next, the silicon layer 110 is etched to form island-shaped silicon layers 112 (Figure 11( See E).

[0144] By following the above steps, transistor 150 can be manufactured.

[0145] Furthermore, after forming the transistor 150, a protective insulating layer is applied to cover the transistor 150. It may also be formed. In addition, in the process shown in Figure 11, after forming the oxide semiconductor layer 108, nitrogen Heat treatment may be performed in an ambient atmosphere or an atmospheric atmosphere.

[0146] Furthermore, when fabricating the transistor shown in Figure 10(C), in Figure 11(A), A conductive material is formed on the insulating layer 104, with a source electrode layer 116a and a drain electrode layer 116b. The film and the metal oxide layers constituting the metal oxide layers 115a and 115b were sequentially laminated to form the film. Afterward, etching can be performed. Also, the structure shown in Figure 10(C) is an oxide semiconductor layer 106. When etching to form island-shaped oxide semiconductor layers 108, metal oxide layers 115a, 1 This shows the case where 15b is also etched at the same time.

[0147] In Figure 11, island-shaped silicon layers 112 are provided to completely cover the oxide semiconductor layer 108. The example shown illustrates the formation process, but it is not limited to this. The silicon layer 112 is at least oxidized. It is sufficient to provide it so as to be in contact with the region where the channel is formed in the material semiconductor layer 108, for example For example, as shown in the transistor 152 in Figure 12, it contacts a part of the oxide semiconductor layer 108. A silicon layer 112 can be provided. In Figure 12, the silicon layer 112 is made of oxide semiconductor. Formed to be in contact with a part of the conductor layer 108 (source electrode layer 116a and drain electrode layer 1 (Formed so as not to be in contact with 16b), silicon layer 112, oxide semiconductor layer 108, source This shows a case where a protective insulating layer 119 is provided on the electrode layer 116a and the drain electrode layer 116b. Yes, they are.

[0148] As the protective insulating layer 119, for example, a silicon oxide film is formed using CVD or sputtering. silicon nitride film, silicon oxide nitride film, silicon oxide nitride film, aluminum oxide film, nitrile Aluminum oxide film, aluminum oxide nitride film, or a single layer of aluminum oxide nitride film, It can be formed by layering.

[0149] Note that in Figure 12, Figure 12(A) shows a top view, and Figure 12(B) shows a top view. This shows a cross-sectional view of A1-B1 in ).

[0150] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0151] (Embodiment 5) In this embodiment, the semiconductor device comprising the transistors shown in Embodiments 1 to 4 above The manufacturing process of a display device, which is an example of its usage, will be explained using drawings. Some of the manufacturing processes (applicable materials, etc.) shown in the form of implementation are largely the same as in Embodiment 1 above. They are similar. Therefore, in the following, we will omit explanations of the overlapping parts and focus on the differences. This will be explained in detail. Note that in the following explanation, Figures 15 to 19 show top views. Figures 13 and 14 show cross-sectional views between A3-B3 and A4-B4 in Figures 15-19. It is.

[0152] First, wiring and electrodes (including gate electrode 102) are placed on a substrate 100 having an insulating surface. The wire, capacitance wiring 308, and first terminal 321 are formed, and then the gate insulating layer 104 and oxidation A semiconductor layer 106 is then formed (see Figures 13(A) and 15).

[0153] The capacitive wiring 308 and the first terminal 321 are formed simultaneously using the same material as the gate electrode 102. It is possible.

[0154] Next, the oxide semiconductor layer 106 is etched to form island-shaped oxide semiconductor layers 108. (See Figure 16) A silicon layer 110 is formed to cover the oxide semiconductor layer 108 (Figure 1 See 3(B). In this case, the island-shaped oxide semiconductor layer 108 is connected to at least the gate electrode 102 The oxide semiconductor layer 106 is etched so that it remains above the above.

[0155] Next, the silicon layer 110 is etched to form island-shaped silicon layers 112 (Figure 13( C), see Figure 17). In this case, the island-shaped silicon layer 112 is at least connected to the gate electrode 102. The silicon layer 110 is etched so that it remains in the overlapping region. The silicon layer 110 is etched so that at least a portion of the body layer 108 is exposed.

[0156] Next, a contact hole 31 is made in the gate insulating layer 104 so as to expose the first terminal 321. After forming layer 3, the gate insulating layer 104, oxide semiconductor layer 108, and silicon layer 112 are covered. A conductive film 114 is formed in this manner (see Figure 13(D)). This creates a bond between the conductive film 114 and the first Terminal 321 of terminal 1 is electrically connected via contact hole 313.

[0157] Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b. This forms the connecting electrode 320 and the second terminal 322 (see Figures 14(A) and 18). The silicon layer 112 functions as a channel protection layer for the oxide semiconductor layer 108.

[0158] The second terminal 322 is electrically connected to the source wiring (source wiring including the source electrode layer 116a). The configuration can be such that the connections are made. In addition, the connecting electrode 320 is in direct contact with the first terminal 321. It can be configured in a continuous manner.

[0159] By following the above steps, transistor 160 can be manufactured.

[0160] Next, heat treatment is performed at temperatures between 200°C and 600°C, typically between 300°C and 500°C. This is preferable. For example, heat treatment is performed at 350°C for 1 hour under a nitrogen atmosphere. This allows for the atomic level of the In-Ga-Zn-O non-single crystal film constituting the oxide semiconductor layer 108. Rearrangement occurs. This heat treatment releases strain that hinders carrier movement, Heat treatment (including photo-annealing) is effective here. The timing for heat treatment is as follows: The process is not particularly limited as long as it is after the deposition of the oxide semiconductor layer 106, for example, the subsequent formation of the pixel This can be done after the poles have formed.

[0161] Next, a protective insulating layer 340 is formed to cover the transistor 160, and the protective insulating layer 34 Selectively etch the 0 to reach the contact hole 325, which is the drain electrode layer 116b. The contact hole 326 that reaches the connecting electrode 320 and the contact that reaches the second terminal 322 Tohole 327 is formed (see Figure 14(B)).

[0162] Next, the transparent conductive layer 310 and connecting electrode 320 are electrically connected to the drain electrode layer 116b. A transparent conductive layer 328 that is electrically connected and a transparent conductive layer that is electrically connected to the second terminal 322 Forms 329 (see Figures 14(C) and 19).

[0163] The transparent conductive layer 310 functions as a pixel electrode, and the transparent conductive layers 328 and 329 connect to the FPC. This will be the electrode or wiring used in the connection electrode 320. More specifically, a transparent The bright conductive layer 328 is used as a terminal electrode for connection that functions as an input terminal for gate wiring, The transparent conductive layer 329 formed on terminal 322 of the 2 is used as the input terminal for the source wiring. It can be used as a terminal electrode for connection.

[0164] Furthermore, the capacitive wiring 308, gate insulation layer 104, protective insulation layer 340, and transparent conductive layer 310 A greater retention capacity can be formed. In this case, the capacitance wiring 308 and the transparent conductive layer 310 The gate insulating layer 104 and the protective insulating layer 340 act as electrodes and dielectrics.

[0165] Transparent conductive layers 310, 328, and 329 are made of indium oxide (In2O3) and indium oxide. Tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy Gold (In2O3-ZnO) and other materials can be formed using sputtering, vacuum deposition, and other methods. For example, after forming a transparent conductive film, a resist mask is formed on the transparent conductive film, By removing unwanted parts through chipping, transparent conductive layers 310, 328, and 329 are formed. It is possible.

[0166] Through the above process, elements such as bottom-gate n-channel thin-film transistors and retaining capacitors are produced. This can be completed. Then, these elements are arranged in a matrix corresponding to individual pixels. By arranging them in this way, an active-matrix type display device can be manufactured.

[0167] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0168] (Embodiment 6) In this embodiment, a liquid crystal display device is shown as an example of a semiconductor device equipped with a thin-film transistor. First, Figure 2 shows the external appearance and cross-section of a liquid crystal display panel, which is a form of semiconductor device. Let's explain using 0. Figures 20(A1)(A2) show the acid formed on the first substrate 4001. Thin-film transistors 4010, 4011, and liquid crystal element 4013 having a crystalline semiconductor layer, This is a top view of the panel sealed between the second substrate 4006 and the panel with a sealing material 4005. Figure 20(B) corresponds to the cross-sectional view at MN in Figures 20(A1) and (A2).

[0169] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0170] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding methods or TAB methods can be used. Figure 20(A1) This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 20(A2) shows, This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0171] Furthermore, the pixel section 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 are It has multiple thin-film transistors, and in Figure 20(B), the thin film transistor included in the pixel section 4002 Thin film transistor 4010 and thin film transistor 401 included in scan line driving circuit 4004 1 is an example. On thin-film transistors 4010 and 4011 are insulating layers 4020 and 40 21 is provided.

[0172] Thin-film transistors 4010 and 4011 can be configured to apply the structure shown in the above embodiment. Yes, it is possible. In this embodiment, thin-film transistors 4010 and 4011 are n-channel type thin-film transistors. It is a film transistor.

[0173] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin-film transistor 4010. They are electrically connected. And the counter electrode layer 4031 of the liquid crystal element 4013 is on the second substrate 40 Formed on 06. Pixel electrode layer 4030, counter electrode layer 4031, and liquid crystal layer 4008 The overlapping portion corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the opposite The electrode layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films. The liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033.

[0174] The first substrate 4001 and the second substrate 4006 are glass, metal (typically stainless steel) Materials such as ceramics and plastics can be used. Examples of plastics include FR. P (Fiberglass-Reinforced Plastics) plate, PVF (Polymer glass) (vinyl fluoride) film, polyester film or acrylic resin film It can be used. Also, aluminum foil can be used with PVF film or polyester film. It is also possible to use a sheet with a structure sandwiched between layers of material.

[0175] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. It is provided for this purpose. A spherical spacer may also be used. Also, the counter electrode layer 403 1 is electrically connected to a common potential line provided on the same substrate as the thin-film transistor 4010. It is possible to use a common connection part to connect the conductive particles placed between the pair of substrates to the counter electrode layer 4 031 and the common potential line can be electrically connected. Note that the conductive particles are sealing material 4 It is to be included in 005.

[0176] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. It is used. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs~ With a short duration of 100 μs and optical isotropy, orientation processing is unnecessary, and it exhibits low field-of-view angle dependence. stomach.

[0177] The liquid crystal display device shown in this embodiment is an example of a transmissive liquid crystal display device, but the liquid crystal display device This method can be applied to both reflective and transflective liquid crystal displays.

[0178] Furthermore, in the liquid crystal display device shown in this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and the inside An example is shown where the coloring layer and the electrode layer used for the display element are arranged in that order, but the polarizing plate is on the inside of the substrate. It may also be provided in this embodiment. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the polarizing plate The coloring layer can be set appropriately depending on the materials and manufacturing process conditions. A light-shielding film that functions as a shield may be provided.

[0179] Furthermore, in this embodiment, in order to reduce surface irregularities of the thin-film transistor, and thin-film transistor To improve the reliability of the transistor, thin-film transistors function as protective films or planarization insulating films. The structure is covered with insulating layers (insulating layer 4020, insulating layer 4021). This is to prevent the entry of pollutants such as organic matter, metals, and water vapor suspended in the atmosphere. Therefore, a dense film is preferred. The protective film is made by sputtering a silicon oxide film, nitride film Silicon oxide film, silicon nitride film, silicon nitride film, aluminum oxide film, aluminum nitride film Aluminum film, aluminum oxide nitride film, or aluminum nitride oxide film, in single or multilayer form This should be done. In this embodiment, an example of forming a protective film by sputtering is shown, but it is not particularly limited. It can be formed using various methods.

[0180] Here, a laminated insulating layer 4020 is formed as a protective film. As the first layer of 0, a silicon oxide film is formed using the sputtering method. When using a recon film, the aluminum film used as the source electrode layer and drain electrode layer is It is effective in preventing lockout.

[0181] Furthermore, an insulating layer is formed as the second layer of the protective film. Here, the second layer of the insulating layer 4020 is Then, a silicon nitride film is formed using the sputtering method. The silicon nitride film is used as a protective film. This allows mobile ions such as sodium to penetrate the semiconductor region, altering the electrical properties of the TFT. It can suppress the process of causing the problem.

[0182] Furthermore, after forming the protective film, the semiconductor layer is annealed (200°C to 400°C). That's fine.

[0183] Furthermore, an insulating layer 4021 is formed as a planar insulating film. The insulating layer 4021 is made of poly Heat-resistant organic materials such as mids, acrylics, benzocyclobutenes, polyamides, and epoxys. Materials can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. Using siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. This can be achieved by stacking multiple insulating films made of these materials. 4021 may be formed.

[0184] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0185] The method for forming the insulating layer 4021 is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used. When forming the insulating layer 4021 using a material liquid, It is also possible to perform annealing of the semiconductor layer (200°C to 400°C) at the same time as the working process. i. By combining the firing process of the insulating layer 4021 and the annealing of the semiconductor layer, semiconductor devices can be manufactured efficiently. It becomes possible to manufacture this.

[0186] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon oxide Electrical materials can be used.

[0187] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrode preferably has a light transmittance of 70% or more at a wavelength of 550 nm. Furthermore, the resistivity of the conductive polymer contained in the conductive composition must be 0.1 Ω·cm or less. preferable.

[0188] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0189] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0190] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. Formed from the same conductive film as 30, the terminal electrode 4016 is made of thin-film transistor 4010, 40 The source electrode layer and drain electrode layer are formed of the same conductive film.

[0191] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0192] Furthermore, in Figure 20, a signal line drive circuit 4003 is formed separately and implemented on the first substrate 4001. Although an example of the configuration is shown, this embodiment is not limited to this configuration. Scan line drive circuit Alternatively, it may be formed and implemented separately, or it may be part of the signal line drive circuit or part of the scan line drive circuit. It is also acceptable to form and implement the component separately.

[0193] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0194] (Embodiment 7) In this embodiment, electronic paper is shown as an example of a semiconductor device equipped with a transistor. .

[0195] Figure 21 shows an example of a semiconductor device: an active-matrix electronic paper. The thin-film transistor 581 used in the device is the thin film shown in Embodiments 1 to 5 above. It can be fabricated in the same way as a transistor.

[0196] The electronic paper in Figure 21 is an example of a display device using a twist ball display method. The Toball display method is an electrode layer that uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer. This method controls and displays the orientation of spherical particles by generating a specific phenomenon.

[0197] The thin-film transistor 581 provided on the substrate 580 is a thin-film transistor with a bottom gate structure. The source electrode layer or drain electrode layer is the first electrode layer 587 and the insulating layer 583, 5 The first electrode is electrically connected via contact holes formed at 84 and 585. Between layer 587 and the second electrode layer 588, there are black region 590a and white region 590b. Furthermore, a spherical particle 589 is provided, which includes a cavity 594 that is filled with liquid. Furthermore, a filler material 595 such as resin is provided around the spherical particles 589 (see Figure 21). In 21, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. This corresponds to a pole. The second electrode layer 588 is provided on the same substrate as the thin-film transistor 581. It is electrically connected to a common potential line. Using the common connection part shown in the above embodiment, a pair The conductive particles placed between the substrates allow the second electrode layer 588 provided on the substrate 596 to communicate with the substrate 596. It can be electrically connected to a common potential line.

[0198] Alternatively, an electrophoretic element can be used instead of a twist ball. In that case, A transparent liquid containing positively charged white particles and negatively charged black particles, with a diameter of 10 Microcapsules of approximately μm to 200 μm are used between the first electrode layer and the second electrode layer. The microcapsules provided are subjected to an electric field by a first electrode layer and a second electrode layer. When this happens, the white and black particles move in opposite directions, allowing for the display of either white or black. This principle is applied to display elements called electrophoretic display elements, and generally refers to electronic paper. It is called that. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights It does not require a power supply, consumes little power, and allows the display to be seen even in dimly lit places. Yes. Furthermore, even if power is not supplied to the display unit, it can retain the image that has been displayed. Because this is possible, a semiconductor device with a display function (simply a display device, or a display) can be transmitted from the radio wave source. Even when the semiconductor device (also called a device equipped with the equipment) is moved away, the displayed image is saved. It becomes possible to do so.

[0199] As described above, highly reliable electronic paper can be manufactured as a semiconductor device.

[0200] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0201] (Embodiment 8) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device equipped with a transistor. In this case, the display element of the display device utilizes light emission through electroluminescence. This is illustrated using an element. Electroluminescent light-emitting devices utilize organic light-emitting materials. They are distinguished by whether they are compound or inorganic compounds; generally, the former are organic EL elements. The latter is called an inorganic EL element.

[0202] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0203] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized type of luminescence used.

[0204] Next, the appearance of a light-emitting display panel (also called a light-emitting panel), which corresponds to a form of semiconductor device, and The cross-section will be explained using Figure 22. Figure 22(A) shows the formation on the first substrate 4501. Thin-film transistors 4509, 4510 and light-emitting element 4511 are placed on a second substrate 450 Figure 22(B) is a top view of the panel, which is sealed with a sealing material 4505 between 6 and 6. This corresponds to the cross-sectional view of HI in Figure 22(A). Note that here, the light-emitting element is This will be explained using an electroluminescent element.

[0205] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0206] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple thin-film transistors. In Figure 22(B), the thin-film transistor 4510 included in the pixel section 4502 and the signal The thin-film transistor 4509 included in the wire drive circuit 4503a is shown as an example.

[0207] Thin-film transistors 4509 and 4510 can be configured to apply the structure shown in the above embodiment. Yes, it is possible. In this embodiment, thin-film transistors 4509 and 4510 are n-channel type thin-film transistors. It is a film transistor.

[0208] Furthermore, 4511 corresponds to a light-emitting element, and the first electrode is a pixel electrode of the light-emitting element 4511. Layer 4517 is electrically connected to the source electrode layer or drain electrode layer of the thin-film transistor 4510. It is connected to the following. The configuration of the light-emitting element 4511 is a first electrode layer 4517 and an electroluminescent layer The stacked structure consists of 4512 and a second electrode layer 4513, but is not limited to the configuration shown in this embodiment. It is not done. The direction of the light emitted from the light-emitting element 4511 is adjusted according to the direction of the light emitted from the light-emitting element 4511. The configuration can be changed as needed.

[0209] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side wall of the opening It is preferable to form it so that it becomes an inclined surface with a continuous curvature.

[0210] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0211] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on 4513 and the partition wall 4520. The protective film may be silicon nitride. It can form films, silicon nitride films, DLC films, and the like.

[0212] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0213] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light-emitting element 4511. Formed from the same conductive film as 517, terminal electrode 4516 is thin-film transistor 4509, 4 It is formed from the same conductive film as the source electrode layer and drain electrode layer of 510.

[0214] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0215] The second substrate 4506, located in the direction of light extraction from the light-emitting element 4511, must be translucent. It must be a glass plate, plastic plate, polyester film or A light-transmitting material, such as acrylic film, is used.

[0216] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV Material A (ethylene vinyl acetate) can be used.

[0217] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0218] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and this embodiment has the configuration shown in Figure 22. Not limited.

[0219] Through the above process, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0220] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0221] (Embodiment 9) The semiconductor device comprising the transistor shown in the above embodiment can be used in various electronic devices (play It can be applied to (including technical equipment). Examples of electronic equipment include television equipment. Television (also called a television receiver), monitors for computers, etc., digital Cameras, digital video cameras, digital photo frames, mobile phones (portable) (Also called a mobile phone or cell phone device), portable game console, personal digital assistant, sound playback device, pachinko Examples include large game machines such as ping pong machines.

[0222] Figure 23(A) shows an example of the television equipment 9600. In the case of 00, the display unit 9603 is incorporated into the housing 9601. The display unit 9603 displays It is possible to display an image. Also, here, the stand 9605 is used to display the housing 9601 This shows a configuration that supports this.

[0223] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys The 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0224] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0225] Figure 23(B) shows an example of the digital photo frame 9700. For example, The photo frame 9700 has a display unit 9703 integrated into the housing 9701. Section 9703 is capable of displaying various images, such as those captured by a digital camera. By displaying the image data, it can function just like a regular photo frame.

[0226] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It is desirable to include it as it improves the design. For example, the recording medium of a digital photo frame. A memory device containing image data captured by a digital camera is inserted into the body insertion site. The system can capture data and display the captured image data on the display unit 9703.

[0227] Furthermore, the digital photo frame 9700 may be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0228] Figure 24(A) shows a portable gaming machine, which consists of two cabinets, cabinet 9881 and cabinet 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display unit The 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. The portable gaming machine shown in 24(A) also includes a speaker section 9884 and a recording medium insertion section 988 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with a function to measure motion, odor, or infrared radiation, a microphone (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least semiconductor equipment Any configuration that includes a storage unit is acceptable, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in Figure 24(A) contains programs or data recorded on the recording medium. It has a function to read data and display it on the display unit, and it can also share information by wirelessly communicating with other portable gaming machines. It has the function of [doing something]. However, the functions of the portable gaming machine shown in Figure 24(A) are not limited to this. It can have various functions.

[0229] Figure 24(B) shows an example of a large-scale gaming machine, the slot machine 9900. The machine 9900 has a display unit 9903 integrated into the casing 9901. The Machine 9900 also features other operating mechanisms such as a start lever and stop switch, and coins. It is equipped with an input slot, speaker, etc. Of course, the configuration of the slot machine 9900 is as described above. It is not limited to just one object, but any configuration that includes at least a semiconductor device, and other auxiliary equipment The configuration can be set as appropriate.

[0230] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. [Explanation of symbols]

[0231] 100 circuit boards 102 Guard Station 104 Gate Insulation Layer 106 Oxide semiconductor layer 10⁸ Oxide semiconductor layer 109a Low resistance region 109b Low resistance region 110 Silicon Layer 111 Silicon layer 112 Silicon Layer 114 Conductive film 115a Metal oxide layer 115b Metal oxide layer 116a Source electrode layer 116b Drain electrode layer 119 Protective insulating layer 120 transistors 121 transistors 122 transistors 123 Transistors 124 transistors 130 transistors 140 transistors 141 Transistors 142 transistors 150 transistors 151 transistors 152 transistors 160 transistors 171 Resist Mask 172 Resist Mask 175 Resist Mask 176 Resist Mask 308 Capacitance wiring 310 Transparent conductive layer 313 Contact Hole 320 connecting electrodes 321 First terminal 322 Second terminal 325 Contact Holes 326 Contact Holes 327 Contact Holes 328 Transparent conductive layer 329 Transparent conductive layer 340 Protective insulating layer 580 circuit boards 581 Thin-film transistor 583 Insulating layer 587 First electrode layer 588 Second electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 circuit boards 4001 First substrate 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 Second substrate 4008 Liquid Crystal Layer 4010 Thin-Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4501 First substrate 4502 pixel section 4503a Signal Line Drive Circuit 4503b Signal line drive circuit 4504a Scan line drive circuit 4504b Scan line drive circuit 4505 Sealant 4506 Second substrate 4507 Filling material 4509 Thin-film transistor 4510 Thin-Film Transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Second electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 First electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 590a black area 590b White area 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand 9607 Display section 9609 Operation Keys 9610 Remote Control Unit 9700 Digital Photo Frame 9701 enclosure 9703 Display section 9881 cabinet 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 cabinet 9893 Connection section 9900 slot machines 9901 cabinet 9903 Display section

Claims

1. It has transistors arranged in the pixel section, It has a first conductive layer that functions as the gate electrode of the transistor, The first conductive layer is provided on the first conductive layer and has a first insulating layer that functions as a gate insulating film of the transistor, A single-layer oxide semiconductor layer is provided on the first insulating layer and has indium (In), gallium (Ga), and zinc (Zn), The silicon oxide layer is provided on the oxide semiconductor layer and is in contact with a first region of the oxide semiconductor layer, The silicon oxide layer has a layer containing silicon on top of the silicon oxide layer, A second conductive layer having a region in contact with the second region of the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the transistor, A third conductive layer having a region in contact with the third region of the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the transistor, The silicon-containing layer has a planarizing insulating film, The planarizing insulating film is provided on the ITO of the second conductive layer and on the ITO of the third conductive layer. The pixel electrode is provided on the planar insulating film and is electrically connected to the ITO of the second conductive layer or the ITO of the third conductive layer via a contact hole provided in the planar insulating film, The pixel electrode has an EL layer on it, The EL layer has a counter electrode, The first region of the oxide semiconductor layer has a channel formation region for the transistor, The oxide semiconductor layer has a second region and a third region that sandwich the channel formation region, The second region and the third region have regions that are not in contact with the silicon oxide layer. The first conductive layer is formed by laminating a titanium (Ti) film with aluminum (Al) or copper (Cu). The second conductive layer has a region in contact with the upper surface of the silicon-containing layer, The third conductive layer has a region in contact with the upper surface of the silicon-containing layer, The silicon oxide layer has a region that is in contact with the side surface of the oxide semiconductor layer. In the channel width direction of the transistor, the silicon-containing layer extends beyond both ends of the oxide semiconductor layer. A display device wherein the silicon-containing layer has a region in contact with the first insulating layer.

2. It has transistors arranged in the pixel section, It has a first conductive layer that functions as the gate electrode of the transistor, The first conductive layer is provided on the first conductive layer and has a first insulating layer that functions as a gate insulating film of the transistor, A single-layer oxide semiconductor layer is provided on the first insulating layer and has indium (In), gallium (Ga), and zinc (Zn), The silicon oxide layer is provided on the oxide semiconductor layer and is in contact with a first region of the oxide semiconductor layer, The silicon oxide layer has a layer containing silicon on top of the silicon oxide layer, The second conductive layer has a region in contact with the first low-resistance region of the oxide semiconductor layer and functions as either the source electrode or the drain electrode of the transistor. A third conductive layer having a region in contact with the second low-resistance region of the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the transistor, The silicon-containing layer has a planarizing insulating film, The planarizing insulating film is provided on the ITO of the second conductive layer and on the ITO of the third conductive layer. The pixel electrode is provided on the planar insulating film and is electrically connected to the ITO of the second conductive layer or the ITO of the third conductive layer via a contact hole provided in the planar insulating film, The pixel electrode has an EL layer on it, The EL layer has a counter electrode, The first region of the oxide semiconductor layer has a channel formation region for the transistor, The oxide semiconductor layer has a first low-resistance region and a second low-resistance region so as to sandwich the channel-forming region. The first low-resistance region and the second low-resistance region have regions that are not in contact with the silicon oxide layer. The first conductive layer is formed by laminating a titanium (Ti) film with aluminum (Al) or copper (Cu). The second conductive layer has a region in contact with the upper surface of the silicon-containing layer, The third conductive layer has a region in contact with the upper surface of the silicon-containing layer, The silicon oxide layer has a region that is in contact with the side surface of the oxide semiconductor layer. In the channel width direction of the transistor, the silicon-containing layer extends beyond both ends of the oxide semiconductor layer. A display device wherein the silicon-containing layer has a region in contact with the first insulating layer.

3. In claim 1 or 2, A display device wherein the oxide semiconductor layer has an In-O-based oxide semiconductor instead of having indium (In), gallium (Ga), and zinc (Zn).

4. An electronic device having a display device according to any one of claims 1 to 3.

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