Semiconductor equipment

Abstract

To provide semiconductor devices suitable for miniaturization, highly reliable semiconductor devices, and semiconductor devices with improved operating speed. [Solution] The memory cell array 300 has a memory cell CL having a first to c (c is a natural number of 2 or more) submemory cells SCL, the j-th submemory cell has a first transistor Ta_j, a second transistor Tb_j, and a capacitive element Ca_j, the first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor have oxide semiconductors, one terminal of the capacitive element is electrically connected to the gate electrode of the second transistor, the gate electrode of the second transistor is electrically connected to either the source electrode or the drain electrode of the first transistor, and when j≧2, the j-th submemory cell is placed on the j-1 submemory cell.

Description

Technical Field

[0001] The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. In addition, in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a computing device, a storage device, an imaging device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, etc.), and an electronic device may have a semiconductor device.

[0002]

Background Art

[0003] Techniques for constructing a transistor using a semiconductor material have attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). As a semiconductor material applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor is attracting attention as another material.

[0004] For example, techniques for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor are disclosed (see Patent Document 1 and Patent Document 2).

[0005] In recent years, with the improvement in performance, miniaturization, or weight reduction of electronic devices, the demand for an integrated circuit in which semiconductor elements such as miniaturized transistors are integrated at a high density has been increasing. ​​​​​​​​​​​[Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] One aspect of the present invention aims to provide a semiconductor device suitable for miniaturization. One of the objectives of this invention is to provide a semiconductor device with a reduced circuit area. One embodiment aims to provide a semiconductor device with improved operating speed. Alternatively, this One aspect of the invention aims to provide a semiconductor device with improved writing speed. Alternatively, one aspect of the present invention aims to provide a semiconductor device with improved readout speed. One aspect of the present invention is to provide a semiconductor device with low power consumption. This will be the first topic.

[0008] Alternatively, one aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide good electrical characteristics to a semiconductor device. Alternatively, one aspect of the present invention provides a semiconductor device having a memory element with good retention characteristics. One of the objectives is to provide a semiconductor device with a novel configuration. Alternatively, one aspect of the present invention provides a semiconductor device with a novel configuration. One of the objectives is to do the following. Alternatively, one of the objectives is to provide a novel semiconductor device. .

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title will become clear from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a memory cell having first to c (where c is a natural number of 2 or more) submembrane cells. Having a Morissel, the j-th (where j is a natural number from 1 to c) submemory cell is the first transistor A transistor has a first half-element, a second transistor and a capacitive element, and the first transistor has a first half The conductive layer and the second semiconductor layer of the second transistor have an oxide semiconductor and a capacitive element One of the child's terminals is electrically connected to the gate electrode of the second transistor, and the second transistor The gate electrode of the transistor is the source electrode or drain electrode of the first transistor. Electrically connected to either of the electrodes, the j-th submemory cell is the j-th submemory cell when j≧2. This is a semiconductor device that is placed on a sub-memory of -1.

[0011] Alternatively, in one aspect of the present invention, the first to c (where c is a natural number of 2 or more) submemory cells It has a memory cell, and the j-th (where j is a natural number from 1 to c) sub-memory cell is the first It has a transistor, a second transistor and a capacitive element, and the first transistor has The first semiconductor layer and the second semiconductor layer of the second transistor have an oxide semiconductor. One terminal of the capacitive element is electrically connected to the gate electrode of the second transistor. The gate electrode of the second transistor is the source electrode of the first transistor. It is electrically connected to one of the drain electrodes, and when j≧2, the j-th submemory The semiconductor layer of the second transistor Tb_j possessed by the ru, and the (j-1) submemory The semiconductor layer of the first transistor Ta_(j-1) in the cell is the first insulating film Touching the upper surface, for j≧2, the second transistor Tb_ of the j-th submemory cell The gate electrode of j and the first transistor T of the (j-1) submemory cell The gate electrode of a_(j-1) is a semiconductor device that is in contact with the lower surface of the second insulating film.

[0012] Alternatively, in one aspect of the present invention, the first to c (where c is a natural number of 2 or more) submemory cells It has a memory cell, and the j-th (where j is a natural number from 1 to c) sub-memory cell is the first It has a transistor, a second transistor and a capacitive element, and when j≧2 the sub-mechanism of the j The molysel is placed on the j-1 submemory, and the first semiconductor of the first transistor The body layer and the second semiconductor layer of the second transistor have an oxide semiconductor, and the first The semiconductor layer of the first transistor or the second transistor in the memory cell One of the semiconductor layers and the semiconductor layer of the third transistor are on the first insulating film. In contact with the first transistor of the c submemory cell, or the c One of the semiconductor layers of the second transistor in the submemory cell and the fourth transistor The semiconductor layer of the transistor is a semiconductor device formed on a second insulating film.

[0013] Furthermore, in the above configuration, the j-th (where j is a natural number from 1 to c) submemory cell has The first semiconductor layer of the first transistor and the second submemory cell of the j The second semiconductor layer of the transistor is an acid containing In, an element represented by M, and Zn. The first semiconductor layer has an oxide semiconductor, and the ratio of the number of In, M, and Zn atoms in the oxide semiconductor is such that It satisfies In:M:Zn=g:h:i, and the oxide semiconductor In of the second semiconductor layer The ratio of the number of M and Zn atoms satisfies In:M:Zn=d:e:f, and g / (g+h+i) is, It is preferable that it is smaller than d / (d+e+f). [Effects of the Invention]

[0014] According to one aspect of the present invention, a semiconductor device suitable for miniaturization can be provided. A semiconductor device with reduced road area can be provided. Furthermore, according to one aspect of the present invention, A semiconductor device with improved processing speed can be provided. Furthermore, according to one aspect of the present invention, A semiconductor device with improved writing speed can be provided. Furthermore, according to one aspect of the present invention, This makes it possible to provide a semiconductor device with improved readout speed. Furthermore, in one aspect of the present invention This makes it possible to provide semiconductor devices with lower power consumption.

[0015] Furthermore, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. According to one aspect of the present invention, good electrical characteristics can be imparted to a semiconductor device. Furthermore, According to one aspect of the present invention, a semiconductor device having a memory element with good retention characteristics is provided. Yes, it is possible. Furthermore, according to one aspect of the present invention, a semiconductor device with a novel configuration can be provided. Furthermore, it is possible to provide novel semiconductor devices.

[0016] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract effects other than those mentioned above from the descriptions in the surfaces, claims, etc. [Brief explanation of the drawing]

[0017] [Figure 1] A diagram showing an example of a semiconductor device and a circuit diagram according to one aspect of the present invention. [Figure 2] A block diagram according to one aspect of the present invention. [Figure 3] A diagram showing a timing chart of a circuit according to one aspect of the present invention. [Figure 4] A circuit diagram according to one aspect of the present invention. [Figure 5] A circuit diagram according to one aspect of the present invention. [Figure 6] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 7] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 8] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 9] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 10] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 11] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 12] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 13] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 15] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 17] A diagram showing an example of a transistor. [Figure 18] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 19] A diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 20] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 21] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 22] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 23] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 24] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 25] A diagram showing a partial band structure of a transistor according to one aspect of the present invention, and a diagram illustrating the current path during conduction. [Figure 26] A circuit diagram relating to an embodiment. [Figure 27] An example of the configuration of an RF tag according to an embodiment. [Figure 28] An example of a CPU configuration according to an embodiment. [Figure 29] Circuit diagram of a memory element according to an embodiment. [Figure 30] An electronic device according to an embodiment. [Figure 31] An example of RF tag usage according to the embodiment. [Modes for carrying out the invention]

[0018] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. Those skilled in the art will readily understand what is possible. Therefore, the present invention is as shown in the following embodiments. It should not be interpreted as being limited to the contents described herein.

[0019] In the configuration of the invention described below, the same part or part having a similar function is The same reference numerals are used consistently across different drawings, and explanations of their repetition are omitted. When referring to the function of [this], the hatch pattern is the same, and sometimes no specific symbol is assigned.

[0020] In each figure described herein, the size, layer thickness, or area of ​​each component is as follows: It may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. stomach.

[0021] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is added for the purpose of providing a numerical limit, and is not intended to limit the number of items.

[0022] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it can be referred to as an "insulator." They may possess the following characteristics. Also, the boundary between "semiconductors" and "insulators" is ambiguous, and strictly speaking, In some cases, they cannot be closely distinguished. Therefore, as used herein, "semiconductor" refers to "insulator". In some cases, this can be rephrased as follows. Similarly, the term "insulator" as used herein may be interpreted as "semiconductor." It can sometimes be rephrased as "body".

[0023] Also, even when the term "semiconductor" is used, for example, if the conductivity is sufficiently high, it can be referred to as a "conductor." They may possess the following characteristics. Also, the boundary between "semiconductors" and "conductors" is ambiguous, and strictly In some cases, they cannot be closely distinguished. Therefore, as used herein, "semiconductor" refers to "conductor". In some cases, this can be rephrased as follows. Similarly, the term "conductor" as used herein may be interpreted as "semiconductor." It can sometimes be rephrased as "body".

[0024] A transistor is a type of semiconductor device that amplifies current and voltage, and controls conduction or non-conductivity. It is possible to realize controlled switching operations, etc. Transistors in this specification are , IGFET(Insulated Gate Field Effect Trans istors and thin-film transistors (TFTs) ) includes.

[0025] Furthermore, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Approximately parallel" refers to a state where two lines are positioned at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two lines are positioned at an angle of 80° to 100°. It refers to a state. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" This refers to a state in which two straight lines are positioned at an angle between 60° and 120°.

[0026] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0027] (Embodiment 1) In this embodiment, the semiconductor device 700 according to one aspect of the disclosed invention has a memory This document describes the circuit configuration and operation of the Luarray 300.

[0028] Furthermore, a semiconductor device refers to a device that has semiconductor elements. It includes a drive circuit for driving a circuit containing semiconductor elements. Furthermore, the semiconductor device includes a memory cell. In addition, it may include drive circuits, power supply circuits, etc., located on a separate circuit board.

[0029] Furthermore, the semiconductor device 700 includes an inverter circuit, a NAND circuit, an AND circuit, and a NOR circuit. Path, OR circuit, buffer, level shifter, XOR circuit, XNOR circuit, AND-NOR circuit Path, OR-NAND circuit, AND-OR-INV circuit, OR-AND-INV circuit, Analog Log switch, flip-flop, settable flip-flop, resettable flip-flop Flip-flops, set and resettable flip-flops, adders, half-adders, multi-flops Chiplexer, demultiplexer, register, scan register, retention register, It may include an isolator, decoder, etc.

[0030] Figure 2 shows an example of a semiconductor device 700 according to one aspect of the present invention. The semiconductor device 700 is a memo It has a recell array 300 and peripheral circuits 500 for the memory cell array. Ray's peripheral circuitry 500 includes row selection drivers, column selection drivers, and A / D converters, etc. It is preferable that it has [this]. Furthermore, the peripheral circuit 500 may have logic circuits, etc. Also, The configuration of the semiconductor device 700 is not limited to the configuration shown in Figure 2.

[0031] Here, the memory cell array 300 and the row selection driver connected to the memory cell array, and the column The configuration, including the selection driver and the A / D converter, may also be referred to as a storage device.

[0032] The memory cell array 300 shown in Figure 1(A) has memory cells CL arranged horizontally in a plane of a units. It is constructed by arranging it in a matrix of × b columns (where a and b are natural numbers).

[0033] Each memory cell CL consists of c submemory cells SCL (where c is a natural number greater than or equal to 2). Here, let SCL_j be the submemory cell of the jth order (where j is a natural number from 1 to c). Morissel SCL_j is a first transistor Ta_j, a second transistor Tb_j and It has a first capacitive element Ca_j.

[0034] In other words, the memory cell CL has c-layer stacked submemory cells SCL_j, and each subme The Morisel SCL consists of a first transistor Ta, a second transistor Tb, and a capacitive element Ca It holds.

[0035] For example, in the case where single-crystal silicon is used for transistor Ta_j or transistor Tb_j Let's consider the combination. In order to obtain excellent single-crystal silicon, a single-crystal silicon substrate etc. is used It is preferable to form a transistor. On the other hand, transistors Ta_j and Tb When using an oxide semiconductor layer for _j, for example, the sputtering method, CVD method, M described later, Since it can be formed by the BE method, PLD method, ALD method, etc., it can be repeatedly laminated. It is easy to form a semiconductor layer by stacking it on top of a transistor. It is easy to form a zista. As shown in Figure 1(A), the c-layer submembrane S This makes it possible to stack CLs. A memory cell CL is a c-layer stacked submemory cell SC. It has L. Therefore, the capacity per unit area can be increased.

[0036] As shown in Figure 1(B), in a memory cell CL consisting of c submemory cells SCL, Each submemory cell SCL_j shares the bit line BL and the source line SL.

[0037] The gate of transistor Ta_j is connected to the write word line WWL_j. The transistor Ta_j has the bit line BL connected to either its source or drain, and A floating node FN is connected to the other end of the drain and the other end of the drain.

[0038] The transistor Tb_j has a floating node FN connected to its gate. The transistor Tb_j has the bit line BL connected to either its source or drain, and the source The source line SL is connected to the other end of the drain and the source line.

[0039] The capacitive element Ca_j has a floating node FN connected to one electrode, and the other electrode The read word line RWL_j is connected to the pole.

[0040] The word signal is applied to the write word line WWL_j.

[0041] The word signal is used to transfer the potential of the bit line BL to the floating node FN, This is a signal that causes the transistor Ta_j to become conductive.

[0042] The bit line BL is given binary or multi-valued data. Multi-valued data is k bits This is data of type (where k is a natural number greater than or equal to 2). Specifically, if the data is 2 bits, it will have 4 values. This data is a signal having one of four voltage levels.

[0043] The readout word line RWL_j is supplied with a readout signal.

[0044] The read signal is used to selectively read data from the memory cell, using the capacitive element Ca_j This is the signal applied to the other electrode.

[0045] The floating node FN is one electrode of the capacitive element Ca_j, and the transistor Ta_j Wiring connecting the source and drain electrodes of the transistor Tb_j, and the gate of the transistor Tb_j. It corresponds to one of the nodes above.

[0046] In this specification, a node refers to a wire provided to electrically connect elements. It refers to one of the above locations.

[0047] In this specification, the word signal applied to the write word line WWL_j is controlled. This causes the potential of the floating node FN to correspond to the potential of the bit line BL. This is called writing data to the memory cell. Also, the read word line RWL_j By controlling the given readout signal, the potential of the bit line BL is controlled by the floating nose. Reading data from a memory cell is when the potential changes according to the potential of the FN terminal.

[0048] The transistor Ta_j preferably has a second gate electrode (BG). Applying a potential lower or higher than the source electrode to the gate electrode creates a threshold for the transistor. The voltage value can be varied in the positive or negative direction. For example, a transistor By varying the threshold voltage of the transistor in the positive direction, even if the gate potential is 0V, the transistor can be controlled. In some cases, a normally off state can be achieved, where the zista becomes non-conductive (off). The voltage applied to the second gate electrode may be variable or fixed. When the voltage applied to the gate electrode of electrode 2 is to be variable, the circuit that controls the voltage is the second gate electrode It may be connected to the pole. Also, the second gate electrode may be connected to the first gate electrode. By connecting the second gate and the first gate and applying the same potential, the on-current increases. In addition, reduction of initial characteristic variation, -GBT (Minus Gate Bias Tempo) (Rature) Suppression of degradation in stress tests, and on-current at different drain voltages It is possible to suppress fluctuations in the rise voltage.

[0049] Also, although not shown in Figure 1(B), transistor Tb_j is also the second gate electrode (B G) may be present. Transistor Tb_j is preferably on current high. By increasing the on-current of the station Tb_j, for example, the reading of the memory cell array 300 It can increase the speed of release.

[0050] Furthermore, the liquid crystal elements and organic EL (Electroluminescent) elements that are electrically connected to node FN. When display elements such as glossy elements are present, for example, one of the memory cell array 300 The part may be used as a pixel in a display device.

[0051] The potential of the floating node FN is determined by the data supplied to the bit line BL. It is in this position. Also, the floating node FN puts transistor Ta_j into a non-conducting state. Therefore, it is in an electrically floating state. If the voltage of the output signal is changed, the potential of the floating node FN will return to its original potential. The potential is increased by the voltage change of the output signal. This potential change affects the readout word line. Capacitive coupling of the capacitive element Ca_j occurs when the readout signal applied to the RWL changes. This is due to...

[0052] Transistor Ta_j switches between conductive and non-conductive states to write data. It functions as a switch to control the input. Also, transistor Ta_j is non-conductive. It has the function of maintaining the potential based on the written data by preserving the state. The transistor Ta_j is also called the first transistor. Furthermore, the transistor Ta_j is, This explanation will be based on the concept of an n-channel transistor.

[0053] Note that in the non-conductive state, the current flowing between the source and drain of transistor Ta_j It is preferable to use a transistor with a low off-current. Here, the off-current Low means that at room temperature, with a voltage of 10V between the source and drain, and a channel width of 1 This means that the normalized off-current per μm is 10 zA or less. An example of a transistor with low current flow is a transistor that has an oxide semiconductor in its semiconductor layer. It is possible.

[0054] By using a transistor with a small off-current as transistor Ta_j, It is possible to maintain the potential of the floating node FN in a non-conductive state for a long period of time. Therefore, the refresh frequency of semiconductor devices can be reduced, thus reducing power consumption. This makes it possible to realize semiconductor devices that require less power.

[0055] Furthermore, the potential held in the floating node FN was maintained at 85°C for 10 years (3.1 5 x 10 8 To maintain this for seconds, the transistor channel width must be 1 μm per 1 fF of capacitance. The off-current value per unit is 4.3 yA (yoctaamperes: 1 yA is 10 -24 A) Less than It is preferable that the allowable fluctuation in the potential of the floating node FN is 0. It is preferable that the voltage is within 5V. Alternatively, at 95°C, the above off-current is less than 1.5yA. It is preferable that it is full. One aspect of the present invention relates to a semiconductor device in which the hydrogen concentration below the barrier film is The degree has been sufficiently reduced. As a result, the transient using oxide semiconductor on the upper layer of the barrier film The sta can achieve extremely low off-current.

[0056] Furthermore, by increasing the capacity, the potential can be maintained at node FN for a longer period of time. In other words, the retention time can be extended.

[0057] In the configuration of the memory cell array 300 shown in Figure 1(B), by maintaining a non-conductive state, It holds the potential based on the written data. Therefore, the floating node FN Transistors with low off-current are used as switches to suppress potential fluctuations accompanied by charge movement. It is especially preferable to use "ta".

[0058] By using a transistor Ta_j with low off-current, the non-conductive state can be maintained. Therefore, the memory cell array 300 can be made into a non-volatile memory. Thus, The data written to the memory cell array 300 is then transmitted back to transistor Ta_j. It can be held in the floating node FN until it is ready.

[0059] The transistor Tb_j, according to the potential of the floating node FN, is sourced and drained. It has the function of passing an electric current Id between it and the cell. Note that the memory cell array 30 shown in Figure 1(A) In configuration 0, the current Id flowing between the source and drain of transistor Tb_j is This is the current flowing between the T-wire BL and the source wire SL. Note that the transistor Tb_j is defined as For example, a transistor using silicon as the semiconductor layer may be used, or an oxide semiconductor may be used. A transistor used in the semiconductor layer may also be used. Here, let's call the transistor Tb_j An example using an oxide semiconductor as the semiconductor layer of a transistor is shown. Note that transistor Tb _j is also called the second transistor. Furthermore, the transistor Tb_j is an n-channel type. This explanation will focus on transistors.

[0060] Transistors Ta_j and Tb_j are, for example, switching speeds. A fast n-channel transistor can be used. For example, the transistor The twisting speed is less than 10 ns, preferably less than 1 ns, more preferably 0.1 ns. It is less than s. For example, oxide semiconductors (preferably containing In, Ga, and Zn oxides) A transistor that includes a material in its channel formation region (hereinafter referred to as an oxide semiconductor transistor) (Also called) can be used.

[0061] Next, the operation of the memory cell array 300 shown in Figure 1(B) will be explained.

[0062] The timing chart shown in Figure 3 is based on the written word line WWL and the read word line shown in Figure 1(B). The branching word line RWL, floating node FN, bit line BL, and source line SL This shows the changes in each given signal.

[0063] First, the writing operation will be explained using Figure 3(A). Here, binary data We will now explain the writing process, but the memory cell array 300 is used for writing binary data. It is not limited and can also write multi-value data. The timing chart shown in Figure 3(A) In this section, the write period T4, the pause period T5, and the non-selection period T6 are shown.

[0064] During the writing period T4, a potential V2 is first applied to the writing word line WWL. Also, The read word line RWL is given a potential V0. Then, the bit line BL is given a binary data A potential corresponding to the t is applied, that is, a potential at the H level or a potential at the L level. A potential of level H is applied to the wire SL.

[0065] Next, during the pause period T5, the read word line RWL and the write word line WWL are powered A potential of V0 is given. Then, an L-level potential is applied to the bit line BL and the source line SL. Here, for example, we can assume that potential V0 is the ground potential and potential V2 is a positive potential. The absolute value of potential V2 is preferably greater than the potential of H level. For example, It should be set to approximately the threshold value of Tb_j, or about three times the threshold value.

[0066] Next, during the non-selection period T6, the read word line RWL and the write word line WWL are powered. A potential V1 is given. Here, the potential V1 can be, for example, a negative potential. The absolute value of is preferably greater than the potential of the H level. Also, the bit line BL and source A potential of level L is applied to line SL.

[0067] Next, the reading operation will be explained using Figure 3(B). The type shown in Figure 3(B) In the mining chart, the potential of the bit line BL is precharged during period T1, and the data is read out. This shows the period T2 during which the bit wire BL is discharged and the non-selective period T3.

[0068] During the period T1 shown in Figure 3(B), the potential of the bit line BL is precharged. The T-line BL is given a potential (potential H') that is approximately the same as the H level. At this time, writing A potential V1 is applied to the word line WWL. Also, a potential V1 is applied to the readout word line RWL. A value is given. Also, the floating node FN holds the potential corresponding to the data. It is. Also, the source line SL is given an L-level potential.

[0069] At this point, the bit line BL becomes electrically detached after being given a high-level potential. In other words, the bit line BL is in a state where the potential fluctuates due to the charging or discharging of charge. This floating state can be achieved by turning off the switch that applies potential to the bit line BL. It is possible.

[0070] Next, during period T2 shown in Figure 3(B), the bit line BL is discharged in order to read the data. Perform the operation. At this time, the writing word line WWL is given potential V1, as in the previous period. Furthermore, the readout word line RWL is given a potential at the H level, in this case the potential V0. Furthermore, the floating node FN will have an increased potential corresponding to each data point. The potential of the bit line BL changes according to the potential of the floating node FN. For example, If a low-level potential is input to the loading node FN, then the bit line BL will A high-level signal (potential H') is output, and a high-level potential is applied to the floating node FN. If input is present, an L-level signal (potential L') is output to bit line BL. Furthermore, the source line SL is supplied with an L-level potential, as in the previous period.

[0071] Next, period T3 shown in Figure 3(B) represents a non-selection state. During period T3, the reading Let V1 be the potential of the output word line RWL.

[0072] Furthermore, the memory cell array 300 may have a circuit configuration as shown in Figure 4. In Figure 4, By connecting the submemory cells SCL_j to the BL wire in an alternating pattern, the memory cell A In some cases, the integration density of Ray300 can be increased. Furthermore, the memory capacity per unit area This can be improved. Here, Figure 4 shows the submemory cells SCL_j from j=1 to c. The diagram shows four submemory cells SCL_j with j=1, 2, 3, and c. The memory cell array 300 may also have a circuit configuration as shown in Figure 5. In Figure 5, compared with Figure 4... This allows for a reduction in the number of source lines SL. Here, Figure 5 shows j=1 to c Of the submemory cells SCL_j, there are four submemory cells SCL_ with j=1, 2, 3, and c j is shown in the diagram. Note that in Figures 4 and 5, transistor Ta_j is shown in Figure 1(B It may also have a second gate electrode (BG), similar to the above.

[0073] [Example of a laminated structure] Next, an example of a stacked structure having the memory cell array 300 described in Figure 1 is shown in Figure 6. explain.

[0074] The stacked structure shown in Figure 6 is a semiconductor device having a memory cell array 300 and peripheral circuits 500. This is an example of a 700 unit.

[0075] Peripheral circuit 500 consists of transistor 130a, transistor 130b, and transistor 23 It has transistor 0a and transistor 230b. Transistor 130a, transistor 130b Transistors 230a and 230b are composed of a first semiconductor material. For example, silicon and gelatin can be used as the first semiconductor material. Semiconductor materials such as arsenic, germanium, gallium, and arginine, silicon, germanium, gallium, and arginine. Compound semiconductor materials containing elements such as aluminum, organic semiconductor materials, or oxide semiconductors. Examples include materials. Here, we consider the case where single-crystal silicon is used as the first semiconductor material. This explains transistors 130a, 130b, and 230. transistors a and 230b can be either p-channel or n-channel, but the circuit The appropriate transistor should be used depending on the configuration and driving method. Here, transistor 13 Examples of n-channel transistors are shown as 0a and transistor 130b. Examples of p-channel transistors are shown for zista 230a and transistor 230b. Here, transistors 130a and 130b have almost the same configuration. Therefore, we will only explain transistor 130a. Also, transistor 230a and transistor 130a will be explained. Since transistor 230b has a nearly identical configuration, only transistor 230a will be explained. Perform.

[0076] The transistor 130a is provided on the semiconductor substrate 131 and is located in a part of the semiconductor substrate 131. A semiconductor layer 132, a gate insulating film 134, a gate electrode 135, and a source region or It has low-resistance layers 133a and 133b that function as rain regions.

[0077] The region where the channel of the semiconductor layer 132 is formed, the region near it, the source region or In the low-resistance layer 133a and low-resistance layer 133b, etc., which constitute the rain region, silicon-based semiconductor It is preferable to include semiconductors such as G e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may also be formed from a material containing GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon with strain in the child is also possible. Alternatively, GaAs and GaAlAs, etc. By using this, transistor 130a is HEMT (High Electron Mo It can also be written as (bility Transistor).

[0078] Furthermore, transistor 130a is in region 17, which is the LDD (Light Doped Drain) region. It may have region 6a and region 176b.

[0079] The low-resistance layers 133a and 133b are semiconductor materials applied to the semiconductor layer 132. In addition, elements that impart n-type conductivity, such as phosphorus, or elements that impart p-type conductivity, such as boron, are used. It contains the element.

[0080] The gate electrode 135 is made of an element that imparts n-type conductivity, such as phosphorus, or a p-type element, such as boron. Semiconductor materials such as silicon, metallic materials, alloy materials, and elements that impart conductivity to the type, Conductive materials such as metal oxide materials can be used. In particular, it is possible to achieve both heat resistance and conductivity. It is preferable to use high melting point materials such as tungsten and molybdenum, and especially tungsten It is preferable to use Ten.

[0081] The transistor 230a is provided on the semiconductor substrate 131 and is located in a part of the semiconductor substrate 131 A semiconductor layer 232, a gate insulating film 134, a gate electrode 235, and a source region or It has low-resistance layers 233a and 233b that function as rain regions.

[0082] For semiconductor layer 232, refer to the description of semiconductor layer 132. Also, low-resistance layer 233a and For the low-resistance layer 233b, refer to the description of the low-resistance layer 133a and the low-resistance layer 133b. Furthermore, for gate electrode 235, refer to the description of gate electrode 135.

[0083] Also, for example, if transistor 130a is an n-channel type transistor, then transistor 2 When 30a is a p-channel type transistor, low-resistance layer 133a and low-resistance layer 1 For example, phosphorus is added to 33b, and for example, boron is added to the low-resistance layer 233a and low-resistance layer 233b. You can add an element. Also, for example, the work function of gate electrode 135 and gate electrode 235 Different materials may be used for each component.

[0084] Here, transistors 130a, 130b, 230a and Transistor 190, as shown in Figure 17, may be used instead of transistor 230b. Oh, Figure 17 shows an example of an n-channel transistor, but a p-channel transistor... A similar structure can be used for the following. The cross-section shown by the dashed line AB in Figure 17(A) This is shown in Figure 17(B). Transistor 190 has a semiconductor layer 132 (semiconductor) where the channel is formed. A portion of the substrate 131 has a convex shape, and the gate insulating film 134 and A gate electrode 135 is provided. Such a transistor 190 is a convex shape on a semiconductor substrate. It is also called a FIN-type transistor because it utilizes a certain part. Furthermore, it may have an insulating film that functions as a mask for forming the protrusions. We have shown the case where a protrusion is formed by processing a part of a semiconductor substrate, but what if we process an SOI substrate? A semiconductor layer having a convex shape may be formed.

[0085] Transistor 130a, transistor 130b, transistor 230a and transistor The insulating film 136, insulating film 137, and insulating film 138 are sequentially laminated over the 230b. It's being kicked.

[0086] In the semiconductor device fabrication process, the insulating film 136 is used to form the low-resistance layer 133a and the low-resistance layer 133b , activation of conductive elements added to the low-resistance layer 233a and low-resistance layer 233b, etc. It functions as a protective film in that case. The insulating film 136 may be omitted if it is not needed.

[0087] When silicon-based semiconductor materials are used for semiconductor layer 132 and semiconductor layer 232, insulating film 13 7 preferably contains an insulating material containing hydrogen. The hydrogen-containing insulating film 137 is used in the transistor. 130a, transistor 130b, transistor 230a and transistor 230b By providing and performing a heat treatment, hydrogen in the insulating film 137 causes the semiconductor layer 132 and semiconductor layer 2 The dangling bond in 32 is terminated, and transistors 130a and 130b are terminated. This improves the reliability of transistors 230a and 230b.

[0088] The insulating film 138 is provided with transistors 130a and 130b located beneath it. Flatten the step created by transistors 230a and 230b, etc. It functions as a flattening layer. The upper surface of the insulating film 138 is treated with CMP to improve the flatness of its upper surface. Planarization using methods such as (Chemical Mechanical Polishing) The processing may have resulted in flattening.

[0089] In addition, insulating film 136, insulating film 137, and insulating film 138 have a low-resistance layer 133a and a low-resistance layer 1 Plugs, etc., that are electrically connected to 33b, low-resistance layer 233a and low-resistance layer 233b, etc. are embedded. It's okay if they're born.

[0090] Furthermore, the memory cell array 300 has transistors made of oxide semiconductors. The stacked structure shown in Figure 6 consists of transistor 130a, transistor 130b, and transistor A barrier film 1 is placed between the transistor 230a and the transistor 230b and the memory cell array 300. It is preferable to have 11.

[0091] The barrier film 111 is a mechanism that suppresses the diffusion of water and hydrogen from the lower layer to the upper layer. It is a layer that has the ability to do so. Furthermore, it is preferable that the barrier film 111 has low oxygen permeability. The barrier film 111 has an electrode or wiring provided above it and an electrode or wiring provided below it. It may have openings or plugs for electrically connecting to wiring. Here, water and water A film that does not easily diffuse elements is, for example, a film that is less diffusive than silicon oxide, which is commonly used as an insulating film. In comparison, it shows a membrane with low water and hydrogen permeability. Also, a membrane with low oxygen permeability is generally... Compared to silicon oxide and other materials used as insulating films, it exhibits a film with lower oxygen permeability.

[0092] Here, in the layer below the barrier film 111, hydrogen and water are reduced as much as possible. This is preferable. Alternatively, it is preferable to suppress the desorption gas. Hydrogen and water are oxide semiconductors. This can be a factor that causes fluctuations in electrical properties. Also, from the lower layer to the upper layer of the barrier film 111 Hydrogen and water diffusing into the layer can be suppressed by the barrier membrane 111, but the barrier membrane 11 In some cases, hydrogen or water may diffuse to the upper layer through openings or plugs provided in 1.

[0093] In order to reduce the amount of hydrogen and water contained in each layer located below the barrier film 111, In order to suppress the desorption of gas, before forming the barrier film 111, or on the barrier film 111, Immediately after forming the opening for forming the lug, hydrogen contained in the layer below the barrier film 111 It is preferable to apply a heat treatment to remove water or to suppress desorbed gases. The heat resistance of conductive films and other components constituting semiconductor devices, and the electrical characteristics of transistors, must not deteriorate. If the temperature is such that the heat treatment temperature is high, then a higher temperature is preferable. Specifically, for example, 450°C or higher is preferable. The temperature should be 490°C or higher, more preferably 530°C or higher, but 650°C or higher is acceptable. The above may also be done. For at least 1 hour, preferably 5 hours, under an inert gas atmosphere or a reduced pressure atmosphere. It is preferable to perform a heat treatment for more than 10 hours, more preferably 10 hours or more. Barrier film 11 The decision should be made considering the heat resistance of the wiring or electrode material located below layer 1, for example. For example, if the heat resistance of the material is low, the temperature should be 550°C or below, or 600°C or below, or 65°C. The process should be carried out at temperatures below 0°C or below 800°C. Furthermore, such heat treatment is performed at least as follows: Doing it once or more is sufficient, but doing it multiple times is preferable.

[0094] The insulating film provided below the barrier film 111 is analyzed by thermal desorption gas spectroscopy (TDS analysis). The amount of hydrogen molecules desorbed at a substrate surface temperature of 400°C, as measured by (also known as) is 30 It is preferable that the amount of hydrogen molecules removed at 0°C is 130% or less, preferably 110% or less. Alternatively, the desorption amount of hydrogen molecules at a substrate surface temperature of 450 °C by TDS analysis is preferably 130% or less, preferably 110% or less of the desorption amount at 350 °C.

[0095] Also, it is preferable that water and hydrogen contained in the barrier film 111 itself are reduced. Or it is preferable that the desorbed gas is suppressed. For example, as the barrier film 111, the desorption amount of hydrogen molecules (M / z = 2) in the range of a substrate surface temperature of 20 °C to 600 °C by TDS analysis is less than 2 × 10 per cm 15 ², preferably less than 1 × 10 2 per cm 15 ², more 2 preferably less than 5 × 10 per cm 14 ². It is preferable to use a material having such a desorption amount as the barrier film 111. 2 Alternatively, the desorption amount of water molecules (M / z = 18) in the range of a substrate surface temperature of 20 °C to 600 °C by TDS analysis is less than 1 × 10 per cm ², preferably less than 5 × 10 16 per cm 2 ², more preferably less than 2 × 10 1 5 per cm 2 ². It is preferable to use a material having such a desorption amount as the barrier film 1 12 11. 2

[0096] Also, the heat treatment can also serve as a treatment (also called hydrogenation treatment) for terminating unpaired bonds of silicon (also called dangling bonds) used in the semiconductor layers of the transistors 130a, 130b, 230a, and 230b with hydrogen. By the hydrogenation treatment, the transistors 130a, 130b, and tra The gate insulating film of transistors 230a and 230b, and the layer below the barrier film 111 Some of the hydrogen contained in the other insulating film formed thereon desorbs, and transistor 130a, Diffusion into the semiconductor layers of transistor 130b, transistor 230a, and transistor 230b. Furthermore, by terminating the dangling bonds in the silicon, transistor 130a, Improved the reliability of transistors 130b, 230a, and 230b. It is possible.

[0097] Materials that can be used for the barrier film 111 include aluminum oxide and hafniac oxide. M, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), striated titanate So-called h such as rontium (SrTiO3) or (Ba,Sr)TiO3 (BST) Insulating films containing igh-k material can be used in single-layer or multi-layer configurations. For example, the border film can contain aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, and sulfite oxide. Lithium oxide, titanium dioxide, tungsten oxide, yttrium oxide, zirconium oxide, gas oxide Alum may be added. Alternatively, these insulating films may be nitrided to form an oxidized nitride film. The above insulating film is used by laminating silicon oxide, silicon oxide nitride, or silicon nitride. Other good options include gallium oxide, etc. In particular, aluminum oxide is effective against water and hydrogen. It is preferable because it has excellent barrier properties.

[0098] The barrier film 111 consists of a layer of material that is impermeable to water and hydrogen, as well as a layer containing other insulating materials. They may be used in a layered configuration. For example, a layer containing silicon oxide or silicon oxide nitride, a metal Layers containing oxides or other materials may be stacked and used.

[0099] Furthermore, it is preferable to use a material that is impermeable to oxygen for the barrier film 111. The material is one that exhibits excellent barrier properties not only against hydrogen and water but also against oxygen. By using this method, the oxygen released when the insulating film 114j is heated is lower than that of the barrier film 111. Diffusion into the layer can be suppressed. As a result, the emission from the insulating film 114j is suppressed. Increase the amount of oxygen that can be supplied to the semiconductor layers of transistor Ta_j and transistor Tb_j. It can be made to happen.

[0100] In this way, the concentration of hydrogen and water in each layer located below the barrier film 111 is reduced. It reduces, removes hydrogen or water, or suppresses desorbed gases, and further, the barrier film 111 This suppresses the diffusion of hydrogen and water into transistors Ta_j and Tb_j. Therefore, insulating film 114j and transistors Ta_j and Tb_j are formed The hydrogen and water content in each layer can be made extremely low. For example, Insulating film 114j, semiconductor layer 101j of transistor Ta_j and transistor Tb_j, Alternatively, the hydrogen concentration contained in the gate insulating film 102j is 5 × 10 18 cm -3 Less than, preferably is 1 x 10 18 cm -3 Less than 3 × 10 17 cm -3 Reduce to less than R It is possible.

[0101] With the above configuration, a peripheral circuit 500 having a transistor using silicon as the semiconductor layer is obtained. And, a memory cell array 300 having transistors using oxide semiconductors as semiconductor layers This makes it possible to achieve high reliability even with misalignment, resulting in an extremely reliable semiconductor device. This can be achieved.

[0102] The above example shows a peripheral circuit 500 that includes a transistor using silicon as the semiconductor layer. As shown, peripheral circuit 500 uses a transistor with silicon as the semiconductor layer and an oxide semiconductor It may also have both a transistor and a semiconductor layer with a conductor. In that case, for example, After forming a barrier film 111 on a transistor using Ricon as the semiconductor layer, A transistor using a semiconductor layer is formed by stacking it on a barrier film 111, and peripheral circuit 5 00 should be formed. Furthermore, on top of the peripheral circuit 500, an oxide semiconductor is used as the semiconductor layer. This can be formed by stacking memory cell arrays 300, each having a transistor.

[0103] Here, a p-channel type transistor using silicon as the semiconductor layer, which can be applied to the peripheral circuit 500, is described. A circuit structure using an n-channel transistor with an oxide semiconductor as the semiconductor layer. Let's explain an example of success.

[0104] [CMOS circuit] The circuit diagram shown in Figure 26(A) is a p-channel type transistor 2200 and an n-channel type This is a so-called CM configuration, where two transistors 2100 are connected in series, and their gates are connected. The diagram shows the configuration of the OS circuit. Note that in the diagram, the transistor to which the second semiconductor material is applied is shown. This is indicated by the symbol "OS".

[0105] [Analog switch] Furthermore, the circuit diagram shown in Figure 26(B) shows the relationship between transistor 2100 and transistor 2200. This shows a configuration where the source and drain are connected. With this configuration, It can function as a so-called analog switch.

[0106] [Example 1 of the stacked structure] Next, an example of the stacked structure of a semiconductor device having a memory cell array 300 and a peripheral circuit 500 will be described with reference to FIG. 6. The memory cell array 300 is provided on the peripheral circuit 500. The memory cell array 300 has memory cells CL. The memory cell CL has c sub-memory cells SCL_j (j is a natural number from 1 to c). FIG. 6 shows an example of the stacked structure of the sub-memory cell SCL_1 and the sub-memory cell SCL_2. Although not shown, the sub-memory cell SCL_3 is further stacked on the sub-memory cell SCL_2, and the sub-memory cells SCL_c are stacked in order. Note that the circuit diagram of the memory cell array 300 is referred to FIG. 1(B). The memory cell array 300 has memory cells CL. The memory cell CL has c sub-memory cells SCL_j (j is a natural number from 1 to c). FIG. 6 shows an example of the stacked structure of the sub-memory cell SCL_1 and the sub-memory cell SCL_2. Although not shown, the sub-memory cell SCL_3 is further stacked on the sub-memory cell SCL_2, and the sub-memory cells SCL_c are stacked in order. Note that the circuit diagram of the memory cell array 300 is referred to FIG. 1(B). [[ID=--snip--]] c sub-memory cells SCL_j (j is a natural number from 1 to c). FIG. 6 shows an example of the stacked structure of the sub-memory cell SCL_1 and the sub-memory cell SCL_2. Although not shown, the sub-memory cell SCL_3 is further stacked on the sub-memory cell SCL_2, and the sub-memory cells SCL_c are stacked in order. Note that the circuit diagram of the memory cell array 300 is referred to FIG. 1(B). An example of the stacked structure of the sub-memory cell SCL_1 and the sub-memory cell SCL_2 is shown, and although not shown, the sub-memory cell SCL_3 is further stacked on the sub-memory cell SCL_2, and the sub-memory cells SCL_c are stacked in order. Note that the circuit diagram of the memory cell array 300 is referred to FIG. 1(B). Although not shown, the sub-memory cell SCL_3 is further stacked on the sub-memory cell SCL_2, and the sub-memory cells SCL_c are stacked in order. Note that the circuit diagram of the memory cell array 300 is referred to FIG. 1(B). Although not shown, the sub-memory cell SCL_3 is further stacked on the sub-memory cell SCL_2, and the sub-memory cells SCL_c are stacked in order. Note that the circuit diagram of the memory cell array 300 is referred to FIG. 1(B). <00,00902>The circuit diagram of the memory cell array 300 is referred to FIG. 1(B).

[0107] The sub-memory cell SCL_j has a transistor Ta_j, a transistor Tb_j, and a capacitor element Ca_j. The transistors Ta_j and Tb_j are composed of an oxide semiconductor material. Here, when j = 1, it is preferable that a barrier film 111 is provided between the transistor Tb_j and the peripheral circuit 500. The sub-memory cell SCL_j has a transistor Ta_j, a transistor Tb_j, and a capacitor element Ca_j. The transistors Ta_j and Tb_j are composed of an oxide semiconductor material. Here, when j = 1, it is preferable that a barrier film 111 is provided between the transistor Tb_j and the peripheral circuit 500. The sub-memory cell SCL_j has a transistor Ta_j, a transistor Tb_j, and a capacitor element Ca_j. The transistors Ta_j and Tb_j are composed of an oxide semiconductor material. Here, when j = 1, it is preferable that a barrier film 111 is provided between the transistor Tb_j and the peripheral circuit 500. The sub-memory cell SCL_j has a transistor Ta_j, a transistor Tb_j, and a capacitor element Ca_j. The transistors Ta_j and Tb_j are composed of an oxide semiconductor material. Here, when j = 1, it is preferable that a barrier film 111 is provided between the transistor Tb_j and the peripheral circuit 500.

[0108] Also, a capacitor element Ca_j is provided on the transistor Tb_j. Also, at least a part of the capacitor element Ca_j is preferably provided so as to overlap the transistor Tb_j. Here, a conductive layer 151j, which is one of the terminals of the capacitor element Ca_j, is electrically connected to the gate electrode 203j of the transistor Tb_j through a plug !41j. Also, an insulating film 216j is provided between the transistor Tb_j and the capacitor element Ca_j. Also, a capacitor element Ca_j is provided on the transistor Tb_j. Also, at least a part of the capacitor element Ca_j is preferably provided so as to overlap the transistor Tb_j. Here, a conductive layer 151j, which is one of the terminals of the capacitor element Ca_j, is electrically connected to the gate electrode 203j of the transistor Tb_j through a plug 141j. Also, an insulating film 216j is provided between the transistor Tb_j and the capacitor element Ca_j. Also, a capacitor element Ca_j is provided on the transistor Tb_j. Also, at least a part of the capacitor element Ca_j is preferably provided so as to overlap the transistor Tb_j. Here, a conductive layer 151j, which is one of the terminals of the capacitor element Ca_j, is electrically connected to the gate electrode 203j of the transistor Tb_j through a plug 141j. Also, an insulating film 216j is provided between the transistor Tb_j and the capacitor element Ca_j. Also, a capacitor element Ca_j is provided on the transistor Tb_j. Also, at least a part of the capacitor element Ca_j is preferably provided so as to overlap the transistor Tb_j. Here, a conductive layer 151j, which is one of the terminals of the capacitor element Ca_j, is electrically connected to the gate electrode 203j of the transistor Tb_j through a plug 141j. Also, an insulating film 216j is provided between the transistor Tb_j and the capacitor element Ca_j. Also, a capacitor element Ca_j is provided on the transistor Tb_j. Also, at least a part of the capacitor element Ca_j is preferably provided so as to overlap the transistor Tb_j. Here, a conductive layer 151j, which is one of the terminals of the capacitor element Ca_j, is electrically connected to the gate electrode 203j of the transistor Tb_j through a plug 141j. Also, an insulating film 216j is provided between the transistor Tb_j and the capacitor element Ca_j.

[0109] A transistor Ta_j is placed on top of the capacitive element Ca_j. Preferably, at least a portion of _j is provided so as to overlap with the capacitive element Ca_j. Here, the gate electrode 203j and the conductive layer 151j are plug 141j and plug 144j Conductive layer 1 acts as the source or drain electrode of transistor Ta_j via It is electrically connected to 04j_b. The insulating film 115j of the capacitive element Ca_j is connected to the conductive layer 1 It is sandwiched between 51j and the conductive layer 152j, forming a capacitance. Also, the capacitive element Ca_j and the transistor An insulating film 156j is provided between the transistor Ta_j. Also, the transistor Ta_ An insulating film 116j is provided on j.

[0110] Conductive layer 204j functions as the source or drain electrode of transistor Tb_j _b is electrically connected to source line SL. Here, plug 143j, conductive layer 154j, p Lug 146j, plug 148j, etc., may also function as source line SL.

[0111] Conductive layer 204j functions as the source or drain electrode of transistor Tb_j _a is connected to transistor Ta via plug 142j, conductive layer 153j, plug 145j, etc. The conductive layer 104j_a is electrically connected to function as the source or drain electrode of _j. Furthermore, conductive layers 204j_a and 104j_a are electrically connected to the bit line BL. To be continued. Here, plug 142j, conductive layer 153j, plug 145j, etc. are connected to bit wire BL. It may function as such.

[0112] Furthermore, submemory cell SCL_j is connected to the adjacent submemory cell SCL_α and plug 1 It shares components such as 42j, conductive layer 153j, plug 145j, plug 147j, etc. Sub-memory SCL_α includes plug 142j, conductive layer 153j, plug 145j, plug 147j, etc. It is electrically connected to the bit line BL via. Similarly, the submemory cell SCL_j is adjacent The submemory cell SCL_β, plug 143j, conductive layer 154j, plug 146j, It shares plug 148j, etc. Submemory cell SCL_β has plug 143j, conductive layer 1 The source line SL is electrically connected via plugs such as 54j, 146j, and 148j. By sharing plugs and conductive layers in this way, the integration density of the memory cell array 300 can be increased. It is possible to do so.

[0113] Here, submemory cell SCL_α is adjacent to memory cell CL and memory cell CL_α These are submemory cells that the device possesses. Here, the adjacent memory cells are the x shown in Figure 1(A). This indicates that the memory cells differ by 1 in either the x or y value at the y-coordinate (x,y). For example, Memory cell CL_α is located at a coordinate that is 1 less in x-coordinate than memory cell CL. For example, memory cell CL_β is located at a coordinate where the x-coordinate is 1 greater than that of memory cell CL. Place it.

[0114] The transistor Tb_j in the submemory cell SCL_j is submemory cell SCL_ The transistor Tb_α possessed by α shares the conductive layer 204j_a. That is, the conductive layer 204j_a acts as either the source or drain electrode of transistor Tb_j. It is capable of functioning as either the source or drain electrode of transistor Tb_α. Furthermore, transistor Tb_j is the transistor T that the submemory cell SCL_β possesses. b_β shares the conductive layer 204j_b. That is, the conductive layer 204j_b functions as the other of the source electrode or the drain electrode of the transistor Tb_j and also functions as one of the source electrode or the drain electrode of the transistor Tb_β. By sharing the conductive layer in this way, the integration degree of the memory cell array 300 can be increased. The transistor Ta_j of the sub-memory cell SCL_j shares the conductive layer 104j_a with the transistor Ta_α of the sub-memory cell SCL_α. That is, the conductive layer 104j_a functions as one of the source electrode or the drain electrode of the transistor Ta_j and also functions as one of the source electrode or the drain electrode of the transistor Ta_α. By sharing the conductive layer in this way, the integration degree of the memory cell array 300 can be increased. Here, the structures of the transistors Ta_j and Tb_j will be described. The transistors Ta_j and Tb_j are transistors having an oxide semiconductor. An example of the transistor structure that can be used for the transistors Ta_j and Tb_j is shown in FIG. 7. FIG. 7(B) is a top view of the transistor structure that can be used for the transistors Ta_j and Tb_j. FIG. 7(A) shows a cross-section of the dashed line A-B shown in FIG. 7(B), and FIG. 7(C) shows a cross-section of the dashed line C-D shown in FIG. 7(B). Here, the transistor Ta_j is shown as an example, but the transistor Tb_j can have a similar structure.

[0115] The transistor Ta_j of the sub-memory cell SCL_j shares the conductive layer 104j_a with the transistor Ta_α of the sub-memory cell SCL_α. That is, the conductive layer 104j_a functions as one of the source electrode or the drain electrode of the transistor Ta_j and also functions as one of the source electrode or the drain electrode of the transistor Ta_α. By sharing the conductive layer in this way, the integration degree of the memory cell array 300 can be increased. Here, the structures of the transistors Ta_j and Tb_j will be described. The transistors Ta_j and Tb_j are transistors having an oxide semiconductor. An example of the transistor structure that can be used for the transistors Ta_j and Tb_j is shown in FIG. 7. FIG. 7(B) is a top view of the transistor structure that can be used for the transistors Ta_j and Tb_j. FIG. 7(A) shows a cross-section of the dashed line A-B shown in FIG. 7(B), and FIG. 7(C) shows a cross-section of the dashed line C-D shown in FIG. 7(B). Here, the transistor Ta_j is shown as an example, but the transistor Tb_j can have a similar structure. Here, the structures of the transistors Ta_j and Tb_j will be described. The transistors Ta_j and Tb_j are transistors having an oxide semiconductor. An example of the transistor structure that can be used for the transistors Ta_j and Tb_j is shown in FIG. 7. FIG. 7(B) is a top view of the transistor structure that can be used for the transistors Ta_j and Tb_j. FIG. 7(A) shows a cross-section of the dashed line A-B shown in FIG. 7(B), and FIG. 7(C) shows a cross-section of the dashed line C-D shown in FIG. 7(B). Here, the transistor Ta_j is shown as an example, but the transistor Tb_j can have a similar structure. Here, the structures of the transistors Ta_j and Tb_j will be described. The transistors Ta_j and Tb_j are transistors having an oxide semiconductor. An example of the transistor structure that can be used for the transistors Ta_j and Tb_j is shown in FIG. 7.

[0116] Here, the structures of the transistors Ta_j and Tb_j will be described. The transistors Ta_j and Tb_j are transistors having an oxide semiconductor. An example of the transistor structure that can be used for the transistors Ta_j and Tb_j is shown in FIG. 7. The transistors Ta_j and Tb_j are transistors having an oxide semiconductor. An example of the transistor structure that can be used for the transistors Ta_j and Tb_j is shown in FIG. 7. FIG. 7(B) is a top view of the transistor structure that can be used for the transistors Ta_j and Tb_j. FIG. 7(A) shows a cross-section of the dashed line A-B shown in FIG. 7(B), and FIG. 7(C) shows a cross-section of the dashed line C-D shown in FIG. 7(B). Here, the transistor Ta_j is shown as an example, but the transistor Tb_j can have a similar structure.

[0117] FIG. 7(B) is a top view of the transistor structure that can be used for the transistors Ta_j and Tb_j. FIG. 7(A) shows a cross-section of the dashed line A-B shown in FIG. 7(B), and FIG. 7(C) shows a cross-section of the dashed line C-D shown in FIG. 7(B). Here, the transistor Ta_j is shown as an example, but the transistor Tb_j can have a similar structure. Here, the transistor Ta_j is shown as an example, but the transistor Tb_j can have a similar structure. Here, the transistor Ta_j is shown as an example, but the transistor Tb_j can have a similar structure. Furthermore, each component of transistor Tb_j is described in the same way as transistor Ta_j. See the documentation. For example, for semiconductor layer 201j, refer to semiconductor layer 101j. For gate insulating film 202j, refer to gate insulating film 102j. Also, gate electrode For 203j, refer to gate electrode 103j. Also, conductive layer 204j_a and conductive For layer 204j_b, refer to conductive layer 104j_a and conductive layer 104j_b. For insulating film 214j, refer to insulating film 114j. Also, for conductive layer 205j... This refers to conductive layer 105j.

[0118] The transistor Ta_j consists of a semiconductor layer 101j in contact with the upper surface of the insulating film 114j, and a conductive layer 104j_a and conductive layer 104j_b and gate insulating film 102j on semiconductor layer 101j The gate electrode 103j overlaps with the semiconductor layer 101j via the gate insulating film 102j, and Furthermore, an insulating film is provided to cover the transistor Ta_j. Here, as shown in the diagram... However, as an insulating film covering the transistor Ta_j, for example, insulating film 112j, insulating film 11 Three layers of 3j and insulating film 116j can be used in a laminated configuration. The 113j and insulating film 116j will be explained in the example fabrication method described later. Conductive layer 104 j_a and conductive layer 104j_b function as the source electrode on one side and the drain electrode on the other. It functions as such.

[0119] The transistor Ta_j shown in Figures 7(A) to (C) consists of a semiconductor layer 101j_a and a semiconductor Semiconductor layer 101j_b in contact with the upper surface of body layer 101j_a, and the upper surface of semiconductor layer 101j_b Conductive layer 104j_a and conductive layer 1 are in contact with and separated in the region overlapping with semiconductor layer 101j_b. 04j_b, semiconductor layer 101j_c in contact with the upper surface of semiconductor layer 101j_b, and semiconductor layer On 101j_c, there is a gate insulating film 102j, and the gate insulating film 102j and semiconductor layer 101j It has a gate electrode 103j that overlaps with the semiconductor layer 101j_b via _c. The transistor Ta_j has a conductive layer 105j that functions as a second gate electrode. Body layer 101j_a is provided between the insulating film 114j and the semiconductor layer 101j_b. Furthermore, the semiconductor layer 101j_c is provided between the semiconductor layer 101j_b and the gate insulating film 102j. Furthermore, conductive layer 104j_a and conductive layer 104j_b are connected to semiconductor layer 101j It touches the upper surface of _b.

[0120] Furthermore, Figure 7(A) is shown in Figure 7(D), and Figure 7(C) is shown in Figure 7(E), respectively. The insulating film 114j has a protrusion, and a semiconductor layer 101j_a and a semiconductor layer 101 j_b may be provided.

[0121] Furthermore, as shown in Figures 18(A) to 18(C), for example, in the cross-section of Figure 18(C), The gate insulating film 102j may also cover the edges of the semiconductor layer 101j_c.

[0122] The semiconductor layer 101j of transistor Ta_j is preferably provided on the insulating film 114j. It is preferable that the insulating film 114j contains an oxide. In particular, some of the oxygen is released by heating. It is preferable that the material contains an oxide material that is removed. Preferably, it contains more oxygen than satisfactorily satisfactorily. It is preferable to use an oxide containing a large amount of oxygen. When the body is used, oxygen detached from the insulating film 114j is supplied to the oxide semiconductor, and the oxide semiconductor This makes it possible to reduce oxygen deficiencies in the conductor. As a result, the electrical characteristics of the second transistor This can suppress gender variability and improve reliability.

[0123] It is preferable that the upper surface of the insulating film 114j is flattened by the planarization treatment described above. .

[0124] The insulating film 114j is preferably made of an oxide material from which some oxygen is desorbed upon heating. stomach.

[0125] As an oxide material that desorbs oxygen upon heating, it contains more oxygen than satisfactorily satisfying the stoichiometric composition. It is preferable to use an oxide containing oxygen. Oxygen-containing oxide films undergo partial oxygen elimination upon heating. Oxide films containing more oxygen than those described above can be analyzed by thermal desorption gas spectroscopy (TDS). The surface temperature of the film is measured by esorption spectroscopy analysis. Acids in the range of 100°C to 700°C, preferably 100°C to 500°C. The amount of elementary molecules to be eliminated is 1.0 × 10⁻⁶ 18 atoms / cm 3 Preferably 3.0 × 10 2 0 atoms / cm 3 The above describes the oxide film.

[0126] For example, a material containing silicon oxide or silicon oxide nitride can be used as such a material. It is preferable to do so. Alternatively, metal oxides can also be used. As metal oxides, Aluminum, aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide It is possible to use materials such as yttrium oxide, hafnium oxide, and hafnium oxide. In this specification, silicon oxidnitride is defined as having a composition that is more oxygen-rich than nitrogen-rich. This refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, has more nitrogen than oxygen. This indicates the material with the highest content.

[0127] Similarly, the semiconductor layer 201j of the transistor Tb_j is provided on the insulating film 214j. It is preferable that this be done.

[0128] Furthermore, it is preferable that the transistor Ta_j has a conductive layer 105j. Conductive layer 10 5j is preferably used as the second gate of transistor Ta_j.

[0129] As shown in Figures 19(A) to 19(C), the transistor Tb_j is in the insulating film 214j A semiconductor layer 201j in contact with the upper surface, conductive layer 204j_a and conductive layer 204j_b, and The gate insulating film 202j on the conductive layer 201j and the semiconductor layer 2 via the gate insulating film 202j It has a gate electrode 203j that overlaps with 01j, and also covers transistor Tb_j. Insulating film 212j, insulating film 213j, and insulating film 216j are provided. Conductive layer 204 j_a and conductive layer 204j_b function as the source electrode on one side and the drain electrode on the other. It functions as such.

[0130] Furthermore, the transistor Tb_j may have a conductive layer 205j. The conductive layer 205j is It may function as the second gate of the lunger Tb_j.

[0131] Here, the conductive layer 105j of transistor Ta_j and the conductive layer of transistor Tb_j When applying a voltage between the electrodes of the conductive layer 205j, the voltage may be different. Here, the difference between the voltage applied to the conductive layer 105j and the source voltage is defined as Vbg_1, and the conductive layer 205 Let Vbg_2 be the difference between the voltage applied to j and the source voltage. In some cases, a lower off-current can be achieved by increasing the absolute value of Vb. If the absolute values ​​of g_1 and Vbg_2 are made too large, the on-current rise voltage will be high. This allows the transistor to operate at a low circuit voltage. In transistor Ta_j, it is preferable to have a lower off-current compared to transistor Tb_j. Considering this, for example, if the absolute value of Vbg_1 is greater than the absolute value of Vbg_2 Good. In this way, by making the absolute values ​​of Vbg_1 and Vbg_2 different, half This improves the retention characteristics of conductor devices and reduces power consumption. Furthermore, it improves the movement of semiconductor devices. The production speed can be increased.

[0132] The semiconductor layer 101j may be formed as a single layer, and as shown in the example in Figure 7, Formed in a stacked structure of body layer 101j_a, semiconductor layer 101j_b, and semiconductor layer 101j_c. It may also be done. Similarly, the semiconductor layer 201j may be formed as a single layer, and the semiconductor layer 20 It is formed in a stacked structure of semiconductor layer 1j_a, semiconductor layer 201j_b, and semiconductor layer 201j_c. That's fine.

[0133] Similar to the barrier film 111, the insulating film 112j can be made of a material that does not easily allow water or hydrogen to diffuse. It is preferable. In particular, it is preferable to use a material that does not easily permeate oxygen as the insulating film 112j. It is fine. Furthermore, the insulating film 112j may be arranged in a stacked structure of two or more layers. In that case, for example... For example, the insulating film 112j is made into a two-layer stacked structure, with the lower layer being, for example, silicon oxide and silicon oxide nitride. silicon nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, nitride acid Aluminum oxide, aluminum nitride, etc. can be used. Also, a barrier film 111 is used on the upper layer. Similarly, it is preferable to use a material that does not easily diffuse water or hydrogen. Furthermore, the insulating film provided in the lower layer is Similar to insulating film 114j, gate insulating film 102 is an insulating film that desorbs oxygen upon heating. Alternatively, oxygen may be supplied from above the semiconductor layer 101j via j.

[0134] By covering the semiconductor layer 101j with an insulating film 112j containing an oxygen-impermeable material, the semiconductor This suppresses the release of oxygen from the body layer 101j above the insulating film 112j. Furthermore, the oxygen detached from the insulating film 114j is trapped below the insulating film 112j. This allows for an increase in the amount of oxygen that can be supplied to the semiconductor layer 101j. .

[0135] Furthermore, the insulating film 112j, which is impermeable to water and hydrogen, prevents external access to the oxide semiconductor. This suppresses the inclusion of impurities such as water and hydrogen, and improves the electrical characteristics of the transistor Ta_j. This suppresses fluctuations and enables the creation of highly reliable transistors.

[0136] Furthermore, below insulating film 112j, oxygen is desorbed by heating, similar to insulating film 114j. An insulating film is provided, and oxygen is also supplied from above the semiconductor layer 101j via the gate insulating film 102j. It may also be supplied in this configuration.

[0137] For the insulating film 212j on transistor Tb_j, refer to the description of insulating film 112j. That's all you need to do.

[0138] As shown in Figure 7(A), the side surface of the semiconductor layer 101j_b of transistor Ta_j is It is in contact with the electrolytic layer 104j_a and the conductive layer 104j_b. Also, the electric field of the gate electrode 103j. This allows the semiconductor layer 101j_b to be electrically surrounded (by the electric field of the conductor). The structure of a transistor, which electrically surrounds a semiconductor, is called a surrounded chan This is called a nel (s-channel) structure. Therefore, the entire semiconductor layer 101j_b Channels may form in the (bulk). In s-channel structures, transients It is possible to pass a large current between the source and drain of the tube, and the current when conducting (on current) is high. It is possible.

[0139] Because it provides a high on-current, the s-channel structure is used in miniaturized transistors. This structure is suitable for [the purpose]. Because the transistor can be miniaturized, semiconductors having the transistor The device can be made into a highly integrated, high-density semiconductor device. For example, The transistor preferably has a channel length of 40 nm or less, and more preferably 30 nm or less. More preferably, it has a region of 20 nm or less, and the transistor has a preferred channel width. or a region of 40 nm or less, more preferably 30 nm or less, and more preferably 20 nm or less. It has a region.

[0140] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the gate electrode overlaps with the part of the semiconductor through which current flows when the inverter is ON. Source (source region or source electrode) in the region where a region or channel is formed. This refers to the distance between the drain (drain region or drain electrode). In a transistor, the channel length is not necessarily the same across all regions. That is, one The channel length of a transistor may not be fixed to a single value. Therefore, in this specification... The channel length is any one value, maximum value, or minimum value in the region where the channel is formed. Use the value or average.

[0141] Channel width refers to, for example, the width of a semiconductor (or transistor) when it is in the ON state. In the region where the current flows (the part) and the gate electrode overlap, or in the region where the channel is formed This refers to the length of the section where the source and drain are facing each other in a single transistor. In a zista, the channel width is not necessarily the same across all regions. That is, one The channel width of a transistor may not be fixed to a single value. Therefore, in this specification... The channel width is any one value, maximum value, or minimum value in the region where the channel is formed. Use the value or average.

[0142] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is the top surface of the transistor. The apparent channel width shown in the figure becomes larger, and its effect cannot be ignored. In some cases, this may occur. For example, in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor The proportion of channel regions formed on the semiconductor surface is compared to the proportion of channel regions formed on the semiconductor surface. The sum may become larger. In that case, the apparent channel width shown in the top view The effective channel width that is actually formed is larger than the theoretical width.

[0143] By the way, in transistors with a three-dimensional structure, the effective channel width is Estimation by measurement can sometimes be difficult. For example, it can be difficult to determine the effective channel width from the design value. For accumulation to occur, it is necessary to assume that the shape of the semiconductor is known. Therefore, the shape of the semiconductor When the exact condition is unknown, it is difficult to accurately measure the effective channel width. .

[0144] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent length of the portion where the source and drain face each other in the region. Channel width is defined as "Surrounded Channel Width (SCW)". It is sometimes referred to as "Width." Also, in this specification, when simply referred to as "channel width," This may refer to the enclosed channel width or the apparent channel width. Or, the true meaning In the detailed documentation, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, and enclosure are also included. Channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. The value can be determined.

[0145] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine the value. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The result may differ from the value obtained when calculating using the channel width.

[0146] Semiconductor layer 101j and semiconductor layer 201j have a larger energy gap than silicon. It is preferable that the semiconductor is included. Preferably, the semiconductor layer 101j contains an oxide semiconductor. This is achieved. Semiconductors have a wider energy gap and lower carrier density than silicon. Using this material is preferable because it can reduce the current when the transistor is off.

[0147] By using such materials as semiconductor layers, fluctuations in electrical properties are suppressed, and reliability is improved. High transistors can be achieved.

[0148] Furthermore, regarding preferred forms of oxide semiconductors applicable to semiconductor layers and methods for forming them, This will be explained in detail in a later embodiment.

[0149] In this specification, when we refer to something as substantially intrinsic, the carrier density of the oxide semiconductor layer is , 1 x 10 17 / cm 3 Less than 1 × 10 15 / cm 3 Less than 1 × 10 13 / cm 3 less than, 8×10 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than, or 1 × 10⁻⁶ 10 / cm 3 Not yet It is full, 1 x 10 -9 / cm 3 That concludes the explanation. By making the oxide semiconductor layer highly pure and intrinsic... This allows for the provision of stable electrical characteristics to the transistor.

[0150] For semiconductor layer 101j_b, for example, In:Ga:Zn=1:1:1, 2:1:3, 3 When using In-Ga-Zn oxides with an atomic ratio of 1:2 or 4:2:3, semiconductors For example, as body layer 101j_a or semiconductor layer 101j_c, In:Ga:Zn=1:3 : 2, 1:3:4, 1:3:6, 1:6:4, 1:6:8, 1:6:10, 1:9:6, An In-Ga-Zn oxide with an atomic ratio such as 1:2:3 can also be used. In addition, the atomic ratios of the semiconductor layer 101j_b, the semiconductor layer 101j_a, and the semiconductor layer 101j_c each include a variation of plus or minus 20% of the above atomic ratio as an error. Also, the semiconductor layer 101j_a and the semiconductor layer 101j_c may use materials with the same composition or materials with different compositions.

[0151] When an In-M-Zn oxide is used as the semiconductor layer 101j_b, the target used to form the semiconductor film that becomes the semiconductor layer 101j_b has an atomic ratio of the metal elements contained in the target of In:M:Zn = x1:y1:z1. When this is the case, the value of x1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and it is preferable to use an oxide with an atomic ratio of z1 / y1 being 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. By setting z1 / y1 to 6 or less, the CAAC-OS film described later is likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 2:1:3, 3:1:2, etc.

[0152] In addition, when an In-M-Zn oxide is used as the semiconductor layer 101j_a and the semiconductor layer 101j_c, the target used to form the semiconductor films that become the semiconductor layer 101j_a and the semiconductor layer 101j_c has an atomic ratio of the metal elements contained in the target of In:M:Zn = x2:y2:z2. When this is the case, x2 / y2 < x1 / y1, and it is preferable to use an oxide with an atomic ratio of z2 / y2 being 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. <00已1259> ​​​​​​​​​​​​​Furthermore, by setting z2 / y2 to 6 or less, the CAAC-OS film described later becomes easier to form. A typical example of the atomic ratio of the target metal elements is In:M:Zn=1:3:4. Examples include 1:3:6 and 1:3:8.

[0153] When depositing oxide semiconductors using the sputtering method, the atomic ratio of the target material deviates from the target material. In some cases, a film with a specific atom ratio may be formed. In particular, zinc can form a film with a higher atom ratio than the target. The atom ratio may become smaller. Specifically, the atom ratio of zinc contained in the target may decrease by 4. The atomic percentage may be between 0% and approximately 90%.

[0154] Conductive layer 104j_a and conductive layer 104j_b are made of aluminum, titanium, chromium, and nickel. Tungsten, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten A metal consisting of this material, or an alloy with this material as the main component, is used as a single-layer or layered structure. For example, a single-layer structure of an aluminum film containing silicon, or a laminated aluminum film on a titanium film. A two-layer structure, a two-layer structure in which an aluminum film is laminated on a tungsten film, copper-magnesium Two-layer structure with a copper film laminated on an aluminum alloy film, and two-layer structure with a copper film laminated on a titanium film. Structure, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and An aluminum film or copper film is laminated on top of a titanium film or titanium nitride film, and further... A three-layer structure in which a titanium film or titanium nitride film is formed on top of a molybdenum film or molybdenum nitride film. A molybdenum film, and an aluminum film or copper film layered on top of the molybdenum film or molybdenum nitride film. A three-layer structure in which a film is stacked and then a molybdenum film or molybdenum nitride film is formed on top of it, etc. There are also transparent conductive materials containing indium oxide, tin oxide, or zinc oxide. stomach.

[0155] The gate insulating film 102j is, for example, silicon oxide, silicon oxide nitride, or silicon oxide nitride. , aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn metal oxides, nitrogen Silicone or similar materials can be used, and they can be provided in a laminated or single-layer configuration.

[0156] Furthermore, as the gate insulating film 102j, hafnium silicate (HfSiO x ), nitrogen Added hafnium silicate (HfSi x O y N z ), nitrogen-added hafnium Aluminate (HfAl x O y N z ), using high-k materials such as yttrium oxide That's fine.

[0157] Furthermore, as the gate insulating film 102j, aluminum oxide, magnesium oxide, silicate Cone, silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, gallium oxide Acids such as lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide silicon nitride insulating film, silicon nitride, silicon oxide nitride, aluminum nitride, aluminum oxide nitride It can be formed using nitride insulating films such as 'mu', or mixtures thereof.

[0158] Furthermore, the gate insulating film 102j satisfies the same stoichiometric composition as insulating film 114j. It is preferable to use an oxide insulating film that contains more oxygen than the amount of oxygen present.

[0159] Furthermore, using certain materials as gate insulating films can trap electrons in the gate insulating film under specific conditions. This can also increase the threshold voltage. For example, silicon oxide and hafni oxide Like a multilayer film of aluminum, a portion of the gate insulating film contains hafnium oxide, aluminum oxide, and oxide Using materials with many electron trapping levels, such as tantalum, allows for higher temperatures (semiconductor operating temperature). Alternatively, temperatures higher than the storage temperature, or between 125°C and 450°C, typically 1 Under temperatures between 50°C and 300°C, the potential of the gate electrode is the same as the potential of the source electrode and the drain electrode. By maintaining a higher state for more than one second, typically more than one minute, the gate electricity from the semiconductor layer is released. Electrons move toward the poles, and some of them are trapped in electron trapping levels.

[0160] In this way, a transistor that has captured the necessary amount of electrons to reach the electron trapping level will have a threshold voltage This shifts to the positive side. The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows for the control of the threshold voltage. Furthermore, it allows for the capture of electrons. The melting process can be performed during the transistor manufacturing process.

[0161] For example, the formation of wiring metal connected to the source or drain electrode of a transistor. Afterwards, or after the completion of the preceding process (wafer processing), or after the wafer dicing process. It is best to do this at some stage before the product leaves the factory, such as after packaging. It is preferable that the product is not subsequently exposed to temperatures above 125°C for more than one hour.

[0162] The gate electrode 103j is made of, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum. A metal selected from den, tungsten, or an alloy containing the above metals, or as described above. It can be formed using alloys that combine various metals. In addition, manganese, zirconium One or more metals selected from the um group may be used. Also, impurities such as phosphorus may be removed. Semiconductors such as polycrystalline silicon doped with elements, and silicon such as nickel silicide Sides may also be used. Also, the gate electrode 103j may be a single layer structure or a stacked structure of two or more layers. It may also be called a structure. For example, a single layer structure of an aluminum film containing silicon, on an aluminum film A two-layer structure in which a titanium film is laminated on top of a titanium nitride film, a two-layer structure in which a titanium film is laminated on top of a titanium nitride film, A two-layer structure consisting of a tungsten film laminated on a tungsten film, tantalum nitride film, or tungsten nitride. A two-layer structure with a tungsten film laminated on top of a film, a titanium film, and aluminum on top of the titanium film. There are also three-layer structures, such as one in which a film is stacked and then a titanium film is formed on top of it. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A combination of one or more selected alloy films, or a nitride film, may be used.

[0163] Furthermore, gate electrode 103j contains indium tin oxide and tungsten oxide. Indium oxide, indium zinc oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Oxides, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide It is also possible to apply transparent conductive materials such as added indium tin oxide. Alternatively, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal can be used.

[0164] Furthermore, the conductive layer 105j can be made of the same material as the gate electrode 103j.

[0165] Furthermore, between the gate electrode 103j and the gate insulating film 102j, an In-Ga-Zn oxynitriding material is used. Monocrystalline semiconductor films, In-Sn-based oxynitride semiconductor films, In-Ga-based oxynitride semiconductor films, In-Z n-based oxynitride semiconductor films, Sn-based oxynitride semiconductor films, In-based oxynitride semiconductor films, metal nitride films (InN, ZnN, etc.) may be provided. These films should have a thickness of 5eV or more, preferably 5.5eV. It has a work function greater than V, and is greater than the electron affinity of oxide semiconductors, therefore oxide It is possible to shift the threshold voltage of a semiconductor transistor to a positive value, so-called no Switching elements with Marie-off characteristics can be realized. For example, In-Ga-Zn oxynitride When using a semiconductor film, the nitrogen concentration must be at least higher than that of the semiconductor layer 101j, specifically 7 ions. A 1% or higher In-Ga-Zn oxynitride semiconductor film is used.

[0166] Note that the configuration shown in Figure 7(A) is the edge of the gate insulating film 102j and semiconductor layer 101j_c They are processed to roughly match, and the gate electrode 103j is located inside the gate insulating film. An example of processing to this extent is shown, but the gate insulating film 102j, semiconductor layer 101j_c and gate The ends of the gate electrode 103j may be machined to roughly coincide. Alternatively, gate insulation The edges of film 102j, semiconductor layer 101j_c, and gate electrode are aligned so that they do not coincide. It can also be used in processing.

[0167] Furthermore, Figure 1 shows examples of different structures of transistors Ta_j and Tb_j. This will be briefly explained using Figures 8(D), 18(E), 19(D), and 19(E). This section explains transistor Ta_j, but the same applies to transistor Tb_j. Such a structure can be used.

[0168] When forming semiconductor layer 101j_a and semiconductor layer 101j_b, the conductive film 104 is formed After forming, a resist mask is formed, and the conductive film 104 is etched, and then the semiconductor layer 101 The semiconductor layer designated as j_a and the semiconductor layer designated as semiconductor layer 101j_b are shaped by etching. The conductive film 104 is then processed again to create the conductive layer 104j_a and the conductive layer 104j_ b can be formed, resulting in a structure as shown in Figure 18(D).

[0169] Furthermore, the semiconductor layer 101j_c is connected to the conductive layer 104j_a and the conductive layer as shown in Figure 18(E). It may be provided in contact with the lower surface of the electrode layer 104j_b. With this configuration, The semiconductor layer 101j_a, semiconductor layer 101j_b, and semiconductor layer 101j_c During the deposition of each film, it is possible to deposit the film continuously without exposing it to the atmosphere. Therefore, the interface defects can be reduced.

[0170] Furthermore, the transistor Ta_j may have the structure shown in Figure 19(D). Figure 19(D) In the example shown, an opening is made in the insulating film 116j to form a plug, and the source electrode and drain It is used as an electrode. Also, transistor Ta_j has an insulating film 112 under insulating film 116j. It may also have j and an insulating film 113j.

[0171] Furthermore, as shown in Figure 19(E), a low-resistance region may be provided in the semiconductor layer 101j. After forming a semiconductor film that will become a semiconductor layer 101j on an insulating film 114j, a resist mask, etc. Formation is performed, etching is carried out to form the semiconductor layer 101j. Next, the gate insulating film 102j An insulating film and a conductive film that will become the gate electrode 103j are formed, and a resist mask and the like are formed. Then, etching is performed to form the gate electrode 103j and the gate insulating film 102j.

[0172] Next, low-resistance regions 171j_a and 171j_b are formed. A semiconductor layer with a high degree of purity will have lower resistance. One way to increase carrier density is, for example, impurities. Examples include the addition of substances and the formation of oxygen deficiencies. For example, as a way to increase carrier density, Elements can be added using ion implantation. Examples of elements that can be used include, for example, A Lugon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, s Candium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, galvanic Germanium, arsenic, yttrium, zirconium, niobium, molybdenum, indigo Choose from tungsten, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. It is preferable to add one or more selected substances. Low resistance region 171j_a and low resistance region For example, 171j_b contains 5 × 10⁻¹⁰ of the aforementioned impurity elements in the semiconductor layer 101j. 19 ato ms / cm 3 Preferably 1 × 10 20 atoms / cm 3 More preferably 2 x 10 20 atoms / cm 3 The above is more comfortable 5x10 20 atoms / cm 3 This area includes the above.

[0173] Such low-resistance regions may, for example, trap unwanted hydrogen. Yes. By trapping unwanted hydrogen in a low-resistance layer, the hydrogen concentration in the channel region can be reduced. Therefore, good characteristics can be obtained for the transistor Ta_j.

[0174] Furthermore, in the transistor examples shown in Figures 7, 18, and 19, the semiconductor layer 101j_b Although a configuration in which semiconductor layers 101j_a and 101j_c are provided in contact with the other layer has been described, Configuration without one or both of the conductive layer 101j_a and / or the semiconductor layer 101j_c. That is also acceptable.

[0175] The above is a description of transistors Ta_j and Tb_j.

[0176] The insulating film 116j covering the transistor Ta_j provides planarization to cover the uneven shape of the underlying layer. It functions as a layer. In addition, insulating film 113j acts as a protective film when insulating film 116j is deposited. It may have the function of [this]. The insulating film 113j may be omitted if it is not needed.

[0177] Similarly, the insulating film 216j covering the transistor Tb_j covers the uneven shape of the underlying layer. It functions as a planarization layer. In addition, insulating film 213j protects when insulating film 216j is deposited. It may have the function of a film. The insulating film 213j may be omitted if it is not needed.

[0178] Furthermore, regarding the insulating film 156j covering the capacitive element Ca_j, for example, the insulating film 116j is described Please refer to the information provided.

[0179] Insulating film 112j, insulating film 113j, and insulating film 116j contain conductive layer 104j_a, etc. Plugs such as the 147j for electrical connection are embedded within.

[0180] Furthermore, the insulating film 212j, insulating film 213j, and insulating film 216j have a gate electrode 203j Plugs such as 141j, which are electrically connected to conductive layers such as 151j, are embedded within the structure.

[0181] Furthermore, as shown in Figure 6, a material similar to the barrier film 111 is applied to the hydrogen-containing insulating film 136. A configuration including an insulating film 137 is also possible. With such a configuration, hydrogen is included This effectively suppresses the upward diffusion of water and hydrogen remaining in the insulating film 136. In this case, before forming the insulating film 137 and after forming the insulating film 137, the barrier Prior to forming the film 111, a total of two or more heat treatments were performed to remove water and hydrogen. That's fine.

[0182] Plugs 141j to 148j, conductive layers 151j to 154j, etc. are made of Conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used. In particular, high-melting-point materials such as tungsten and molybdenum that offer both heat resistance and conductivity are used. It is preferable to use titanium nitride or titanium Materials such as titanium can be used in lamination with other materials. For example, titanium nitride or titanium can be used. This improves the airtightness to the opening. Also, plug 141j or plug The lugs 148j, conductive layers 151j to 154j, etc., are configured to be embedded in the insulating film. It is preferable that the top surfaces of each part are flattened.

[0183] By repeatedly stacking oxide semiconductor layers on transistors Ta_j and Tb_j By forming a semiconductor layer, a sub-memory of the c-layer is created, as shown in Figures 1(A) and 6. It becomes possible to stack cells SCL. Therefore, the capacity per unit area can be increased. ru.

[0184] Conventional transistors using silicon, germanium, and their compounds are particularly fine. In elements with a long channel length, the gate electric field is strengthened to suppress the short-channel effect. It is preferable that the gate insulating film be made thinner in order to strengthen the gate electric field.

[0185] On the other hand, transistors using oxide semiconductor films are storage-type transistors that use electrons as the majority carriers. It is a transistor. Therefore, it has a shorter channel compared to an inverting transistor with a pn junction. One of the effects is DIBL (Drain-Induced Barrier Lowering). The effect of (ing) is small. Transistors using oxide semiconductor films are resistant to short-channel effects. This can also be rephrased as having resistance to it.

[0186] Because of their high resistance to short-channel effects, transistors using oxide semiconductor films This makes it possible to make the gate insulating film thicker than in conventional transistors using silicon, etc. For example, even in a minute transistor with a channel length and channel width of 50 nm or less, 1 A gate insulating film with a thickness of about 0 nm may be used. Here, by increasing the thickness of the gate insulating film... This allows for a further reduction in parasitic capacitance, which can sometimes improve the dynamic characteristics of the circuit. Furthermore, by increasing the thickness of the gate insulating film, leakage current can be reduced, and power consumption can be lowered. There is a match.

[0187] Furthermore, as the channel length is miniaturized, the drain electric field strengthens, so silicon and other materials are used. In conventional transistors, hot carriers are particularly problematic when the channel length is very short. The decrease in reliability due to degradation becomes more pronounced. On the other hand, in oxide semiconductors, the energy gap Large (for example, in oxide semiconductors containing indium, gallium, and zinc, 2.5 eV or less) (Above) Because electrons are not easily excited and the effective mass of holes is large, conventional Compared to transistors using recon technology, avalanche decay and other issues may be less likely to occur. Therefore, for example, it may be possible to suppress hot carrier degradation caused by avalanche collapse. be.

[0188] By increasing the thickness of the gate insulating film, the breakdown voltage of the gate insulating film can be increased, resulting in a higher The transistor can be driven by the gate voltage. Furthermore, hot carrier degradation is suppressed. This allows the transistor to be driven with a high drain voltage without increasing the channel length. This allows for improved transistor reliability in circuits where high voltages are input. This allows for a reduction in channel length, thereby increasing the integration density of the circuit. ru.

[0189] Furthermore, in transistors using intrinsic or substantially intrinsic oxide semiconductor films, the source power When the distance between the pole and drain electrodes is sufficiently small, the influence of the source and drain electric fields is reduced. This lowers the energy at the bottom of the conduction band, bringing the energy of the conduction band closer to the Fermi level. This phenomenon is called the Conduction Band Lowering Effect. This is called the CBL effect. Due to the CBL effect, the low voltage near 0V in the Vg-Id characteristic Lowering the transistor's drive voltage is necessary because drain current begins to flow from the drive voltage. It is sometimes possible.

[0190] Here, it is preferable to use a CAAC-OS film as the oxide semiconductor film. A high CAAC ratio in the OS film is preferable. By increasing the CAAC ratio, for example, This reduces the effects of carrier scattering in transistors and allows for high field-effect mobility. This is possible. Also, the influence of grain boundaries can be reduced, so the transistor This reduces variations in on-state characteristics, thus enabling the creation of highly reliable semiconductor devices. This can be done. Furthermore, by using transistors with small variations, the drive voltage can be reduced. Furthermore, power consumption can be reduced. Also, for example, a CAAC-OS film with a low defect density can be used. This can be achieved. Furthermore, it is possible to create CAAC-OS films with fewer impurities. By reducing defect density, for example, extremely low off-current characteristics can be achieved. The CAAC-OS membrane will be discussed later.

[0191] Here, the semiconductor layer 101j_b of transistor Ta_j and transistor Tb_ The semiconductor layer 201j_b of j may be formed from a different material. For example, semiconductor layer 10 When using In-M-Zn oxide for 1j_b and semiconductor layer 201j_b, indium, Materials with different atomic ratios of element M and zinc may be used.

[0192] Furthermore, transistors Ta_j and Tb_j are transistors with different structures. It may be used. Also, the channel widths of transistors Ta_j and Tb_j are They may be different. Similarly, the channels of transistor Ta_j and transistor Tb_j The lengths of the 'ru's can be different for each.

[0193] Furthermore, the semiconductor layer 101j of transistor Ta_j and the transistor Tb_j The semiconductor layer 201j has an oxide semiconductor containing In, an element represented by M, and Zn. It is preferable to do so. The number of atoms of In, M, and Zn in the oxide semiconductor of the semiconductor layer 101j The ratio satisfies In:M:Zn=a:b:c, and the oxide semiconductor possessed by semiconductor layer 201j This explanation will cover the case where the ratio of the number of atoms of In, M, and Zn satisfies In:M:Zn = d:e:f. Here, for example, it is preferable that a / (a+b+c) is smaller than d / (d+e+f). It is because increasing the indium content allows more s orbitals to overlap, thus increasing the indium content. Oxides with a high indium content exhibit higher mobility compared to oxides with a low indium content. Therefore, by using an oxide with a high indium content in the oxide semiconductor film, Carrier mobility can be increased. On the other hand, reducing the indium content can lead to off This may allow for a lower current, which is preferable.

[0194] [Example of a layered structure 2] Furthermore, the stacked structure shown in Figure 8 is an example of a stacked structure for a semiconductor device that differs from that shown in Figure 6. The semiconductor device shown in 8 has a memory cell array 300 and peripheral circuits 500. 8 indicates stacking up to j=4, but in reality, submemory cells with j=5 or higher can also be stacked. Furthermore, a larger number of stacks allows for a higher degree of memory integration, which is therefore preferable. (See Figure 8) For example, see Figure 4 for the circuit diagram of the memory cell array 300 shown. Here, in Figure 8 To make the diagram easier to understand, some parts of the film interface, etc., have been omitted.

[0195] Here, layer 291 shown in Figure 8 has a transistor. Also, layer 292 and shown in Figure 8 Layer 293 has a conductive layer. Also, layer 294, shown in Figure 8, has a transistor. Layers 295 and 296 shown in Figure 8 have conductive layers. Each top view is shown in Figure 10.

[0196] Figure 6 shows transistor, capacitive element, transistor, transistor, capacitive element, transistor In contrast to the stacking of zistas in order, Figure 8 shows that the submemory cells are arranged alternately. Therefore, the transistors and capacitive elements are stacked in the order of transistor, capacitive element, transistor, and capacitive element. The process can be simplified.

[0197] Figure 9 is an enlarged view of a portion of Figure 8. A capacitive element Ca is located above the transistor Tb_j. _j is provided. In addition, at least a portion of the capacitive element Ca_j is transistor Tb It is preferable that it be provided so as to overlap with _j. Also, a portion of the capacitive element Ca_j is adjacent The submemory cells may be positioned to overlap with the transistors they have. (See Figure 9) For example, the capacitive element Ca_3 in the submemory cell SCL_3 is a submemory cell It is positioned so as to overlap with transistor Ta_2 of SCL_2, and memory cell A This allows for increased integration density of Ray300.

[0198] Furthermore, submemory cells SCL_2 and SCL_3 are paired left and right in Figure 9. It has a specific structure. By adopting this structure, the submemory cells are arranged in an alternating pattern. It is possible to form a capacitive element on the transistor of an adjacent submemory cell. This allows for increased density. Also, by arranging them alternately, compared to Figure 6, This simplifies the process. In other words, the submembrane cells stacked vertically are the same It has transistors formed in the same layer. More specifically, for example, a submemory cell SCL The transistor Ta_j(j=m-1) possessed by _j(j=m-1) and the submemory cell S The transistor Tb_j(j=m) possessed by CL_j(j=m) is formed in the same layer. That is, for example, transistor Ta_j (j=m-1) and transistor Tb_j (j= m) is formed in contact with the first insulating film. That is, for example, transistor Ta_j( The semiconductor layer 101j (j=m-1) of j=m-1 and the transistor Tb_j (j= The semiconductor layer 201j (j=m) of m) is formed in contact with the first insulating film. The memory cell array 300 consists of semiconductor layer 101j (j=m-1) and semiconductor layer 201j ( It has a first insulating film in contact with the transistor Ta_j(j=m). Alternatively, for example, transistor Ta_j(j=m -1) has gate electrode 103j (j=m-1) and transistor Tb_j (j=m A second insulating film is formed so as to be in contact with the gate electrode 203j (j=m) of the ). Alternatively, the memory cell array 300 has gate electrode 103j (j=m-1) and gate electrode 2 It has a second insulating film in contact with 03j (j=m), where m is a natural number greater than or equal to 2.

[0199] In this way, some of the transistors in the vertically adjacent submemory cells are in the same layer. This allows the memory cell array 300 to be fabricated in fewer steps. By manufacturing with fewer steps, the yield can be increased. Also, when laminated... Because the number of layers can be reduced, the parasitic capacitance of the entire circuit can be reduced.

[0200] Furthermore, as the number of stacked layers increases, the properties of, for example, insulating films, conductive films, semiconductor films, etc. Due to the resulting film stress, delamination or cracking may occur. Therefore, the number of layers stacked... By reducing this, it is possible to reduce failures of semiconductor devices due to film peeling and other issues.

[0201] The conductive layer 151j, which is one of the terminals of the capacitive element Ca_j, is connected to the plug 141j. Electrically connect gate electrode 203j of transistor Tb_j.

[0202] A transistor Ta_j is placed on top of the capacitive element Ca_j. It is preferable that at least a portion of the element Ta_j overlaps with the capacitance element Ca_j. Here, the gate electrode 203j and the conductive layer 151j are plug 141j and plug 1 The conductor 44j acts as either the source or drain electrode of transistor Ta_j. It is electrically connected to the electrochemical layer 104j_b. The insulating film 115j of the capacitive element Ca_j is conductive It is sandwiched between the electrolytic layer 151j and the conductive layer 152j, forming a capacitance.

[0203] Conductive layer 204j functions as the source or drain electrode of transistor Tb_j _b is electrically connected to the source line SL.

[0204] Conductive layer 204j functions as the source or drain electrode of transistor Tb_j _a is the source electrode or drain electrode of transistor Ta_j via plug 142j, etc. It is electrically connected to the conductive layer 104j_a which functions as a pole. The conductive layer 104j_a is electrically connected to the bit line BL.

[0205] Furthermore, submemory cell SCL_j shares conductive layers and plugs with adjacent submemory cells. It is preferable to do so. For example, the transistor Tb_j of the submemory cell SCL_2 The conductive layer 204j_a, which functions as the source or drain electrode, is adjacent to the subme Shared with the source or drain electrode of transistor Ta_j of Morissel SC_1 Also, the source electrode or of the transistor Ta_j of the submemory cell SCL_2 The conductive layer 104j_a, which functions as a rain electrode, is a component of the submemory cell SCL_3. It is shared with the source or drain electrode of the transistor Tb_j. In this way the conductive layer By sharing, the integration density of the memory cell array 300 can be increased.

[0206] Furthermore, transistors 198 and 199 shown in Figure 8 are both sub-memories. This is a so-called dummy transistor, not even included in the cell. Therefore, transistor 198 And transistor 199 is generally considered unnecessary as a memory cell array. However, by providing transistors 198 and 199, Layer 299 can be created using the same mask as layer 294, etc. Therefore, the required number of cells This reduces the number of sheets required, leading to cost reductions. Furthermore, in the lithography process... Especially when forming fine patterns, changes in the distance between lines will affect the final line. The width and other dimensions may change. Therefore, a lithography process is used in the fabrication of the memory cell array 300. When used, layer 294 and layer 299 are formed using the same mask, for example Conditions such as the distance between patterns can be made common, and fine details can be made in layers 294 and 299. This is preferable because it makes it easier to form a pattern. Also, the semiconductor of the finished transistor This is preferable because it allows for the uniformity of the sizes of layers, conductive layers, gate electrodes, etc. Because the distance between transistors, between transistors and their wiring, and between wirings does not change significantly, This reduces variations in characteristics between sub-memories by making electric field interference, such as capacitance between wiring, more uniform. This may be possible. Note that the gates of transistors 198 and 199 The electrodes and conductive layers do not need to be connected to other transistors or wiring. In that case, they are unnecessary. The formation of plugs and wiring can be omitted. Also, although not shown in Figure 8, the memory cell A Similarly, it is preferable to provide a dummy transistor on the top layer of Ray 300.

[0207] Here, dummy transistors, transistor 198 and transistor 199, are written Input word line WWL, read word line RWL, bit line BL, floating node F It may be connected to part of the N and source line SL, or it may not be connected to any of them.

[0208] For example, dummy transistors such as transistor 198 and transistor 199 are It may be connected only to the source line SL, or to both the source line SL and the bit line BL. stomach.

[0209] Alternatively, for example, dummy transistors such as transistor 198 and transistor 199 are One terminal of the capacitive element is connected, and the other terminal of the capacitive element is connected to the write word line WWL. You don't have to continue.

[0210] Here, in Figure 8, for example, layers 299 and 294 have the same number of transistors. This is preferable. Alternatively, it is preferable to have transistors with substantially the same shape.

[0211] Alternatively, in Figure 8, for example, layer 299 and layer 294 may have the same number of semiconductor layers. Preferably, it is preferable to have a semiconductor layer with substantially the same shape.

[0212] Alternatively, in Figure 8, for example, layers 299 and 294 may have the same number of gate electrodes. This is preferable. Alternatively, it is preferable to have a gate electrode with substantially the same shape.

[0213] [Example 3 of a laminated structure] Furthermore, the stacked structure shown in Figure 11 is an example of a stacked structure for a semiconductor device that differs from those shown in Figures 6 and 8. Figure 11(A) shows a top view of the submemory cells of the memory cell array 300. Furthermore, Figure 11(B) shows the cross-sections A-A' and A'-B as shown in Figure 11(A), and Figure 11(C) shows the cross-section between B and B'. Figure 11(C) shows the cross-section between C and C' shown in Figure 11(A). The semiconductor device shown in Figure 11(B) has a memory cell array 300 and peripheral circuits 500. Note that Figure 11 shows stacking up to j=2, but in reality, submembrane cells with j=3 or more are used. It is preferable that these are stacked, and the more layers there are, the higher the memory integration density can be. Therefore, it is more preferable. The circuit diagram of the memory cell array 300 shown in Figure 8 is, for example, the same as Figure 1(B). Refer to.

[0214] In the structure shown in Figure 11(B), one terminal of the capacitive element Ca_j and the gate electrode 203j Because it can serve multiple purposes, the process can be simplified.

[0215] [Example 4 of a layered structure] Furthermore, the stacked structure shown in Figure 12 is a different stacked structure of a semiconductor device from those shown in Figures 6, 8, and 11. This is one example of a structure. Furthermore, the laminated structure shown in Figure 12 is a different laminated structure of a semiconductor device from that shown in Figure 6. This is one example. The semiconductor device shown in Figure 12 consists of a memory cell array 300 and peripheral circuits 500. It has the following. Note that Figure 12 shows stacking up to j=4, but in reality, there are sub-memories of j=5 or more. Cells can be stacked, and the more cells there are, the higher the memory integration density can be. More preferable. The circuit diagram of the memory cell array 300 shown in Figure 12 is, for example, shown in Figure 4. .

[0216] The memory cell array 300 shown in Figure 12 has submemory cells arranged in an alternating pattern. The points are the same as those in Figure 8. Submembrane cells SCL1 to submembrane cells shown in Figure 12 In SCL4, both SCL2 and SCL4 have semiconductor layer 101j of transistor Tb_j. The gate electrode 203j, also known as the bottom gate, located below the capacitive element Ca_j, is electrically connected to the bottom gate. The way the components are connected differs from other structures. Also, the stacking order of the two transistors and the capacitive element is different. Also, the capacitive element Ca_j is located on top of the transistor Ta_j, and the capacitor Ca_j is located on top of the transistor Ta_j. It differs from the other structures in that it is located where the lunger Tb_j is situated.

[0217] On the other hand, in SCL_1 and SCL_3, on the semiconductor layer 101j of transistor Tb_j The gate electrode 203j located there is electrically connected to the capacitive element Ca_j. Also, the two The stacking order of transistors and capacitive elements is such that the capacitive element Ca_j is positioned on top of the transistor Tb_j. The transistor Ta_j is positioned above the capacitive element Ca_j. This is the example shown in Figure 12. Therefore, the structure of the submemory cell SCL_j differs depending on whether j is odd or even. Also, see Figure 1. In the example shown in 2, it is necessary to form transistors Ta_j and Tb_j on the same layer. Without it, the semiconductor layer 101j of transistor Ta_j and the semiconductor layer of transistor Tb_j In the case where the semiconductor layer 201j is formed by oxide semiconductor layers with different constituent elements and atomic ratios, for example In this case, it is preferable because it is easy to manufacture.

[0218] The above is an explanation of the example configuration.

[0219] [Example of manufacturing method] In the following, an example of a method for manufacturing the semiconductor device shown in the above configuration example is described in Figures 13 to 1. I will explain using number 6.

[0220] First, prepare the semiconductor substrate 131. For example, the semiconductor substrate 131 can be a single-crystal silicon semiconductor substrates (including p-type or n-type semiconductor substrates), silicon carbide, and gallium nitride. Compound semiconductor substrates made of um can be used. SOI substrates may also be used. In the following, single-crystal silicon is used as the semiconductor substrate 131. This section explains the case using this method.

[0221] Next, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer is LOC OS (Local Oxidation of Silicon) method or STI (Sh If formed using methods such as the allow Trench Isolation method or the mesa separation method, good.

[0222] When forming p-type and n-type transistors on the same substrate, semiconductor substrate 1 n-wells or p-wells may be formed in part of 31. For example, n-type semiconductor substrate 13 By adding impurity elements such as boron that impart p-type conductivity to 1, a p-well is formed, and the same n-type transistors and p-type transistors may be formed on the substrate.

[0223] Next, an insulating film that will become a gate insulating film 134 is formed on the semiconductor substrate 131. For example, The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, an acid is removed by thermal oxidation. After forming silicon oxide, the surface of the silicon oxide film is nitrided by performing a nitriding treatment. By doing so, a laminated structure of a silicon oxide film and a silicon oxide-nitride film may be formed. These include silicon oxide, silicon oxynitride, and high-dielectric materials (also called high-k materials). Certain tantalum oxides, hafnium oxide, hafnium silicate oxide, zirconium oxide, Metal oxides such as aluminum oxide and titanium oxide, or rare earth oxides such as lanthanum oxide. You may use objects or other items.

[0224] The insulating film is produced by sputtering, CVD (Chemical Vapor Deposition). sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method (including PECVD (Plasma Enhanced CVD) method, MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition method, or PLD (Pulsed Laser Deposit) It may also be formed by depositing a film using methods such as the ion method.

[0225] Next, a conductive film to form the gate electrode 135 is deposited. The conductive film is made of tantalum, tan Metals selected from gusten, titanium, molybdenum, chromium, niobium, etc., or these It is preferable to use alloy materials or compound materials that have metal as the main component. Also, phosphorus, etc. Polycrystalline silicon with added impurities can be used. In addition, a metal nitride film and the above A layered structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. Titanium nitride can be used. By providing a metal nitride film, the density of the metal film can be increased. Adhesion can be improved, and peeling can be prevented.

[0226] Conductive films are produced by sputtering, evaporation, and CVD (thermal CVD, MOCVD, PEC). The film can be deposited using methods such as the VD method. For this purpose, thermal CVD, MOCVD, or ALD methods are preferred.

[0227] Next, a resist mask is formed on the conductive film using a lithography method or the like, and the conductive Remove the unnecessary parts of the film. Then, remove the resist mask to create the gate electrode. 135 can be formed.

[0228] Here, we will explain the processing method for the film to be processed. When processing the film to be processed finely, Various microfabrication techniques can be used. For example, formed by photolithography, etc. A method of performing a slimming process on the resist mask may also be used. A dummy pattern was formed using a roughing method, and sidewalls were then formed on the dummy pattern. Later, the dummy pattern is removed, and the remaining sidewall is used as a resist mask. The film to be processed may be etched. Furthermore, as an etching method for the film to be processed, a high aspect ratio may be used. To achieve this, it is preferable to use anisotropic dry etching. Furthermore, inorganic films Alternatively, a hard mask made of a metal film may be used.

[0229] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) and g-line (wavelength 43 nm). Light can be used that emits 6nm light, h-line light (wavelength 405nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, or ArF laser light can also be used. Alternatively, exposure may be performed using immersion lithography. Furthermore, the light used for exposure may be extreme ultraviolet light. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Alternatively, an electron beam can be used instead of the light used for exposure. Extreme ultraviolet light, X-rays or Using an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam, such as those mentioned above, a photomask is not required.

[0230] Furthermore, before forming the resist film that will serve as the resist mask, the tightness between the film to be processed and the resist film is An organic resin film having a function to improve adhesion may be formed. The organic resin film may be, for example, made of s The surface is formed by covering the steps in the underlying layer using methods such as pin coating to create a flat surface. This allows for the reduction of variations in the thickness of the resist mask provided on the upper layer of the organic resin film. It is possible. Furthermore, when performing particularly fine processing, the organic resin film is made resistant to the light used for exposure. It is preferable to use a material that functions as an anti-reflective coating. Examples of resin films include BARC (Bottom Anti-Reflection). This includes coating films, etc. This organic resin film is removed at the same time as the resist mask is removed. Alternatively, you can remove it after removing the resist mask.

[0231] After the gate electrode 135 is formed, a side wall is formed to cover the side of the gate electrode 135. Alternatively, the sidewall may be formed by depositing an insulating film thicker than the thickness of the gate electrode 135. Anisotropic etching is performed, leaving the insulating film only on the side portion of the gate electrode 135. It can be formed by [this method].

[0232] Figure 13 shows an example where the gate insulating film is not etched during sidewall formation. However, when the sidewall is formed, the insulating film that becomes the gate insulating film 134 is also etched at the same time. Alternatively, the gate insulating film 134 is located at the bottom of the gate electrode 135 and the sidewall. It is formed.

[0233] Next, the gate electrode 135 (and sidewall) of the semiconductor substrate 131 is provided. An element that imparts n-type conductivity, such as phosphorus, or a p-type conductivity, such as boron, to a region where there is no conductivity. The elements to be added are then added. A schematic cross-sectional view at this stage corresponds to Figure 13(A).

[0234] Next, after forming the insulating film 136, the elements that impart conductivity as described above are activated. The first heat treatment is performed.

[0235] The insulating film 136 is, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride Recon, aluminum oxide, aluminum oxide nitride, aluminum nitride A material such as nium may be used, and it can be provided in a multilayer or single layer. The insulating film 136 is formed by sputtering. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, it can be formed using methods such as PLD. In particular, the insulating film can be formed by CVD, preferably... Alternatively, deposition by plasma CVD is preferred because it can improve coverage. Furthermore, to reduce damage caused by plasma, thermal CVD, MOCVD, or A The LD method is preferred.

[0236] The first heat treatment is performed under an inert gas atmosphere such as a noble gas or nitrogen gas, or under a reduced pressure atmosphere. For example, this can be done at temperatures above 400°C but below the substrate's strain point.

[0237] At this stage, transistors 130a, 130b, 230a and Transistor 230b is formed.

[0238] Next, insulating film 137 is formed to obtain the cross-section shown in Figure 13(A). Then, insulating film 138 is formed. To form.

[0239] The insulating film 137 is made of materials that can be used for the insulating film 136, as well as nitrogen containing oxygen and hydrogen. Using silicon dioxide (SiNOH) increases the amount of hydrogen that is desorbed by heating. This is preferable because it allows for this. Also, the insulating film 138 is a material that can be used for the insulating film 136. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or A silica oxide with good step-coating properties formed by reacting silane or the like with oxygen or nitrous oxide. It is preferable to use an element.

[0240] Insulating film 137 and insulating film 138 are, for example, produced by sputtering, CVD (thermal CVD), Using methods such as MOCVD, PECVD, MBE, ALD, or PLD It can be formed by a CVD method, preferably a plasma CVD method. Therefore, forming a film is preferable because it can improve coverage. To reduce damage, thermal CVD, MOCVD, or ALD methods are preferred.

[0241] Next, the upper surface of the insulating film 138 is planarized using the CMP method or the like. A planarized film may also be used. In that case, planarization by CMP or similar methods is not necessarily required. For the formation of the planarized film, methods such as atmospheric pressure CVD or coating can be used. Examples of films that can be formed using the VD method include BPSG (Boron Phosphor). Examples include (us Silicate Glass), etc. Furthermore, it can be formed using a coating method. Examples of suitable membranes include HSQ (hydrogen silsesquioxane).

[0242] Subsequently, the dangling bonds in the semiconductor layer 132 are detached from the insulating film 137 by hydrogen. A second heat treatment is performed to terminate the process. In addition, the second heat treatment is performed to contain in each layer By removing the water and hydrogen that are present, the water and hydrogen content can be reduced.

[0243] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. For example, The conditions described in section 1 (heat treatment) can be used.

[0244] Next, a barrier film 111 is formed. The barrier film 111 is formed by, for example, sputtering, CV Method D (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or It can be formed using methods such as the PLD method. In particular, the insulating film can be formed by the CVD method, preferably Plasma CVD is preferred for film deposition because it can improve coverage. Furthermore, to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. It is preferable.

[0245] Next, conductive films such as conductive layer 105j and conductive layer 153j are formed on the barrier film 111. The formation of conductive films such as conductive layer 105j and conductive layer 153j can be done, for example, by sputtering. CVD methods (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method Alternatively, it can be formed using methods such as PLD. In particular, the insulating film can be formed by CVD, preferably Plasma CVD is preferred because it can improve the coverage when the film is deposited. Furthermore, to reduce damage caused by plasma, thermal CVD, MOCVD, or AL can be used. Method D is preferred.

[0246] Next, a resist mask is formed, and the conductive film, which will be the conductive layer 105j, conductive layer 153j, etc. The essential parts are removed by etching. Then the resist mask is removed, and the conductive layer 105j This forms a conductive layer 153j, etc.

[0247] Next, the insulating film 214j is deposited. The insulating film 214j is deposited by, for example, sputtering, CV Method D (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or It can be formed using methods such as the PLD method. In particular, the insulating film can be formed by the CVD method, preferably Plasma CVD is preferred for film deposition because it can improve coverage. Furthermore, to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. This is preferable. Regarding the insulating film 214j, please refer to the description of the insulating film 114j above. Yes.

[0248] In order to make the insulating film 214j contain an excess of oxygen, for example, the insulating film 2 A 14J film can be deposited. Alternatively, oxygen can be introduced into the 214J insulating film after deposition to remove oxygen. A region containing an excess may be formed, or both methods may be combined.

[0249] For example, oxygen (at least oxygen radicals, oxygen atoms, oxygen atoms, etc.) is present in the insulating film 214j after film formation. A region containing an excess of oxygen is formed by introducing either ON or ON. The methods include ion implantation, ion doping, and plasma immersion ion implantation. Plasma treatment and other methods can be used.

[0250] For the oxygen introduction treatment, an oxygen-containing gas can be used. Examples of oxygen-containing gases include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc., can be used. Furthermore, in the oxygen introduction treatment, a noble gas may be added to the oxygen-containing gas. Alternatively, hydrogen It may also include the following. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used. stomach.

[0251] Furthermore, after molding the insulating film 214j, methods such as CMP are used to improve the flatness of its upper surface. A flattening process may be performed.

[0252] Next, the source electrode or drain electrode of transistor Tb_j is placed on the conductive layer 153j, etc. A plug for connecting to the following may be formed. First, an opening is made in the insulating film 214j ( See Figure 13(B). Next, a conductive film 153 that will serve as a plug is formed to fill the opening. (See Figure 13(C)). For the formation of the conductive film 153, for example, the conductive layer 105j is formed. Refer to conductive films, etc.

[0253] Next, the conductive film 153 is subjected to a planarization treatment so that the surface of the insulating film 214j is exposed. This forms plug 148j, etc. (see Figure 13(D)).

[0254] Next, transistors such as transistor Tb_j are formed on the insulating film 214j. For instructions on how to fabricate transistor Ta_j, please refer to the instructions for fabricating transistor Tb_j. can.

[0255] A semiconductor film that will become semiconductor layer 201j_a, etc., and a semiconductor film that will become semiconductor layer 201j_b, etc. The films are deposited sequentially. It is preferable to deposit the semiconductor films continuously without exposing them to the atmosphere. It is important to remember that semiconductors that become semiconductor layer 201j_a and semiconductors that become semiconductor layer 201j_b. This involves thin-film deposition using methods such as sputtering, CVD, MBE, PLD, or ALD. That's all you need to do.

[0256] Furthermore, semiconductors such as semiconductor layer 201j_a and semiconductor layer 201j_b When depositing an In-Ga-Zn oxide layer as a semiconductor using the MOCVD method, the raw material gas If trimethylindium, trimethylgallium, and dimethylzinc are used as the base material, Good. Furthermore, the combination of raw material gases is not limited to the above, and trimethylindium can be replaced with... You may also use ethylindium or similar. Alternatively, you can substitute triethyl for trimethylgallium. Gallium may be used instead. Diethylzinc may also be used instead of dimethylzinc. good.

[0257] It is preferable to perform a fourth heat treatment after forming the oxide film and the semiconductor film. The heat treatment is At a temperature of 250°C to 650°C, preferably 300°C to 500°C, an inert gas The procedure can be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere for the heat treatment is an inert gas atmosphere, and after the heat treatment, to replenish the oxygen that has been removed. The process may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The heat treatment is performed to deposit the semiconductor film. It can be done immediately afterwards, or the semiconductor film can be processed to create island-shaped semiconductor layers 201j_a, 201j_ This may be performed after forming b, etc. Heat treatment is performed to separate the insulating film 214j and the oxide film from the semiconductor film. Oxygen is supplied to the body membrane, reducing oxygen deficiency in the semiconductor film.

[0258] Then, a resist mask is formed, and the unnecessary parts are removed by etching. By removing the dyst mask, island-shaped semiconductor layer 201j_a, semiconductor layer 201j_ A layered structure such as b can be formed (see Figure 13(E)). Note that the semiconductor film is etched. During etching, a portion of the insulating film 214j is etched, and the semiconductor layer 201j_a and the semiconductor layer The insulating film 214j may become thinner in regions not covered by 201j_b, etc. Therefore, in order to prevent the insulating film 214j from disappearing due to the etching, it is formed thickly in advance. It is preferable to leave it there.

[0259] Subsequently, a conductive film 204j is formed. The conductive film 204j is formed by, for example, sputtering. method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD It can be formed using methods such as CVD or PLD. In particular, the insulating film can be formed using CVD or PLD. Alternatively, deposition by plasma CVD can improve coverage, making it preferable. It seems so. Also, to reduce damage caused by plasma, thermal CVD, MOCVD, or The ALD method is preferred.

[0260] Next, a resist mask is formed, and any unwanted portions of the conductive film 204j are removed by etching. Then, remove the resist mask and form conductive layer 204j_a, conductive layer 204j_b, etc. This is achieved (see Figure 14(A)). Here, during etching of the conductive film, the semiconductor layer 201j_ b and a portion of the upper part of the insulating film 114j are etched, and conductive layer 204j_a and conductive layer 2 The portion that does not overlap with 04j_b may become a thin film. Therefore, the semiconductor layer 201j_ The thickness of the semiconductor film, etc., that will become b is formed to be thick in advance, taking into account the depth to be etched. This is preferable.

[0261] Next, the gate insulating film 202j and the semiconductor layer 201j_c are deposited. j and semiconductor layer 201j_c become gate insulating film 202j and semiconductor layer 201j_c. Formed by depositing a film, then forming a resist mask, and processing by etching. This may be done. Next, a conductive film that will become the gate electrode 203j is deposited. After that, a resist mask A gate is formed, processed by etching, and then the resist mask is removed. Electrode 203j is formed (see Figure 14(B)). The semiconductor that will become the semiconductor layer 101j_c is The film is deposited using sputtering, CVD, MBE, PLD, ALD, etc. Yes.

[0262] Furthermore, the semiconductor that will become the semiconductor layer 101j_c is an In-Ga-Zn oxide layer MOC When forming films using the VD method, trimethylindium and trimethylgalium are used as raw material gases. You may use materials such as methyl zinc and dimethyl zinc. However, this is not limited to the above combination of raw material gases. Furthermore, triethylindium or other similar substances may be used instead of trimethylindium. Triethylgallium or other alternatives may be used instead of methylgallium. Dimethylzinc may also be used. Diethylzinc or the like may be used instead.

[0263] At this stage, transistors such as transistor Tb_j are formed.

[0264] Next, the insulating film 212j is formed. The insulating film 212j is formed by, for example, sputtering, CV Method D (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or It can be formed using methods such as the PLD method. In particular, the insulating film can be formed by the CVD method, preferably Plasma CVD is preferred for film deposition because it can improve coverage. Furthermore, to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. It is preferable.

[0265] It is preferable to perform a fifth heat treatment after the deposition of the insulating film 212j. The heat treatment provides an insulating layer. Oxygen is supplied from the edge film 214j, etc., to the semiconductor layer 201j, and oxygen in the semiconductor layer 201j Defects can be reduced. Also, at this time, the oxygen that is released from the insulating film 214j is removed. Blocked by the film 111 and insulating film 212j, below the barrier film 111 and insulated Since it does not diffuse above the border film 212j, the oxygen can be effectively contained. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 201j can be increased, and the semiconductor layer This can effectively reduce oxygen deficiency during 201J.

[0266] Furthermore, the insulating film 212j may be arranged in a laminated structure of two or more layers. In that case, for example, insulation The film 212j has a two-layer stacked structure, with the lower layer consisting of, for example, silicon oxide, silicon oxide nitride, and nitride. Silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride Aluminum, aluminum nitride, etc., can be used. Also, the upper layer can be made in the same way as the barrier film 111. It is preferable to use a material that does not easily diffuse water or hydrogen. Furthermore, the insulating film provided in the lower layer is an insulating material. Similar to film 214j, the gate insulating film 102j is used as an insulating film that desorbs oxygen upon heating. Alternatively, oxygen may be supplied from above the semiconductor layer 101j.

[0267] Next, the insulating film 213j is formed (see Figure 14(C)). The insulating film 213j is, for example, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. can be used. The insulating film 113j is formed in a laminated or single layer. The insulating film 113j is formed by, for example, sputtering, CVD (thermal) (including CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or PLD method It can be formed using methods such as the CVD method, preferably the plasma CVD method. Depositing the film in this way is preferable because it allows for good coverage. Also, when using plasma To reduce damage, thermal CVD, MOCVD, or ALD methods are preferred.

[0268] To avoid complexity, Figures 6 to 9, 11, 12, and 18 show insulating films. 112j, 113j, insulating film 212j, and insulating film 213j are not shown in the illustration.

[0269] Next, an insulating film 216j is formed. The insulating film 216j is made of, for example, silicon oxide, nitrogen oxide. Silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride Aluminum nitride, aluminum oxide, aluminum nitride, etc., can be used, and the layers can be stacked or single-layered. The insulating film 216j can be manufactured by, for example, sputtering, CVD (thermal CVD, MOCVD). Formed using methods such as the PECVD method, MBE method, ALD method, or PLD method. This is possible. Also, when using an organic insulating material such as an organic resin as the insulating film 216j, Alternatively, it may be formed using a coating method such as spin coating. It is preferable to perform a planarization treatment on the upper surface afterwards. Also, as the insulating film 216j Alternatively, the materials and formation methods shown in insulating film 138 may be used.

[0270] Next, insulating film 216j, insulating film 213j, insulating film 212j, gate insulating film 202j and An opening is provided in the semiconductor layer 201j_c that reaches the conductive layer 204j_a, conductive layer 204j_b, etc. The openings are then filled with plugs 141j, 142j, 143j, etc. A conductive film is formed, and a planar treatment is performed so that the surface of the insulating film 216j is exposed, and plug 14 This forms plugs 1j, 142j, 143j, etc. (see Figure 15(A)).

[0271] Next, conductive layers 151j, 153j, 15 A conductive film of 4j, etc. is formed, a mask is formed and etching is performed, and conductive layers 151j, 15 Form layers such as 3j and 154j. Then, form an insulating film of 115j (see Figure 15(B)). The insulating film 115j can function as an insulating film for the capacitive element Ca_j. Insulating film 1 For materials that can be used for 15j, please refer to the description for gate insulating film 202j, for example. good.

[0272] Next, a conductive layer 152j, etc., is formed on the insulating film 115j in the same manner as the conductive layer 151j. See Figure 15(C). Used in conductive layers 151j, 153j, 154j, conductive layer 152j, etc. For information on the materials that can be used, see, for example, the description of conductive layer 205j. This allows for the formation of a capacitive element Ca_j.

[0273] Next, an insulating film 156j is formed on the conductive layer 152j and the insulating film 115j. The upper surface of 6j may be flattened. For insulating film 156j, see insulating film 216j. See the list.

[0274] Next, a transistor Ta_j is formed on the insulating film 156j. First, the insulating film 156j A conductive layer 105j, etc., is formed on top. The conductive layer 105j, etc., is formed in the same manner as the conductive layer 205j. This can be done. Next, an insulating film 114j is formed (see Figure 16(A)). Insulating film 11 4j can be formed in the same way as the insulating film 214j.

[0275] Next, openings are made in the insulating film 156j and insulating film 114j, and guided to fill the openings. An electrical film is formed, and the surface of the conductive film is flattened so that the insulating film 114j is exposed, and plug 144 j, plug 145j, etc. are formed.

[0276] Next, transistors such as Ta_j are formed (see Figure 16(B)). Transistor Ta_ For the formation of j, refer to the description of transistor Tb_j. Here, Figure 16( As shown in B), the transistor Ta_j (j=1) of the submemory cell SCL_1 And simultaneously form the transistor Tb_j (j=2) of the submemory cell SCL_2. It is possible.

[0277] Next, by repeatedly forming capacitive elements Ca_j, transistors Ta_j, etc. in the same manner... This allows for the fabrication of semiconductor devices as shown in Figure 8.

[0278] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0279] (Embodiment 2) In this embodiment, transistors Ta_j and Tb_ shown in Embodiment 1 are used. An oxide semiconductor that can be suitably used for j will be described. Note that transistor Tb For _j, refer to the description of transistor Ta_j. Also, semiconductor layer 201j_a For semiconductor layer 201j_b and semiconductor layer 201j_c, semiconductor layer 101j You can refer to the descriptions of _a, semiconductor layer 101j_b, and semiconductor layer 101j_c. However, semiconductor layer 101j_a and semiconductor layer 201j_a do not necessarily have to be made of the same material. This is also good. That is, for example, In-MZ When using n oxides, for example, if the atomic ratio of indium, element M, and zinc is the same, It is not necessary. Also, for example, semiconductor layer 101j_a and semiconductor layer 201j_a are energy - The gap does not need to use the same material. Also, semiconductor layer 101j_b and semiconductor layer 20 The same applies to 1j_b, or semiconductor layer 101j_c and semiconductor layer 201j_c.

[0280] Here, as shown in Figure 6 and other examples, the semiconductor layer 101j_a is used as the oxide semiconductor. An example is shown in which three layers, semiconductor layer 101j_b and semiconductor layer 101j_c, are stacked and used. The oxide semiconductor that can be used in the transistor Ta_j may be a single layer. Any of the body layer 101j_a, semiconductor layer 101j_b, and semiconductor layer 101j_c Alternatively, the structure may not have either of these features.

[0281] Semiconductor layer 101j_b is, for example, an oxide semiconductor containing indium. Semiconductor layer 1 For example, if 01j_b contains indium, its carrier mobility (electron mobility) will increase. Furthermore, the semiconductor layer 101j_b preferably contains element M. Element M is preferably A Examples include luminium, gallium, yttrium, or tin. Applicable to other elements M. Possible elements include boron, silicon, titanium, iron, nickel, germanium, and yttrium. Umium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum Examples include tungsten and others. However, even if you combine multiple of the aforementioned elements as element M... There are cases where this is acceptable. Element M is, for example, an element with a high bond energy with oxygen. For example, it is an element whose bonding energy with oxygen is higher than that of indium. Or, element M is, For example, it is an element that has the function of increasing the energy gap of oxide semiconductors. The semiconductor layer 101j_b preferably contains zinc. Oxide semiconductors become crystalline when zinc is present. It may become easier to transform.

[0282] However, the semiconductor layer 101j_b is not limited to an oxide semiconductor containing indium. The conductive layer 101j_b is made of, for example, zinc tin oxide, gallium tin oxide, etc. Oxide semiconductors that do not contain zinc, oxide semiconductors that contain gallium, oxide semiconductors that contain tin It could be a semiconductor or something similar.

[0283] For example, the semiconductor layer 101j_b uses an oxide with a large energy gap. The energy gap of layer 101j_b is, for example, between 2.5eV and 4.2eV. Preferably between 2.8eV and 3.8eV, and more preferably between 3eV and 3.5eV. do.

[0284] For example, semiconductor layer 101j_a and semiconductor layer 101j_c are semiconductor layer 101j_b It is an oxide semiconductor composed of one or more elements other than oxygen. One or more elements other than oxygen that constitute the semiconductor layer 101j_b are used to form the semiconductor. Since layer 101j_a and semiconductor layer 101j_c are formed, semiconductor layer 101j_a and The interface with semiconductor layer 101j_b, and the interface between semiconductor layer 101j_b and semiconductor layer 101j_c At the interface, interface states are less likely to form.

[0285] Semiconductor layer 101j_a, semiconductor layer 101j_b, and semiconductor layer 101j_c are less It is preferable that both contain indium. Furthermore, the semiconductor layer 101j_a is In-M-Zn oxide. When the sum of In and M is 100 atomic%, preferably In is 50 a Less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 25 at Less than 0 omic%, M is higher than 75 atomic%. Also, semiconductor layer 101j_b is In -When M-Zn oxide is used, when the sum of In and M is 100 atomic%, the preferred In is higher than 25 atomic%, and M is less than 75 atomic%, more preferably. The ratio of In to M is set to be higher than 34 atomic%, and M is set to be less than 66 atomic%. When the body layer 101j_c is In-M-Zn oxide, the sum of In and M is 100 atomi When c%, preferably In is less than 50 atomic%, and M is 50 atomic%, It is more preferably that In is less than 25 atomic%, and M is more than 75 atomic%. It is expensive. Furthermore, even if semiconductor layer 101j_c uses the same type of oxide as semiconductor layer 101j_a, That's fine.

[0286] Semiconductor layer 101j_b is more electrically charged than semiconductor layer 101j_a and semiconductor layer 101j_c. Use an oxide with high affinity for its offspring. For example, as semiconductor layer 101j_b, semiconductor layer 10 1j_a and semiconductor layer 101j_c have electron affinity of 0.07eV to 1.3eV Preferably, 0.1 eV to 0.7 eV, and more preferably 0.15 eV to 0. Use oxides with an electron affinity of 4 eV or less. Note that electron affinity is the energy between the vacuum level and the lower edge of the conduction band. That's the difference with ghee.

[0287] Furthermore, indium gallium oxide has low electron affinity and high oxygen blocking properties. Therefore, it is preferable that the semiconductor layer 101j_c contains indium gallium oxide. The lium atom ratio [In / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it should be 90% or more.

[0288] Furthermore, it is more preferable that the semiconductor layer 101j_c contains gallium oxide. Semiconductor layer 1 Adding gallium oxide to 01j_c may result in lower off-currents.

[0289] When an electric field is applied to the gate electrode of the transistor, semiconductor layer 101j_a, semiconductor layer 10 Of the semiconductor layers 1j_b and 101j_c, the semiconductor layer 101j_b has a higher electron affinity. A channel is formed.

[0290] The band structure is shown in Figure 25(A). Figure 25(A) shows the vacuum level (vac (Denoted as uum level.), the energy at the bottom of the conduction band of each layer (denoted as Ec.) and This indicates the energy at the top of the valence band (denoted as Ev).

[0291] Here, between semiconductor layer 101j_a and semiconductor layer 101j_b, semiconductor layer 101j There may be a mixed region of _a and semiconductor layer 101j_b. Also, semiconductor layer 101j Between _b and semiconductor layer 101j_c, semiconductor layer 101j_b and semiconductor layer 101j_c It may have a mixed region. In the mixed region, the interface state density is low. Therefore, half The laminate of conductive layer 101j_a, semiconductor layer 101j_b, and semiconductor layer 101j_c is Near each interface, the energy changes continuously (also called a continuous junction). It will have a D structure.

[0292] Note that in Figure 25(A), the Ec of semiconductor layer 101j_a and the second semiconductor layer 101j_c is shown. The example shown is for cases where they are similar, but they may also be different. For example, semiconductor layer The Ec of the semiconductor layer 101j_c may have a higher energy than that of 101j_a.

[0293] At this time, the electrons are not in semiconductor layer 101j_a and semiconductor layer 101j_c, It mainly moves within the semiconductor layer 101j_b (see Figure 25(B)). As mentioned above, Interface state density at the interface between semiconductor layer 101j_a and semiconductor layer 101j_b, semiconductor To lower the interface state density at the interface between layer 101j_b and semiconductor layer 101j_c Therefore, electron movement in the semiconductor layer 101j_b is less inhibited, and transistor The on-current can be increased.

[0294] Furthermore, if the transistor has an s-channel structure, the semiconductor layer 101j_b A channel is formed throughout. Therefore, the thicker the semiconductor layer 101j_b, the larger the channel area. The range becomes larger. In other words, the thicker the semiconductor layer 101j_b, the higher the on-current of the transistor. This can be achieved. For example, 20 nm or more, preferably 40 nm or more, more preferably The semiconductor layer 101j has a region with a thickness of 60 nm or more, more preferably 100 nm or more. _b would be fine. However, this may reduce the productivity of semiconductor devices, for example, 3 A region with a thickness of 00 nm or less, preferably 200 nm or less, and more preferably 150 nm or less. This can be done by using a semiconductor layer 101j_b that has a region.

[0295] Furthermore, in order to increase the on-current of the transistor, the thickness of the semiconductor layer 101j_c should be small. The more preferable. For example, less than 10 nm, preferably 5 nm or less, and even more preferably 3 A semiconductor layer 101j_c having a region of less than nm can be used. On the other hand, semiconductor layer 101j_ c is the oxygen that constitutes the adjacent insulator to the semiconductor layer 101j_b where the channel is formed. It has a function to block outside elements (such as hydrogen and silicon) from entering. Therefore, it is preferable that the semiconductor layer 101j_c has a certain thickness. For example, 0.3 Semi-semi The conductive layer 101j_c is used. Also, the semiconductor layer 101j_c is the gate insulating film 102 To suppress the outward diffusion of oxygen released from sources such as j, it has properties that block oxygen. It would be preferable if that happened.

[0296] Furthermore, in order to increase reliability, the semiconductor layer 101j_a is thicker, and the semiconductor layer 101j_ c is preferably thin. For example, 10 nm or more, preferably 20 nm or more, even more preferably A semiconductor layer 101 having a region with a thickness of 40 nm or more, more preferably 60 nm or more. Let it be j_a. By increasing the thickness of the semiconductor layer 101j_a, the adjacent insulator From the interface with semiconductor layer 101j_a to semiconductor layer 101j_b where the channel is formed The distance can be increased. However, this may reduce the productivity of semiconductor devices, for example. If, the thickness is 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The semiconductor layer 101j_a has the region shown.

[0297] When an oxide semiconductor film contains a large amount of hydrogen, it combines with the oxide semiconductor, causing water to form. Some of the elements become donors, generating electrons, which are carriers. This causes the transistor The threshold voltage of the film shifts in the negative direction. Therefore, the formation of oxide semiconductor films is affected. Subsequently, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or water from the oxide semiconductor film. It is preferable to remove impurities and purify the material to a high degree to minimize its content.

[0298] Furthermore, by dehydrating (dehydrogenating) the oxide semiconductor film, Oxygen levels may also decrease at the same time. Therefore, dehydration treatment of oxide semiconductor films (dehydration) A process to add oxygen to an oxide semiconductor to compensate for the oxygen deficiency increased by the chemical treatment. It is preferable to do so. In this specification, etc., when oxygen is supplied to an oxide semiconductor film, This is sometimes referred to as oxygenation treatment, or the process of removing oxygen contained in an oxide semiconductor film from its stoichiometric composition. When the amount of oxygen is increased, it is sometimes referred to as peroxygenation treatment.

[0299] Thus, oxide semiconductor films undergo dehydration treatment (dehydrogenation treatment) to remove hydrogen or water. The oxygen deficiency is removed and compensated for by oxygenation treatment, resulting in type i (true) and This can be an oxide semiconductor film that is very close to type i and is essentially type i (intrinsic). Furthermore, "substantially true" means that there are very few donor-derived carriers in the oxide semiconductor film. (Close to zero), carrier density is 1 × 10⁻⁶ 17 / cm 3Below, 1 x 10 16 / cm 3 below , 1 x 10 15 / cm 3 Below, 1 x 10 14 / cm 3 Below, 1 x 10 13 / cm 3 Below To say something

[0300] Furthermore, transistors having an oxide semiconductor film that is of type i or substantially type i are This enables extremely excellent off-current characteristics. For example, a transient using an oxide semiconductor film The drain current when the switch is off is 1 × 10⁻¹⁰ at room temperature (approximately 25°C). -18 Below A, Preferably 1 × 10 -21 A or less, more preferably 1 × 10 -24 A or lower, or 85 1 × 10°C -15 A or less, preferably 1 × 10 -18 A or less, more preferably 1× 10 -21 It can be less than or equal to A. Note that the transistor being in the off state is n-channel. In the case of a transistor of this type, this refers to the state where the gate voltage is sufficiently lower than the threshold voltage. Specifically, if the gate voltage is 1V, 2V, or 3V lower than the threshold voltage The transistor then turns off.

[0301] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0302] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) is used. Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors (such as ke Oxide Semiconductors).

[0303] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. They can be divided into conductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC-O Examples include S, polycrystalline oxide semiconductors, and nc-OS.

[0304] Generally, an amorphous structure is defined as a structure that is not fixed in a metastable state and is isotropic. It is known that it does not have a heterogeneous structure. Also, the bond angles are flexible and short distance It can also be described as a structure that possesses order but lacks long-range order.

[0305] Conversely, in the case of oxide semiconductors, which are inherently stable, a completely amorphous (complete) semiconductor is possible. It cannot be called an oxide semiconductor (ely amorphous). Furthermore, it is not isotropic. For example, an oxide semiconductor (having a periodic structure in a minute region) is made of a completely amorphous oxide It cannot be called a semiconductor. However, a-like OS exhibits periodicity in a minute region. Although it has a structure, it is unstable due to its porous (also called void) nature. Therefore, In terms of physical properties, it can be said to be similar to an amorphous oxide semiconductor.

[0306] <caac-os> First, let me explain CAAC-OS.

[0307] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0308] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-frequency analysis) is obtained using the scope. Also called a resolving TEM image.) When observing this image, multiple pellets can be identified. In high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It cannot be clearly confirmed that CAAC-OS occurs at the grain boundaries. This means that a decrease in electron mobility due to this is less likely to occur.

[0309] The following describes CAAC-OS as observed by TEM. Figure 20(A) shows, This shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The Corrector function was used. High-resolution TEM images using spherical aberration correction were obtained. This is specifically called a Cs-corrected high-resolution TEM image. Acquisition of Cs-corrected high-resolution TEM images is, for example, done in Japan. This is performed using an atomic-resolution analytical electron microscope, such as the JEM-ARM200F, manufactured by this electronics company. It is possible.

[0310] Figure 20(B) shows a magnified Cs-corrected high-resolution TEM image of region (1) in Figure 20(A). Figure 20(B) shows that the metal atoms in the pellet are arranged in layers. The arrangement of metal atoms in each layer is such that the surface forming the CAAC-OS film (also called the surface to be formed) Alternatively, it reflects the irregularities of the upper surface and is parallel to the surface or upper surface of the CAAC-OS that is formed.

[0311] As shown in Figure 20(B), CAAC-OS has a characteristic atomic arrangement. Figure 20(C) The characteristic atomic arrangement is shown with auxiliary lines. Figures 20(B) and 20(C) Furthermore, the size of a single pellet can be 1 nm or larger, or 3 nm or larger. It can be seen that the size of the gap created by the tilt between the pellet and the material is approximately 0.8 nm. Therefore, pellets can also be called nanocrystals (nc). Also, CAAC-OS is CANC(C-Axis Aligned nanocry It can also be called an oxide semiconductor containing stals.

[0312] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 5120 are... The arrangement of the To 5100 can be schematically represented as a structure resembling stacked bricks or blocks. (See Figure 20(D).) The tilt between the pellets observed in Figure 20(C) The area where the condensation is occurring corresponds to region 5161 shown in Figure 20(D).

[0313] Furthermore, Figure 21(A) shows the Cs in the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 21(A). Magnified Cs-corrected high-resolution TEM images are shown in Figures 21(B), 21(C), and 21(C), respectively. As shown in 21(D). From Figures 21(B), 21(C), and 21(D), the pellets are It can be confirmed that metal atoms are arranged in a triangular, square, or hexagonal shape. However, However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0314] Next, the CA was analyzed by X-ray diffraction (XRD). Let's discuss AC-OS. For example, CAAC-OS, which has an InGaZnO4 crystal. In contrast, when structural analysis is performed using the out-of-plane method, as shown in Figure 22(A)... In some cases, a peak may appear at a diffraction angle (2θ) near 31°. This peak is in InGaZ Since it is attributed to the (009) plane of the nO4 crystal, the CAAC-OS crystal is c-axis oriented. It can be confirmed that the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0315] In addition, in the structural analysis using the out-of-plane method of CAAC-OS, 2θ is 31°. In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak indicates that some of the crystals in CAAC-OS do not have c-axis orientation. This indicates that the more preferable CAAC-OS is the structural solution by the out-of-plane method. Analysis revealed a peak around 31° for 2θ, but no peak around 36° for 2θ.

[0316] On the other hand, for CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plan configuration. Structural analysis using the e method reveals a peak near 2θ = 56°. This peak corresponds to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is 56 The sample is fixed in the vicinity of °, and the analysis is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis). Even after performing a φ scan, no clear peak appears, as shown in Figure 22(B). Furthermore, if it is a single-crystal oxide semiconductor of InGaZnO4, then fixing 2θ to around 56°, φs If this occurs, the pi is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 22(C). Six lines are observed. Therefore, structural analysis using XRD indicates that CAAC-OS is It can be confirmed that the orientation of the a-axis and b-axis is irregular.

[0317] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe with a diameter of 300 nm is placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern like the one shown in Figure 23(A) (limited field transmission electron diffraction) is observed. Sometimes a pattern (also called a diffraction pattern) may appear. This diffraction pattern is indicative of InGaZnO4. The spot originates from the (009) plane of the crystal. Therefore, electron diffraction also reveals... The pellets contained in CAAC-OS have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be seen that it is oriented in a vertical direction. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. Figure 23(B) shows the diffraction pattern when an electron beam with a diameter of 300 nm is incident on the surface. Figure 23 (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also shows that It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. Note that the first ring in Figure 23(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be caused by the (100) surface, etc. Also, the second ring in Figure 23(B) is (110) This is thought to be caused by the surface, etc.

[0318] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Crystallinity can decrease due to the inclusion of impurities or the formation of defects, so the opposite perspective is needed. CAAC-OS can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0319] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0320] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers It can become a source of emissions. Furthermore, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, it may act as a carrier source by capturing hydrogen.

[0321] CAAC-OS, with its low impurity and oxygen vacancies, is an oxide semiconductor with a low carrier density. Specifically, 8 x 10 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than, More preferably 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 The above career It can be made into a high-density oxide semiconductor. Such an oxide semiconductor can be made into a high-purity intrinsic or It is essentially a high-purity, intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and defects. It has a low energy level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0322] <nc-os> Next, I will explain nc-OS.

[0323] nc-OS is a region in which the crystalline part can be confirmed in high-resolution TEM images, and is clearly It has regions where the crystalline portion cannot be confirmed. The crystalline portion contained in nc-OS is They are often between 1 nm and 10 nm in size, or between 1 nm and 3 nm. Oxide semiconductors with a crystal size greater than 10 nm and less than or equal to 100 nm are subjected to microcrystalline oxidation. It is sometimes called a solid semiconductor. nc-OS, for example, in high-resolution TEM images, shows grain boundaries. It may not be possible to confirm this clearly. Furthermore, nanocrystals are the pellets in CAAC-OS. They may share the same origin. Therefore, in the following, the crystalline portion of nc-OS will be referred to as a pellet. There are cases where this happens.

[0324] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS can be classified as a-like OS or amorphous oxide semiconductor. In some cases, it may be difficult to distinguish between them. For example, with nc-OS, X has a larger diameter than the pellet. When using lines, out-of-plane analysis detects peaks that indicate crystal planes. It is not released. Also, for nc-OS, a probe diameter larger than the pellet (e.g., 50n) is required. When electron diffraction is performed using an electron beam (of m or greater), a diffraction pattern similar to a halo pattern can be observed. It is measured. On the other hand, compared to nc-OS, the size is close to or smaller than the pellet size. When nanobeam electron diffraction is performed using an electron beam of a certain diameter, spots can be observed. When nanobeam electron diffraction is performed on c-OS, a high-brightness ring-shaped pattern is observed. A region may be observed. Furthermore, multiple spots may be observed within a ring-shaped region. There are cases where this is the case.

[0325] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc- The OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor having ).

[0326] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0327] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0328] a-like OS may exhibit porosity in high-resolution TEM images. In the high-resolution TEM image, there are regions where the crystalline structure can be clearly identified, and regions where the crystalline structure cannot be identified. It has areas that cannot be accessed.

[0329] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0330] The samples to be irradiated with electrons are a-like OS (referred to as sample A) and nc-OS ( Prepare Sample B (referred to as Sample B) and CAAC-OS (referred to as Sample C). The sample is also an In-Ga-Zn oxide.

[0331] First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of them have crystalline parts.

[0332] The determination of which part should be considered a single crystal can be made as follows. For example, The unit cell of an InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which 6 layers, totaling 9 layers, are stacked in layers along the c-axis. The spacing between adjacent layers is approximately the same as the spacing between grid planes (also called the d value) of the (009) plane. Yes, and its value has been determined to be 0.29 nm from crystal structure analysis. Therefore, the lattice fringes Areas with a spacing of 0.28 nm or more and 0.30 nm or less are considered to be the crystalline regions of InGaZnO4. This can be done. Note that the lattice patterns correspond to the ab-plane of the InGaZnO4 crystal.

[0333] Figure 24 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 24, a-lik It can be seen that the crystalline portion of eOS increases in proportion to the cumulative amount of electron irradiation. As shown in (1) in Figure 24, the initial TEM observation is approximately 1.2 nm. The crystal region (also called the initial nucleus), which was initially 4.2 × 10¹⁶ in size, changed when the cumulative irradiation dose reached 4.2 × 10¹⁶. 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS And CAAC-OS has a cumulative electron dose of 4.2 × 10⁻⁶ from the start of electron irradiation. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. Specifically, Figure As shown in (2) and (3) of 24, regardless of the cumulative dose of electrons, nc-OS and The size of the crystalline portion of CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively. It becomes clear that...

[0334] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It can be seen that it cannot be seen. That is, a-like OS is nc-OS and CAAC-O Compared to S, it is clear that it has an unstable structure.

[0335] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density will be between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are difficult to deposit into film.

[0336] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of a single crystal InGaZnO4 having a polyhedral crystal structure is 6.357 g / cm 3 Thus, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a-like OS is 5.0 g / cm or more and less than 5.9 g / cm 3 . Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], 3 the density of nc-OS and the density of CAAC-OS are 5.9 g / cm or more and less than 6.3 g / cm . 3 3

[0337] Note that there may be no single crystal with the same composition. In that case, by combining single crystals with different compositions in any ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

[0338] As described above, oxide semiconductors have various structures and each has various characteristics. Also, the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, a-like OS, nc-OS, CAAC-OS.

[0339] Consider the case where the oxide semiconductor has indium, element M, and zinc. Here, element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements applicable to such element M include boron, silicon, titanium, iron, nickel, germanium, and Manium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include hafnium, tantalum, and tungsten. However, as element M, the aforementioned elements are used. In some cases, multiple combinations are acceptable. Oxide semiconductors contain indium, element M and This section describes the preferred range for the ratio of zinc atoms, x:y:z.

[0340] In oxides containing indium, element M, and zinc, InMO3(ZnO) m (m is natural It is known that there exists a homologous phase (homologous series) represented by a number. Now, let's consider the case where element M is Ga as an example.

[0341] For example, as a compound having a spinel-type crystal structure, ZnM2 such as ZnGa2O4 Compounds represented by O4 are known. Also, compositions near ZnGa2O4, i.e., x, When y and z have values ​​close to (x,y,z)=(0,1,2), a spinel-type connection is formed. Crystal structures are easily formed or mixed. Here, the oxide semiconductor is CAAC-OS. It is preferable that CAAC-OS does not contain a spinel-type crystal structure. It is preferable. Furthermore, to increase carrier mobility, it is preferable to increase the In content. In oxide semiconductors containing indium, element M, and zinc, the s orbitals of heavy metals are primarily capsulated. It contributes to rear conduction, and by increasing the indium content, more s orbitals are created. Because of the overlap, oxides with a high indium content and oxides with a low indium content In comparison, the mobility is higher. Therefore, oxide semiconductors with a high indium content are more suitable. By using this, it is possible to increase career mobility.

[0342] For example, by increasing the atomic ratio of indium, carrier mobility can be increased. This is preferable for the following reasons. For example, the number of atoms of indium, element M and zinc in the oxide semiconductor. When the ratio is expressed as x:y:z, it is preferable that x is 1.75 times or more y.

[0343] Furthermore, in order to further increase the CAAC ratio of oxide semiconductors, the atomic ratio of zinc must be increased. This is preferable. For example, the atomic ratio of the In-Ga-Zn oxide is set to a range that can be in the solid solution region. By doing so, the CAAC ratio can sometimes be increased. Indium and galvanic acid Increasing the ratio of zinc atoms to the sum of mu atoms widens the range in which solid solutions can exist. There is a tendency to increase the ratio of zinc atoms to the sum of indium and gallium atoms. This can sometimes increase the CAAC ratio of oxide semiconductors. Then, the ratio of the number of atoms of indium, element M, and zinc in the oxide semiconductor is expressed as x:y:z. In this case, it is preferable that z is 0.5 times or more of x+y. On the other hand, the atomic ratio of indium is To increase carrier mobility, it is preferable that z is less than or equal to twice x+y.

[0344] As a result, the proportion of spinel-type crystal structures observed in nanobeam electron diffraction was eliminated. It is possible to do so, or to make it extremely low. Therefore, a superior CAAC-OS It can be obtained. Also, carriers at the boundary between the CAAC structure and the spinel-type crystal structure. Because scattering and other factors can be reduced, when oxide semiconductors are used in transistors, high This enables the realization of transistors with high field-effect mobility. Furthermore, highly reliable transistors can be realized. It is possible to achieve this goal.

[0345] As a result, oxide semiconductors with a high CAAC ratio can be realized. In other words, high quality This makes it possible to realize CAAC-OS. Furthermore, in the region where a spinel-type crystal structure is observed... It is possible to realize CAAC-OS with no or very few boundaries. For example, a high quality If it is CAAC-OS, the CAAC ratio should be 50% or more, preferably 80% or more, more preferably The percentage is preferably 90% or more, and more preferably 95% to 100%.

[0346] Furthermore, when depositing oxide semiconductors using the sputtering method, the atomic ratio of the target is... A film with an atomic ratio that is different from that of the target may be formed. In particular, zinc may have an atomic ratio that is different from that of the target. The atomic ratio of the film may become smaller. Specifically, the number of zinc atoms contained in the target. The ratio may be between 40 atomic% and approximately 90 atomic%.

[0347] Therefore, the atomic ratio of the target is greater than that of the oxide semiconductor obtained by the sputtering method. It is preferable that the ratio of zinc atoms be high.

[0348] Furthermore, the oxide semiconductor may consist of multiple stacked films. Also, the CAA of each of the multiple films The C ratio may differ. Also, of the multiple layered films, at least one film may be, for example It is preferable that the CAAC ratio is 90% higher, and more preferably 95% or higher. It is even more preferable that the percentage be between 7% and 100%.

[0349] CAAC-OS films can be formed, for example, by the following method.

[0350] CAAC-OS films are, for example, polycrystalline oxide semiconductor sputtering targets. The film is deposited using sputtering. Sputtering methods include RF sputtering and D C sputtering, AC sputtering, etc. can be used. Also, the thickness of the oxide semiconductor film To improve the uniformity of the distribution, film composition, or crystallinity, RF sputtering is more effective than It is preferable to use either the DC sputtering method or the AC sputtering method.

[0351] By increasing the substrate temperature during film deposition, the migration of sputtering particles after reaching the substrate is reduced. This occurs. Specifically, the substrate temperature is between 100°C and 740°C, preferably between 200°C and 740°C. The film is deposited at a temperature of 500°C or lower. By increasing the substrate temperature during film deposition, sputtering particles are formed. When the sputtering particles reach the substrate, migration occurs on the substrate, and the sputtering particles become flat. The surface adheres to the substrate. At this time, the sputtering particles become positively charged, causing sputtering. Because the ring particles repel each other while adhering to the substrate, the sputtering particles become unevenly distributed and non-uniform. This allows for the formation of a CAAC-OS film with uniform thickness without overlapping.

[0352] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities present in the deposition chamber (such as hydrogen, water, carbon dioxide, and nitrogen) can be measured. It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0353] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce the amount of oxygen. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100%. This is expressed as a percentage by volume.

[0354] Alternatively, the CAAC-OS film is formed by the following method.

[0355] First, a first oxide semiconductor film is deposited with a thickness of 1 nm or more and less than 10 nm. The semiconductor film is deposited using the sputtering method. Specifically, the substrate temperature is set to 100°C or higher. The temperature should be 500°C or lower, preferably 150°C to 450°C, and the oxygen content in the film-forming gas should be 30%. The film is formed at a volume of % or more, preferably 100% by volume.

[0356] Next, a heat treatment is performed to transform the first oxide semiconductor film into a highly crystalline first CAAC-OS film. The heat treatment temperature shall be 350°C to 740°C, preferably 450°C to 650°C. The temperature should be below ℃. Furthermore, the heat treatment time should be between 1 minute and 24 hours, preferably between 6 minutes and 4 hours. The temperature should be below a certain level. Furthermore, the heat treatment may be carried out in an inert or oxidizing atmosphere. Alternatively, the material is heated in an inert atmosphere, followed by heat treatment in an oxidizing atmosphere. Heat treatment in an air-filled environment allows for a rapid reduction in the impurity concentration of the first oxide semiconductor film. Yes, it is possible. On the other hand, heat treatment in an inert atmosphere generates oxygen vacancies in the first oxide semiconductor film. This can occur. In such cases, the oxygen deficiency is reduced by heat treatment in an oxidizing atmosphere. It is possible. Furthermore, the heat treatment can be performed at 1000 Pa or less, 100 Pa or less, or 10 Pa or less. This may be carried out under reduced pressure of 1 Pa or less. Under reduced pressure, the impurity concentration of the first oxide semiconductor film This can be reduced in an even shorter amount of time.

[0357] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm, so the thickness is 1 Compared to cases where the wavelength is 0 nm or greater, crystallization can be easily achieved by heat treatment.

[0358] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is made 10 nm or more in thickness. The first film is deposited to a thickness of 0 nm or less. The second oxide semiconductor film is deposited using the sputtering method. Specifically, the substrate temperature is set to 100°C to 500°C, preferably 150°C to 450°C. The temperature should be below ℃, and the oxygen content in the film-forming gas should be 30% by volume or more, preferably 100% by volume. To form a membrane.

[0359] Next, a heat treatment is performed to solid-phase grow a second oxide semiconductor film from the first CAAC-OS film. This process creates a second CAAC-OS film with high crystallinity. The heat treatment temperature is 350°C. The temperature should be between 740°C and 750°C, preferably between 450°C and 650°C. The interval shall be between 1 minute and 24 hours, preferably between 6 minutes and 4 hours. Furthermore, the heat treatment shall be as follows: The process can be carried out in an inert or oxidizing atmosphere. Preferably, the heat treatment is performed in an inert atmosphere. After this, heat treatment is performed in an oxidizing atmosphere. Heat treatment in an inert atmosphere produces a second acid The impurity concentration of the ionized semiconductor film can be reduced in a short time. On the other hand, in an inert atmosphere... Heat treatment can create oxygen vacancies in the second oxide semiconductor film. In that case, oxidation The oxygen deficiency can be reduced by heat treatment in a suitable atmosphere. Note that the heat treatment is 1 It can also be done under reduced pressure of 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be reduced even more quickly. Cut.

[0360] In this manner, a CAAC-OS film with a total thickness of 10 nm or more is formed. It is possible.

[0361] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0362] (Embodiment 3) In this embodiment, the memory device such as the memory cell array 300 exemplified in the above embodiment is used. The RF tag is explained using Figure 27. Here, the memory device is a memory cell array. Includes a configuration that includes a row selection driver, a column selection driver, and an A / D converter to be connected. That's good too.

[0363] The RF tag in this embodiment has a memory circuit inside, and the memory circuit records the necessary information. This involves using contactless means, such as wireless communication, to exchange information with the outside world. Based on these characteristics, RF tags identify items by reading individual information about those items. It can be used in individual authentication systems, etc. However, to use it for these purposes... Extremely high reliability is required.

[0364] The configuration of an RF tag will be explained using Figure 27. Figure 27 shows an example of an RF tag configuration. This is a block diagram.

[0365] As shown in Figure 27, the RF tag 800 is connected to the communicator 801 (interrogator, reader / writer, etc.) An antenna that receives a radio signal 803 transmitted from antenna 802 connected to (also known as) It has 804. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit. It has 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, the reverse current in the rectifying transistor included in the demodulation circuit 807 is sufficiently suppressed. A configuration using a material that can be controlled, such as an oxide semiconductor, may also be used. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This prevents the output of the demodulation circuit from becoming more linear to the input of the demodulation circuit. Yes, it is possible. The data transmission method involves a pair of coils facing each other and communicating through mutual induction. Electromagnetic coupling methods, electromagnetic induction methods that communicate using induced electromagnetic fields, and methods that communicate using radio waves. They can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment does not use any of these methods. It can also be used in formulas.

[0366] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with the antenna 802. Also, a rectifier circuit... 805 processes the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is then smoothed by a capacitive element placed in the subsequent stage. This is a circuit for generating input potential by smoothing. Note that the input side of the rectifier circuit 805... Alternatively, a limiter circuit may be provided on the output side. A limiter circuit controls the amplitude of the input AC signal. When the internally generated voltage is high, do not input power above a certain level to the subsequent circuit. This is a circuit for controlling it in that way.

[0367] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is the circuit. Note that the constant voltage circuit 806 has a reset signal generation circuit inside. Good. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 8. This is a circuit for generating the 09 reset signal.

[0368] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 is used to process the data output from the antenna 804. This is a circuit for modulating accordingly.

[0369] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is It is a circuit that holds the input information, such as a row decoder, column decoder, and memory area. It has the following. Furthermore, ROM811 stores a unique number (ID), etc., and outputs according to the processing. This is the circuit for performing the action.

[0370] Furthermore, the circuits described above can be selected or omitted as needed.

[0371] Here, the memory circuit described in the previous embodiment can be used in the memory circuit 810. A memory circuit according to one aspect of the present invention can retain information even when the power supply is cut off. It can be suitably used in RF tags. Furthermore, a storage circuit according to one aspect of the present invention stores data Because the power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, data It is also possible to eliminate the difference in the maximum communication distance between data reading and writing. This prevents malfunctions or incorrect data writing that may occur due to insufficient power during data writing. It is possible.

[0372] Furthermore, a memory circuit according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will need to provide the ROM811. A separate command is provided for writing the data, preventing users from freely rewriting it. It is preferable that the producer writes a unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, we assign one to each good product that is shipped. It becomes possible to assign a unique number, and the unique numbers of products after shipment will not be discontinuous. This eliminates the need for post-shipment product management, making customer management easier.

[0373] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0374] (Embodiment 4) This embodiment includes at least the memory cell array 300 described in the embodiment. This section describes a CPU that includes a memory device. Here, the memory device is connected to a memory cell array. The configuration may include a row selection driver, a column selection driver, and an A / D converter, etc.

[0375] Figure 28 shows an example of a CPU that uses at least part of the storage device described in the previous embodiment. This is a block diagram showing the structure.

[0376] The CPU shown in Figure 28 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a face 1189 (ROM I / F). The substrate 1190 is a semiconductor substrate, SOI A circuit board, glass substrate, etc. are used. ROM1199 and ROM interface1189 This may be provided on a separate chip. Of course, the CPU shown in Figure 28 has a simplified configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, a configuration including a CPU or arithmetic circuit as shown in Figure 28 is considered one core, and multiple such cores are... It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by arithmetic circuits and data buses is, for example, 8 bits, 16 bits, 32 bits, 6 bits. It can be set to 4 bits, for example.

[0377] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0378] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. It generates a dress and reads or writes to register 1196 depending on the CPU state. .

[0379] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, Instruction decoder 1193, Interrupt controller 1194, It generates signals to control the timing of the operation of the register controller 1197. The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates the CLK2 signal, and the internal clock signal CLK2 is raised It supplies power to the various circuits listed.

[0380] In the CPU shown in Figure 28, a memory cell is located in register 1196. The transistor shown in the previous embodiment can be used as the memory cell of TA1196. Cut.

[0381] In the CPU shown in Figure 28, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, the data will not be rewritten to the capacitive element. This process can be performed to stop the supply of power voltage to the memory cell in register 1196. ru.

[0382] Figure 29 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data volatilizes when the power is cut off, and a memory element 1200 that volatilizes when the power is cut off. Circuit 1202 that prevents data loss, switch 1203, switch 1204, and logic It comprises element 1206, capacitive element 1207, and a circuit 1220 having a selection function. The path 1202 is connected to the capacitive element 1208, transistor 1209, and transistor 1210. , has. The memory element 1200 may include a diode, a resistor, an industrial diode as needed. It may also have other elements such as culverters. Transistor 1209 is an oxide semiconductor It is preferable that the transistor has channels formed in its body layers.

[0383] Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory element 1200 is stopped, the transistor 12 of circuit 1202 The gate of transistor 09 is input to ground potential (0V) or the potential that turns off transistor 1209. The configuration will continue to be such that the gate of transistor 1209 is connected via a load such as a resistor. The configuration will be grounded.

[0384] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The configuration is such that the switch 1204 has a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example is shown using transistor 1214. Here, the first of switch 1203 The terminals correspond to one of the source and drain terminals of transistor 1213, and the other terminal of switch 1203. Terminal 2 corresponds to the source and drain of transistor 1213, and switch 1203 The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. The continuity or non-continuity between the terminals (i.e., the ON or OFF state of transistor 1213) The state is selected. The first terminal of switch 1204 is connected to the source and dot of transistor 1214. Corresponding to one side of the rain, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of transistor 1214 is selected.

[0385] One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One of them is electrically connected to the gate of transistor 1210. Here, the connection Let the section be node M2. One of the sources and drains of transistor 1210 is connected to the low power supply. It is electrically connected to a wire that can supply a value (e.g., a GND wire), and the other is a switch The first terminal of transistor 1203 (one of the source and drain of transistor 1213) is electrically connected. The second terminals of switch 1203 (source and drain of transistor 1213) are connected. The other side is the first terminal of switch 1204 (source and drain of transistor 1214) The second terminal of switch 1204 (of transistor 1214) is electrically connected to the other terminal. The source and drain (the other side) are electrically connected to wiring capable of supplying the power potential VDD. The second terminal of switch 1203 (in addition to the source and drain of transistor 1213) is used. (one side) and the first terminal of switch 1204 (one side of the source and drain of transistor 1214) (one side) and the input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207 , are electrically connected. Here, the connection point is called node M1. The other electrode in a pair can be configured to receive a constant potential input. For example, low The configuration can be configured to receive either a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) as input. The other electrode of the pair of electrodes of the capacitive element 1207 is capable of supplying a low power supply potential. It is electrically connected to the wiring (e.g., the GND wire). Of the pair of electrodes of the capacitive element 1208 The other configuration can be one in which a constant potential is input. For example, a low power supply potential (GND). The configuration can be such that a high power supply potential (VDD, etc.) is input. Capacitive element 12 The other of the pair of electrodes in 08 is a wire capable of supplying a low power potential (e.g., GN It is electrically connected to the D line.

[0386] Capacitive elements 1207 and 1208 are used to reduce parasitic capacitance in transistors and wiring, etc. It is also possible to omit this by actively using [a specific method / technique].

[0387] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal R than control signal WE. D selects a conductive or non-conductive state between the first terminal and the second terminal, and one of them When there is conductivity between the first and second terminals of one switch, the first terminal of the other switch and The second terminal becomes non-conductive.

[0388] The source and drain of transistor 1209 are connected to the data held by circuit 1201. A signal corresponding to the traffic signal is input. In Figure 29, the signal output from circuit 1201 is the traffic signal. An example is shown where the source and drain of the inverter 1209 are input to the other side. Switch 1203 The signal output from the second terminal (the other of the source and drain of transistor 1213) is The logic value is inverted by the logic element 1206, becoming an inverted signal, and then transmitted through the circuit 1220. This is then input to circuit 1201.

[0389] Note that in Figure 29, the second terminal of switch 1203 (the source of transistor 1213 and The signal output from the other side of the drain is transmitted via logic element 1206 and circuit 1220. An example of input to circuit 1201 is shown, but it is not limited to this. The second terminal of switch 1203 The signal output from the child (the other side of the source and drain of transistor 1213) is the logical value It may be input to circuit 1201 without being inverted. For example, in circuit 1201 In the case where there exists a node that holds a signal inverted from the logical value of the signal input from the input terminal In addition, the second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from ) can be input to the node in question.

[0390] Furthermore, in Figure 29, among the transistors used in the memory element 1200, The transistors other than STA1209 are made of a layer or substrate 11 made of a semiconductor other than an oxide semiconductor. A transistor can be formed with a channel at 90. For example, a silicon layer or This can be a transistor in which a channel is formed on a silicon substrate. All transistors used in the child 1200 have channels formed by an oxide semiconductor layer. It can also be a transistor. Alternatively, the memory element 1200 is a transistor 1209 or higher. In addition, it may include transistors in which the channel is formed by an oxide semiconductor layer, and the rest The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be considered a transistor.

[0391] In Figure 29, circuit 1201 can be, for example, a flip-flop circuit. Furthermore, the logic element 1206 can be, for example, an inverter or a clocked inverter. It is possible.

[0392] In a semiconductor device according to one aspect of the present invention, while the memory element 1200 is not supplied with a power supply voltage, The data stored in circuit 1201 is transferred to the capacitive element 1208 provided in circuit 1202. Therefore, it can be retained.

[0393] Furthermore, transistors with channels formed in the oxide semiconductor layer exhibit extremely low off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer is due to its crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 1209, the memory element Even when power voltage is not supplied to 1200, the signal held in the capacitive element 1208 will remain for a long period of time. The memory element 1200 retains its stored contents even when the power supply voltage is interrupted. It is possible to retain data.

[0394] Furthermore, by providing switches 1203 and 1204, pre-charge Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, circuit 1201 This can shorten the time it takes to re-store the original data.

[0395] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is a transistor It is input to the gate of TA 1210. Therefore, the power supply voltage to memory element 1200 is restored. After opening, the signal held by the capacitive element 1208 is controlled by the state of transistor 1210. It can be converted to (on state or off state) and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal remains. It is possible to read the issue number accurately.

[0396] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. It is possible to restore the system to its state before the power supply was interrupted in a short time after the power supply voltage is restored. Therefore, it can be attributed to the entire processor, or to one of the components of the processor. Alternatively, in multiple logic circuits, power can be shut off even for a short time, thus reducing power consumption. It can suppress this.

[0397] In this embodiment, the memory element 1200 was described as an example of being used in a CPU, but the memory element 1200 is a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), etc. Also supports RFID (Radio Frequency Identification). It is usable.

[0398] For example, in this specification, it is possible to form transistors using various substrates. It will come. The type of circuit board is not limited to a specific one. One example of such a circuit board is a semi-circular one. Conductive substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, metal substrates, stainless steel substrates, stainless steel foil Substrates containing tungsten, tungsten substrates, substrates containing tungsten foil, flexible substrates, adhesive Examples include laminated films, paper containing fibrous materials, or base films. One example is a glass substrate. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples include glass. Flexible substrates, laminated films, and base films are examples of such materials. The following are examples: For example, polyethylene terephthalate (PET), polyethylene Plasti There are acrylics. Or, as an example, synthetic resins such as acrylic. Or, as an example, For example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Yes, there are. Or, as an example, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition. These include films and paper products. In particular, semiconductor substrates, single crystal substrates, or SOI substrates. By using this to manufacture transistors, variations in characteristics, size, or shape can be reduced. It is possible to manufacture transistors that are small, have high current capacity, and are small in size. When circuits are constructed using transistors, the power consumption of the circuit can be reduced, or the integration of the circuit can be increased. It is possible to measure this.

[0399] Furthermore, a flexible substrate is used as the substrate, and transistors are formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After partially or completely completing a semiconductor device, it is separated from the circuit board and transferred to another circuit board. It can be used in this way. In this case, the transistor can be used on substrates with poor heat resistance or flexible substrates. It can be mounted. Furthermore, the aforementioned release layer may include, for example, an inorganic tungsten film and a silicon oxide film. This method utilizes a layered film structure or a configuration in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0400] In other words, a transistor is formed using one substrate, and then the transistor is placed on another substrate. The transistor may be transposed and placed on a different substrate. As an example, in addition to the substrates on which the transistors described above can be formed, paper substrates, cellophane Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) (or recycled fibers (acetate, cupro, rayon, recycled polyester, etc.)) These include leather substrates and rubber substrates. By using these substrates, a tiger with good characteristics can be produced. Formation of transistors, formation of low-power transistors, manufacturing of durable devices, heat resistance This allows for the addition of features, weight reduction, or thinning of the material.

[0401] For example, if it is explicitly stated in this specification, etc., that X and Y are connected, , when X and Y are electrically connected, and when X and Y are functionally connected. This includes the case where X and Y are directly connected. Therefore, the given connection relationship For example, not limited to the connection relationships shown in the diagram or text, but the connections shown in the diagram or text This includes things other than relationships.

[0402] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0403] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which the current flows. It has a function to switch between them.

[0404] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc. ), voltage source, current source, switching circuit, amplification circuit (can increase signal amplitude or current amount, etc.) (Signal generators, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation It is possible to connect one or more (such as a circuit, memory circuit, control circuit, etc.) between X and Y. Yes. For example, even if another circuit is placed between X and Y, the signal output from X If a signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0405] Furthermore, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. If they are connected (that is, if X and Y are connected with another element or circuit in between) (when X and Y are functionally connected) and when X and Y are functionally connected (i.e., when there is no other circuit between X and Y) (When they are functionally connected with a sash in between) and when X and Y are directly connected (that is (including cases where X and Y are connected without another element or circuit in between) In other words, if you explicitly state that they are electrically connected, then simply say they are connected. This is equivalent to the case where it is explicitly stated that it is present.

[0406] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (or Without an intermediary, X is electrically connected, and the drain of the transistor (or the second terminal, etc.) is connected. If Y is electrically connected via (or without) Z2, or if the transistor's saw A part of Z1 (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are indirectly connected, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When they are connected and another part of Z2 is directly connected to Y, the following table It can be expressed.

[0407] For example, "X and Y and the source (or first terminal, etc.) and drain (or the first terminal) of the transistor" Terminals 2, etc., are electrically connected to each other, and X is the source of the transistor (or The electrical components are connected in the following order: the first terminal (or the second terminal), the transistor's drain (or the second terminal), and Y. It can be expressed as "connected to the source of the transistor (or The first terminal (or the second terminal) is electrically connected to X, and the drain of the transistor (or the second terminal) (etc.) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Y is electrically connected to X, via the drain (or second terminal, etc.) and X, and the trap Transistor source (or first terminal, etc.), transistor drain (or second terminal, etc.) It can be expressed as, "Y is provided in this connection order." By specifying the order of connections in a circuit configuration using various methods of expression, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the inverter are separated. The technical scope can be determined separately. Note that these expressions are just examples. The method of representation is not limited to these. Here, X, Y, Z1, and Z2 are the object (for example, equipment). (Examples include: placement, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.)

[0408] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0409] (Embodiment 5) A semiconductor device according to one aspect of the present invention is a display device, a personal computer, and a recording medium. Equipped with an image playback device (typically DVD: Digital Versatile Disc) (Used in a device that has a display capable of playing back recording media such as c and displaying the images thereof) This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention. Examples include mobile phones, portable game consoles, portable data terminals, e-readers, and video cameras. Cameras such as digital still cameras, goggle-type displays (head-mounted displays) Playback), navigation system, sound playback device (car audio, digital audio) (Optical players, etc.), photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 30. show.

[0410] Figure 30(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display Unit 904, microphone 905, speaker 906, operation key 907, stylus 90 It has 8, etc. Note that the portable game console shown in Figure 30(A) has two display units 903 and Although it has a display unit 904, the number of display units that a portable game console has is not limited to this. stomach.

[0411] Figure 30(B) shows a portable data terminal, consisting of a first housing 911, a second housing 912, and a first display unit. It has 913, a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 91 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. And the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing in the connection unit 915. The configuration may also be configured to switch according to the angle between 912 and 913. A display in which at least one of the and the second display unit 914 has a function as a position input device. A device may be used. Note that the function as a position input device is controlled by touching the display device. It can be added by installing a panel. Alternatively, the function as a position input device is It can also be added by installing a photoelectric conversion element, also called an optical sensor, in the pixel section of the display device. It is possible.

[0412] Figure 30(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, It includes a keyboard 923, a pointing device 924, and the like.

[0413] Figure 30(D) shows an electric refrigerator-freezer, consisting of a casing 931, a refrigerator door 932, and a freezer door 9 It has 33, etc.

[0414] Figure 30(E) shows a video camera, consisting of a first housing 941, a second housing 942, and a display unit 943. It has an operation key 944, a lens 945, a connecting part 946, etc. The operation key 944 and lens The Z945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. Yes. The video in the display unit 943 is connected to the first housing 941 and the second housing 9 in the connection unit 946. It could also be configured to switch according to the angle between 42 and 42.

[0415] Figure 30(F) is a regular passenger car, consisting of a body 951, wheels 952, dashboard 953, It has lights such as the 954.

[0416] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0417] (Embodiment 6) In this embodiment, an example of the use of an RF tag according to one aspect of the present invention will be shown with reference to Figure 31. Let me explain. RF tags have a wide range of applications, such as banknotes, coins, securities, and unmarked items. Bonds, certificates (such as driver's licenses and residence certificates, see Figure 31(A)), packaging containers (wrapping paper) (See Figure 31(C) for bottles, etc.), recording media (DVDs, videotapes, etc., see Figure 31(B)). (See Figure 31(D)), vehicles (bicycles, etc.), personal belongings (bags, glasses, etc.), food items, Plants, animals, human bodies, clothing, household goods, medical products including drugs and pharmaceuticals, or electronic devices ( Articles such as liquid crystal displays, EL displays, television equipment, or mobile phones, or It can be used by attaching it to luggage tags (see Figures 31(E) and 31(F)) etc. that are attached to each item. can.

[0418] An RF tag 4000 according to one aspect of the present invention can be attached to or embedded on a surface. It is fixed to an object. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. If so, it is embedded inside the organic resin and fixed to each article. RF type according to one aspect of the present invention The G4000 achieves a small, thin, and lightweight design, and even after being fixed to an object, it does not affect the object itself. It does not impair the design. Also, banknotes, coins, securities, bearer bonds, or certificates. By attaching an RF tag 4000 according to one aspect of the present invention to documents, etc., an authentication function is provided. This authentication function can be used to prevent counterfeiting. The present invention applies to utensils, recording media, personal belongings, food products, clothing, household goods, or electronic devices, etc. By attaching RF tags according to one embodiment, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RF tag according to one aspect of the present invention to vehicles as well. This can enhance security against theft and other crimes.

[0419] As described above, the RF tag according to one aspect of the present invention can be used for each of the applications listed in this embodiment. This reduces the operating power, including the power required for writing and reading information, thus extending the maximum communication distance. It becomes possible to store information for a long period of time. Furthermore, even when the power is cut off, information can be stored for an extremely long period of time. Because it can retain data for extended periods, it can be suitably used in applications where the frequency of writing and reading is low. Cut.

[0420] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0421] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other content (even partial content) described in form, and / or one or more other facts The content described in the form of implementation (even if only a part of it) may be applied, combined, or replaced. It is possible to perform tasks such as drawing.

[0422] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0423] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. , other figures (even partial ones) described in the embodiment, and / or one or more In the diagram (or even just a part of it) described in another embodiment of the number, by combining them... This allows for the creation of even more diagrams.

[0424] Furthermore, any content not specified in the drawings or text within the specification will be excluded. This can constitute one embodiment of the invention that specifies that, or, for a certain value, an upper limit When a numerical range is specified, such as a value and a lower limit, you can arbitrarily narrow that range. Or, by excluding one point within that scope, one aspect of the invention that excludes part of that scope is defined. This can be determined. For example, the prior art falls within the technical scope of one aspect of the present invention. It is possible to specify that it does not fall under this category.

[0425] A concrete example is a circuit diagram that uses transistors 1 through 5 in a certain circuit. Let's assume that it is described. In that case, the circuit does not have a sixth transistor. It is possible to define the following as an invention. Or, the circuit does not have a capacitive element. It is possible to define that the circuit takes a certain connection structure. The invention can be defined as not having a sixth transistor like the one present. Alternatively, the circuit does not have capacitive elements that have a certain connection structure. The invention can be defined as follows: For example, the gate is in contact with the gate of the third transistor. It is possible to define the invention as not having a sixth transistor that is subsequently connected. Alternatively, for example, a capacitive element in which the first electrode is connected to the gate of the third transistor It is possible to define the invention as not possessing such a feature.

[0426] Another concrete example is, for a certain value, for example, "a certain voltage is between 3V and 10V." Let's say it is stated that "it is preferable that there is a certain voltage." In that case, for example, if a certain voltage is -2 It is possible to define one aspect of the invention as "except when V is greater than or equal to 1V." For example, one aspect of the invention can be defined as "except when a certain voltage is 13V or higher." It is possible. Furthermore, for example, the invention could be defined as having a voltage of 5V or more and 8V or less. This is also possible. Furthermore, for example, the invention could be defined as having a voltage of approximately 9V. That is the case. However, for example, the voltage is between 3V and 10V, but is 9V. It is also possible to define the invention in this way. Furthermore, for a certain value, it is stated that "it is within this range." If it was stated that "it is preferable" or "it is preferable to satisfy these conditions", However, certain values ​​are not limited to those listed. In other words, "preferred" or "suitable" Even if it is stated otherwise, it is not necessarily limited to those statements.

[0427] Another concrete example would be, for a certain value, for example, "It is preferable that a certain voltage is 10V." Let's assume it is stated as "suitable". In that case, for example, if a certain voltage is between -2V and 1V It is possible to define one aspect of the invention as, except in the case below. Or, for example, a It is possible to define one aspect of the invention as "except when the voltage is 13V or higher."

[0428] Another concrete example is describing the properties of a certain substance, for instance, "A certain film is an insulating film." Let's assume it is stated as follows. In that case, for example, except when the insulating film is an organic insulating film. It is possible to define one aspect of the invention as follows: or, for example, the insulating film is inorganic It is possible to define one aspect of the invention as "except when it is an insulating film." Or, for example, It is possible to define one aspect of the invention as, except when the film is a conductive film. Alternatively, one aspect of the invention may be defined as, for example, except when the film is a semiconductor film. It is possible.

[0429] Another concrete example is a layered structure, for example, "a certain film between film A and film B." It is stated that "a film is provided." In that case, for example, if the film is made up of four or more layers The invention can be defined as "except in the case of a multilayer film." Or, for example, film A and It is possible to define the invention as "except in cases where a conductive film is provided between that film and the other film." ru.

[0430] Furthermore, one aspect of the invention described herein may be implemented by various people. This is possible. However, its implementation may involve multiple people. For example, in the case of a transmission and reception system, Company A manufactures and sells the transmitter, and Company B manufactures the receiver. They may manufacture and sell machines. Another example is having transistors and light-emitting elements. In the case of a light-emitting device, the semiconductor device on which the transistor is formed is manufactured by Company A. They will buy and sell it. Then, Company B will purchase the semiconductor device and add a light-emitting element to it. In some cases, the material is made into a film and then completed as a light-emitting device.

[0431] In such a case, it would be possible to claim patent infringement against either Company A or Company B. One aspect of the invention can be constructed. That is, one aspect of the invention that only Company A would implement. It is possible to construct such an invention, and as another aspect of the invention, an invention that is implemented only by Company B. It is possible to constitute one aspect of this. Furthermore, it is possible to assert patent infringement against Company A or Company B. One aspect of the invention that can be made is clear and is deemed to be described in this specification, etc. Yes, it is possible. For example, in the case of a transmission / reception system, it is possible to describe the case with only the transmitter, or the case with the receiver. Even if there is no description of such a case in this specification, the transmitter alone constitutes one aspect of the invention. It is possible to constitute one aspect of another invention with only a receiver, and one aspect of those inventions The description is clear and can be judged as being described in this specification, etc. In the case of a light-emitting device having a transistor and a light-emitting element, the transistor is formed This document describes the case where only semiconductor devices are used, or where only light-emitting devices with light-emitting elements are used. Even if not specified in the specification, the semiconductor device on which the transistor is formed alone constitutes one aspect of the invention. It is possible to construct one aspect of the invention using only a light-emitting device having a light-emitting element. It is possible, and one aspect of those inventions is clearly described in this specification, etc. It is possible.

[0432] In this specification, active elements (transistors, diodes, etc.) and passive elements are used. For all terminals of components such as capacitive and resistive elements, specify their connection destinations. Even without this, a person skilled in the art may be able to constitute one aspect of the invention. Even without specifying the destination, one aspect of the invention can be said to be clear. And the destination of the connection is specified. If the content described herein is included, then one aspect of the invention that does not specify the connection destination is considered to be in accordance with the present invention. In some cases, it may be possible to determine that this information is described in the detailed documentation. This is especially true when there are multiple connection points for the terminal. In cases where this is a possibility, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, active elements (transistors, diodes, etc.), passive elements (capacitive elements, resistive elements) By specifying the connection destination for only some of the terminals that such as (etc.) have, the invention It may be possible to constitute one aspect of this.

[0433] Furthermore, in this specification, etc., if a certain circuit is specified, then at least the connection destination is identified. If you are a professional, you may be able to identify the invention. Or, regarding a certain circuit, Even without specifying the function, a person skilled in the art may be able to identify the invention. In other words, if the function is specified, then one aspect of the invention can be said to be clear. In some cases, it may be possible to determine that one aspect of the invention described herein is included in this specification. Therefore, for a given circuit, even without specifying its function, if the connection destination is specified, one can identify the invention. This is disclosed as an embodiment and can constitute one aspect of the invention. In a given circuit, even without specifying the connection destination, if the function is specified, it can be considered one aspect of the invention. This is disclosed and can constitute one aspect of the invention.

[0434] In this specification, etc., the figures or text described in a particular embodiment may differ from the actual figures or text. Therefore, it is possible to take a part of it and constitute one aspect of the invention. If a diagram or text describing a particular part is included, then a portion of that diagram or text may be taken. The content disclosed is also disclosed as one aspect of the invention and constitutes one aspect of the invention. It is possible to do so. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements) (e.g., resistive elements), conductive layer, insulating layer, semiconductor layer, organic material, inorganic material, component, device, operation In drawings or documents describing one or more methods, manufacturing methods, etc., a part thereof It is possible to extract N items and constitute one aspect of the invention. For example, N items (N From a circuit diagram having circuit elements (such as transistors and capacitor elements) (where is an integer), it is possible to extract M (where M is an integer and M < N) circuit elements (such as transistors and capacitor elements) and form one aspect of the invention. As another example, from a cross-sectional view having N (where N is an integer) layers it is possible to extract M (where M is an integer and M < N) layers and form one aspect of the invention. As yet another example, from a flowchart having N (where N is an integer) elements it is possible to extract M (where M is an integer and M < N) elements and form one aspect of the invention. As yet another example, from a sentence described as "A has B, C, D, E, or F", by arbitrarily extracting some elements, it is possible to form one aspect of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E". [[ID=ll]]<0oo3418>

[0435] In addition, in this specification and the like, when at least one specific example is described in a figure or sentence described in a certain embodiment, those skilled in the art can easily derive the upper concept of that specific example. Therefore, when at least one specific example is described in a figure or sentence described in a certain embodiment, the upper concept of that specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And it can be said that that aspect of the invention is clear.

[0436] In addition, in this specification and the like, at least the content described in the figure (even a part of the figure)

[0437] is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if a certain content is described in a diagram, it can be described using text. Even if it is not disclosed, the content is disclosed as one aspect of the invention, and one aspect of the invention It is possible to construct it. Similarly, a diagram showing a part of the figure is also one embodiment of the invention. This is disclosed as such, and it can constitute one aspect of the invention. One aspect of the invention can be said to be clear. [Explanation of Symbols]

[0437] 101j semiconductor layer 101j_a Semiconductor layer 101j_b semiconductor layer 101j_c Semiconductor layer 102j gate insulator 103j gate 104 Conductive film 104j_a Conductive layer 104j_b Conductive layer 105j conductive layer 111 Barrier film 112j insulating film 113j insulating film 114j insulating film 115j insulating film 116j insulating film 130a transistor 130b Transistor 131 Semiconductor substrates 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 Grid gate 136 Insulating film 137 Insulating Film 138 Insulating film 141j plug 142j plug 143j plug 144j plug 145j plug 146j plug 147j plug 148j plug 151j conductive layer 152j conductive layer 153 Conductive film 153j conductive layer 154j conductive layer 156j insulating film 171j_a Low resistance area 171j_b Low resistance region 176a area 176b area 190 transistors 198 transistors 199 transistors 201j semiconductor layer 201j_a Semiconductor layer 201j_b Semiconductor layer 201j_c Semiconductor layer 202j gate insulating film 203j tter 204j Conductive film 204j_a Conductive layer 204j_b Conductive layer 205j conductive layer 212j insulating film 213j insulating film 214j insulating film 216j insulating film 230a Transistor 230b Transistor 232 Semiconductor layer 233a Low resistance layer 233b Low resistance layer 235 Terminal 300 memory cell array 500 Peripheral Circuits 700 Semiconductor Equipment 800 RF tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 cabinet 912 cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive element 1208 Capacitive element 1209 Transistors 1210 Transistors 1213 Transistors 1214 Transistors 1220 Circuit 2100 transistors 2200 transistors 4000 RF tags 5100 pellets 5120 circuit board 5161 area

Claims

1. It has a first circuit, a second circuit, a first wiring, a second wiring, and a third wiring. The first circuit and the second circuit each include a first transistor, a second transistor, and a capacitor. The source or drain of the first transistor in the first circuit is electrically connected to the first wiring. The source or drain of the first transistor in the first circuit is electrically connected to the second wiring. The source or drain of the first transistor in the second circuit is electrically connected to the first wiring. The source or drain of the first transistor in the second circuit is electrically connected to the third wiring. The gate of the first transistor in the first circuit is electrically connected to either the source or the drain of the second transistor in the first circuit. The source or drain of the second transistor in the first circuit is electrically connected to the second wiring. The gate of the first transistor in the second circuit is electrically connected to either the source or the drain of the second transistor in the second circuit. The source or drain of the second transistor in the second circuit is electrically connected to the third wiring. The capacitance of the first circuit has the function of maintaining the gate potential of the first transistor of the first circuit. The capacitance of the second circuit has the function of maintaining the gate potential of the first transistor of the second circuit. The gate of the first transistor in the first circuit is input with a potential corresponding to the first data. A semiconductor device is provided, in which the gate of the first transistor in the second circuit is input with a potential corresponding to the second data, It comprises a first semiconductor layer, a first insulating layer, a first conductive layer, a second conductive layer, a second insulating layer, a second semiconductor layer, and a third insulating layer. The first semiconductor layer has a channel formation region for the first transistor, The first insulating layer has a region located above the first semiconductor layer, The first conductive layer has a region located above the first insulating layer, The first conductive layer functions as one of the pair of electrodes of the capacitance, The second conductive layer functions as the other of the pair of electrodes with the capacitance, The second insulating layer has a region located above the second conductive layer, The second semiconductor layer has a region located above the second insulating layer, The second semiconductor layer has a channel formation region for the second transistor. The third insulating layer has a region located above the second semiconductor layer, The first wiring has a region that penetrates the third insulating layer, a region that penetrates the second insulating layer, and a region that penetrates the first insulating layer. The second wiring has a region that penetrates the third insulating layer, a region that penetrates the second insulating layer, and a region that penetrates the first insulating layer. The third wiring has a region that penetrates the third insulating layer, a region that penetrates the second insulating layer, and a region that penetrates the first insulating layer. A semiconductor device wherein a region of the first conductive layer that overlaps with the second conductive layer overlaps with the first semiconductor layer.

2. It has a first circuit, a second circuit, a first wiring, a second wiring, and a third wiring. The first circuit and the second circuit each include a first transistor, a second transistor, and a capacitor. The source or drain of the first transistor in the first circuit is electrically connected to the first wiring. The source or drain of the first transistor in the first circuit is electrically connected to the second wiring. The source or drain of the first transistor in the second circuit is electrically connected to the first wiring. The source or drain of the first transistor in the second circuit is electrically connected to the third wiring. The gate of the first transistor in the first circuit is electrically connected to either the source or the drain of the second transistor in the first circuit. The source or drain of the second transistor in the first circuit is electrically connected to the second wiring. The gate of the first transistor in the second circuit is electrically connected to either the source or the drain of the second transistor in the second circuit. The source or drain of the second transistor in the second circuit is electrically connected to the third wiring. The capacitance of the first circuit has the function of maintaining the gate potential of the first transistor of the first circuit. The capacitance of the second circuit has the function of maintaining the gate potential of the first transistor of the second circuit. The gate of the first transistor in the first circuit is input with a potential corresponding to the first data. A semiconductor device is provided, in which the gate of the first transistor in the second circuit is input with a potential corresponding to the second data, It comprises a first semiconductor layer, a first insulating layer, a first conductive layer, a second conductive layer, a second insulating layer, a second semiconductor layer, and a third insulating layer. The first semiconductor layer has a channel formation region for the first transistor, The first insulating layer has a region located above the first semiconductor layer, The first conductive layer has a region located above the first insulating layer, The first conductive layer functions as one of the pair of electrodes of the capacitance, The second conductive layer functions as the other of the pair of electrodes with the capacitance, The second insulating layer has a region located above the second conductive layer, The second semiconductor layer has a region located above the second insulating layer, The second semiconductor layer has a channel formation region for the second transistor. The third insulating layer has a region located above the second semiconductor layer, The first wiring has a region that penetrates the third insulating layer, a region that penetrates the second insulating layer, and a region that penetrates the first insulating layer. The second wiring has a region that penetrates the third insulating layer, a region that penetrates the second insulating layer, and a region that penetrates the first insulating layer. The third wiring has a region that penetrates the third insulating layer, a region that penetrates the second insulating layer, and a region that penetrates the first insulating layer. The region of the first conductive layer that overlaps with the second conductive layer has an overlap with the first semiconductor layer. A semiconductor device in which, in a cross-sectional view taken along the direction connecting the source and drain of the first transistor, the first wiring is arranged between the second wiring and the third wiring.

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