Receiving circuit

Abstract

To provide a receiving circuit that is suppressed in deterioration in noise characteristics thereof within a range of small input current, and furthermore can suppress increase in offset of a differential signal.SOLUTION: A receiving circuit comprises: a first transimpedance amplifier that receives a first input current and outputs a first voltage; a second transimpedance amplifier that receives a second input current and outputs a second voltage; a first reference voltage circuit that generates a first reference voltage depending on a first feedback current; a second reference voltage circuit that generates a second reference voltage depending on a third feedback current; first and second offset control circuits; and a differential amplifier circuit that outputs a differential signal depending on the first and second voltages. The first offset control circuit adjusts the first feedback current depending on an average voltage value of the first voltage, or alternatively, subtracts a second feedback current from the first input current. The second offset control circuit adjusts the third feedback current depending on an average voltage value of the second voltage, or alternatively, subtracts a fourth feedback current from the second input current.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0001] The present disclosure relates to a receiving circuit.

Background Art

[0002] A receiving circuit used in optical communication receives a current signal converted from an optical signal by a photodiode or the like as an input current, and converts the received current signal into a voltage signal by a transimpedance amplifier. Further, a receiving circuit that outputs a differential voltage signal may have an automatic offset control circuit that compensates for an offset generated in the differential voltage signal. The automatic offset control circuit extracts a part of the input current to compensate for the offset. For example, the automatic offset control circuit controls the amount of extraction from the input current so that the magnitude of the offset becomes smaller.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, if extraction is performed even when the input current is close to zero in order to compensate for the offset with respect to the input current within the receivable range, the noise characteristics of the receiving circuit may deteriorate. Further, if extraction from the input current is stopped in a range where the input current value is small in order to suppress deterioration of the noise characteristics, there is a risk that the offset cannot be compensated.

[0005] Therefore, an object of the present disclosure is to provide a receiving circuit capable of suppressing deterioration of noise characteristics in a range where the input current value is small and suppressing an increase in the offset between the voltage of the voltage signal converted from the input current and the reference voltage.

Means for Solving the Problems

[0007] According to this disclosure, it is possible to provide a receiving circuit that can suppress the deterioration of noise characteristics in a range of small input current values, while suppressing the increase in the offset between the voltage of the voltage signal converted from the input current and the reference voltage. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing an example of a receiving circuit according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the transimpedance amplifier stage in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing an example of the automatic offset control circuit shown in Figure 1. [Figure 4] Figure 4 shows the DC transfer characteristics of the automatic offset control circuit shown in Figure 3. [Figure 5] Figure 5 shows an example of the operating characteristics of the receiving circuit in Figure 1. [Figure 6] Figure 6 is a block diagram showing an example of a receiving circuit according to the second embodiment. [Figure 7] Figure 7 is a circuit diagram showing an example of the automatic offset control circuit shown in Figure 6. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0010] [1] A receiving circuit according to one aspect of the present disclosure comprises: a first input terminal for receiving a first input current; a first transimpedance amplifier having a first input node for converting a first current signal input to the first input node into a first voltage signal; a first reference voltage circuit for generating a first reference voltage according to a first feedback current; a first offset control circuit for generating a first feedback current and a second feedback current according to an offset between the first voltage signal and the first reference voltage; a second input terminal for receiving a second input current; a second transimpedance amplifier having a second input node for converting a second current signal input to the second input node into a second voltage signal; a second reference voltage circuit for generating a second reference voltage according to a third feedback current; a second offset control circuit for generating a third feedback current and a fourth feedback current according to an offset between the second voltage signal and the second reference voltage; and a differential amplifier circuit for generating a differential signal according to the voltage difference between the first voltage signal and the second voltage signal, wherein the first input node is the The first input node is electrically connected to the first input terminal, and the second input node is electrically connected to the second input terminal. The first offset control circuit adjusts the first feedback current so that the offset between the first voltage signal and the first reference voltage falls within a predetermined range when the average voltage value of the first voltage signal is greater than the first reference voltage, and subtracts the second feedback current from the first input current so that the offset between the first voltage signal and the first reference voltage falls within the predetermined range when the average voltage value of the first voltage signal is less than the first reference voltage. The second offset control circuit adjusts the third feedback current so that the offset between the second voltage signal and the second reference voltage falls within a predetermined range when the average voltage value of the second voltage signal is greater than the second reference voltage, and subtracts the fourth feedback current from the second input current so that the offset between the second voltage signal and the second reference voltage falls within the predetermined range when the average voltage value of the second voltage signal is less than the second reference voltage.

[0011] In this receiving circuit, the second feedback current is not flowed when the average voltage value of the first voltage signal is greater than the first reference voltage. Therefore, noise degradation in the range of small first input current values ​​can be suppressed while suppressing the increase in the offset between the voltage of the first voltage signal and the first reference voltage. Furthermore, the fourth feedback current is not flowed when the average voltage value of the second voltage signal is greater than the second reference voltage. Therefore, noise degradation in the range of small second input current values ​​can be suppressed while suppressing the increase in the offset between the voltage of the second voltage signal and the second reference voltage. Consequently, in a receiving circuit that generates a differential signal according to the received first and second input currents, noise degradation in the range of small input current values ​​can be suppressed while suppressing the increase in the offset between the voltage of the voltage signal converted from the input current and the reference voltage.

[0012] [2] In the above [1], the first transimpedance amplifier may include a first amplification circuit that converts a first current signal input to the first input node into a first intermediate voltage signal, and a first level shift circuit comprising a first resistive element and a first current source, which generates a first voltage signal by level shifting the first intermediate voltage signal using the voltage drop caused by the first current supplied by the first current source flowing through the first resistive element. By level shifting the first intermediate voltage signal from the first amplification circuit and supplying it to the differential amplification circuit, the voltage value of the first voltage signal can be set to a voltage range that allows the differential amplification circuit to operate appropriately. As a result, the differential amplification circuit can generate an appropriate differential signal according to the input current.

[0013] [3] In [2] above, the first reference voltage circuit includes a second amplifier circuit that generates a first reference voltage, a second resistor element, and a second current source, and a second level shift circuit that generates the first reference voltage by level-shifting the first reference voltage by a voltage drop generated when a second current supplied by the second current source flows through the second resistor element. The first feedback current may flow through the second resistor element in the same direction as the flow direction of the second current. By flowing the first feedback current from the first offset control circuit through the second resistor element in the same direction as the flow direction of the second current, it is possible to suppress an increase in the offset between the voltage of the first voltage signal and the first reference voltage while suppressing noise degradation in a range where the first input current value is small.

[0014] [4] In [2] above, the first reference voltage circuit includes a second amplifier circuit that generates a first reference voltage, a second resistor element, and a second current source, and a second level shift circuit that generates the first reference voltage by level-shifting the first reference voltage by a voltage drop generated when a second current supplied by the second current source flows through the second resistor element. The first offset control circuit may draw the first feedback current from an input node of the second amplifier circuit. By drawing the first feedback current from the input node of the second amplifier circuit by the first offset control circuit, it is possible to suppress an increase in the offset between the voltage of the first voltage signal and the first reference voltage by adjusting the input voltage of the second amplifier circuit.

[0015] [5] In [3] or [4] above, the second amplifier circuit may be composed of the same circuit elements as the first amplifier circuit. Thereby, it is possible to accurately adjust the offset between the voltage of the first voltage signal and the first reference voltage. In addition, since common design data can be used, the circuit design of the receiving circuit can be simplified.

[0016] [6] In any of [1] to [5] above, the first offset control circuit includes a differential integrator that generates a control voltage according to the offset between the first voltage signal and the first reference voltage, and the magnitude relationship between the magnitude of the first feedback current and the magnitude of the second feedback current may be reversed according to the control voltage. Thereby, based on the control voltage generated by the differential integrator according to the first voltage signal that changes depending on the first input current, the generation and switching of the first feedback current and the second feedback current can be controlled.

[0017] [7] In any of [1] to [6] above, the value of the first reference voltage when the first feedback current is zero is set to be smaller than the average voltage value of the first voltage signal when the first current signal is zero, and the value of the second reference voltage when the first feedback current is zero may be set to be smaller than the average voltage value of the second voltage signal when the second current signal is zero.

[0018] Thereby, when the first input signal is small and the average voltage value of the first voltage signal is larger than the first reference voltage, the first offset control circuit adjusts the first feedback current, and when the first input signal becomes large and the average voltage value of the first voltage signal is smaller than the first reference voltage, the second feedback current is adjusted to perform automatic offset control to suppress an increase in the offset between the voltage of the first voltage signal and the first reference voltage. Also, when the second input signal is small and the average voltage value of the second voltage signal is larger than the second reference voltage, the second offset control circuit adjusts the third feedback current, and when the second input signal becomes large and the average voltage value of the second voltage signal is smaller than the second reference voltage, the fourth feedback current is adjusted to perform automatic offset control to suppress an increase in the offset between the voltage of the second voltage signal and the second reference voltage.

[0019] [8] In any of [1] to [7] above, the first transimpedance amplifier, the first reference voltage circuit, the second transimpedance amplifier, the second reference voltage circuit, the first offset control circuit, the second offset control circuit, and the differential amplifier circuit may be integrated on a single semiconductor integrated circuit chip. This reduces variations in electrical characteristics between multiple circuits formed using the same elements. As a result, the accuracy of adjusting the offset between the voltage of the first voltage signal and the first reference voltage by the first offset control circuit can be improved. Furthermore, the accuracy of adjusting the offset between the voltage of the second voltage signal and the second reference voltage by the second offset control circuit can be improved.

[0020] [Details of the embodiments of this disclosure] A specific example of the receiving circuit of this disclosure will be described below with reference to the drawings. In the following description, the same or corresponding elements will be denoted by the same reference numeral, and their descriptions may be omitted. In addition, the numerals for terminals, signal lines, and nodes will also be used to indicate signals, voltages, or currents.

[0021] [First Embodiment] [Circuit configuration of the receiving circuit] Figure 1 is a block diagram showing an example of the configuration of a receiving circuit according to the first embodiment. For example, the receiving circuit 100 shown in Figure 1 is included in an optical receiver that receives an optical signal. The receiving circuit 100 has input terminals InP / InN that receive a pair of input currents IinP / IinN, and output terminals OutN / OutP that output voltage signals amplified according to the pair of input currents IinP / IinN as differential signals OutN / OutP.

[0022] For example, an optical receiver used in a digital coherent optical communication system generates a pair of mutually orthogonal optical signals by interfering the received light transmitted through the optical fiber cable with the local light emitted within the optical receiver, and inputs the generated pair of optical signals to a pair of photodetectors to generate a pair of current signals. The input terminals InP / InN of the receiving circuit 100 can receive such a pair of current signals as a pair of input currents IinP / IinN. The receiving circuit 100 outputs a voltage signal as a differential signal OutN / OutP. The differential signal OutN / OutP has a pair of output signals OutP and OutN.

[0023] One of the pair of output signals, OutP, is also called the positive-sequence signal, and the other, OutN, is also called the negative-sequence signal. The positive-sequence signal OutP and the negative-sequence signal OutN are complementary signals, and the positive-sequence signal OutP has a phase that is 180° different from the phase of the negative-sequence signal OutN. For example, when the positive-sequence signal OutP increases, the negative-sequence signal OutN decreases, and when the positive-sequence signal OutP decreases, the negative-sequence signal OutN increases. For example, when the positive-sequence signal OutP reaches its peak value, the negative-sequence signal OutN reaches its bottom value, and when the positive-sequence signal OutP reaches its bottom value, the negative-sequence signal OutN reaches its peak value. For example, the negative-sequence signal OutN has the same amplitude as the positive-sequence signal OutP.

[0024] When offset compensation is not performed, the receiving circuit 100 decreases the voltage value (DC component) of the output signal OutN when the average value (DC component) of the input current IinP increases, and increases the voltage of the output signal OutN (DC component) when the average value (DC component) of the input current IinP decreases.

[0025] As a result, the receiving circuit 100 increases the voltage difference between the differential signals OutN and OutP when the average difference between the input currents IinP and IinN increases, and decreases the voltage difference between the differential signals OutN and OutP when the average difference between the input currents IinP and IinN decreases. More specifically, the receiving circuit 100 reduces the difference between the voltage value (DC component) of the output signal OutP and the voltage value (DC component) of the output signal OutN by performing offset compensation. The offset represents the difference between the voltage value (DC component) of the output signal OutP and the voltage value (DC component) of the output signal OutN.

[0026] In other words, offset compensation means bringing the offset closer to zero. The receiving circuit 100 amplifies the signal component (AC component) of the input current and converts it into a voltage signal, outputting it as the signal component (AC component) of the differential signal OutN / OutP. The amplitude of the signal component of the differential signal OutN / OutP is equal to the difference between the signal component of the positive-sequence signal OutP and the signal component of the negative-sequence signal OutN. For example, if the amplitude of the signal component of the input current Iin increases, the amplitude of the signal component of the differential signal OutN / OutP also increases. The differential signal OutN / OutP output from the output terminals OutN / OutP is output to a signal processing circuit such as a DSP (Digital Signal Processor) and processed.

[0027] The receiving circuit 100 includes, for example, a transimpedance amplifier stage TIAP, a level shift circuit LS1N, a dummy transimpedance amplifier stage DTIAP, a level shift circuit LS2N, and an automatic offset control circuit AOC1. Furthermore, the receiving circuit 100 includes, for example, a transimpedance amplifier stage TIAN, a level shift circuit LS1P, a dummy transimpedance amplifier stage DTIAN, a level shift circuit LS2P, and an automatic offset control circuit AOC2. Additionally, the receiving circuit 100 includes buffers BUF1 and BUF2 and an automatic offset control circuit AOC3.

[0028] For example, each circuit of the receiving circuit 100 is integrated onto a single semiconductor integrated circuit chip. This reduces variations in electrical characteristics between multiple circuits formed using the same circuit elements. For instance, by making the transimpedance amplifier stage TIAP and the dummy transimpedance amplifier stage DTIAP have similar circuit configurations, the influence of variations in their respective electrical characteristics can be reduced. Similarly, by making the level shift circuits LS1N and LS2N have similar circuit configurations, the influence of variations in their respective electrical characteristics can be reduced. As a result, the accuracy of the DC (Direct Current) offset adjustment of voltage VtiaN and reference voltage VrefN by the automatic offset control circuit AOC1 can be improved.

[0029] Alternatively, the transimpedance amplifier stage TIAP and the dummy transimpedance amplifier stage DTIAP may be configured with the same circuit configuration to ensure that their electrical characteristics are identical. Furthermore, the transimpedance amplifier stage TIAN and the dummy transimpedance amplifier stage DTIAN may be configured with the same circuit configuration to ensure that their electrical characteristics are identical.

[0030] Furthermore, the transimpedance amplifier stages TIAP and TIPN and the dummy transimpedance amplifier stages DTIAP and DTIAN may have the same circuit configuration as each other. Level shift circuits LS1N and LS2N may have the same circuit configuration as each other so that their electrical characteristics are the same. Also, level shift circuits LS1P and LS2P may have the same circuit configuration as each other so that their electrical characteristics are the same. Furthermore, level shift circuits LS1N, LS2N, LS1P, and LS2P may have the same circuit configuration as each other.

[0031] Similarly, by making the transimpedance amplifier stage TIAN and the dummy transimpedance amplifier stage DTIAN have similar circuit configurations, the influence of variations in their respective electrical characteristics can be reduced. Furthermore, by making the level shift circuits LS1P and LS2P have similar circuit configurations, the influence of variations in their respective electrical characteristics can be reduced. As a result, the accuracy of the DC offset adjustment between voltage VtiaP and reference voltage VrefP by the automatic offset control circuit AOC2 can be improved.

[0032] The transimpedance amplifier stage TIAP and level shift circuit LS1N are examples of a first transimpedance amplifier. The dummy transimpedance amplifier stage DTIAP and level shift circuit LS2N are examples of a first reference voltage circuit. The transimpedance amplifier stage TIAP is an example of a first amplification circuit. The dummy transimpedance amplifier stage DTIAP is an example of a second amplification circuit that generates a first reference voltage.

[0033] The transimpedance amplifier stage TIAN and level shift circuit LS1P are examples of a second transimpedance amplifier. The dummy transimpedance amplifier stage DTIAN and level shift circuit LS2P are examples of a second reference voltage circuit. Buffers BUF1 and BUF2 are examples of differential amplifier circuits. Hereafter, the transimpedance amplifier stages TIAP and TIAN will also be simply referred to as the TIAP stage and TIAN stage, respectively. The dummy transimpedance amplifier stages DTIAP and DTIAN will also be simply referred to as the DTIAP stage and DTIAN stage, respectively.

[0034] The TIAP stage includes an inverter amplifier INVP1 and a resistor RP1. The input of the inverter amplifier INVP1 is electrically connected to the input terminal InP via the input node TIAPin of the TIAP stage. The output of the inverter amplifier INVP1 is connected to the level shift circuit LS1N via the output node TIAPout of the TIAP stage. The resistor RP1 is connected between the input node TIAPin and the output node TIAPout.

[0035] The TIAP stage converts the input current IinP input to the input node TIAPin into a voltage signal using an inverter amplifier INVP1 and a resistor RP1, amplifies it through inversion, and outputs the inverted amplified voltage signal to the output node TIAPout. The inverter amplifier INVP1 is, for example, an inverting amplifier circuit. For example, when the input current IinP increases, the voltage output to the output node TIAPout decreases, and when the input current IinP decreases, the voltage output to the output node TIAPout increases. The gain of the TIAP stage is expressed as impedance (resistance value). The gain of the TIAP stage is mainly determined by the resistance value of the resistor RP1.

[0036] The level shift circuit LS1N includes, for example, a resistor RLS1N, a capacitive element CLS1N, and a current source ILS1N. The resistor RLS1N and the capacitive element CLS1N are connected in parallel between the output node TIAPout of the TIAP stage and node VtiaN, which is connected to one input of buffer BUF1. The current source ILS1N is connected between the power line VCC and node VtiaN.

[0037] The level shift circuit LS1N generates a voltage signal VtiaN by shifting the voltage signal TIAPout output from the TIAP stage to a higher potential side due to the voltage drop across the resistor RLS1N caused by the current supplied by the current source ILS1N flowing through it. The voltage signal TIAPout is an example of a first intermediate voltage signal. The capacitive element CLS1N transmits the high-frequency components of the signal input to the level shift circuit LS1N to the output faster than the resistor RLS1N. For example, the falling edge and degradation of the falling edge of the pulse wave that is level shifted by the level shift circuit LS1N are suppressed by the capacitive element CLS1N. The capacitive element CLS1N is a so-called speed-up capacitor.

[0038] The current source ILS1N can be constructed, for example, by a p-channel MOS (Metal Oxide Semiconductor) transistor. Furthermore, to adjust the amount of current supplied, the current source ILS1N may be constructed using a current mirror circuit including a p-channel MOS transistor. Alternatively, the current source ILS1N may be constructed using a resistive element instead of a p-channel MOS transistor.

[0039] This allows the average output voltage of the level shift circuit LS1N to be greater than the average input voltage of the level shift circuit LS1N. The level shift circuit LS1N then sets the voltage of the voltage signal VtiaN input to buffer BUF1 to a voltage range necessary for buffer BUF1 to operate properly.

[0040] For example, the signal component of the voltage signal VtiaN, which is generated in response to the signal component of the input current IinP, is superimposed on the voltage value (average value) of the voltage signal VtiaN and input to the buffer BUF. Note that the current from the current source ILS1N flows into the TIAP stage, but the current flowing from the current source ILS1N into the TIAP stage is canceled out by increasing the current amount of the internal current source (ITIA in Figure 2) of the TIAP stage.

[0041] Alternatively, instead of increasing the current of the internal current source in the TIAP stage, a current source may be added between the input node of the level shift circuit LS1N connected to the output node TIAPout and the ground line GND, and current from the current source ILS1N may be passed through this current source. This added current source can be configured, for example, by an n-channel MOS transistor. To adjust the current amount, it may also be configured by a current mirror circuit including an n-channel MOS transistor. Alternatively, the added current source may be configured using a resistor instead of an n-channel MOS transistor.

[0042] The DTIAP stage has the same circuit configuration as the TIAP stage, except that no input current is input to the input terminal. By configuring the DTIAP stage with the same circuit elements as the TIAP stage, the circuit design of the receiving circuit 100 can be simplified. The DTIAP stage includes an inverter amplifier INVP2 and a resistor RP2 connected between the output and input of the inverter amplifier INVP2.

[0043] For example, the circuit configuration of inverter amplifier INVP2 may be the same as that of inverter amplifier INVP1, and the resistance value of resistor element RP2 may be the same as that of resistor element RP1. The DTIAP stage generates a predetermined reference voltage and outputs the generated reference voltage to the level shift circuit LS2N. For example, the voltage value of the reference voltage of the DTIAP stage is set to be smaller than the voltage value of the voltage signal TIAPout output from the TIAP stage when the input current IinP is zero (note that no pulling occurs when the input current IinP is zero).

[0044] The level shift circuit LS2N includes, for example, a resistor RLS2N, a capacitive element CLS2N, and a current source ILS2N. The resistor RLS2N is connected between the output of the DTIAP stage and the reference voltage line VrefN. The capacitive element CLS2N is connected between the reference voltage line VrefN and the ground line GND. The current source ILS2N is connected between the power line VCC and the reference voltage line VrefN.

[0045] The level shift circuit LS2N generates a reference voltage VrefN on the reference voltage line VrefN by shifting the reference voltage output from the DTIAP stage to a higher potential side through the voltage drop across the resistor RLS2N caused by the current supplied by the current source ILS2N flowing through the resistor RLS2N. Similar to the level shift circuit LS1N, the level shift circuit LS2N can make the average output voltage of the level shift circuit LS2N greater than the average value of the input voltage of the level shift circuit LS2N.

[0046] The capacitive element CLS2N directs noise generated on the reference voltage line VrefN to the ground line GND, stabilizing the voltage on the reference voltage line VrefN (reference voltage VrefN). The capacitive element CLS2N is a so-called bypass capacitor. The current source ILS2N can be constructed, for example, by a p-channel MOS transistor. In addition, to adjust the amount of current supplied, the current source ILS2N may be constructed by a current mirror circuit including a p-channel MOS transistor. Alternatively, the current source ILS2N may be constructed using a resistive element instead of a p-channel MOS transistor.

[0047] For example, if the current source ILS1N is constructed using a p-channel MOS transistor, the current source ILS2N may also be constructed using a p-channel MOS transistor. In that case, it is preferable that the p-channel MOS transistors constituting the current source ILS2N have the same electrical characteristics as the p-channel MOS transistors constituting the current source ILS1N.

[0048] Incidentally, the current from the current source ILS2N flows into the DTIAP stage, but the current flowing from the current source ILS2N into the DTIAP stage is offset by increasing the current amount of the current source inside the DTIAP stage. Alternatively, instead of increasing the current amount of the current source inside the DTIAP stage, a current source may be added between the input node of the level shift circuit LS2N connected to the output node of the DTIAP stage and the ground line GND, and the current from the current source ILS2N may be passed through this current source.

[0049] As described later, the reference voltage VrefN is set to a value smaller than the average voltage value of the voltage signal VtiaN when the input current IinP is zero, in the state where the automatic offset control circuit AOC1 is not operating (feedback current Iaoc1P=0). As the input current IinP increases, the voltage value (average value) of the voltage signal VtiaN decreases, and if the input current IinP continues to increase further, it will eventually become smaller than the reference voltage VrefN.

[0050] When the voltage value (average value) of the voltage signal VtiaN is smaller than the reference voltage VrefN, the current signal input to the input node TIAPin is reduced by drawing the feedback current Iaoc1P from the input current IinP input to the input terminal InP, thereby increasing the voltage of the voltage signal VtiaN and bringing it closer to the reference voltage VrefN. As a result, the automatic offset control circuit AOC1 can perform automatic offset control to suppress the increase in the DC offset between the voltage VtiaN and the reference voltage VrefN.

[0051] The TIAN stage includes an inverter amplifier INVN1 and a resistor RN1. The input of the inverter amplifier INVN1 is electrically connected to the input terminal InN via the input node TIANin of the TIAN stage. The output of the inverter amplifier INVN1 is connected to the level shift circuit LS1P via the output node TIANout of the TIAN stage. The resistor RN1 is connected between the input node TIANin and the output node TIANout.

[0052] The TIAN stage converts the input current IinN input to the input node TIANin into a voltage signal using an inverter amplifier INVN1 and a resistor element RN1, amplifies it through inversion, and outputs the inverted amplified voltage signal to the output node TIANout. The inverter amplifier INVN1 is, for example, an inverting amplifier circuit. For example, when the input current IinN increases, the voltage output to the output node TIANout decreases, and when the input current IinN decreases, the voltage output to the output node TIANout increases. The gain of the TIAN stage is expressed as impedance (resistance value). The gain of the TIAN stage is mainly determined by the resistance value of the resistor element RN1.

[0053] The level shift circuit LS1P includes, for example, a resistor RLS1P, a capacitive element CLS1P, and a current source ILS1P. The resistor RLS1P and the capacitive element CLS1P are connected in parallel between the output node TIANout of the TIAN stage and node VtiaP, which is connected to the other input of buffer BUF1. The current source ILS1P is connected between the power line VCC and node VtiaP.

[0054] The level shift circuit LS1P generates a voltage signal VtiaP by shifting the voltage signal TIANout output from the TIAN stage to a higher potential side due to the voltage drop across the resistor RLS1P caused by the current supplied by the current source ILS1P flowing through RLS1P. The capacitive element CLS1P transmits the high-frequency components of the signal input to the level shift circuit LS1P to the output faster than the resistor RLS1P. For example, the falling edge and degradation of the falling edge of the pulse wave that is level shifted by the level shift circuit LS1P are suppressed by the capacitive element CLS1P. The capacitive element CLS1P is a so-called speed-up capacitor.

[0055] The current source ILS1P can be constructed, for example, by a p-channel MOS (Metal Oxide Semiconductor) transistor. Alternatively, to adjust the amount of current supplied, the current source ILS1P may be constructed using a current mirror circuit including a p-channel MOS transistor. Or, the current source ILS1P may be constructed using a resistive element instead of a p-channel MOS transistor.

[0056] This allows the average output voltage of the level shift circuit LS1P to be greater than the average input voltage of the level shift circuit LS1P. The level shift circuit LS1P then sets the voltage of the voltage signal VtiaP input to buffer BUF1 to a voltage range necessary for buffer BUF1 to operate properly.

[0057] For example, the signal component of the voltage signal VtiaP generated in response to the signal component of the input current IinN is superimposed on the voltage value (average value) of the voltage signal VtiaP and input to the buffer BUF. Note that the current from the current source ILS1P flows into the TIAN stage, but the current flowing from the current source ILS1P into the TIAN stage is canceled out by increasing the amount of current from the internal current source of the TIAN stage (for example, similar to ITIA in the TIAP stage shown in Figure 2).

[0058] Alternatively, instead of increasing the current of the internal current source of the TIAN stage, a current source may be added between the input node of the level shift circuit LS1P connected to the output node TIANout and the ground line GND, and current from the current source ILS1P may be passed through this current source. This added current source can be configured, for example, by an n-channel MOS transistor. To adjust the amount of current, it may also be configured by a current mirror circuit including an n-channel MOS transistor. Alternatively, the added current source may be configured using a resistor instead of an n-channel MOS transistor.

[0059] The DTIAN stage has the same circuit configuration as the TIAN stage, except that no input current is applied to the input terminal. By configuring the DTIAN stage with the same circuit elements as the TIAN stage, the circuit design of the receiving circuit 100 can be simplified. The TIAP stage, DTIAP stage, DIAN stage, and DTIAN stage may be configured with the same circuit elements as each other. Also, the level shift circuits LS1N, LS2N, LS1P, and LS2P may be configured with the same circuit elements as each other.

[0060] The DTIAN stage comprises an inverter amplifier INVN2 and a resistor RN2 connected between the output and input of the inverter amplifier INVN2. For example, the circuit configuration of the inverter amplifier INVN2 may be the same as that of the inverter amplifier INVN1, and the resistance value of resistor RN2 may be the same as that of resistor RN1. The DTIAN stage generates a predetermined reference voltage and outputs the generated reference voltage to the level shift circuit LS2P. For example, the voltage value of the reference voltage of the DTIAN stage is set to the voltage value of the voltage signal TIAPout output from the TIAN stage when the input current IinN is zero (note that no pulling occurs when the input current IinN is zero).

[0061] The level shift circuit LS2P includes, for example, a resistor RLS2P, a capacitive element CLS2P, and a current source ILS2P. The resistor RLS2P is connected between the output of the DTIAN stage and the reference voltage line VrefP. The capacitive element CLS2P is connected between the reference voltage line VrefP and the ground line GND. The current source ILS2P is connected between the power line VCC and the reference voltage line VrefP.

[0062] The level shift circuit LS2P generates a reference voltage VrefP on the reference voltage line VrefP by shifting the reference voltage output from the DTIAN stage to a higher potential side through the voltage drop across the resistor RLS2P caused by the current supplied by the current source ILS2P flowing through the resistor RLS2P. Similar to the level shift circuit LS1P, the level shift circuit LS2P can make the average output voltage of the level shift circuit LS2P greater than the average value of the input voltage of the level shift circuit LS2P.

[0063] The capacitive element CLS2P directs noise generated on the reference voltage line VrefP to the ground line GND, stabilizing the voltage on the reference voltage line VrefN (reference voltage VrefN). The capacitive element CLS2P is a so-called bypass capacitor. The current source ILS2P can be constructed, for example, by a p-channel MOS transistor. In addition, to adjust the amount of current supplied, the current source ILS2P may be constructed by a current mirror circuit including a p-channel MOS transistor. Alternatively, the current source ILS2P may be constructed using a resistive element instead of a p-channel MOS transistor.

[0064] For example, if the current source ILS1P is constructed using a p-channel MOS transistor, the current source ILS2P may also be constructed using a p-channel MOS transistor. In that case, it is preferable that the p-channel MOS transistors constituting the current source ILS2P have the same electrical characteristics as the p-channel MOS transistors constituting the current source ILS1P.

[0065] Incidentally, the current from the current source ILS2P flows into the DTIAN stage, but the current flowing from the current source ILS2P into the DTIAN stage is offset by increasing the current amount of the current source inside the DTIAN stage. Alternatively, instead of increasing the current amount of the current source inside the DTIAN stage, a current source may be added between the input node of the level shift circuit LS2P connected to the output node of the DTIAN stage and the ground line GND, and the current from the current source ILS2P may be passed through this current source.

[0066] As described later, the reference voltage VrefP is set to a value smaller than the average voltage value of the voltage signal VtiaP when the input current IinN is zero, in the state where the automatic offset control circuit AOC2 is not operating (feedback current Iaoc1N=0). As the input current IinN increases, the voltage value (average value) of the voltage signal VtiaP decreases, and if the input current IinN continues to increase further, it will eventually become smaller than the reference voltage VrefP.

[0067] When the average voltage value of the voltage signal VtiaP is smaller than the reference voltage VrefP, the voltage of the voltage signal VtiaP can be increased to approach the reference voltage VrefP by drawing a feedback current Iaoc1N from the input current IinN input to the input terminal InN. As a result, the automatic offset control circuit AOC2 can perform automatic offset control to suppress the increase in the DC offset between the voltage VtiaP and the reference voltage VrefP.

[0068] The automatic offset control circuit AOC1 has input terminals Inp and Inn connected to nodes VrefN and VtiaN, respectively, a feedback current terminal Iaoc1 connected to input terminal InP, and a feedback current terminal Iaoc2 connected to reference voltage line VrefN. Depending on the difference VrefN-VtiaN between the reference voltage VrefN and the voltage VtiaN, the automatic offset control circuit AOC1 subtracts the feedback current Iaoc1P from the input current IinP input to input terminal InP, or outputs a feedback current Iaoc2N to reference voltage line VrefN.

[0069] The automatic offset control circuit AOC1 controls the characteristics of the changes in the feedback currents Iaoc1P and Iaoc2N depending on whether the input current value IinP is less than or greater than a predetermined value. For example, when the input current value IinP is less than a predetermined value, the automatic offset control circuit AOC1 controls the system to not flow the feedback current Iaoc1P, but instead flow the feedback current Iaoc2N, which is added to the current supplied by the current source ILS2N.

[0070] Here, the summation of currents is performed by flowing a feedback current Iaoc2 through the resistor RLS2 in the same direction as the current supplied by the current source ILS2. In addition, the automatic offset control circuit AOC1 controls the flow of feedback currents Iaoc1P and Iaoc2N according to the input current IinP when the input current IinP is greater than or equal to a predetermined value. Feedback current Iaoc2N is an example of the first feedback current, and feedback current Iaoc1P is an example of the second feedback current.

[0071] The reference voltage VrefN and voltage VtiaN vary depending on the input current IinP. For example, if no feedback current Iaoc1P is flowing, as the input current IinP increases, the voltage signal VtiaN decreases. Conversely, as the input current IinP decreases, the voltage signal VtiaN increases. Therefore, the voltage signal VtiaN is generated as an inverted amplified signal of the input current IinP. Also, by flowing the feedback current Iaoc2N, the reference voltage VrefN becomes greater than when no feedback current Iaoc2N is flowing.

[0072] Therefore, the automatic offset control circuit AOC1 can perform the automatic offset control described above by monitoring the reference voltage VrefN and voltage VtiaN. In other words, the automatic offset control circuit AOC1 can control the feedback current Iaoc1P (0mA or more) and feedback current Iaoc2N (0mA or more) so that the DC offset between the reference voltage VrefN and voltage VtiaN falls within an acceptable range.

[0073] As a result, the buffer BUF1 can be operated at an appropriate operating point regardless of the magnitude of the input current IinP, and good amplification characteristics with suppressed DC offset can be obtained. An example of the circuit configuration of the automatic offset control circuit AOC1 is shown in Figure 3, and an example of the operation of the automatic offset control circuit AOC1 is shown in Figure 4.

[0074] Furthermore, when the input current IinP is greater than a predetermined value, the automatic offset control circuit AOC1 may supply not only the feedback current Iaoc1P but also the feedback current Iaoc2N in response to an increase in the input current IinP. This allows the base-collector voltage VcbP of the first stage cascode transistor (Q2 in Figure 2) of the TIAP stage to be increased.

[0075] More specifically, by passing the feedback current Iaoc2N, the reference voltage VrefN increases slightly with increasing input current IinP, bringing the average value of the voltage signal VtiaN closer to the reference voltage VrefN. As a result, the average value of the voltage signal VtiaN becomes larger compared to the case where no feedback current Iaoc2 is passed. Therefore, the operating margin of the transimpedance amplifier (TIAP stage + LS1N) can be increased when the input current IinP is large.

[0076] The current value of the input current IinP, which switches the characteristics of the changes in the feedback currents Iaoc1P and Iaoc2N, can be set by adjusting the reference voltage VrefN when the feedback current Iaoc2N = 0mA. For example, the reference voltage VrefN when the feedback current Iaoc2N = 0mA is set to be smaller than the voltage value (average value) of the voltage signal VtiaN when the input current IinP = 0mA. The adjustment of the reference voltage VrefN is performed by adjusting the current value of the current source ILS2N of the level shift circuit LS2N. For example, let Iswitch be the current value of the input current IinP that switches the characteristics of the changes in the feedback currents Iaoc1P and Iaoc2N.

[0077] In this case, the current supplied to the current source ILS2N is set so that the reference voltage VrefN is equal to the "average value of the voltage signal VtiaN when IinP=Iswitch". For example, assume that the electrical characteristics of the transimpedance amplifier (TIAP stage + LS1N) and the reference voltage circuit (DTIAP stage + LS2N) are the same, and the resistance values ​​of the resistors RLS1N and RLS2N are the same. In this case, the current value of the current source ILS1N is set to be greater than the current value of the current source ILS2N.

[0078] The automatic offset control circuit AOC2 has, for example, the same circuit configuration as the automatic offset control circuit AOC1. The automatic offset control circuit AOC2 has, for example, the same electrical characteristics as the automatic offset control circuit AOC1. Therefore, the automatic offset control circuit AOC2 operates in the same way as the automatic offset control circuit AOC1. The automatic offset control circuit AOC2 has input terminals Inp and Inn connected to nodes VrefP and VtiaP, respectively, a feedback current terminal Iaoc1 connected to input terminal InN, and a feedback current terminal Iaoc2 connected to the reference voltage line VrefP.

[0079] The automatic offset control circuit AOC2 subtracts the feedback current Iaoc1N from the input current IinN, or outputs the feedback current Iaoc2P to the reference voltage line VrefP, depending on the difference between the reference voltage VrefP and voltage VtiaP received at the input terminals Inp and Inn, respectively. The feedback current Iaoc2P is an example of a third feedback current, and the feedback current Iaoc1N is an example of a fourth feedback current.

[0080] The reference voltage VrefP and voltage VtiaP change depending on the input current IinN. Therefore, the automatic offset control circuit AOC2 can perform automatic offset control by monitoring the reference voltage VrefP and voltage VtiaP. In other words, the automatic offset control circuit AOC2 can control the feedback current Iaoc1N (0mA or more) and feedback current Iaoc2P (0mA or more) so that the DC offset between voltage VtiaP and the reference voltage VrefP remains within an acceptable range. As a result, the buffer BUF1 can be operated at an appropriate operating point regardless of the magnitude of the input current IinN, and good amplification characteristics with suppressed DC offset can be obtained.

[0081] Furthermore, when the input current value IinN is greater than a predetermined value, the base-collector voltage of the cascode transistor in the first stage of the TIAN stage can be increased by flowing not only the feedback current Iaoc1N but also the feedback current Iaoc2P in response to the increase in the input current IinN. More specifically, by flowing the feedback current Iaoc2P, the reference voltage VrefP increases slightly in response to the increase in the input current IinN, bringing the voltage value (average value) of the voltage signal VtiaP closer to the reference voltage VrefP. As a result, the voltage value (average value) of the voltage signal VtiaN becomes larger compared to the case where the feedback current Iaoc2P is not flowing. This increases the operating margin of the transimpedance amplifier (TIAN stage + LS1P) when the input current value IinN is large.

[0082] The input current IinN, which switches the characteristics of the changes in the feedback currents Iaoc1N and Iaoc2P, can be set by adjusting the reference voltage VrefP when the feedback current Iaoc2P = 0mA. For example, the reference voltage VrefP when the feedback current Iaoc2P = 0mA is set to be smaller than the voltage value (average value) of the voltage signal VtiaP when the input current IinN = 0mA. The reference voltage VrefP is adjusted by adjusting the current value of the current source ILS2P of the level shift circuit LS2P.

[0083] Buffer BUF1 has a differential input and a differential output. Buffer BUF1 amplifies the voltage difference VtiaN-VtiaP between a pair of voltage signals VtiaN and VtiaP received at the differential input, and outputs the amplified differential signal to buffer BUF2. Buffer BUF2 has a differential input and a differential output. Buffer BUF2 amplifies the differential signal received from buffer BUF1 and outputs it as differential signals OutN / OutP to the output terminals OutN / OutP. The differential signals OutN / OutP correspond to the voltage difference OutN-OutP between a pair of voltage signals OutN and OutP.

[0084] For example, voltage signal VtiaN is input to the non-inverting input terminal of buffer BUF1, and voltage signal VtiaP is input to the non-inverting input terminal of buffer BUF1. The non-inverting output terminal of buffer BUF1 is connected to the non-inverting input terminal of buffer BUF2, and the inverting output terminal of buffer BUF1 is connected to the inverting input terminal of buffer BUF2. In addition, voltage signal OutN is output from the non-inverting output terminal of buffer BUF2, and voltage signal OutP is input to the non-inverting input terminal of buffer BUF2. As a result, the receiving circuit 100 can amplify the differential voltage signals VtiaN and VtiaP generated from the differential input currents IinP / IinN and output them as differential signals OutN / OutP.

[0085] The automatic offset control circuit AOC3 is connected between the input and output of buffer BUF2. The automatic offset control circuit AOC3 monitors the voltage of the differential signals OutN / OutP output from buffer BUF2. Then, based on the monitoring results, the automatic offset control circuit AOC3 performs automatic offset control to suppress the increase in the DC offset of the differential signals OutP / OutN by supplying current to at least one of the differential outputs of buffer BUF1.

[0086] [Circuit configuration of the transimpedance amplifier stage] Figure 2 is a circuit diagram showing an example of the transimpedance amplifier stage TIAP in Figure 1. The circuit configuration of the TIAN stage in Figure 1 is the same as that of Figure 2. The circuit configurations of the DTIAP and DTIAN stages in Figure 1 are the same as those in Figure 2, except that no input current is input to the input terminals (the input terminals are open).

[0087] The TIAP stage has a load resistor RL connected in series between the power line VCC and the ground line GND, and cascode-connected transistors Q2 and Q1. The TIAP stage also has a transistor Q3 connected in series between the power line VCC and the ground line GND, and a current source ITIA. Furthermore, the TIAP stage has a feedback resistor RF connected between the input terminal TIAPin and the output terminal TIAPout. The feedback resistor RF corresponds to the resistor RP1 in Figure 1.

[0088] Transistor Q2 receives a bias voltage Vcas at its base and operates as a cascode transistor. Transistor Q1 has its base connected to the input terminal TIAPin and receives an input current IinP. Transistor Q1 has its emitter grounded to the ground line GND and its collector connected to the emitter of transistor Q2, and operates as an amplifying transistor. The collector voltage of transistor Q1 is kept constant according to the bias voltage Vcas even when transistor Q1 is amplifying, thus suppressing the Miller effect of the base-collector capacitance of transistor Q1. The collector current of transistor Q1 flows through transistor Q2 to the resistor RL, causing a voltage drop. The collector voltage of transistor Q2 is a voltage corresponding to the voltage drop across the resistor RL, with the power supply voltage Vcc as the reference potential.

[0089] Transistor Q3 operates as an emitter follower, with its base connected to the collector of transistor Q2 and its emitter connected to the output terminal TIAPout. The TIAP stage operates as an inverting amplifier, outputting a voltage from the output terminal TIAPout that is an inverted amplified version of the voltage corresponding to the input current IinP received at the input terminal TIAPin. The current source ITIA can be constructed, for example, using an n-channel MOS transistor. Alternatively, to adjust the amount of current, it may be constructed using a current mirror circuit including an n-channel MOS transistor. Or, the current source ITIA may be constructed using a resistive element instead of an n-channel MOS transistor.

[0090] Furthermore, since the collector of transistor Q2 is connected to the base of the emitter follower transistor Q3, the collector voltage of transistor Q2 has the same polarity as the output voltage TIAPout. Therefore, when the output voltage TIAPout decreases, the collector voltage of transistor Q2 also decreases, and the base-collector voltage value VcbP of transistor Q2 decreases. When the output voltage TIAPout increases, the collector voltage of transistor Q2 also increases, and the base-collector voltage value VcbP of transistor Q2 increases. When the base-collector voltage value Vcb decreases, the operating margin of transistor Q2 decreases, so it is preferable to keep it above a predetermined value.

[0091] [Circuit configuration of the automatic offset control circuit AOC1] Figure 3 is a circuit diagram showing an example of the automatic offset control circuit AOC1 of Figure 1. The automatic offset control circuit AOC1 includes a differential integrator DI, p-channel MOS (Metal Oxide Semiconductor) transistors PM1, PM2, PM3, PM4, PM5, and n-channel MOS transistors NM1, NM2, NM3, NM4. The automatic offset control circuit AOC1 also includes diodes D1, D2 and current sources I1, I2. Hereafter, the p-channel MOS transistors PM1-PM5 and the n-channel MOS transistors NM1-NM4 will be referred to as transistors PM1-PM5 and transistors NM1-NM4, respectively.

[0092] As shown in Figure 1, the automatic offset control circuit AOC1 receives a reference voltage VrefN at the input terminal Inp and a voltage VtiaN at the input terminal Inn. The automatic offset control circuit AOC1 also outputs a feedback current Iaoc2N from the feedback current terminal Iaoc2 and draws a feedback current Iaoc1P into the feedback current terminal Iaoc1.

[0093] The circuit configuration of the automatic offset control circuit AOC2 in Figure 1 is the same as that in Figure 3. The automatic offset control circuit AOC2 receives a reference voltage VrefP at the input terminal Inp and a voltage VtiaP at the input terminal Inn. The automatic offset control circuit AOC2 also outputs a feedback current Iaoc2P from the feedback current terminal Iaoc2 and draws a feedback current Iaoc1N into the feedback current terminal Iaoc1.

[0094] The differential integrator DI comprises resistors R31 and R32, capacitors C31 and C32, and an operational amplifier OPA. One input (non-inverting input terminal) of the operational amplifier OPA is connected to input terminal Inp via resistor R31, and the other input (inverting input terminal) of the operational amplifier OPA is connected to input terminal Inn via resistor R32. Capacitor C31 is connected between one input and the other output (inverting output terminal) of the operational amplifier OPA. The other output of the operational amplifier OPA is connected to control terminal Vaoc1. Capacitor C32 is connected between the other input and the one output (non-inverting output terminal) of the operational amplifier OPA. The one output of the operational amplifier OPA is connected to control terminal Vaoc2.

[0095] The differential integrator DI generates control voltages Vaoc1 and Vaoc2 depending on the voltage of the voltage signal VtiaN and the reference voltage VrefN. Then, as shown in Figure 4, the automatic offset control circuit AOC1 inverts the magnitude relationship between the magnitudes of the feedback currents Iaoc2N and Iaoc1P in Figure 1, depending on the input voltage VrefN / VtiaN.

[0096] The resistor element R31 and the capacitor element C31, and the resistor element R32 and the capacitor element C32, each function as an RC filter (low-pass filter). The differential integrator DI then smooths the input voltages Inp and Inn. The operational amplifier OPA acts as a differential integrator, differentially amplifying the smoothed voltage signals received through the resistor elements R31 and R32, respectively, and outputting them as control voltages Vaoc1 and Vaoc2.

[0097] For example, if the average value of the input voltage Inp is greater than the average value of the input voltage Inn, the control voltage Vaoc1 will be less than the control voltage Vaoc2. If the average value of the input voltage Inp is less than the average value of the input voltage Inn, the control voltage Vaoc1 will be greater than the control voltage Vaoc2. In other words, when the difference voltage VInP - VinN between the average value of the input voltage InP and the average value of the input voltage InN is positive, the control voltage Vaoc2 generated by the non-inverting amplification operation of the operational amplifier OPA will be greater than the control voltage Vaoc1 generated by the inverting amplification operation of the operational amplifier OPA. Also, when the difference voltage VInP - VinN is negative, the control voltage Vaoc2 generated by the non-inverting amplification operation of the operational amplifier OPA will be less than the control voltage Vaoc1 generated by the inverting amplification operation of the operational amplifier OPA.

[0098] The control terminal Vaoc1 is connected to the gate of transistor NM4 and the current source I1 via diode D1. Therefore, the voltage applied to the gate of transistor NM4 is the control voltage Vaoc1 minus the voltage drop generated by diode D1.

[0099] The control terminal Vaoc2 is connected to the gate of transistor NM1 and the current source I2 via diode D2. Therefore, the voltage applied to the gate of transistor NM1 is the control voltage Vaoc2 minus the voltage drop generated by diode D2.

[0100] Transistors PM1 and NM1 are connected in series between the power line VCC and the ground line GND. Transistors PM2 and NM2 are connected in series between the power line VCC and the ground line GND. Transistor PM3 is connected between the power line VCC and the feedback current terminal Iaoc2, and its gate is connected to the drain of transistor NM1. Transistors PM4 and NM4 are connected in series between the power line VCC and the ground line GND.

[0101] For more details, The source of transistor NM1 is connected to the ground line GND, the drain of transistor NM1 is connected to the drain of transistor PM1, and the source of transistor PM1 is connected to the power line VCC. Transistors PM2, NM2 and PM4, NM4 are connected in the same way as transistors PM1, NM1, so their explanation is omitted.

[0102] Transistors PM1, PM2, and PM3 operate as a current mirror circuit, with their sources commonly connected to the power line VCC and their gates commonly connected to the drain of transistor NM1. The drain of transistor PM3 is connected to the feedback current terminal Iaoc2.

[0103] Transistors NM2 and NM3 operate as a current mirror circuit, with their sources commonly connected to the ground line GND and their gates commonly connected to the drain of transistor PM2. The drain of transistor NM3 is connected to the feedback current terminal Iaoc1. Transistors PM4 and PM5 operate as a current mirror circuit, with their sources commonly connected to the power line VCC and their gates commonly connected to the drain of transistor NM4. The drain of transistor PM5 is connected to the feedback current terminal Iaoc2.

[0104] Transistor NM1 turns on when the control voltage Vaoc2 is greater than or equal to a predetermined value, and turns off when the control voltage Vaoc2 is less than the predetermined value. Transistor NM1 turns on when the difference voltage VInP - VinN, which is the difference voltage between the average value of the input voltage InP and the average value of the input voltage InN, exceeds a predetermined value, and turns off when the difference voltage VInP - VinN is less than the predetermined value.

[0105] While transistor NM1 is ON, current flows through the current mirror circuit (first current mirror circuit) formed by transistors PM1, PM2, and PM3, and current flows through the current mirror circuit (second current mirror circuit) formed by transistors NM2 and NM3. As a result, a feedback current Iaoc2 is output from the feedback current terminal Iaoc2, and a feedback current Iaoc1 is drawn in from the input terminal InP (Figure 1) via the feedback current terminal Iaoc1.

[0106] Transistor NM4 turns on when the control voltage Vaoc1 is greater than or equal to a predetermined value, and turns off when the control voltage Vaoc1 is less than the predetermined value. Regarding the input to the differential integrator DI, transistor NM4 turns on when the difference voltage VInP - VinN, which is the difference voltage between the average value of the input voltage InP and the average value of the input voltage InN, is less than a predetermined value, and transistor NM4 turns off when the difference voltage VInP - VinN exceeds the predetermined value. While transistor NM4 is on, a feedback current Iaoc1 is output from the current mirror circuit (third current mirror circuit) formed by transistors PM4 and PM5 to the reference voltage line VrefN (Figure 1) via the feedback current terminal Iaoc2.

[0107] The automatic offset control circuit AOC1 is configured such that, by adjusting the current amounts of current sources I1 and I2, transistor NM1 turns on and transistor NM4 turns off when the average value of the input voltage Inp is greater than the average value of the input voltage Inn. In this case, current flows through both the feedback current terminals Iaoc1 and Iaoc2. The automatic offset control circuit AOC1 is also configured such that, by adjusting the current amounts of current sources I1 and I2, transistor NM1 turns off and transistor NM4 turns on when the average value of the input voltage Inp is less than the average value of the input voltage Inn. In this case, current flows only through the feedback current terminal Iaoc2.

[0108] As described above, in the automatic offset control circuit AOC1, the input terminal Inp is connected to the reference voltage line VrefN in Figure 1, and the input terminal Inn is connected to the voltage line VtiaN in Figure 1. Therefore, when the input current IinP is less than a predetermined value and the voltage value (average) of the voltage signal VtiaN is greater than the reference voltage value VrefN, current flows only through the feedback current terminal Iaoc2. When the input current value IinP is greater than a predetermined value and the voltage value (average) of the voltage signal VtiaN is less than the reference voltage value VrefN, current flows through both the feedback current terminals Iaoc1 and Iaoc2.

[0109] Thus, the automatic offset control circuit AOC1 switches the path of the circuit that operates to generate the feedback currents Iaoc1 and Iaoc2 depending on the polarity of the differential output (Vaoc1-Vaoc2) of the differential integrator DI. The differential integrator DI operates by receiving a voltage VtiaN that changes according to the input current IinP and a reference voltage VrefN at the input terminals Inn / Inp. In other words, the differential integrator DI generates control voltages Vaoc1 / Vaoc2 according to the input current IinP.

[0110] Therefore, the automatic offset control circuit AOC1 can control the generation and switching of feedback currents Iaoc1P and Iaoc2N according to the control voltages Vaoc1 / Vaoc2 generated by the differential integrator DI in response to the input current IinP. In other words, the automatic offset control circuit AOC1 can invert the magnitude relationship between the magnitudes of feedback current Iaoc1P and feedback current Iaoc2N according to the control voltages Vaoc1 / Vaoc2.

[0111] Note that transistor PM3 may be omitted from the automatic offset control circuit AOC1. In this case, when the input voltage value Inn is smaller than the input voltage value Inp, that is, when the voltage value VtiaN is smaller than the reference voltage value VrefN, only the feedback current Iaoc1P may flow. For example, when the input current value IinP increases, the voltage value (average value) of the voltage signal TIAPout output from the TIAP stage decreases, but if the TIAP stage can perform a predetermined amplification operation in response to such a decrease in the voltage value (average value) of the voltage signal TIAout, only the feedback current Iaoc1P may flow when the input current IinP is greater than a predetermined value. Similarly, if the automatic offset control circuit AOC2 has the same circuit configuration as the automatic offset control circuit AOC1 in Figure 1, transistor PM3 may be omitted.

[0112] Figure 4 shows the DC transfer characteristics of the automatic offset control circuit AOC1 shown in Figure 3. Figure 4 shows the simulation results, with the horizontal axis representing the differential input voltage VInP-VInN and the vertical axis representing the feedback currents Iaoc1 (Iaoc1P in Figure 1) and Iaoc2 (Iaoc2N in Figure 1). The symbol VInP represents the voltage at the input terminal Inp of the automatic offset control circuit AOC1 (reference voltage VrefN in Figure 1). The symbol VInN represents the voltage at the input terminal InN of the automatic offset control circuit AOC1 (voltage VtiaN in Figure 1). Note that the positive direction of the arrows in the feedback currents Iaoc1P and Iaoc2N shown in Figure 1 is considered positive for feedback currents Iaoc1 and Iaoc2, respectively.

[0113] The automatic offset control circuit AOC1 inverts the relationship between the magnitudes of the feedback currents Iaoc2 and Iaoc1 based on the control voltages Vaoc1 and Vaoc2 generated by the differential integrator DI according to the value of the differential input voltages VInP-VInN. For example, when the differential input voltages VInP-VInN are negative, i.e., when the average value (DC component) of the voltage value VtiaN is greater than the reference voltage value VrefN, the feedback current Iaoc1P does not flow (0mA), and only the feedback current Iaoc2N flows. When the differential input voltages VInP-VInN are positive, i.e., when the average value (DC component) of the voltage value VtiaN is less than the reference voltage value VrefN, both the feedback currents Iaoc1P and Iaoc2N flow.

[0114] Furthermore, there exists a region where both the feedback currents Iaoc1P and Iaoc2N are zero near 0mV when the differential input voltage VInP-VInN is close to zero. This region arises when both the control voltage Vaoc2 and the control voltage Vaoc1 are below a predetermined value. By providing such a region where both the feedback currents Iaoc1P and Iaoc2N are reliably zero, the generation and switching of the feedback currents Iaoc1P and Iaoc2N can be performed stably.

[0115] Thus, the automatic offset control circuit AOC1 can control the generation and switching of the feedback currents Iaoc1P and Iaoc2N in accordance with the voltage VtiaN which changes depending on the input current IinP. As a result, a receiver circuit 100 having the operating characteristics shown in Figure 5 can be configured, suppressing noise in the region where the input current value Iin is small, while suppressing the increase in the DC offset of the differential signals OutP / OutN.

[0116] Furthermore, by continuing to flow the feedback current Iaoc2N even after the feedback current Iaoc1P has started to flow due to the increase in the input current IinP, the operating margin of the transimpedance amplifier (TIAP stage + LS1N) can be increased. The same effect as described above can also be obtained in the automatic offset control circuit AOC2.

[0117] [Operating characteristics of the receiving circuit] Figure 5 shows an example of the operating characteristics (DC operating characteristics) of the receiver circuit 100 in Figure 1. Figure 5 shows the simulation results. The horizontal axis of Figure 5 represents the input currents IinP and IinN. The vertical axis of Figure 5 represents the output voltages OutP and OutN, voltages VtiaP and VtiaN, base-collector voltages VcbP and VcbN, and feedback currents Iaoc1P, Iaoc1N, Iaoc2N, and Iaoc2P, respectively. The base-collector voltage VcbN is the base-collector voltage of the cascode transistor (corresponding to Q2 in Figure 2) in the first stage of the TIAN stage inverter amplifier INVN1 in Figure 1. Note that all values ​​represent the average value (DC component) of the respective voltage or current.

[0118] Figure 5 shows that when the input current value Iin is less than approximately 0.06mA, the output voltage value OutP is less than the output voltage value OutN, and when the input current value Iin is greater than approximately 0.06mA, the output voltage value OutP is greater than the output voltage value OutN. In other words, the automatic offset control circuit AOC1 switches the control of the feedback currents Iaoc1 and Iaoc2 using, for example, an input current Iin = 0.06mA as a threshold. This threshold for the input current Iin can be set by making the voltage value of the reference voltage Vref slightly smaller than the voltage value of the voltage signal Vtia when the input current Iin is zero.

[0119] In other words, while the input current Iin is zero and up to a certain level, the voltage value of the voltage signal Vtia becomes greater than the voltage value of the reference voltage Vref, and the inverting amplification operation of the buffer BUF causes the output voltage value OutP to become less than the output voltage value OutN. Furthermore, when the input current Iin becomes larger than a certain level, the voltage value of the voltage signal Vtia becomes less than the voltage value of the reference voltage Vref, and the inverting amplification operation of the buffer BUF causes the output voltage value OutP to become greater than the output voltage value OutN.

[0120] The automatic offset control circuit AOC1 shown in Figure 3 sets the feedback current Iaoc1P to 0mA in the region where the input current value IinP is small, and instead of flowing the feedback current Iaoc1P, it flows the feedback current Iaoc2N through the reference voltage line VrefN. Similarly, the automatic offset control circuit AOC2 shown in Figure 3 sets the feedback current Iaoc1N to 0mA in the region where the input current value IinN is small, and instead of flowing the feedback current Iaoc1N, it flows the feedback current Iaoc2P through the reference voltage line VrefP.

[0121] For example, in the region where the input currents IinP and IinN are both approximately 0.06mA or less, the feedback currents Iaoc1P and Iaoc1N are 0mA. This allows the DC offset of voltages VtiaN and VrefN to be reduced regardless of the input current IinP, and the DC offset of voltages VtiaP and VrefP to be reduced regardless of the input current IinN. As a result, the voltages VtiaN and VtiaP supplied to buffer BUF1 can be set to a voltage range that allows buffer BUF1 to operate properly.

[0122] Furthermore, by setting the feedback currents Iaoc1P and Iaoc1N to 0mA, respectively, in the region where the input current values ​​IinP and IinN are small, the noise in the region where the input current values ​​IinP and IinN are small can be reduced. Therefore, the receiving circuit 100 can reduce the DC offset of voltages VtiaN and VrefN, and reduce the DC offset of voltages VtiaP and VrefP, while suppressing the degradation of noise characteristics in the region where the input current values ​​IinP and IinN are small.

[0123] Furthermore, the feedback currents Iaoc2N and Iaoc2P decrease to 0mA when the control of the automatic offset control circuits AOC1 and AOC2 switches, respectively, and then increase along with the feedback currents Iaoc1P and Iaoc1N in response to an increase in the input currents IinP and IinN. This allows the base-collector voltages VcbP and VcbN of the first-stage cascode transistors of the TIAP and TIAN stages to be increased in the region where the input current values ​​IinP and IinN are large. As a result, the operating margin of the transimpedance amplifier (TIAP stage + LS1N and TIAN stage + LL1P) can be increased.

[0124] More specifically, by feeding the feedback current Iaoc2N into the level shift circuit LS2N, the voltage value of the reference voltage VrefN is increased, and the automatic offset control circuit AOC1 works to bring the voltage value (average) of the voltage signal VtiaN closer to the reference voltage VrefN. As a result, the voltage value (average) of the voltage signal TIAPout increases, and the base-collector voltage VcbP increases. Note that the feedback current Iaoc1P increases slightly compared to the case where the feedback current Iaoc2N is not flowing in order to increase the voltage value (average) of the voltage signal TIAPout.

[0125] Furthermore, by supplying the feedback current Iaoc2P to the level shift circuit LS2P, the voltage value of the reference voltage VrefP is increased, and the automatic offset control circuit AOC2 brings the voltage value (average) of the voltage signal VtiaP closer to the reference voltage VrefP. As a result, the voltage value (average) of the voltage signal TIANout increases, and the base-collector voltage VcbN rises. Note that the feedback current Iaoc1N increases slightly compared to the case where the feedback current Iaoc2P is not supplied in order to increase the voltage value (average) of the voltage signal TIANout.

[0126] In this embodiment, it is possible to suppress the deterioration of noise characteristics in the range where input current values ​​IinP and IinN are small, while suppressing the increase in DC offset between the voltage VtiaN converted from the input current IinP and the reference voltage VrefN. Furthermore, it is possible to suppress the increase in DC offset between the voltage VtiaP converted from the input current IinN and the reference voltage VrefP. As a result, the accuracy of the voltage signals VtiaN and VtiaP converted from the input currents IinP and IinN can be improved, and the accuracy of the differential signals OutN / OutP output from the receiving circuit 100 can be improved.

[0127] By level-shifting the output signal voltage of inverter amplifier INVP1 using level-shift circuit LS1N to generate voltage VtiaN, voltage VtiaN can be set to the voltage range necessary for buffer BUF1 to operate properly. Similarly, by level-shifting the output signal voltage of inverter amplifier INVN1 using level-shift circuit LS1P to generate voltage VtiaP, voltage VtiaP can be set to the voltage range necessary for buffer BUF1 to operate properly. As a result, buffers BUF1 and BUF2 can generate appropriate differential signals OutN / OutP according to the input currents IinP and IinN.

[0128] The level shift circuit LS2N adds the feedback current Iaoc2N from the automatic offset control circuit AOC1 to the current from the current source ILS2N and flows it through the resistor RLS2N. Similarly, the level shift circuit LS2P adds the feedback current Iaoc2P from the automatic offset control circuit AOC2 to the current from the current source ILS2P and flows it through the resistor RLS2P. This suppresses the degradation of noise characteristics while preventing increases in the DC offset between voltage VtiaN and reference voltage VrefN, and between voltage VtiaP and reference voltage VrefP, in the range where input current values ​​IinP and IinN are small.

[0129] The dummy transimpedance amplifier stage DTIAP is constructed with the same circuit elements as the transimpedance amplifier stage TIAP, and the level shift circuit LS2N is constructed with the same circuit elements as the level shift circuit LS1N. The dummy transimpedance amplifier stage DTIAN is constructed with the same circuit elements as the transimpedance amplifier stage TIAN, and the level shift circuit LS2P is constructed with the same circuit elements as the level shift circuit LS1P. This allows for accurate adjustment of the DC offset between voltage VtiaN and reference voltage VrefN, and accurate adjustment of the DC offset between voltage VtiaP and reference voltage VrefP. Furthermore, since common design data can be used, the circuit design of the receiving circuit 100 can be simplified.

[0130] As shown in Figure 4, the automatic offset control circuit AOC1 inverts the relationship between the magnitude of the feedback current Iaoc2 and the magnitude of the feedback current Iaoc1 according to the control voltages Vaoc1 and Vaoc2. The automatic offset control circuit AOC2 operates similarly to the automatic offset control circuit AOC1, with the characteristics shown in Figure 4. This allows for the configuration of a receiver circuit 100 having the operating characteristics shown in Figure 5. In other words, it is possible to suppress noise characteristics in the region where input current values ​​IinP and IinN are small, while suppressing the increase in DC offset between the voltage value (average value) of the voltage signal VtiaN and the reference voltage VrefN, and the increase in DC offset between the voltage value (average value) of the voltage signal VtiaP and the reference voltage VrefP.

[0131] When the input current IinP exceeds a predetermined threshold, the reference voltage VrefN is greater than the average voltage value of the voltage signal VtiaN, allowing the voltage VtiaN to be increased in response to the withdrawal of the feedback current Iaoc1P, bringing it closer to the reference voltage VrefN. Similarly, when the input current IinN exceeds a predetermined threshold, the reference voltage VrefP is greater than the average voltage value of the voltage signal VtiaP, allowing the voltage VtiaP to be increased in response to the withdrawal of the feedback current Iaoc1N, bringing it closer to the reference voltage VrefP.

[0132] As a result, the automatic offset control circuit AOC1 can perform automatic offset control to suppress the increase in DC offset between voltage VtiaN and reference voltage VrefN. Similarly, the automatic offset control circuit AOC2 can perform automatic offset control to suppress the increase in DC offset between voltage VtiaP and reference voltage VrefP.

[0133] By integrating each circuit of the receiving circuit 100 onto a single semiconductor integrated circuit chip, variations in the electrical characteristics of, for example, the TIAP stage and the DTIAP stage can be reduced, and variations in the electrical characteristics of the level shift circuits LS1N and LS2N can be reduced. For example, by configuring each with the same circuit elements, the power supply voltage dependence (or temperature dependence) of the electrical characteristics of the dummy transimpedance amplifier stage can be matched to the power supply voltage dependence (or temperature dependence) of the electrical characteristics of the corresponding transimpedance amplifier stage TIA, allowing the receiving circuit 100 to operate more stably against fluctuations in power supply voltage (or temperature). As a result, the accuracy of the DC offset adjustment between voltage VtiaN and reference voltage VrefN by the automatic offset control circuit AOC1 can be improved.

[0134] [Second Embodiment] [Circuit configuration of the receiving circuit] Figure 6 is a block diagram showing an example of a receiving circuit according to the second embodiment. Elements similar to those in the receiving circuit 100 of Figure 1 are denoted by the same reference numerals, and detailed explanations are omitted. The receiving circuit 102 in Figure 6 has the same configuration as the receiving circuit 100 of Figure 1, except that it has automatic offset control circuits AOC4 and AOC5 instead of automatic offset control circuits AOC1 and AOC2, respectively. For example, the receiving circuit 102 is formed by integrating each circuit element onto a single semiconductor integrated circuit chip.

[0135] In this embodiment, the feedback current terminal Iaoc2 of the automatic offset control circuit AOC4 is connected to the input of the inverter amplifier INVP2 of the DTIAP stage. The automatic offset control circuit AOC4 differs from the automatic offset control circuit AOC1 in Figure 1 in that it has the function of drawing a feedback current Iaoc2N from the input node of the DTIAP stage.

[0136] The feedback current terminal Iaoc2 of the automatic offset control circuit AOC5 is connected to the input of the inverter amplifier INVN2 of the DTIAN stage. The automatic offset control circuit AOC5 differs from the automatic offset control circuit AOC2 in Figure 1 in that it has the function of drawing the feedback current Iaoc2P from the input node of the DTIAN stage. The other configurations of the receiving circuit 102 are the same as those of the receiving circuit 100 in Figure 1. As in Figure 1, the arrows pointing in the direction of the feedback currents Iaoc1P, Iaoc2N, Iaoc1N, and Iaoc2P are considered positive.

[0137] Figure 7 is a circuit diagram showing an example of the automatic offset control circuit AOC4 shown in Figure 6. Elements similar to those in the automatic offset control circuit AOC1 in Figure 3 are denoted by the same reference numerals, and detailed explanations are omitted. The circuit configuration of the automatic offset control circuit AOC5 in Figure 6 is the same as that of Figure 7.

[0138] The automatic offset control circuit AOC4 has been modified from the automatic offset control circuit AOC1 in Figure 3 in order to draw the feedback current Iaoc2 (Iaoc2N) from the input of the inverter amplifier INVP2. Specifically, in the automatic offset control circuit AOC4, transistor PM3 is removed and transistors NM5, NM6, and NM7 are added compared to the automatic offset control circuit AOC1 in Figure 3. Transistors NM5, NM6, and NM7 are n-channel MOS transistors.

[0139] Transistor NM5 has its source connected to the ground line GND, its drain connected to the feedback current terminal Iaoc2, and its gate connected to the drain of transistor PM2. Transistors NM6 and NM7 have their sources commonly connected to the ground line GND, and their gates commonly connected to the drain of transistor PM5, and they operate as a current mirror circuit. The drain of transistor NM6 is connected to the drain of transistor PM5. The drain of transistor NM7 is connected to the feedback current terminal Iaoc2.

[0140] Furthermore, when the input voltage value Inp is higher than the input voltage value Inn, the automatic offset control circuit AOC4 turns on transistor NM1 and turns off transistor NM4, and adjusts current sources I1 and I2 so that current flows to both feedback current terminals Iaoc1 and Iaoc2. Also, when the input voltage value Inp is lower than the input voltage value Inn, the automatic offset control circuit AOC4 turns off transistor NM1 and turns on transistor NM4, and adjusts current sources I1 and I2 so that current flows only to feedback current terminal Iaoc2.

[0141] The operating characteristics of the receiver circuit 102 shown in Figure 6 are the same as those of the receiver circuit 100 shown in Figure 5, except that the polarity of the feedback currents Iaoc2N and Iaoc2P is reversed. In other words, the receiver circuit 102 can suppress noise in the region where the input current value Iin is small, while suppressing the increase in the DC offset of the voltages Vtia and Vref, and the DC offset of the output voltages OutP and OutN.

[0142] Furthermore, transistor NM5 may be removed from the automatic offset control circuit AOC4. In this case, when the input voltage value Inn is smaller than the input voltage value Inp, that is, when the voltage value VtiaN is smaller than the reference voltage value VrefN, only the feedback current Iaoc1P may flow. For example, when the input current value IinP increases, the voltage value (average) of the voltage signal TIAPout output from the TIAP stage decreases, but if the TIAP stage can perform a predetermined amplification operation in response to such a decrease in the voltage value (average) of the voltage signal TIAPout, only the feedback current Iaoc1P may flow when the input current IinP is greater than a predetermined value. Similarly, if the automatic offset control circuit AOC5 has the same circuit configuration as the automatic offset control circuit AOC4 in Figure 7, transistor NM5 may be removed.

[0143] As described above, this embodiment can also obtain the same effects as the embodiment described above. For example, it is possible to suppress the deterioration of noise characteristics in the range where input current values ​​IinP and IinN are small, while suppressing the increase in the DC offset between the voltage value (average value) of the voltage signal VtiaN and the reference voltage VrefN, and the increase in the DC offset between the voltage value (average value) of the voltage signal VtiaP and the reference voltage VrefP.

[0144] Furthermore, in this embodiment, the automatic offset control circuit AOC4 draws a feedback current Iaoc2N from the input node of the inverter amplifier INVP2. This allows the reference voltage VrefN to be adjusted by adjusting the input voltage of the inverter amplifier INVP2, thereby suppressing the increase in the DC offset between the voltage value (average value) of the voltage signal VtiaN and the reference voltage VrefN.

[0145] Furthermore, the automatic offset control circuit AOC5 draws a feedback current Iaoc2P from the input node of the inverter amplifier INVN2. This allows the reference voltage VrefP to be adjusted by adjusting the input voltage of the inverter amplifier INVN2, thereby suppressing the increase in the DC offset between the voltage value (average value) of the voltage signal VtiaP and the reference voltage VrefP.

[0146] While embodiments of this disclosure have been described above, this disclosure is not limited to the embodiments described above. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These, too, naturally fall within the technical scope of this disclosure. [Explanation of Symbols]

[0147] 100, 102, 104 receiving circuits AOC1, AOC2, AOC3, AOC4, AOC5 Automatic Offset Control Circuits BUF1, BUF2 buffers DI differential integrator DTIAN, DTIAP Dummy Transformer Impedance Amplifier Stage Iaoc1N, Iaoc1P Feedback Current Iaoc2N, Iaoc2P Feedback Current IinN, IinP Input current ILS1N, ILS2N current source ILS1P, ILS2P current source Inn, InN, Inp, InP input terminals INVN1, INVN2 Inverter Amplifier INVP1, INVP2 Inverter Amplifiers LS1N, LS1P Level Shift Circuit LS2N, LS2P level shift circuit OutN, OutP output terminals RLS1N, RLS1P Resistors RLS2N, RLS2P Resistors TIAP, TIAN Transimpedance Amplifier Stage TIANin, TIAPin input terminals TIANout, TIAPout output terminals VcbN, VcbP Base-collector voltage VrefN, VrefP reference voltage VtiaN, VtiaP Voltage

Claims

1. A first input terminal that receives the first input current, A first transimpedance amplifier having a first input node, which converts a first current signal input to the first input node into a first voltage signal, A first reference voltage circuit that generates a first reference voltage in accordance with the first feedback current, A first offset control circuit that generates a first feedback current and a second feedback current according to the offset between the first voltage signal and the first reference voltage, A second input terminal that receives the second input current, A second transimpedance amplifier having a second input node, which converts a second current signal input to the second input node into a second voltage signal, A second reference voltage circuit that generates a second reference voltage in response to a third feedback current, A second offset control circuit that generates the third feedback current and the fourth feedback current according to the offset between the second voltage signal and the second reference voltage, A differential amplifier circuit that generates a differential signal according to the voltage difference between the first voltage signal and the second voltage signal, Equipped with, The first input node is electrically connected to the first input terminal, The second input node is electrically connected to the second input terminal, The first offset control circuit, such that the offset between the first voltage signal and the first reference voltage falls within an acceptable range, flows the first feedback current without flowing the second feedback current when the first input current is less than a first predetermined value, and flows at least the second feedback current when the first input current is equal to or greater than the first predetermined value. The second offset control circuit, such that the offset between the second voltage signal and the second reference voltage falls within an acceptable range, flows the third feedback current without flowing the fourth feedback current when the second input current is less than a second predetermined value, and flows at least the fourth feedback current when the second input current is equal to or greater than the second predetermined value. The first transimpedance amplifier is, A first amplifier circuit that converts a first current signal input to the first input node into a first intermediate voltage signal, A first level shift circuit comprising a first resistive element and a first current source, which generates a first voltage signal by level shifting the first intermediate voltage signal using the voltage drop caused by the first current supplied by the first current source flowing through the first resistive element, Includes, The first reference voltage circuit is, A second amplifier circuit that generates a first reference voltage, A second level shift circuit comprises a second resistive element and a second current source, which generates the first reference voltage by level shifting the first reference voltage using the voltage drop caused by the second current supplied by the second current source flowing through the second resistive element, Includes, The first feedback current flows through the second resistive element in the same direction as the second current. The first current signal is obtained by subtracting the second feedback current from the first input current. The second current signal is obtained by subtracting the fourth feedback current from the second input current. Receiving circuit.

2. The first offset control circuit draws the first feedback current from the input node of the second amplifier circuit. The receiving circuit according to claim 1.

3. The second amplifier circuit is composed of the same circuit elements as the first amplifier circuit. The receiving circuit according to claim 1 or claim 2.

4. The first offset control circuit is, Includes a differential integrator that generates a control voltage in accordance with the offset between the first voltage signal and the first reference voltage, The relationship between the magnitude of the first feedback current and the magnitude of the second feedback current is reversed according to the control voltage. A receiving circuit according to any one of claims 1 to 3.

5. The value of the first reference voltage when the first feedback current is zero is set to be smaller than the average voltage value of the first voltage signal when the first current signal is zero. The value of the second reference voltage when the third feedback current is zero is set to be smaller than the average voltage value of the second voltage signal when the second current signal is zero. A receiving circuit according to any one of claims 1 to 4.

6. The first transimpedance amplifier, the first reference voltage circuit, the second transimpedance amplifier, the second reference voltage circuit, the first offset control circuit, the second offset control circuit, and the differential amplifier circuit are integrated on a single semiconductor integrated circuit chip. A receiving circuit according to any one of claims 1 to 5.

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