Method for manufacturing silicon carbide epitaxial substrate and method for manufacturing semiconductor device

Abstract

To provide a method of manufacturing an SiC epitaxial substrate capable of preventing expansion of lamination defects, and of suppressing deterioration in forward characteristics of a semiconductor device.SOLUTION: A method of manufacturing a silicon carbide epitaxial substrate includes: a step (S1) of growing an epitaxial layer on a silicon carbide substrate; a step (S2) of expanding lamination defects propagated from the substrate to the epitaxial layer and originating from basal plane dislocations into the epitaxial layer by irradiating the epitaxial layer with light; and a step (S6) of heating the epitaxial layer with the expanded lamination defects to reduce lamination defects. In step (S2) of expanding lamination defects, irradiation with light is stopped before the lamination defects are overlapped with each other in a film thickness direction of the epitaxial layer.SELECTED DRAWING: Figure 19

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a silicon carbide (SiC) epitaxial substrate and a method for manufacturing a semiconductor device. [Background technology]

[0002] In pin diodes using silicon carbide (SiC) epitaxial substrates, an increase in forward resistance is known. This resistance increase is thought to occur because stacking faults expand (proliferate) starting from basal plane dislocations (BPDs) present in the n-type epitaxial layer. Specifically, this occurs when minority carriers (holes in the n-type epitaxial layer) injected from the p-type anode region are injected into the electronic energy levels created by stacking faults in the n-type epitaxial layer. These electronic energy levels are known to be located approximately 0.3 eV below the lower end of the conduction band in the 4H-SiC crystal, and it is thought that the expansion of stacking faults occurs when electrons from the conduction band, generated by current flow or photoexcitation, recombine with holes at the stacking fault levels. BPDs in the substrate are generated to relieve stress inside the crystal due to temperature inhomogeneity during the substrate formation stage, with approximately 1000 BPDs / cm² in a single substrate. 2 They exist with the above frequencies.

[0003] Since it is known that this increase in forward resistance does not originate from through-edge dislocations (TEDs) approximately perpendicular to the substrate surface, technological development to increase the conversion rate from BPDs to TEDs is ongoing. For example, it is known that BPDs in the substrate are converted to TEDs during the process of depositing an n-type defect conversion layer with a lower impurity concentration than the substrate on the substrate. Furthermore, by providing an n-type recombination promoting layer on top of the n-type defect conversion layer and promoting the recombination of holes and electrons injected from the p-type anode region, the hole density is increased to 1 × 10⁻¹⁶, which is said to be the point at which stacking faults begin to expand from BPDs near the interface between the substrate and the epitaxial layer. 15 / cm 3 It is known that the following measures can prevent defect expansion. Furthermore, it has been reported that implanting inert ions such as argon (Ar) into the substrate surface increases the conversion rate from BPD to TED.

[0004] Patent Document 1 discloses a method for manufacturing a silicon carbide epitaxial substrate, which includes the steps of expanding stacking faults within an epitaxial layer by light irradiation and reducing stacking faults by heating. Patent Document 2 discloses a method for manufacturing a semiconductor device, which includes the steps of expanding stacking faults within a SiC substrate and forming a SiC film in the expanded state. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2019-140184 [Patent Document 2] Patent No. 7023882 specification [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As mentioned above, in pin diodes using SiC epitaxial substrates, a method has been proposed to prevent the expansion of stacking faults during current flow by forming a layer on the substrate with controlled impurity concentration and type, thereby converting BPDs, which cause the expansion of stacking faults, into harmless TEDs, and this method has a certain effect in preventing the expansion of stacking faults.

[0007] However, if the amount of current applied to the diode is increased or the current application time is lengthened, stacking defects will occur and expand starting from BPDs near the interface between the epitaxial layer and the substrate, so complete prevention is not achieved. The reason for this is that at the interface between the substrate and the epitaxial layer, partial dislocations of the silicon (Si) core, which are easy to move, remain in the portion converted from BPD to TED. These partial dislocations of the Si core are immobile due to the presence of ions in the substrate where high impurity concentration ion implantation has been performed, but are in a mobile state in the epitaxial layer that operates as a device because the impurity concentration is lower than that of the substrate. Therefore, when the Si core obtains the energy required for movement due to an increase in the amount of current applied or long-term current application, it is considered that the Si core moves and the stacking defects expand. Therefore, it is difficult to sufficiently prevent the expansion of stacking defects and suppress the deterioration of the forward characteristics of the semiconductor device.

[0008] An object of the present invention is to provide a method for manufacturing a SiC epitaxial substrate and a method for manufacturing a semiconductor device that can prevent the expansion of stacking defects and suppress the deterioration of the forward characteristics of the semiconductor device.

Means for Solving the Problems

[0009] To achieve the above object, one aspect of the present invention includes: (a) a step of growing an epitaxial layer on a silicon carbide substrate, and a step of irradiating the epitaxial layer with light to expand stacking defects starting from basal plane dislocations propagated from the substrate to the epitaxial layer within the epitaxial layer; and (b) a step of heating the epitaxial layer in which the stacking defects have expanded to reduce the stacking defects. The gist of the method for manufacturing a SiC epitaxial substrate is that in the step of expanding the stacking defects, the light irradiation is stopped before the stacking defects overlap each other in the film thickness direction of the epitaxial layer.

[0010] In another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: (a) epitaxially growing a running layer of a first conductivity type on a silicon carbide substrate; (b) irradiating the running layer with light to expand stacking defects starting from basal plane dislocations propagated from the substrate into the running layer within the running layer, and heating the running layer in which the stacking defects have expanded to reduce the stacking defects; and (c) forming an implantation region of a second conductivity type on top of the running layer, wherein the step of expanding the stacking defects is to stop the light irradiation before the stacking defects overlap with each other in the film thickness direction of the running layer.

Advantages of the Invention

[0011] According to the present invention, it is possible to provide a method for manufacturing a SiC epitaxial substrate and a method for manufacturing a semiconductor device that can prevent the expansion of stacking defects and suppress the deterioration of the forward characteristics of the semiconductor device.

Brief Description of the Drawings

[0012] [Figure 1] It is a cross-sectional view showing an example of a semiconductor device according to an embodiment. [Figure 2] It is a cross-sectional view showing an example of an epitaxial substrate. [Figure 3] It is a schematic diagram showing how stacking defects expand. [Figure 4] It is a schematic diagram showing how stacking defects expand, following FIG. 3. [Figure 5] It is a schematic diagram showing how stacking defects expand, following FIG. 4. [Figure 6] It is a schematic diagram showing how stacking defects shrink, following FIG. 5. [Figure 7] It is a schematic diagram showing how stacking defects shrink, following FIG. 6. <…> [Figure 8] It is another cross-sectional view showing an example of an epitaxial substrate. [Figure 9] It is a plan view showing how stacking defects expand. [Figure 10] It is a plan view showing how stacking defects expand, following FIG. 9. [Figure 11] This is a plan view, following Figure 10, showing how stacking faults expand. [Figure 12] This is a plan view, following Figure 11, showing how stacking faults expand. [Figure 13] This is a plan view of a case where stacking faults overlap. [Figure 14] Figure 13 is a cross-sectional view of the epitaxial substrate as seen from the HH direction. [Figure 15] Figures 13 and 14 are scaled-down plan views of the stacking faults. [Figure 16] This is a cross-sectional view of the epitaxial substrate as seen from direction II in Figure 15. [Figure 17] This is a photoluminescence (PL) image of a stacking fault after full magnification. [Figure 18] Figure 17 shows a reduced PL image of the stacking faults. [Figure 19] This is a flowchart showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 20] This is a plan view of the stacking faults after partial magnification. [Figure 21] Figure 20 is a cross-sectional view of the epitaxial substrate as seen from the JJ direction. [Figure 22] This is another plan view showing the case where stacking faults overlap. [Figure 23] This is another plan view after partially enlarging the stacking faults. [Figure 24] This graph shows the relationship between light irradiation energy density and the rate of suppression of defect re-expansion. [Figure 25] This is a PL image of the stacking fault after full magnification in the example. [Figure 26] This is a PL image of the stacking faults after reduction in the example. [Figure 27] This is a PL image of a stacking fault after simulated current application in the example. [Figure 28] This is a cross-sectional view showing an example of a semiconductor device according to a modified embodiment. [Modes for carrying out the invention]

[0013] Embodiments will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of the present invention, and the technical concept of the present invention is not limited to the materials, shapes, structures, arrangements, etc. of the components described below.

[0014] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of the present invention. For example, it is obvious that if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0015] Furthermore, the following explanation uses the example of the case where the first conductivity type is n-type and the second conductivity type is p-type. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, the "+" and "-" attached to "n" and "p" indicate semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without "+" and "-" attached. However, even if two semiconductor regions are labeled with the same "n," this does not mean that the impurity concentrations of each semiconductor region are exactly the same. In addition, in the following explanation, in Miller index notation, "-" represents a bar attached to the exponent immediately following it, and placing "-" before an exponent indicates a negative exponent.

[0016] Furthermore, while the following description uses a pin diode as an example of the semiconductor device of the present invention, the semiconductor device of the present invention is not limited to a pin diode. For example, it may be an insulated-gate bipolar transistor (IGBT), an electrostatic induction thyristor (SI thyristor), or a gate turn-off thyristor (GTO) in which forward current is passed through the pn junction. It may also be a MOS field-effect transistor (FET), MISFET, or electrostatic induction transistor (SIT) with a structure in which a body diode having an epitaxially grown drain region on a substrate is parasitic.

[0017] (Embodiment) <Semiconductor device> As shown in Figure 1, the semiconductor device according to this embodiment has a first conductivity type (n + A discharge layer 1 of type (n), a running layer 2 provided on the upper side of the discharge layer 1 and having a lower impurity concentration than the discharge layer 1 and having a first conductivity type (n), and a second conductivity type (p) provided on the upper part of the running layer 2. + This is a pin diode with injection region 3 of type (type).

[0018] The discharge layer 1, the running layer 2, and the injection region 3 are made of silicon carbide (SiC) crystals. SiC crystals exist in polymorphisms, the main ones being cubic 3C and hexagonal 4H and 6H. The reported band gaps at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In this embodiment of the present invention, the case where the discharge layer 1, the running layer 2, and the injection region 3 are made of 4H-SiC will be described.

[0019] The discharge layer 1 is made of a SiC substrate. The discharge layer 1 functions as a cathode region that discharges carriers that become the main current. The surface of the discharge layer 1 is the (0001)Si plane. <0001> The (c-axis) direction has an off-angle of approximately 0° to 8° in the <11-20> direction. The running layer 2 and injection area 3 above the discharge layer 1 also have the same off-angle as the discharge layer 1.

[0020] The running layer 2 is composed of an epitaxial layer made of SiC. The running layer 2 functions as a drift region where carriers discharged from the discharge layer 1 travel in a drift electric field. Since the impurity concentration of the running layer 2 is a low impurity concentration close to that of an intrinsic semiconductor, it can be regarded as an "i layer", and p + type injection region 3, i-type running layer 2, and n + type discharge layer 1 constitute a "pin diode". The n-type impurity of the running layer 2 is, for example, nitrogen (N). The impurity concentration of the running layer 2 is, for example, 1×10 15 cm -3 or more and 1×10 18 cm -3 or less, and is appropriately adjusted according to the breakdown voltage specification of the pin diode. The thickness of the running layer 2 is, for example, 1 μm or more and several hundred μm or less, and is appropriately adjusted according to the breakdown voltage specification of the pin diode.

[0021] The injection region 3 functions as an anode region for injecting minority carriers into the running layer 2. The injection region 3 is formed by selectively adding an impurity of a conductivity type opposite to that of the impurity of the running layer 2 on the upper part of the running layer 2. p + type injection region 3 and n-type running layer 2 constitute a p + n junction for controlling carrier injection.

[0022] A surface electrode (anode electrode) 4 is provided on the upper surface of the injection region 3. The anode electrode 4 may include a contact layer, a barrier metal layer, a surface electrode layer, etc. For example, the contact layer can be a nickel silicide (NiSi x ) film, the barrier metal layer can be a titanium nitride (TiN) film, and the surface electrode layer can be an aluminum (Al) film.

[0023] A back surface electrode (cathode electrode) 5 is provided on the lower surface of the discharge layer 1. The cathode electrode 5 can be, for example, a single-layer film made of gold (Au), or a metal film laminated in the order of Al, nickel (Ni), and Au. The cathode electrode 5 may include a contact layer.

[0024] Figure 2 shows a schematic cross-sectional view of the epitaxial substrate (1s, 2e) which will be the discharge layer 1, the traveling layer 2, and the injection region 3 shown in Figure 1. The epitaxial substrate (1s, 2e) is composed of substrate 1s and epitaxial layer 2e. Substrate 1s and epitaxial layer 2e have an off-angle θ1.

[0025] The increase in the forward resistance of the PIN diode occurs due to the expansion of stacking faults, starting from basal plane dislocations 11 present in the epitaxial layer 2e. More specifically, it occurs when minority carriers (in this case, holes) are injected from the p-type injection region 3 shown in Figure 1 into the electronic energy levels created by the stacking faults in the n-type epitaxial layer 2e. The electronic energy levels of these stacking faults are known to be located 0.2 eV to 0.3 eV below the lower end of the conduction band of the 4H-SiC crystal. The expansion of the stacking faults occurs when electrons in the conduction band, generated by current flow or photoexcitation, recombine with holes at the electronic energy levels of the stacking faults. Basal plane dislocations 11 in the substrate 1s are generated to relieve stress inside the crystal caused by temperature inhomogeneities during the substrate manufacturing process, and occur at a rate of 1000 dislocations / cm² in the substrate 1s. 2 It exists on a stand.

[0026] As shown in Figure 2, the basal plane dislocation 11 propagates within the basal plane 10 from the substrate 1s to the epitaxial layer 2e, penetrates the epitaxial layer 2e, and reaches the surface. When a PIN diode is manufactured using such an epitaxial substrate (1s,2e), the basal plane dislocation 11 in the epitaxial layer 2e can become the starting point for the expansion of stacking faults when current is applied. That is, when holes, which are minority carriers, are injected into the epitaxial layer 2e from the p-type injection region 3 shown in Figure 1, the basal plane dislocation 11 can become the starting point for the expansion of stacking faults.

[0027] On the other hand, the basal plane dislocation 12 propagates within the basal plane 10 from the substrate 1s to the epitaxial layer 2e, but is converted into a through-edge dislocation (TED) 12x parallel to the c-axis of the SiC crystal within the epitaxial layer 2e. The through-edge dislocation 12x does not expand into a stacking fault. However, in the structure shown in Figure 1, when holes injected from the p-type injection region 3 reach near the interface between the discharge layer 1 and the running layer 2, stacking fault expansion can occur. In Figure 2, when the injected holes reach near the interface between the substrate 1s and the epitaxial layer 2e, the holes are injected into the electronic levels of the stacking fault originating from the basal plane dislocation 12 near the interface between the substrate 1s and the epitaxial layer 2e. In a stacking fault originating from the basal plane dislocation 12, the hole density near the interface between the substrate 1s and the epitaxial layer 2e is 1 × 10⁻¹⁶. 15 cm -3 It is said that expansion will begin once these points are reached.

[0028] Next, referring to Figures 3 to 7, we will explain the mechanism by which stacking faults expand starting from basal plane dislocations 12 in the boundary region (near the interface) of the interface between the substrate 1s and the epitaxial layer 2e due to energy application by light irradiation or electric current, and then shrink due to subsequent heating.

[0029] As schematically shown in Figure 3, the basal plane dislocation 12 is divided into two parts: a Si-core partial dislocation Si(g) (shown as a dashed line) consisting of a Si-Si bond, and a C-core partial dislocation C(g) (shown as a solid line) consisting of a CC bond. Note that "(g)" indicates that the glide plane is the slip plane of the dislocation. The partial dislocation Si(g) is a mobile dislocation that moves easily, while the partial dislocation C(g) is a stationary dislocation that does not move easily. A stacking fault 21 exists between the two partial dislocations Si(g) and C(g). Near the interface between the substrate 1s and the epitaxial layer 2e, when the basal plane dislocation 12 is converted into a through-edge dislocation, the partial dislocations Si(g) and C(g) of the basal plane dislocation 12 come into close proximity to each other and become a single through-edge dislocation (not shown). At the conversion point 12a to this through-edge dislocation, a partial dislocation Si(g) exists on the epitaxial layer 2e side from the interface between the epitaxial layer 2e and the substrate 1s.

[0030] In this state, when holes exceeding the band gap of 4H-SiC, which is 3.2 eV, are injected by energy application through light irradiation or electric current, as shown in Figure 4, the easily mobile partial dislocations Si(g) move starting from the partial dislocation Si(g) at conversion point 12a, accompanied by the less mobile partial dislocations C(g), and the stacking fault 21 expands in the epitaxial layer 2e. Furthermore, as shown in Figure 5, the stacking fault 21 expands completely, and the partial dislocations Si(g) on ​​the surface side of the epitaxial layer 2e disappear.

[0031] Next, when the fully enlarged stacking fault 21 is heated, as shown in Figure 6, the partial dislocation Si(g) moves in the shrinking direction, the stacking fault 21 in the epitaxial layer 2e shrinks, and the stacking fault 21 in the epitaxial layer 2e and the conversion point 12b near the interface between the epitaxial layer 2e and the substrate 1s are separated. The conversion point 12b is closed by the partial dislocation C(g). Since the partial dislocation C(g) is difficult to move even when a hole is injected, even if a hole is injected into the substrate 1s afterward, the stacking fault will not easily expand starting from the conversion point 12b. Furthermore, as shown in Figure 7, the stacking fault 21 in the epitaxial layer 2e shrinks and disappears.

[0032] Figure 8 shows a stacking fault 21 expanded from a basal plane dislocation 12 near the interface between the substrate 1s and the epitaxial layer 2e, starting from point A. Point A is the conversion point of the basal plane dislocation 12 to a through-edge dislocation (not shown) in the boundary region (near the interface) of the interface between the substrate 1s and the epitaxial layer 2e, and a partial dislocation with a Si core is present. The size of the partial dislocation with a Si core is about several hundred nanometers. The stacking fault 21 has expanded completely and reached the surface of the epitaxial layer 2e.

[0033] Referring to Figures 9 to 12, the expansion of the stacking fault 21 shown in Figure 8 will be explained. As shown in Figure 9, upon light irradiation, the stacking fault 21 expands from the starting point A of the basal plane dislocation 12. The edges 21a and 21b of the stacking fault 21 are partial dislocations at the C core. Furthermore, as shown in Figure 10, the stacking fault 21 expands and reaches the surface of the epitaxial layer 2e. The edge 21b of the stacking fault 21 becomes the surface edge of the epitaxial layer 2e. Furthermore, as shown in Figure 11, the stacking fault 21 expands and becomes trapezoidal in plan view. Furthermore, as shown in Figure 12, the stacking fault 21 expands completely, and the projected shape of the stacking fault 21 in plan view becomes triangular.

[0034] Edge 21a of stacking fault 21 is the line segment between starting point A and vertex B, edge 21b is the line segment between vertices B and C, and edge 21c is the line segment between starting point A and vertex C. In plan view, the angle between edges 21a and 21b is a right angle, the angle between edges 21a and 21c is 60°, and the angle between edges 21b and 21c is 30°. When the off-angle θ1 is 4° and the thickness of the epitaxial layer 2e is 10 μm, the length of edge 21a is: <1120> In that direction, the length is 10 μm / tan 4° = 143 μm, and the length of side 21b is <1100> The distance in that direction is √3 × 10 ÷ sin4° = 248.3 μm.

[0035] Here, as shown in Figures 13 and 14, multiple stacking faults 21 and 22 in the epitaxial layer 2e may overlap each other in the thickness direction of the epitaxial layer 2e. Figure 13 is a plan view of the stacking faults 21 and 22 in the epitaxial layer 2e, and Figure 14 is a cross-sectional view of the epitaxial substrate (1s, 2e) as seen from the HH direction in Figure 13.

[0036] As shown in Figures 13 and 14, stacking faults 21 and 22 are defects that have been completely expanded from basal plane dislocations 12 and 13 near the interface between the substrate 1s and the epitaxial layer 2e, with starting points A and D, respectively, and form a triangle in plan view. When the starting points A and D of stacking faults 21 and 22 are close together, completely expanding the stacking faults 21 and 22 generates a region A1 in the film thickness direction within the epitaxial layer 2e where the stacking faults 21 and 22 overlap. The region A1 where the stacking faults 21 and 22 overlap is in a more energetically stable state than the region other than the region A1 where the stacking faults 21 and 22 overlap.

[0037] Figure 15 is a plan view of the fully enlarged stacking faults 21 and 22 shown in Figures 13 and 14 after they have been reduced by heating, and Figure 16 is a cross-sectional view of the epitaxial substrate (1s, 2e) as seen from direction II in Figure 15. As shown in Figures 15 and 16, in regions other than region A1 where the stacking faults 21 and 22 overlap, the stacking faults 21 and 22 have shrunk and disappeared. On the other hand, in region A1 where the stacking faults 21 and 22 overlap, the reduction stops because it is in an energetically stable state, and the stacking faults 21 and 22 remain.

[0038] Figure 16 shows PL images of stacking faults 31-34 after complete magnification by light irradiation. Of the stacking faults 31-34, each of stacking faults 31 and 32 is composed of multiple stacking faults, and has regions where parts of the multiple stacking faults overlap each other. On the other hand, each of stacking faults 33 and 34 is composed of a single stacking fault.

[0039] Figure 17 shows the PL image of stacking faults 31-34, which were fully enlarged as shown in Figure 16, after being reduced in size by heating at 600°C. As shown in Figure 17, in stacking faults 31 and 32, which are composed of multiple stacking faults, the areas other than the overlapping regions of the multiple stacking faults have shrunk, but the overlapping regions remain. On the other hand, stacking faults 33 and 34, which are composed of a single stacking fault, have shrunk and almost disappeared.

[0040] Therefore, the semiconductor device manufacturing method according to this embodiment focuses on the overlapping of such stacking faults and controls the expansion of stacking faults so that they do not overlap during the stacking fault expansion process, in order to perform a detoxification process without sacrificing the cycle time of the stacking fault reduction process by heating.

[0041] <Manufacturing method for semiconductor devices> Next, referring to the flowchart in Figure 19, a method for manufacturing a semiconductor device according to an embodiment, including a method for manufacturing a SiC epitaxial substrate according to the embodiment, will be explained using the case of a pin diode as an example. It should be noted that the method for manufacturing a pin diode described below is just one example, and it is of course possible to realize this within the scope of the claims, including this modification, by various other manufacturing methods.

[0042] In step S1 of Figure 19, the n of the 4H-SiC crystal shown in Figure 2 + A substrate 1s of type n is prepared. Substrate 1s is a (0001) Si surface whose main surface is 4° off in the <11-20> direction. Then, an n-type epitaxial layer 2e is epitaxially grown on substrate 1s. Substrate 1s and epitaxial layer 2e constitute an epitaxial substrate (1s,2e). The epitaxial layer 2e contains n-type impurities such as nitrogen (N), for example, 1 × 10⁻¹⁶ 15 cm -3 The above is 1 x 10 18 cm -3 The impurities are added at the following concentrations. The thickness of the epitaxial layer 2e is approximately 1 μm or more and several hundred μm or less. In the following explanation, the thickness of the epitaxial layer 2e will be assumed to be 10 μm.

[0043] In step S2, stacking faults are expanded by light irradiation, starting from basal plane dislocations propagated from the substrate 1s to the epitaxial layer 2e. The expansion process is performed by uniformly irradiating the entire surface of the epitaxial layer 2e with light. If the beam diameter of the light source is smaller than the surface size of the epitaxial layer 2e, the irradiation light is scanned to uniformly irradiate the entire surface.

[0044] The irradiation light is ultraviolet (UV) light with a wavelength shorter than the absorption edge wavelength of 388 nm, which is the band gap energy of the 4H-SiC crystal. Preferably, the irradiation light is UV light with a band gap energy of around 3.2 eV (approximately 305 nm in wavelength), which is the 4H-SiC band gap energy of the 4H-SiC crystal. Furthermore, the irradiation energy density should be, for example, 1000 J / cm². 2 The above, and 5000 J / cm² 2 It is preferable that it be within the following range.

[0045] UV lasers and UV lamps are used as light sources. Suitable UV lasers include excimer lasers and helium-cadmium (He-Cd) lasers. Third or fourth harmonics of yttrium-aluminum-garnet (YAG) or yttrium-vanadite (YVO4) lasers may also be used. Suitable UV lamps include mercury lamps, xenon lamps, metal halide lamps, deuterium lamps, and halogen lamps.

[0046] The relationship between the light intensity of the irradiated light (light irradiation density) and the rate of expansion of stacking faults is given by the following equation (1).

[0047]

number

[0048] In equation (1), V is the stacking fault propagation rate, Vo is the initial velocity, ΔE is the activation energy, k is the Boltzmann constant, T is the temperature, and I is the light intensity, where Vo and ΔE are material-specific constants. As shown in equation (1), the higher the light intensity I and the higher the temperature T, the higher the stacking fault propagation rate V. However, in the case of 4H-SiC, stacking faults tend to shrink more easily when the temperature T is higher than a predetermined value. Therefore, the temperature T in equation (1) is adjusted within a range that does not hinder the propagation of stacking faults. The temperature T during light irradiation is set, for example, from room temperature to less than 400°C.

[0049] In the process of expanding stacking faults by light irradiation, the light irradiation is stopped and the stacking fault expansion process is halted before at least a portion of the stacking faults overlap. For example, the light irradiation time is adjusted to be shorter than the light irradiation time until the stacking faults overlap, based on the positions that can be the starting points of multiple stacking faults on the wafer surface of the epitaxial substrate (1s,2e). Alternatively, the light irradiation time may be adjusted to be shorter than the light irradiation time until the stacking faults are fully expanded, based on the types and shapes of the multiple stacking faults formed on the epitaxial substrate (1s,2e). By stopping the light irradiation before the stacking faults are fully expanded, the area in which the stacking faults overlap can be reduced compared to the case where the stacking faults are fully expanded.

[0050] For example, the location of basal plane dislocations that can serve as the starting point for stacking faults within the wafer surface of the epitaxial substrate (1s,2e), and the direction in which the stacking faults can expand, are detected using a photovoltaic (PL) or X-ray topography. Alternatively, using a different wafer of the same type as the epitaxial substrate (1s,2e), stacking fault expansion processing may be performed by light irradiation, and then the location of the starting point of the stacking fault, the type and shape of the stacking fault, and the direction in which the stacking fault expands may be detected using a PL or X-ray topography. Furthermore, the expansion rate of the stacking fault when the epitaxial layer 2e is irradiated with light is calculated based on the light intensity of the light source used, using equation (1), etc. Then, based on the detected location of the starting point of the stacking fault, the direction in which the stacking fault can expand, and the calculated expansion rate of the stacking fault, a light irradiation time shorter than the time it takes for the expanded stacking faults from the starting point to overlap is determined. Using the determined light irradiation time, the stacking fault expansion processing by light irradiation is performed.

[0051] The stacking fault (Stack Fault) expansion process using light irradiation causes multiple stacking faults to expand, but stops before they are fully expanded. It is not necessary for all of the stacking faults to be in a state before full expansion; that is, some of the stacking faults may be in a state before full expansion, while the remaining some may be fully expanded.

[0052] Figure 20 is a plan view of the stacking faults 21 and 22 after they have been enlarged by the light irradiation process in step S2 of Figure 19, and Figure 21 shows a cross-sectional view of the epitaxial substrate (1s, 2e) as seen from the JJ direction in Figure 20. As shown in Figures 20 and 21, the stacking faults 21 and 22 are enlarged starting from basal plane dislocations 12 and 13 near the interface between substrate 1s and epitaxial layer 2e, with starting points A and D. The stacking faults 21 and 22 are separated by a distance D1.

[0053] The stacking faults 21 and 22 are not fully enlarged and have a rhombus shape in plan view. The ends of edges 21a and 21c extending from the starting point A of stacking fault 21 and the ends of edges 22a and 22c extending from the starting point D of stacking fault 22 do not reach the surface of the epitaxial layer 2e and are located inside the epitaxial layer 2e. The lengths of edges 21a of stacking fault 21 and 22a of stacking fault 22 are shorter than the lengths of edges 21a of stacking fault 21 and 22a of stacking fault 22 shown in Figure 13. The lengths of edges 21c of stacking fault 21 and 22c of stacking fault 22 are shorter than the lengths of fully enlarged edges 21c of stacking fault 21 and 22c of stacking fault 22 shown in Figure 13.

[0054] Figure 22 shows another example where stacking faults 21 and 22 in the epitaxial layer 2e overlap each other in the thickness direction of the epitaxial layer 2e. Stacking faults 21 and 22 are defects that have fully expanded from basal plane dislocations 12 and 13 near the interface between the substrate 1s and the epitaxial layer 2e, originating from points A and D, respectively, and form a triangle in plan view. Stacking faults 21 and 22 overlap each other in the triangular region A2 in plan view.

[0055] Figure 23 shows the state after stopping the light irradiation process in step S2 of Figure 19 to enlarge the stacking faults before the stacking faults 21 and 22 shown in Figure 22 overlap. The stacking faults 21 and 22 are separated by a distance D2. The stacking faults 21 and 22 are not fully enlarged and form a trapezoid in plan view. The ends of edge 21a extending from the starting point A of stacking fault 21 and edge 22a extending from the starting point D of stacking fault 22 reach the surface of the epitaxial layer 2e. The ends of edge 21c extending from the starting point A of stacking fault 21 and edge 22c extending from the starting point D of stacking fault 22 do not reach the surface of the epitaxial layer 2e and are located inside the epitaxial layer 2e. The edges 21c of stacking fault 21 and 22c of stacking fault 22 are shorter than the lengths of the fully enlarged edges 21c of stacking fault 21 and 22c of stacking fault 22 shown in Figure 22.

[0056] In step S3 of Figure 19, the shape, position, and spacing of stacking faults within the wafer surface of the epitaxial substrate (1s,2e) are detected using a PL (photovoltaic) or X-ray topography. For example, the shape, position, and spacing of stacking faults can be detected by observing the PL image during the light irradiation process. The PL image can be observed using an optical filter (bandpass filter) that transmits only wavelengths near the emission wavelength of approximately 428 nm from the electronic level of the stacking fault. Alternatively, the emission image (PL image) of the stacking faults may be detected by exciting them with light irradiation at a wavelength shorter than approximately 428 nm.

[0057] In step S4, based on the shape, position, and spacing of the stacking faults detected in step S3, it is determined whether the stacking faults can be further expanded within a range where they do not overlap, by comparing them with a predetermined threshold. If it is determined in step S4 that the stacking faults can be further expanded, the process returns to step S2 and further light irradiation is performed. On the other hand, if it is determined in step S4 that the stacking faults cannot be further expanded, the process proceeds to step S5.

[0058] In step S5, based on the shape, location, and spacing of the stacking faults detected in step S3, it is determined whether or not there are areas on the wafer surface where stacking faults overlap. If it is determined in step S5 that there are no areas where stacking faults overlap, the process proceeds to step S6. Steps S3 to S5 may be omitted, and the process may proceed from step S2 to step S6.

[0059] In step S6, the expanded stacking faults are reduced by heating. When the reduction process is performed in an atmospheric environment, the epitaxial substrate (1s,2e) is heated to a temperature of approximately 400°C to 800°C to prevent oxidation of the crystal. The heating can be done by directly heating the substrate or by heating the entire atmosphere. For example, if the reduction process is performed in air, the reduction process temperature is, for example, 430°C, and the reduction process time is approximately 2 hours. If the reduction process is performed in an inert gas such as nitrogen gas (N2), there is no risk of oxidation of the SiC crystal, so the temperature can be set to approximately 800°C to 1000°C. If the reduction process temperature is higher than 1000°C, the C core will also become movable, which is undesirable.

[0060] During the reduction process, the epitaxial substrate (1s, 2e) may be irradiated with light having a wavelength below the absorption edge wavelength (second light). This can shorten the reduction process time. The requirements for the second light are the same as those for the light used in the expansion process (first light) in step S2. The same light source as the first light may be used for the second light.

[0061] In step S2, the stacking fault expansion process suppresses the overlapping of stacking faults. Therefore, in step S6, the stacking fault reduction process ensures that no overlapping regions remain, and the stacking faults are reliably reduced and eliminated.

[0062] On the other hand, if it is determined in step S5 that there are regions where stacking faults overlap, the process proceeds to step S7. In step S7, the shrinkage process is performed using heating conditions (second condition) that are different from the heating conditions (first condition) of step S6. In other words, in steps S6 and S7, the heating conditions for the shrinkage process are adjusted according to the stacking fault detection results.

[0063] For example, in the second condition of step S7, the shrinkage process is performed at a higher temperature and for a longer period than in the first condition of step S6. For example, if the first condition of step S6 is set to a heating temperature of approximately 400°C to 800°C and a heating time of approximately 2 hours, the second condition of step S7 may be set to a heating temperature of approximately 800°C to 1000°C and a heating time of approximately 4 hours. This allows for a greater reduction in stacking faults than when the shrinkage process is performed under the first condition. In addition, areas where stacking faults are determined to overlap within the wafer surface of the epitaxial substrate (1s,2e) may be left unused.

[0064] In step S8, the shape and size of the stacking faults are detected using PL or X-ray topography, and it is determined whether the stacking faults have shrunk sufficiently by comparing them with a predetermined threshold. For example, the stacking faults may be detected by detecting the PL image of the stacking faults by exciting them with light irradiation at a wavelength shorter than approximately 428 nm.

[0065] In step S9, an ion implantation mask is formed by photolithography, and p-type impurities such as Al are ion-implanted into the upper part of the epitaxial layer 2e. Subsequently, the ion-implanted p-type impurities are activated by heat treatment, selectively forming a p-type implantation region 3 on the upper part of the epitaxial layer 2e, with the remaining epitaxial layer 2e becoming the running layer 2. Subsequently, the lower surface of the substrate 1s is polished to adjust its thickness by chemical mechanical polishing (CMP), etc., to finish the discharge layer 1 to the specifications of a cathode region. Furthermore, a back electrode (cathode electrode) 5 made of Aμ, etc. is formed on the lower surface of the discharge layer 1 by sputtering or vacuum deposition, etc. Furthermore, a metal film such as Al is deposited by sputtering or vacuum deposition, etc., to form a surface electrode (anode electrode) 4. In this way, the semiconductor device according to the embodiment is completed.

[0066] According to the semiconductor device manufacturing method of the embodiment, in the stacking fault expansion process by light irradiation, the light irradiation is stopped before the stacking faults originating from basal plane dislocations overlap in the film thickness direction of the epitaxial layer 2e. This prevents the stacking fault reduction process from stopping midway during the subsequent heating process to reduce the stacking faults, thereby enabling more reliable reduction of the stacking faults. As a result, the expansion of stacking faults that first become apparent when the device is actually powered up can be suppressed, and the deterioration of electrical characteristics during power-up can be suppressed.

[0067] The thickness and impurity concentration of the i-layer, the running layer 2, of the PIN diode vary depending on the voltage rating of the PIN diode. For example, the thickness of the running layer 2 is approximately 5 μm to several hundred μm for voltage ratings ranging from 600 V to several tens of kV. Light with wavelengths below the absorption edge wavelength of 4H-SiC is absorbed by the SiC crystal, so the penetration depth into the crystal is limited. For example, the penetration depth of light with a wavelength of 310 nm is about 10 μm, but the penetration depth of light with a wavelength of 250 nm is shallower, at about 1 μm. Since basal plane dislocations, which are the starting points for stacking faults, exist near the interface between the discharge layer 1 and the running layer 2, it is desirable to use UV light with a wavelength that penetrates to about the thickness of the running layer 2 in order to enlarge stacking faults. Although the penetration depth of UV light with a wavelength of 250 nm is about 1 μm, the diffusion length of holes, which are minority carriers, is about 10 μm, so it can be used to enlarge stacking faults.

[0068] Furthermore, in design specifications requiring a thickness of approximately 100 μm for the running layer 2, stacking fault expansion treatment may be performed using UV light with a wavelength of approximately 300 nm or less. In this case, a base epitaxial layer with a UV light penetration depth of, for example, approximately 10 μm is grown on substrate 1s, and stacking fault expansion and reduction treatment is performed to immobilize the stacking faults. Subsequently, a new epitaxial layer with a thickness of approximately 90 μm is grown on the base epitaxial layer to fabricate an epitaxial substrate (1s, 2e). Because the stacking faults are immobilized in the base epitaxial layer, it is possible to prevent the stacking faults from expanding into the new epitaxial layer by applying current or light irradiation.

[0069] <Examples> As an example, multiple SiC wafers were prepared, each being 4H-SiC with an off-angle of 4°, an epitaxial film thickness of 10 μm, and a substrate thickness of 350 μm. Each SiC wafer was then subjected to sequential treatments: expansion of stacking faults by light irradiation, reduction of stacking faults by heating, and simulated current application by irradiating with light energy equivalent to the current density of the device.

[0070] A 355 nm UV laser was used for light irradiation, and the SiC wafer temperature during irradiation was set to 250°C. The light irradiation conditions for the photo-stack fault expansion process were defined as the irradiation energy density (in J / cm²), which is calculated by dividing the light source power supplied per unit area by the irradiation area and multiplying by the irradiation time. 2 The irradiation energy density was varied for each SiC wafer, as defined by the specified parameters. The conditions for reducing stacking faults by heating and for simulated current application were common to all SiC wafers. The stacking fault reduction treatment by heating was performed at 700°C for 12 hours. For each SiC wafer, the shape of the stacking faults was observed after the stacking fault expansion treatment by light irradiation, after the stacking fault reduction treatment by heating, and at the time of simulated current application. The location and number of expanded stacking faults were also identified during the observation at the time of simulated current application.

[0071] Figure 24 shows the relationship between irradiation energy density and defect re-expansion obtained from the observation results of each wafer, with the ratio of the number of defects that expanded during simulated energization to the total number of stacking faults being expressed as the re-expansion suppression rate (%). The plot in region P1 of Figure 24 corresponds to 1000 J / cm². 2 Below a certain threshold, the re-expansion suppression rate was 50% to 75%, and stacking faults did not expand after the stacking fault expansion treatment. The stacking faults that expanded during the simulated current application were found to be the parts where the stacking fault could not be expanded due to the low irradiation energy of the light during the stacking fault expansion treatment.

[0072] Furthermore, the 5000 J / cm² plot corresponds to the region P3 in Figure 24. 2 At temperatures exceeding a certain level, the re-expansion suppression rate was 5% to 10%, and re-expansion of stacking faults was observed. It was found that the re-expanded stacking faults were the parts that remained after the stacking fault expansion process, when the stacking fault completely expanded, creating overlapping regions that were not reduced during the reduction process.

[0073] Furthermore, the 1000 J / cm² plot corresponding to region P2 in Figure 24 is also relevant. 2 More than 5000J / cm 2In the range T below, the re-expansion suppression rate was 100%, meaning that the re-expansion of all stacking faults was suppressed. This is thought to be because the stacking faults were expanded in a range where they did not overlap during the expansion process, and then reduced and immobilized during the reduction process. Therefore, the irradiation energy density during the stacking fault expansion process was 1000 J / cm². 2 More than 5000J / cm 2 The following is preferable.

[0074] Figure 25 shows the Si wafer of the example, with a temperature of 5000 J / cm². 2 This is a PL image after processing stacking faults by light irradiation at an irradiation energy density exceeding [a certain value]. Stacking faults 41-44 shown in Figure 25 are completely enlarged. Of stacking faults 41-44, stacking faults 41 and 42 are composed of multiple stacking faults and have regions where multiple stacking faults overlap. On the other hand, stacking faults 43 and 44 are composed of a single stacking fault. Figure 26 is a PL image after stacking faults 41-44 shown in Figure 25 have been reduced by heating. As shown in Figure 26, in stacking faults 41 and 42, regions where multiple stacking faults overlap have not been completely reduced and remain. On the other hand, stacking faults 43 and 44 have been reduced and disappeared. Figure 27 is a PL image of stacking faults 41 and 42 shown in Figure 26 during simulated energization. As shown in Figure 27, during simulated energization, stacking faults 41 and 42 re-enlarge from the remaining parts.

[0075] (modified version) As shown in Figure 28, the semiconductor device according to a modified embodiment has an n provided between the discharge layer 1 and the traveling layer 2. + The semiconductor device differs from the embodiment shown in Figure 1 in that it further includes a buffer layer 6 of the type 1. The buffer layer 6 comprises a defect conversion layer 6a provided on the discharge layer 1 and a recombination promotion layer 6b provided on the defect conversion layer 6a. In Figure 25, the case in which the buffer layer 6 has a multilayer structure (composite structure) of a defect conversion layer 6a and a recombination promotion layer 6b is illustrated, but the buffer layer 6 may have only a defect conversion layer 6a, or only a recombination promotion layer 6b.

[0076] The defect conversion layer 6a is an epitaxial growth layer made of SiC. The defect conversion layer 6a has the function of converting, for example, about 95% of basal plane dislocations into through dislocations. The recombination promotion layer 6b is an epitaxial growth layer made of SiC. The recombination promotion layer 6b is p + It has the function of recombining holes injected from the injection region 3 of the mold with electrons, thereby reducing the number of minority carriers injected from the traveling layer 2 side to the discharge layer 1 side.

[0077] In the semiconductor device according to a modified embodiment, basal plane dislocations propagated from the discharge layer 1 reside within the defect conversion layer 6a. While a thicker defect conversion layer 6a reduces the frequency of stacking faults, increasing its thickness leads to a decrease in the epitaxial growth throughput, so it is preferable to thin it to, for example, 1 μm or less. To reduce the hole density injected into the basal plane dislocations present in the defect conversion layer 6a, the defect conversion layer 6a has a higher impurity concentration than the running layer 2. + It is preferable to use a type epitaxial layer.

[0078] Furthermore, the recombination-promoting layer 6b increases the hole density to 1 × 10⁻⁶. 15 cm -3 The number can be reduced to below a certain level. In addition to the n-type main impurity, the recombination promoting layer 6b is doped with a secondary impurity that forms hole trapping levels. The higher the impurity concentration of the main impurity, the lower the hole density can be. As secondary impurities, Al, boron (B), vanadium (V), titanium (Ti), iron (Fe), and chromium (Cr) can be used. The other configurations of the semiconductor device according to the modified embodiment are substantially the same as those of the semiconductor device according to the embodiment shown in Figure 1, so redundant descriptions are omitted.

[0079] As a method for manufacturing a semiconductor device according to a modified embodiment, n of 4H-SiC crystal + n on type substrate 1s + The n-type buffer layer 6 and the n-type epitaxial layer 2e are grown epitaxially in succession. The substrate 1s is a (0001) Si plane with its main surface 4° off in the <11-20> direction. The buffer layer 6 contains n-type impurities such as nitrogen (N) at a concentration of 1 × 10⁻¹⁶. 18 cm-3 The above is 1 x 10 19 cm -3 The following impurities are added. The thickness of the buffer layer 6 is, for example, about 1 μm. Since the buffer layer 6 is epitaxially grown on the substrate 1s, basal plane dislocations propagating from the substrate 1s are converted into threading dislocations within the buffer layer 6. The epitaxial layer 2e has n-type impurities added at a lower impurity concentration than the buffer layer 6. The thickness of the epitaxial layer 2e is, for example, about 10 μm.

[0080] Then, in the process of expanding stacking faults by light irradiation, the light irradiation is stopped before the stacking faults, which expand starting from basal plane dislocations near the interface between the substrate 1s and the buffer layer 6, overlap in the thickness direction of the buffer layer 6. The other steps of the method for manufacturing a semiconductor device according to the modified embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the embodiment, so redundant explanations are omitted.

[0081] According to a modified embodiment of the method for manufacturing a semiconductor device, in the process of expanding stacking faults by light irradiation, the light irradiation is stopped before the stacking faults, which expand starting from basal plane dislocations near the interface between the substrate 1s and the buffer layer 6, overlap in the thickness direction of the buffer layer 6. This reduces the overlap of stacking faults in the buffer layer 6. Therefore, in the stacking fault reduction process that follows the stacking fault expansion process, it is possible to prevent the reduction of stacking faults from stopping midway, and to reduce stacking faults more reliably.

[0082] Furthermore, buffer layer 6 is doped with n-type impurities at a higher impurity concentration than epitaxial layer 2e. Therefore, the hole density injected from epitaxial layer 2e into basal plane dislocations present at the interface between substrate 1s and buffer layer 6 is set to a threshold of 1 × 10⁻⁶. 15 cm -3 The number can be reduced to below a certain level. As a result, it is possible to prevent basal plane dislocations from expanding into stacking faults.

[0083] (Other embodiments) As described above, embodiments have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0084] As described above, although the embodiment was explained using 4H-SiC crystals, other crystal polymorphs such as cubic 3C-SiC and hexagonal 6H-SiC may also be used.

[0085] Furthermore, while the embodiment described an overlap of stacking faults where the fully enlarged shape forms a triangle in plan view, it is not limited to stacking faults that form a triangle. For example, it can be similarly applied to overlaps of stacking faults of other shapes, such as stacking faults where the fully enlarged shape forms a rectangle in plan view, or stacking faults where the longer side of the rectangle is serrated.

[0086] Furthermore, while the embodiments mainly described stacking faults originating from conversion points of basal plane dislocations distributed near the interface between the substrate 1s and the epitaxial layer 2e to through-edge dislocations, the embodiments can also be applied to overlapping stacking faults originating from basal plane dislocations that reach the surface of the epitaxial layer 2e without being converted to through-edge dislocations.

[0087] Furthermore, the configurations disclosed in the embodiments can be combined as appropriate, within the bounds of consistency. Thus, the present invention naturally includes various embodiments not described herein, such as configurations that arbitrarily apply the configurations described in the above embodiments and their respective modifications. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are reasonable given the above description. [Explanation of Symbols]

[0088] 1...Exhaust layer 1s… circuit board 2…Training Layer 2e…Epitaxial layer 3…Injection area 4…Anode electrode 5… Cathode electrode 6…Buffer layer 6a... Defect conversion layer 6b...Recombination promotion layer 10...Basal plane 11-13...Basal transposition 12x... Penetrating edge-shaped dislocation 21, 22…Stack faults 21a, 21b, 21c, 22a, 22b, 22c... sides 31-34, 41-44...Stack faults A,D…Starting point B, C, E, F... vertices A1,A2…area C(g), Si(g)...partial transposition D1,D2…interval T...range P1~P3…area θ1…Off-angle

Claims

1. A process for growing an epitaxial layer on a silicon carbide substrate, A step of irradiating the epitaxial layer with light having a wavelength less than or equal to the absorption edge wavelength of silicon carbide to expand stacking faults originating from basal plane dislocations propagated from the substrate to the epitaxial layer within the epitaxial layer, A step of heating the epitaxial layer in which the stacking fault has been enlarged to reduce the stacking fault, Includes, The step of expanding the stacking faults is characterized by calculating the light irradiation time until the expanded stacking faults overlap each other, based on the interval between the starting points of the multiple stacking faults, and irradiating with light for a time shorter than the light irradiation time.

2. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1, characterized in that the stacking fault originates from the basal plane dislocation in the boundary region of the interface between the substrate and the epitaxial layer.

3. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1 or 2, characterized in that the step of expanding the stacking fault is stopped before the ends of the two sides extending from the starting point of the stacking fault reach the surface of the epitaxial layer.

4. The irradiation energy density of the aforementioned light is 1000 J / cm². ２ Above, 5000J / cm ２ A method for producing a silicon carbide epitaxial substrate according to claim 1 or 2, characterized in that it is as follows.

5. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1 or 2, characterized in that the light is irradiated onto the surface of the epitaxial layer all at once.

6. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1 or 2, characterized in that the light is irradiated while scanning the surface of the epitaxial layer with an irradiation area smaller than the surface area of ​​the epitaxial layer.

7. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1 or 2, characterized in that the light is laser light.

8. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1 or 2, characterized in that the step of reducing stacking faults is to heat the epitaxial layer at a temperature of 400°C or higher and 1000°C or lower.

9. A method for manufacturing a silicon carbide epitaxial substrate according to claim 1 or 2, further comprising a step of detecting the stacking fault between the step of enlarging the stacking fault and the step of reducing the stacking fault.

10. The method for manufacturing a silicon carbide epitaxial substrate according to claim 9, characterized in that the step of reducing stacking faults is to adjust the heating conditions of the epitaxial layer according to the detection results of the stacking faults.

11. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1 or 2, characterized in that the substrate is a polymorph crystal of any of 4H, 6H, and 3C.

12. A process of epitaxially growing a first conductive running layer on a silicon carbide substrate, A step of irradiating the traveling layer with light having a wavelength less than or equal to the absorption edge wavelength of silicon carbide, thereby expanding stacking faults originating from basal plane dislocations propagated from the substrate to the traveling layer within the traveling layer, A step of heating the running layer in which the stacking fault has been enlarged to reduce the stacking fault, A step of forming a second conductive injection region on the upper part of the aforementioned running layer, Includes, A method for manufacturing a semiconductor device, characterized in that the step of expanding the stacking faults involves calculating the light irradiation time until the expanded stacking faults overlap each other, based on the interval between the starting points of the multiple stacking faults, and irradiating the light for a time shorter than the light irradiation time.

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