Arithmetic processing unit and arithmetic processing method

Abstract

To provide an arithmetic processing unit capable of improving computing performance, and an arithmetic processing method.SOLUTION: A state management unit 134 is configured to calculate stride width based on the requested address of each of the two memory access instructions indicated by a given program counter and detect the occurrence of stride access based on the request address of multiple memory access instructions indicated by a given program counter and the calculated stride width. A prefetch request generation unit 133 is configured so as to, when stride access is detected by the state management unit 134, issue a prefetch request based on the stride width.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an arithmetic processing unit and an arithmetic processing method.

Background Art

[0002] A computer has a cache memory with multiple levels between a CPU (Central Processing Unit) core and a main memory device, aiming to conceal the access latency to the main memory device and lower-level cache memories and improve the throughput shortage. Furthermore, in recent years, the cores in CPUs have been becoming faster and more cores have been added, making it important to improve the hit rate of cache memory and conceal cache miss latency.

[0003] As one of the methods for improving the hit rate of cache memory and concealing cache miss latency, the introduction of a prefetch technique that reduces the occurrence of cache misses by preloading data predicted to be used in the near future into the cache memory in advance is progressing. As a method for realizing prefetch, there are a software-based method called software prefetch and a hardware-based method called hardware prefetch.

[0004] Conventionally, as hardware prefetch techniques, a technique called stream prefetch and a technique called stride prefetch have been widely adopted. Stream prefetch is a hardware prefetch technique that performs prefetch for stream access, which is continuous access in cache line units. Stride prefetch is a hardware prefetch technique that performs prefetch for regular stride access at a fixed interval.

[0005] Here, we will explain the case where memory access instructions such as load and store instructions, such as access A1, access A2, etc., access predetermined locations in main memory in sequential order. For example, if access A1, access A2, etc. access sequentially on a cache line basis, the CPU can handle this with stream prefetching. For example, the CPU detects that it is a stream access from the cache memory addresses accessed by access A1, access A2, and access A3. The CPU then predicts that an access will come to the next cache memory address after access A3, and prefetches the area that access A4 will access into the cache memory in advance. As a result, since the data is already registered in the cache memory when the instruction access A4 is executed, the CPU can reduce the occurrence of cache misses and improve computational performance.

[0006] On the other hand, if access A1, access A2, ... access the cache line at regular intervals, the CPU can handle this with stride prefetching. For example, the CPU detects that access A1, access A2, and access A3 are accessing the cache memory address (address) that was accessed, skipping one address each time. The CPU then predicts that the next access after access A3 will also skip one address, and prefetches the area that access A4 will access into the cache memory in advance. In this case as well, since the data is already registered in the cache memory when the instruction for access A4 is executed, the CPU can reduce the occurrence of cache misses and improve computational performance. The width of this regular interval of the cache line is called the stride width.

[0007] Here, stride access can be divided into single-stride and multi-stride. Single-stride access occurs when access always occurs with a constant stride width. In contrast, multi-stride access occurs when access occurs with a mixture of multiple stride widths. For example, multi-stride access occurs when a certain number of accesses occur with a first stride width, followed by accesses with a different second stride width. However, even with multi-stride access, if there is a mixture of two types of stride widths—one within the cache line size and one exceeding the cache line size—it can be considered as single-stride access on a cache line basis.

[0008] One proposed prefetching technique involves determining the stride width based on the difference between the preceding and succeeding addresses, counting the number of stride widths for each memory access, and performing a prefetch when the counter exceeds an upper limit. Another proposed technique involves incrementing or decrementing a counter depending on whether the stride width falls within a predetermined range, and then calculating the stride width based on the counter value to perform a prefetch. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Special Publication No. 2006-510082 [Patent Document 2] Special Publication No. 2013-539117 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] However, conventional stride prefetching targets single-stride accesses. Conventional stride prefetching does not distinguish between multi-stride and single-stride access patterns, and triggers single-stride prefetching even for multi-stride accesses. Triggering single-stride prefetching for multi-stride accesses can result in prefetching at incorrect addresses. This can lead to cache contamination due to storing unnecessary data in the cache and pressure on memory bandwidth, potentially causing a decrease in CPU performance.

[0011] For example, since many stride widths are 128 bytes, conventional techniques often initiate prefetching at 128 bytes. However, if the stride width changes to another width, such as 192 bytes, the prefetch destination address may point to inappropriate data, resulting in an incorrect prefetch. This is true even for multiple strides, which can be viewed as a single stride on a cache line basis.

[0012] Furthermore, in techniques that perform prefetching when the stride width count exceeds an upper limit, there is a risk of incorrect prefetching because the system may not be able to adequately track changes in stride width. Also, in techniques that calculate and perform prefetching based on a counter that is increased or decreased depending on whether the stride width falls within a predetermined range, it is difficult to reliably determine the stride width, and there is a risk of incorrect prefetching. Therefore, it is difficult to improve the CPU's computational performance using any of these techniques.

[0013] The disclosed technology was made in view of the above, and aims to provide a processing unit and a processing method that improve computational performance. [Means for solving the problem]

[0014] In one embodiment of the arithmetic processing unit and arithmetic processing method disclosed in this application, If a cache miss occurs in the first memory access instruction indicated by a predetermined program counter, and a predetermined entry containing the information of the predetermined program counter does not exist in the prefetch queue, the monitoring unit registers the predetermined entry containing the information of the predetermined program counter in the prefetch queue. The management department, Multiple second memory access instructions are indicated by the request address of the first memory access instruction and the predetermined program counter following the predetermined entry.Calculate the stride width based on each requested address of the memory access instruction The predicted address is registered in the predetermined entry, and the predicted address calculated by adding the stride width to the request address of the second memory access instruction is registered in the predetermined entry, the predicted address is sequentially updated with a value calculated by adding the stride width to each of the request addresses of the plurality of third memory access instructions indicated by the predetermined program counter that follow the second memory access instruction, and the request address of each of the third memory access instructions is compared with the predicted address registered in the predetermined entry. Detect the occurrence of a stride access. When the stride access is detected by the management unit, the prefetch request generation unit issues a prefetch request based on the stride width.

Effect of the Invention

[0015] In one aspect, the present invention can improve the computing performance.

Brief Description of the Drawings

[0016] [Figure 1] FIG. 1 is a schematic diagram showing the overall configuration of an information processing apparatus. [Figure 2] FIG. 2 is a block diagram showing the details of the CPU according to the embodiment. [Figure 3] FIG. 3 is a diagram showing an example of the format of an entry stored in the prefetch queue according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing a state machine for managing the state of an entry in the prefetch queue. [Figure 5] FIG. 5 is a diagram showing a list of information updated in each entry during state transition. [Figure 6] FIG. 6 is a diagram showing an example of the transition of an entry in the case of a single stride. [Figure 7] FIG. 7 is a diagram showing an example of access and prefetch in the case of a single stride. [Figure 8] FIG. 8 is a diagram showing an example of the transition of an entry in the case of multiple strides. [Figure 9] FIG. 9 is a diagram showing an example of access in the case of multiple strides. [Figure 10] FIG. 10 is a diagram showing an example of the transition of an entry in the case of multiple strides but a single stride when viewed in terms of cache lines. [Figure 11]FIG. 11 is a diagram showing an example of access and prefetch when there are multiple strides but it becomes a single stride when viewed in terms of cache lines. [Figure 12] FIG. 12 is a flowchart of prefetch processing by the CPU according to Example 1. [Figure 13] FIG. 13 is a flowchart of state update processing by the state management unit. [Figure 14] FIG. 14 is a flowchart of the execution of state update processing in State #2. [Figure 15] FIG. 15 is a flowchart of the execution of state update processing in State #3. [Figure 16] FIG. 16 is a flowchart of the execution of state update processing in State #4. [Figure 17] FIG. 17 is a diagram showing an example of the format of an entry stored in the prefetch queue according to Example 2. [Figure 18] FIG. 18 is a diagram showing an example of a state machine for replacement control. [Figure 19] FIG. 19 is a flowchart of prefetch processing by the CPU according to Example 2.

Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments of the arithmetic processing apparatus and arithmetic processing method disclosed in the present application will be described in detail based on the drawings. Note that the arithmetic processing apparatus and arithmetic processing method disclosed in the present application are not limited by the following embodiments.

Examples

[0018] Figure 1 is a schematic diagram showing the overall configuration of an information processing device. As shown in Figure 1, the information processing device 1 includes an arithmetic unit 11, an L1 cache 12, a lower cache 13, a main memory 14, an auxiliary storage device 15, a display device 16, and an input device 17. The arithmetic unit 11 is connected by bus to the L1 cache 12, the lower cache 13, the main memory 14, the auxiliary storage device 15, the display device 16, and the input device 17. The arithmetic unit 11, the L1 cache 12, and the lower cache 13 are mounted, for example, on a CPU 10, which is an arithmetic processing device.

[0019] The arithmetic unit 11 is, for example, a CPU (Central Processing Unit) core. The arithmetic unit 11 reads various programs stored in the auxiliary storage device 15, loads them into the main memory 14, and performs calculations using the L1 cache 12, the lower cache 13, and the data stored in the main memory 14.

[0020] The L1 cache 12 is a cache memory that operates quickly and has a smaller capacity than the lower cache 13, and is the first cache memory read when the arithmetic unit 11 accesses data. The L1 cache 12 is, for example, SRAM (Static Random Access Memory).

[0021] The lower cache 13 is a cache memory that operates quickly and generally has a larger capacity than the L1 cache 12. It is the next cache memory that is read when a cache miss occurs in the L1 cache 12 during data access by the arithmetic unit 11. The lower cache 13 is the L2 cache or L3 cache. The lower cache 13 is also, for example, SRAM.

[0022] Here, there is no particular limit to the number of layers in the lower cache 13. For example, the information processing device 1 may have two layers or four or more layers as cache layers.

[0023] Main memory 14 is a main memory that operates at a slower speed and has a larger capacity compared to the L1 cache 12 and the lower cache 13. Data used by the arithmetic unit 11 for calculations is stored in main memory 14. Main memory 14 is accessed by the arithmetic unit 11 when the data to be accessed is not found in either the L1 cache 12 or the lower cache 13. Main memory 14 is, for example, DRAM (Dynamic Random Access Memory).

[0024] The auxiliary storage device 15 is, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive). The auxiliary storage device 15 stores the OS (Operating System) and various programs for performing calculations.

[0025] The display device 16 is, for example, a monitor or display. The display device 16 presents the calculation results from the calculation unit 11 to the user. The input device 17 is, for example, a keyboard or mouse. The user inputs data and commands to the information processing device 1 using the input device 17 while referring to the screen displayed on the display device 16. The display device 16 and the input device 17 may be configured as a single piece of hardware.

[0026] Figure 2 is a block diagram showing the details of a CPU according to an embodiment. The CPU 10 has an instruction issuing unit 101, an L1 cache control unit 102, a stride prefetch control unit 103, an L1 cache 12, and a lower cache 13, all of which are part of the arithmetic unit 11.

[0027] The instruction issuing unit 101 issues memory access instructions, such as read instructions, to the L1 cache control unit 102 in response to calculations performed by the arithmetic unit 11. The instruction issuing unit 101 also notifies the stride prefetch control unit 103 of the requested address and program counter of the memory access instruction.

[0028] The L1 cache control unit 102 receives a memory access instruction from the instruction issuing unit 101. The L1 cache control unit 102 then receives a PC (Program Counter) miss notification from the pattern monitoring unit 132, which notifies the stride prefetch control unit 103 that no data exists in the prefetch queue 131. The L1 cache control unit 102 then determines whether the data specified by the memory access instruction is stored in the L1 cache 12. Hereinafter, if the data specified by the memory access instruction is not stored in the L1 cache 12, it will be called an L1 cache miss. Conversely, if the data specified by the memory access instruction is stored in the L1 cache 12, it will be called an L1 cache hit.

[0029] In the event of an L1 cache hit, the L1 cache control unit 102 retrieves the data specified by the memory access instruction from the L1 cache 12 and outputs it to the arithmetic unit 11. The L1 cache control unit 102 also notifies the pattern monitoring unit 132 of the L1 cache hit.

[0030] In contrast, in the event of an L1 cache miss, the L1 cache control unit 102 outputs a request to retrieve the data specified by the memory access instruction to the lower cache 13. Subsequently, the L1 cache control unit 102 retrieves the data specified by the memory access instruction from the lower cache 13, outputs it to the arithmetic unit 11, and stores it in the L1 cache 12. The L1 cache control unit 102 also notifies the pattern monitoring unit 132 of the L1 cache miss.

[0031] The stride prefetch control unit 103 includes a prefetch queue 131, a pattern monitoring unit 132, a prefetch request generation unit 133, and a state management unit 134.

[0032] The prefetch queue 131 has, for example, N+1 entries. Figure 3 shows an example of the format of entries stored in the prefetch queue according to Embodiment 1. Each entry in the prefetch queue 131 registers program counter, state information, stride information, confidence counter, and address information, as shown in format 201.

[0033] The program counter represents the program counter for memory access instructions for prefetched data stored in the prefetch queue 131. The state information indicates the state of an entry in the prefetch queue 131. In this embodiment, there are five states: states #1 to #4. State #0 represents an invalid state, i.e., an empty entry. State #1 represents the initial registration state. State #2 represents the stride width registration state. State #3 represents a state where the address was hit in the previous access. State #4 represents a state where the address was missed in the previous access. The confidence counter is information indicating the confidence of the stride access.

[0034] Returning to Figure 2, the pattern monitoring unit 132 receives notification of the requested address and program counter of the memory access instruction from the instruction issuing unit 101 when the instruction issuing unit 101 issues a memory access instruction. The pattern monitoring unit 132 then searches the prefetch queue 131 using the program counter of the memory access instruction. In the following, if an entry with a matching program counter is registered in the prefetch queue 131, this will be referred to as a "PC (Program Counter) hit." Conversely, if no entry with a matching program counter is registered in the prefetch queue 131, this will be referred to as a "PC miss."

[0035] In the event of a PC hit, the pattern monitoring unit 132 notifies the state management unit 134 of the value of the entry's program counter along with the notification of the PC hit.

[0036] In the case of a PC error, the pattern monitoring unit 132 notifies itself of the PC error. Subsequently, in the case of an L1 cache error, the pattern monitoring unit 132 receives notification of the L1 cache error from the L1 cache control unit 102. The pattern monitoring unit 132 then determines whether or not there is space in the prefetch queue 131 to store a new entry.

[0037] If there is space available in the prefetch queue 131, the pattern monitoring unit 132 sets the state information of the newly registered entry for the memory access instruction that has experienced an L1 cache miss to state #1. The pattern monitoring unit 132 also sets the program counter of the newly registered entry to the program counter of the memory access instruction. Furthermore, the pattern monitoring unit 132 registers the requested address of the memory access instruction as the predicted address in the address information of the newly registered entry. Here, since the stride width information is invalid in state #1, the pattern monitoring unit 132 registers an arbitrary value, such as a predetermined initial value, as the stride width information. Then, the pattern monitoring unit 132 registers the new entry in the prefetch queue 131 with the above information.

[0038] In response to this, if there is no space available in the prefetch queue 131, the pattern monitoring unit 132 searches for and deletes the entry with the longest storage time in the prefetch queue 131. Subsequently, the pattern monitoring unit 132 registers the entry corresponding to the memory access instruction that caused the L1 cache miss in the prefetch queue 131 using the same procedure as when there is space available in the prefetch queue 131. This pattern monitoring unit 132 is an example of a "monitoring unit". Furthermore, the memory access instruction corresponding to the newly registered entry by the pattern monitoring unit 132 is an example of a "first memory access instruction". Furthermore, this newly registered entry by the pattern monitoring unit 132 is an example of a "predetermined entry".

[0039] Thus, if a cache miss occurs in the first memory access instruction indicated by a predetermined program counter, and a predetermined entry containing the information of the predetermined program counter does not exist in the prefetch queue 131, the pattern monitoring unit 132 performs the following processing: The pattern monitoring unit 132 registers a predetermined entry containing the information of the predetermined program counter in the prefetch queue 131.

[0040] Figure 4 shows a state machine that manages the state of entries in the prefetch queue. Since no new entries are added unless a cache miss occurs, the pattern monitoring unit 132 maintains the state of entries in the prefetch queue 131 at that time (step S1).

[0041] In contrast, if a cache miss occurs, the pattern monitoring unit 132 registers a new entry in the prefetch queue 131 containing the program counter value of the memory access instruction that caused the cache miss, and sets the state information to state #1. That is, the pattern monitoring unit 132 transitions the entry that was in state #0 to state #1 (step S2).

[0042] Returning to Figure 2, the explanation continues. The state management unit 134 receives notification of a PC hit and the value of the program counter for the entry that was hit by the PC from the pattern monitoring unit 132. The state management unit 134 then updates the state information and the confidence counter value of the entry in the prefetch queue 131 that was hit by the PC according to the state machine. This state management unit 134 is an example of a "management unit".

[0043] The process of updating state information is described below with reference to Figure 4. Here, an entry in which a PC hit occurs and the state management unit 134 obtains the program counter value from the pattern monitoring unit 132 is called a "target entry". Also, below, when the state information of an entry is states #1 to #4, it may simply be said that the entry is in states #1 to #4. The state management unit 134 obtains the state information, stride width information, confidence counter value, and address information of the target entry from the prefetch queue 131.

[0044] If the target entry is in state #1, the state management unit 134 changes the state information of the target entry to state #2, transitioning the target entry from state #1 to state #2. The state management unit 134 also subtracts the predicted address registered in the entry from the request address of the memory access instruction that hit the PC, and registers the calculation result as the stride width from the previous access in the stride width information of the target entry. Furthermore, the state management unit 134 calculates the predicted address by adding the request address and the calculated stride width, and registers the calculated predicted address in the address information of the target entry (step S3). The predicted address stored in this address information is the predicted value of the request address of the next memory access instruction with the same program counter.

[0045] If the target entry is in one of states #2 to #4, the address information contains the predicted address of the next identical program counter to be issued. Therefore, if the target entry is in one of states #2 to #4, the state management unit 134 performs an address hit determination to determine whether the requested address matches the predicted address registered in the entry. When the requested address matches the predicted address registered in the entry, it is called an "address hit". Conversely, when the requested address does not match the predicted address registered in the entry, it is called an "address miss".

[0046] If an address hit occurs when the target entry is in state #2, the state management unit 134 transitions the target entry to state #3. The state management unit 134 also sets the confidence counter to 3 (step S4).

[0047] In contrast, if an address error occurs when the target entry is in state #2, the state management unit 134 transitions the target entry to state #4. Furthermore, the state management unit 134 sets the confidence counter to 1 (step S5).

[0048] Furthermore, the state management unit 134 calculates a predicted address by adding the stride width to the requested address in both the case of an address hit and an address miss, and registers the calculated predicted address in the address information of the target entry.

[0049] If an address hit occurs when the target entry is in state #3, the state management unit 134 increments the confidence counter by one while maintaining the state information of the target entry as state #3 (step S6).

[0050] In contrast, if an address error occurs when the target entry is in state #3, the state management unit 134 determines whether the value of the target entry's confidence counter has reached a predetermined upper limit. If the value of the target entry's confidence counter has not reached the upper limit, the state management unit 134 sets the confidence counter to 1. On the other hand, if the value of the target entry's confidence counter has reached the upper limit, the state management unit 134 decrements the confidence counter by one while maintaining the target entry's state information in state #4. Then, the state management unit 134 transitions the target entry to state #4 (step S7).

[0051] If an address hit occurs when the target entry is in state #4, the state management unit 134 transitions the target entry to state #3. Furthermore, the state management unit 134 increments the confidence counter of the target entry by one (step S8).

[0052] In contrast, if an address error occurs when the target entry is in state #4, the state management unit 134 decrements the confidence counter of the target entry by one while maintaining the state information of the target entry (step S9). The state management unit 134 then determines whether the value of the confidence counter is 0 or not. If the value of the confidence counter is not 0, the state management unit 134 maintains the state of the target entry at that time. In contrast, if the value of the confidence counter is 0, the state management unit 134 transitions the target entry to state #0 and puts it into an invalid state (step S10).

[0053] The target entry is an example of a "predetermined entry." Furthermore, a memory access instruction with a program counter registered in the target entry, from the time the target entry is registered in the prefetch queue 131 until the transition to state #3, is an example of a "second memory access instruction." Furthermore, a memory access instruction with a program counter registered in the target entry after the transition to state #3 is an example of a "third memory access instruction." In other words, the state management unit 134 calculates the stride width based on the request address of the first memory access instruction and the request addresses of each of the multiple second memory access instructions indicated by the predetermined program counter following the predetermined entry, and registers it in the predetermined entry. In addition, the state management unit 134 registers the predicted address calculated by adding the stride width to the request address of the second memory access instruction in the predetermined entry. Furthermore, the state management unit 134 sequentially updates the predicted address with a value calculated by adding the stride width to each of the multiple third memory access instructions indicated by the predetermined program counter following the second memory access instruction. The state management unit 134 then detects the occurrence of a stride access by comparing the requested address of each third memory access instruction with the predicted address registered in a predetermined entry.

[0054] Figure 5 shows a list of information updated in each entry during a state transition. Next, referring to Table 202 in Figure 5, we will explain the information other than the confidence counter that is updated in each entry during a state transition. In Table 202 in Figure 5, the confidence counter value has been omitted.

[0055] When transitioning a target entry from state #0 to state #1, the pattern monitoring unit 132 registers the program counter of the memory access instruction as the program counter of the target entry. The pattern monitoring unit 132 also registers the requested address of the memory access instruction as the predicted address. In this case, the pattern monitoring unit 132 may register an appropriate value for the stride width.

[0056] When transitioning a target entry from state #1 to state #2, the state management unit 134 maintains the value of the program counter. In state #1, the address information stores the previous requested address as the predicted address, so the state management unit 134 calculates the stride width by subtracting the predicted address from the requested address. The state management unit 134 also calculates the predicted address by adding the stride width to the requested address, registers it as address information, and updates it.

[0057] When transitioning the target entry from state #4 to state #0, or when not transitioning from state #0, the pattern monitoring unit 132 and the state management unit 134 do not update any information other than the entry's confidence counter.

[0058] In cases other than the state transitions described above, the state management unit 134 maintains the value of the program counter. The state management unit 134 also maintains the stride width information. Furthermore, the state management unit 134 calculates a predicted address by adding the stride width to the requested address, registers it as address information, and updates it.

[0059] Returning to Figure 2, the explanation continues. After updating the state information of the target entry, the state management unit 134 determines whether the conditions for issuing a prefetch request to the lower cache 13 are met for the target entry. If the conditions for issuing a prefetch request are met, the state management unit 134 infers that a stride access will be performed with the stride width indicated by the stride width information. If it determines that the conditions for issuing a prefetch request are met, the state management unit 134 requests the prefetch request generation unit 133 to issue a prefetch request. At this time, the state management unit 134 outputs the value of the program counter of the entry that met the conditions for issuing a prefetch request to the prefetch request generation unit 133.

[0060] Here, the conditions for issuing a prefetch request are that the target entry is an address hit, the state is #3, and the value of the confidence counter exceeds a threshold. A higher threshold for the confidence counter improves the accuracy of stride access determination, but delays the initiation of prefetching. In other words, it is preferable to set the threshold for the confidence counter value according to the operation, taking into account the balance between the accuracy of stride access determination and the initiation of prefetching. If the threshold is, for example, 6, the state management unit 134 sets the confidence counter to 3 when an address hit occurs in state #1. Then, if there are four consecutive accesses with the same stride width, the state management unit 134 sets the confidence counter to 6 and determines that the conditions for issuing a prefetch request are met. In other words, the state management unit 134 determines that stride access is being performed with that stride width.

[0061] The prefetch request generation unit 133 receives a request to issue a prefetch request from the state management unit 134, along with the program counter value of the entry that satisfies the conditions for issuing a prefetch request. Next, the prefetch request generation unit 133 obtains stride width information from the entry that has the obtained program counter value. Then, the prefetch request generation unit 133 issues a prefetch request to the lower cache 20 at an address calculated by adding a value obtained by multiplying the acquired stride width by a predetermined number to the request address of the memory access instruction that missed the cache. Here, the predetermined number is an arbitrary integer value, and for example, a value is set that allows data to be registered in the L1 cache 12 before the memory access instruction for the address for which the prefetch request was issued is issued by the instruction issuing unit 101.

[0062] Figure 6 shows an example of entry transitions in the case of a single stride. Next, we will explain a specific example of entry transitions in the case of a single stride, referring to Figure 6. Here, we will use a convenient number of 100 as the stride width and assume a cache line size of 50. In Figure 6, a single stride access is performed, with memory access instructions starting at address 0 and continuing with a stride width of 100. Also, the program counter is assumed to be memory access instructions for address 1000 as an example. Furthermore, the upper limit of the confidence counter that issues prefetch is set to 6. The arrows in each column of Figure 6 represent the update of information from below the arrow to the next arrow.

[0063] The instruction issuing unit 101 issues a memory access request to an address with address number 0. When an L1 cache miss occurs, the pattern monitoring unit 132 initially registers an entry in the prefetch queue 131. Then, the pattern monitoring unit 132 sets the entry's state information to state #1, registers 1000 in the program counter, and registers 0 as the address information (step S11).

[0064] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 100. When an L1 cache miss occurs, the pattern monitoring unit 132 detects a PC hit for entry 1000 in the program counter. The state management unit 134 then subtracts the 0s stored in the address information from the requested address 100 to determine the stride width as 100. Next, the state management unit 134 registers the determined stride width as stride width information and registers 200, which is the sum of the requested address 100 and the stride width 100, as the predicted address in the address information. Furthermore, the state management unit 134 changes the state information from state #1 to state #2 (step S12).

[0065] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 200. This memory access request is an address hit because the requested address matches the predicted address registered in the entry where the program counter is 1000. Therefore, the state management unit 134 changes the state information from state #2 to state #3. Furthermore, the state management unit 134 sets the confidence counter to 3. The state management unit 134 also registers 300, which is the value obtained by adding the stride width of 100 to the requested address 200, as the predicted address in the address information (step S13).

[0066] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 300. Since this memory access request also results in an address hit, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains state information and stride width information for the entry. The state management unit 134 also registers 400, which is the value obtained by adding the stride width of 100 to the requested address 300, as the predicted address in the address information (step S14).

[0067] Next, since the memory access request to address number 400 issued by the instruction issuing unit 101 also results in an address hit, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains state information and stride width information for the entry. The state management unit 134 also registers 500, which is the value obtained by adding the stride width of 100 to the requested address 400, as the predicted address in the address information (step S15).

[0068] Next, since the memory access request to address number 500 issued by the instruction issuing unit 101 also results in an address hit, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains state information and stride width information for the entry. The state management unit 134 also registers 600, which is the value obtained by adding the stride width of 100 to the requested address 500, as the predicted address in the address information. Furthermore, since the confidence counter becomes 6 or greater, the state management unit 134 determines that the conditions for issuing a prefetch request have been met. The state management unit 134 then requests the prefetch request generation unit 133 to issue a prefetch request. The prefetch request generation unit 133 performs a prefetch at an address with the address number 500 + 100 × N, which is obtained by adding a value obtained by multiplying the stride width of 100 by a predetermined number N to the requested address 500 (step S16).

[0069] Next, since the memory access request to address number 600 issued by the instruction issuing unit 101 also results in an address hit, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains state information and stride width information for the entry. The state management unit 134 also registers 700, which is the value obtained by adding the stride width of 100 to the requested address 600, as the predicted address in the address information. Furthermore, since the confidence counter is 6 or greater, the state management unit 134 determines that the conditions for issuing a prefetch request have been met. The state management unit 134 then requests the prefetch request generation unit 133 to issue a prefetch request. The prefetch request generation unit 133 performs a prefetch at an address with an address number of 600 + 100 × N (step S17).

[0070] Figure 7 shows an example of access and prefetching in the case of a single stride. Here, we will explain the case where the predetermined number N used during prefetching is 2.

[0071] As shown in Figure 7, in the case of a single stride, accesses with a stride width of 100 are repeated. Therefore, the state management unit 134 increments the confidence counter with each memory access instruction. When the confidence counter then reaches its upper limit, the state management unit 134 performs a prefetch for an address whose address number is obtained by adding 100 × 2 to the requested address, with a stride width of 100. In this case, since it is a single stride, the prefetch is successful.

[0072] Figure 8 shows an example of entry transitions in the case of multiple strides. Next, with reference to Figure 8, a specific example of entry transitions in the case of multiple strides will be explained. Here, we will use round numbers such as 100 and 2000 as stride widths, and the cache line size will be assumed to be 50. In Figure 8, multiple stride access is performed, and the instruction issuer 101 issues three consecutive memory access instructions with a stride width of 100, starting with address 0, followed by one memory access instruction with a stride width of 2000, and repeats this instruction issuance. Also, the program counter is assumed to be a memory access instruction of 1000 as an example. Furthermore, the upper limit of the confidence counter for issuing prefetches is set to 6. The arrows in each column of Figure 8 represent the update of information from the bottom to the end of the arrow.

[0073] The instruction issuing unit 101 issues a memory access request to an address with address number 0. When an L1 cache miss occurs, the pattern monitoring unit 132 initially registers an entry in the prefetch queue 131. Then, the pattern monitoring unit 132 sets the entry's state information to state #1, registers 1000 in the program counter, and registers 0 as the address information (step S21).

[0074] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 100. When an L1 cache miss occurs, the pattern monitoring unit 132 detects a PC hit for entry 1000 in the program counter. The state management unit 134 then subtracts the 0s stored in the address information from the requested address 100 to determine the stride width as 100. Next, the state management unit 134 registers the determined stride width as stride width information and registers 200, which is the sum of the requested address 100 and the stride width 100, as the predicted address in the address information. Furthermore, the state management unit 134 changes the state information from state #1 to state #2 (step S22).

[0075] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 200. This memory access request is an address hit because the requested address matches the predicted address registered in the entry where the program counter is 1000. Therefore, the state management unit 134 changes the state information from state #2 to state #3. Furthermore, the state management unit 134 sets the confidence counter to 3. The state management unit 134 also registers 300, which is the value obtained by adding the stride width of 100 to the requested address 200, as the predicted address in the address information (step 23).

[0076] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 300. Since this memory access request also results in an address hit, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains state information and stride width information for the entry. The state management unit 134 also registers 400, which is the value obtained by adding the stride width of 100 to the requested address 300, as the predicted address in the address information (step S24).

[0077] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 2300. In this memory access request, the requested address does not match the predicted address registered in the entry where the program counter is 1000, resulting in an address error. Therefore, the state management unit 134 changes the state information from state #3 to state #4. Also, since the confidence counter value is 4 and has not reached its upper limit, the state management unit 134 changes the confidence counter to 1. Furthermore, the state management unit 134 registers 2400, which is the value obtained by adding the stride width of 100 to the requested address 2300, as the predicted address in the address information (step S25).

[0078] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 2400. In this memory access request, the requested address matches the predicted address registered in the entry where the program counter is 1000, so the state management unit 134 changes the state information from state #4 to state #3. Furthermore, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains the state information and stride width information for the entry. The state management unit 134 also registers 2500, which is the value obtained by adding the stride width of 100 to the requested address 2400, as the predicted address in the address information (step S26).

[0079] Next, since the memory access request to address number 2500 issued by the instruction issuing unit 101 also results in an address hit, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains state information and stride width information for the entry. The state management unit 134 also registers 2600, which is the value obtained by adding the stride width of 100 to the requested address 2500, as the predicted address in the address information (step S27).

[0080] Next, since the memory access request to address number 2600 issued by the instruction issuing unit 101 also results in an address hit, the state management unit 134 increments the confidence counter. In this case, the state management unit 134 maintains state information and stride width information for the entry. The state management unit 134 also registers 2700, which is the value obtained by adding the stride width of 100 to the requested address 2600, as the predicted address in the address information (step S28).

[0081] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 4600. In this memory access request, the requested address does not match the predicted address registered in the entry where the program counter is 1000, resulting in an address error. Therefore, the state management unit 134 changes the state information from state #3 to state #4. Furthermore, since the confidence counter value is 4 and has not reached its upper limit, the state management unit 134 changes the confidence counter to 1. In addition, the state management unit 134 registers 4700, which is the value obtained by adding the stride width of 100 to the requested address 4600, as the predicted address in the address information (step S29).

[0082] In this way, the state management unit 134 can determine that it is not a single stride because the confidence counter does not reach its upper limit, and can suppress the issuance of erroneous prefetches.

[0083] Figure 9 shows an example of access in the case of multiple strides. As shown in Figure 9, in the case of multiple strides, as long as accesses with a stride width of 100 are repeated, the state management unit 134 increases the confidence counter with each memory access instruction. However, before the confidence counter reaches its upper limit, an access with a stride width of 2000 occurs, resulting in an address miss, and the state management unit 134 decreases the value of the confidence counter. Therefore, the confidence counter does not reach its upper limit, and the state management unit 134 can avoid incorrect prefetching.

[0084] Figure 10 shows an example of entry transitions when there are multiple strides but when viewed as a single stride on a cache line basis. Next, referring to Figure 10, a specific example of entry transitions in the case of multiple strides will be explained. Here, we will use stride widths of 8 and 68, and the cache line size will be assumed to be 50. In Figure 10, multiple stride access is performed, and the instruction issuer 101 issues three consecutive memory access instructions with a stride width of 8, starting with address 0, followed by one memory access instruction with a stride width of 68, and repeats this instruction issuance. In other words, when viewed on a stride width basis, the instruction issuer 101 can be said to be repeatedly issuing memory access instructions with a stride width of 100. Also, the program counter is assumed to be a memory access instruction of 1000 as an example. Furthermore, the upper limit of the confidence counter for issuing prefetch is assumed to be 6. The arrows in each column of Figure 10 represent the update of information from the source to the end of the arrow.

[0085] The instruction issuing unit 101 issues a memory access request to an address with address number 0. When an L1 cache miss occurs, the pattern monitoring unit 132 initially registers an entry in the prefetch queue 131. Then, the pattern monitoring unit 132 sets the entry's state information to state #1, registers 1000 in the program counter, and registers 0 as the address information (step S31).

[0086] Next, the instruction issuing unit 101 sequentially issues memory access requests to addresses with address numbers 8, 16, and 32. Access to addresses with address numbers 8, 16, and 32 is the same cache line access as access to an address with address number 0. Hereafter, the fact that a subsequent memory access request is to the same cache line as a previous memory access request will simply be referred to as "access to the same cache line". The pattern monitoring unit 132 determines whether or not it is an access to the same cache line based on the state information, address information, and stride width information stored in the prefetch queue 131. For example, in the case of a memory access request to an address with address numbers 8, 16, and 32, the pattern monitoring unit 132 confirms that the state is #1 and the stride width is before registration. Furthermore, the pattern monitoring unit 132 compares the address stored in the address information with the requested address and determines that it is an access to the same cache line. In the case of an access to the same cache line, the state management unit 134 does not update the entry information (steps S32 to S34).

[0087] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 100. When an L1 cache miss occurs, the pattern monitoring unit 132 detects a PC hit for entry 1000 in the program counter. The state management unit 134 then subtracts the 0s stored in the address information from the requested address 100 to determine the stride width as 100. Next, the state management unit 134 registers the determined stride width as stride width information and registers 200, which is the value obtained by adding the stride width of 100 to the requested address 100, as the predicted address in the address information. Furthermore, the state management unit 134 changes the state information from state #1 to state #2 (step S35).

[0088] Next, the instruction issuing unit 101 sequentially issues memory access requests to addresses with address numbers 108, 116, and 132. Access to addresses with address numbers 108, 116, and 132 is to the same cache line as access to address number 100. The pattern monitoring unit 132 determines whether or not it is an access to the same cache line based on the state information, address information, and stride width information stored in the prefetch queue 131. For example, in the case of a memory access request to an address with address numbers 108, 116, and 132, the pattern monitoring unit 132 confirms that the state is #2 and the stride width has been registered. Then, the pattern monitoring unit 132 compares the requested address with the address obtained by subtracting the stride width from the address stored in the address information and determines that it is an access to the same cache line. In the case of an access to the same cache line, the state management unit 134 does not update the entry information (steps S36-S38).

[0089] Next, the instruction issuing unit 101 issues a memory access request to an address with address number 200. When an L1 cache miss occurs, the pattern monitoring unit 132 detects a PC hit for the entry with program counter 1000. In this memory access request, the requested address matches the predicted address registered in the entry with program counter 1000, so the state management unit 134 changes the state information from state #2 to state #3. Furthermore, the state management unit 134 sets the confidence counter to 3. The state management unit 134 also registers 300, which is the value obtained by adding the stride width of 100 to the requested address 200, as the predicted address in the address information (step 39).

[0090] From this point onward, the state management unit 134 repeats the same actions. The operation of the state machine shown in Figure 10 is the same as the state machine operation in Figure 6, except for accesses with a stride width smaller than that of the cache line that do not update the information of the entries in the prefetch queue 131. Therefore, as in the case of Figure 6, the confidence counter reaches 6, and the state management unit 134 causes the prefetch request generation unit 133 to issue a prefetch request.

[0091] Figure 11 shows an example of access and prefetching in a case where there are multiple strides, but when viewed on a cache line basis, it is a single stride. Here, the case where the predetermined number N used during prefetching is 2 is explained.

[0092] As shown in Figure 11, when the stride width is 8, it results in access to the same cache line. Then, each time the stride width changes to 66 and access to a different cache line occurs, the state management unit 134 increments the confidence counter. After that, when the confidence counter reaches its upper limit, the state management unit 134 sets the stride width to 100 and performs a prefetch for the address whose address number is obtained by adding 100 x 2 to the requested address. In this way, even though there are multiple strides, if they are considered as a single stride on a cache line basis, the state management unit 134 performs a prefetch with a stride width that can be considered as a single stride.

[0093] Figure 12 is a flowchart of the prefetching process performed by the CPU in Example 1. Next, the flow of the prefetching process performed by the CPU 10 in Example 1 will be explained with reference to Figure 12.

[0094] The instruction issuing unit 101 issues a memory access instruction (step S101).

[0095] The pattern monitoring unit 132 determines whether or not an entry exists in the prefetch queue 131 in which the program counter value of a memory access request is registered, that is, whether it is a PC hit or a PC miss (step S102).

[0096] If a PC hit occurs (step S102: affirmative), the pattern monitoring unit 132 notifies the state management unit 134 of the information of the program counter that triggered the PC hit. Hereinafter, the entry in which the program counter that triggered the PC hit is registered will be referred to as the target entry. Upon receiving the notification, the state management unit 134 executes the state update process for the target entry (step S103).

[0097] Subsequently, the state management unit 134 determines whether the target entry satisfies the conditions for issuing a prefetch request (step S104). If the target entry does not satisfy the conditions for issuing a prefetch request (step S104: negative), the CPU 10 terminates the current prefetch process.

[0098] In response, if the target entry satisfies the conditions for issuing a prefetch request (step S104: affirmative), the state management unit 134 requests the prefetch request generation unit 133 to issue a prefetch request. The prefetch request generation unit 133 receives the request, generates a prefetch request, and issues the generated prefetch request to the lower cache 20 (step S105).

[0099] On the other hand, if a PC error occurs (step S102: negative), the pattern monitoring unit 132 notifies the L1 cache control unit 102 of the PC error. Upon receiving the notification, the L1 cache control unit 102 determines whether the data specified by the requested address of the memory access request is stored in the L1 cache 12, that is, whether it is an L1 cache hit or an L1 cache miss (step S106). If it is an L1 cache hit (step S106: negative), the CPU 10 terminates the current prefetch process.

[0100] In contrast, if an L1 cache miss occurs (step S106: affirmative), the pattern monitoring unit 132 receives notification of the L1 cache miss from the L1 cache control unit 102 and determines whether or not there is an empty entry in the prefetch queue 131 (step S107). If there is an empty entry in the prefetch queue 131 (step S107: affirmative), the pattern monitoring unit 132 proceeds to step S109.

[0101] If there are no free entries in the prefetch queue 131 (step S107: negative), the pattern monitoring unit 132 invalidates the entry with the longest storage time in the prefetch queue 131 (step S108). Then, the pattern monitoring unit 132 proceeds to step S109.

[0102] Then, the pattern monitoring unit 132 transitions the state of the target entry from state #0 to state #1 (step S109).

[0103] Next, the pattern monitoring unit 132 registers the program counter of the memory access instruction as a new entry in the prefetch queue 131 (step S110).

[0104] Furthermore, the pattern monitoring unit 132 registers the requested address of the memory access instruction as a predicted address in the address information of the newly registered entry (step S111).

[0105] Figure 13 is a flowchart of the state update process performed by the state management unit. The flow shown in Figure 13 is an example of the process performed in step S103 in Figure 12.

[0106] The pattern monitoring unit 132 determines whether the memory access request is an access to the same cache line (step S120). If it is an access to the same cache line (step S120: affirmative), the state update process ends.

[0107] In contrast, if it is not an access to the same cache line (step S120: negation), the state management unit 134 determines whether the target entry is in state #1 or not (step S121).

[0108] If the target entry is in state #1 (step S121: affirmative), the state management unit 134 transitions the target state from state #1 to state #2 (step S122).

[0109] Next, the state management unit 134 calculates the stride width by subtracting the predicted address stored in the address information of the target entry from the request address of the memory access instruction (step S123).

[0110] Next, the state management unit 134 registers and updates the stride width information of the target entry using the calculated stride width (step S124).

[0111] Next, the state management unit 134 calculates a predicted address by adding the stride width to the requested address of the memory access instruction. Then, the state management unit 134 registers the calculated predicted address in the address information of the target entry and updates it (step S125).

[0112] On the other hand, if the target entry is not in state #1 (step S121: negative), the state management unit 134 determines whether the target entry is in state #2 or not (step S126). If the target entry is in state #2 (step S126: positive), the state management unit 134 executes the state update process in state #2 (step S127).

[0113] In response to this, if the target entry is not in state #2 (step S126: negative), the state management unit 134 determines whether the target entry is in state #3 or not (step S128). If the target entry is in state #3 (step S128: positive), the state management unit 134 executes the state update process in state #3 (step S129).

[0114] In response to this, if the target entry is not in state #3 (step S128: negation), the state management unit 134 determines that the target entry is in state #4. Then, the state management unit 134 executes the state update process in state #4 (step S130).

[0115] Figure 14 is a flowchart of the state update process in state #2. The flow shown in Figure 14 is an example of the process performed in step S127 in Figure 13.

[0116] The state management unit 134 determines whether an address hit has occurred because the requested address of the memory access instruction matches the predicted address registered in the target entry in the prefetch queue 131 (step S141).

[0117] If an address hit occurs (step S141: affirmative), the state management unit 134 transitions the target entry from state #2 to state #3 (step S142).

[0118] Next, the state management unit 134 sets the confidence counter of the target entry to 3 (step S143). After that, the state management unit 134 proceeds to step S146.

[0119] In contrast, if an address error occurs (step S141: negation), the state management unit 134 transitions the target entry from state #2 to state #4 (step S144).

[0120] Next, the state management unit 134 sets the confidence counter of the target entry to 1 (step S145). After that, the state management unit 134 proceeds to step S146.

[0121] Then, the state management unit 134 adds the stride width registered in the target entry to the requested address and registers and updates the address information (step S146).

[0122] Figure 15 is a flowchart of the state update process in state #3. The flow shown in Figure 15 is an example of the process performed in step S129 in Figure 13.

[0123] The state management unit 134 determines whether an address hit has occurred because the requested address of the memory access instruction matches the predicted address registered in the target entry in the prefetch queue 131 (step S151).

[0124] If an address hit occurs (step S151: affirmative), the state management unit 134 increments the confidence counter of the target entry by one (step S152). Then, the state management unit 134 proceeds to step S157.

[0125] In contrast, if an address error occurs (step S151: negation), the state management unit 134 transitions the target entry from state #3 to state #4 (step S153).

[0126] Next, the state management unit 134 determines whether the confidence counter has reached its upper limit (step S154).

[0127] If the confidence counter has reached its upper limit (step S154: affirmative), the state management unit 134 decrements the confidence counter of the target entry by one (step S155). Then, the state management unit 134 proceeds to step S157.

[0128] In contrast, if the confidence counter has not reached its upper limit (step S154: negative), the state management unit 134 sets the confidence counter of the target entry to 1 (step S156). After that, the state management unit 134 proceeds to step S157.

[0129] Then, the state management unit 134 adds the stride width registered in the target entry to the requested address and registers and updates the address information (step S157).

[0130] Figure 16 is a flowchart of the state update process in state #4. The flow shown in Figure 16 is an example of the process performed in step S130 in Figure 13.

[0131] The state management unit 134 determines whether an address hit has occurred because the requested address of the memory access instruction matches the predicted address registered in the target entry in the prefetch queue 131 (step S161).

[0132] If an address hit occurs (step S161: affirmative), the state management unit 134 transitions the target entry from state #4 to state #3 (step S162).

[0133] Next, the state management unit 134 increments the confidence counter of the target entry by one (step S163). After that, the state management unit 134 proceeds to step S166.

[0134] In contrast, if an address error occurs (step S161: negation), the state management unit 134 decrements the confidence counter of the target entry by one (step S164).

[0135] Next, the state management unit 134 determines whether the confidence counter is 0 or not (step S165). If the confidence counter is not 0 (step S165: negative), the state management unit 134 proceeds to step S166.

[0136] Then, the state management unit 134 adds the stride width registered in the target entry to the requested address and registers and updates the address information (step S166).

[0137] In contrast, if the confidence counter is 0 (step S165: affirmative), the state management unit 134 transitions the target entry from state #4 to state #0 (step S167). As a result, the target entry becomes invalid.

[0138] As described above, the arithmetic processing unit according to this embodiment uses a state machine to manage candidate entries for prefetching stored in a prefetch queue, changes the confidence level according to the stride width, and performs prefetching when the confidence level reaches a certain value. In this way, the arithmetic processing unit according to this embodiment distinguishes between single-stride and multi-stride access patterns and performs stride prefetching in the case of a single stride. This makes it possible to suppress prefetching at incorrect addresses that may occur in the case of multi-strides, thereby improving computational performance.

[0139] Furthermore, even if there are multiple strides, if they can be considered as a single stride on a cache line basis, the arithmetic processing unit according to this embodiment performs prefetching with a stride width that can be treated as a single stride. This makes it possible to suppress prefetching at incorrect addresses while increasing the frequency of prefetching, thereby further improving computational performance. [Examples]

[0140] Next, we will describe Example 2. The CPU 10 in this example is also represented by the block diagram in Figure 2. The CPU 10 in this example differs from Example 1 in that it uses a state machine for replacement control to replace entries in the prefetch queue 131. The replacement of entries by the CPU 10 in this example will be described in detail below. In the following description, the operation of each part, which is the same as in Example 1, will be omitted.

[0141] Figure 17 shows an example of the format of entries stored in the prefetch queue according to Embodiment 2. As shown in format 203 of Figure 17, each entry in the prefetch queue 131 registers program counter, state information, reliability counter, replace state information, and address information.

[0142] Replacement state information is information that indicates the state of an entry, used to control the replacement of an entry, that is, to delete an entry and disable it. There are three replacement states, #R0 to #R3. Replacement state #R0 represents the disabled state of the entry. In other words, when a particular entry transitions to replacement state #R0, that particular entry is disabled.

[0143] If no PC hit occurs and an L1 cache miss occurs, the pattern monitoring unit 132 determines whether there is an empty entry in the prefetch queue 131. If there is an empty entry, the pattern monitoring unit 132 sets the state information of the newly registered entry for the memory access instruction that caused the L1 cache miss to state #1. At this time, the pattern monitoring unit 132 sets the replacement state information of the newly registered entry to replace state #R2. The pattern monitoring unit 132 also sets the program counter of the newly registered entry to the program counter of the memory access instruction. Furthermore, the pattern monitoring unit 132 registers the requested address of the memory access instruction as the predicted address in the address information of the newly registered entry. Here, since the stride width information is invalid in state #1, the pattern monitoring unit 132 sets an arbitrary value, such as a predetermined initial value, as the stride width information. Then, the pattern monitoring unit 132 registers the new entry in the prefetch queue 131 with the above information.

[0144] In response to this, if there are no available entries in the prefetch queue 131, the pattern monitoring unit 132 selects an entry to be replaced that satisfies one of the following two conditions. The first condition is to select an entry that is in state #4 and whose confidence counter is below the confidence threshold. The pattern monitoring unit 132 can set the confidence threshold to, for example, 2. The first condition is based on the reason that accesses that regularly experience address misses are not used for stride prefetching and should therefore be removed from the entry. Since accesses that regularly experience address misses will periodically have their confidence counter fall below the confidence threshold, the pattern monitoring unit 132 can select the entry for that access to be replaced.

[0145] The second condition is that an entry set to replacement state #R0 in the state machine for replacement control is invalidated. That is, if there are no entries that satisfy the first condition and there are no available entries, the pattern monitoring unit 132 generates a decrement event in the state machine for replacement control. A decrement event is an event that transitions the replacement state of all entries to the next lower replacement state. If the decrement event is repeated several times, an entry will be set to replacement state #R0, and the pattern monitoring unit 132 can invalidate the entry according to the second condition. Here, if the pattern monitoring unit 132 sets the replacement state information of an entry to replacement state #R0, it also updates the state information of that entry to state #0.

[0146] If a PC hit occurs, no entry with replacement state #R0 is generated, so the pattern monitoring unit 132 uses the first condition to select the entry to be replaced. If a PC miss occurs, the confidence counter will not be updated, so there is a possibility that no entries will satisfy the first condition. However, when PC hits cease, one of the entries will enter replacement state #R0 and satisfy the second condition.

[0147] When a PC hit occurs, the pattern monitoring unit 132 updates the replacement state information of the target entry to replacement state #R3. Furthermore, if the pattern monitoring unit 132 sets the state information of an entry to state #0, it also updates the replacement state information of that entry to replacement state #R0.

[0148] Figure 18 shows an example of a state machine for replacement control. Next, referring to Figure 18, the transitions of the replacement state will be summarized.

[0149] If a PC error and an L1 cache error occur with respect to a received memory access instruction, the pattern monitoring unit 132 registers a new entry containing the program counter for that memory access instruction. The pattern monitoring unit 132 then performs an initial registration, setting the state information of the newly registered entry to state #1 and the replace state information to replace state #R2 (step S201).

[0150] Furthermore, if a PC miss and an L1 cache miss occur with respect to a received memory access instruction, the pattern monitoring unit 132 executes the following process: If there are no available entries in the prefetch queue 131 and no entries satisfy the first condition, the pattern monitoring unit 132 generates a decrement event (steps S202, S203, S204). This may invalidate the entry, and if the entry is invalidated, the pattern monitoring unit 132 can register a new entry for the memory access instruction.

[0151] Furthermore, if a PC hit occurs, the pattern monitoring unit 132 transitions the target entry to replace state #R3, regardless of whether the target entry is in replace state #R1 or #R2 (steps S205, S206).

[0152] Figure 19 is a flowchart of the prefetching process performed by the CPU in Example 2. Next, the flow of the prefetching process performed by the CPU 10 in this example will be explained with reference to Figure 19.

[0153] The instruction issuing unit 101 issues a memory access instruction (step S211).

[0154] The pattern monitoring unit 132 determines whether or not an entry exists in the prefetch queue 131 in which the program counter value of a memory access request is registered, that is, whether it is a PC hit or a PC miss (step S212).

[0155] If a PC hit occurs (step S212: affirmative), the pattern monitoring unit 132 updates the target entry that triggered the PC hit to replace state #R3 (step S213).

[0156] Furthermore, the pattern monitoring unit 132 notifies the state management unit 134 of the program counter information of the PC hit along with the PC hit. Hereinafter, the entry in which the PC hit program counter is registered will be referred to as the target entry. Upon receiving the notification, the state management unit 134 executes the state update process for the target entry (step S214).

[0157] Subsequently, the state management unit 134 determines whether the target entry satisfies the conditions for issuing a prefetch request (step S215). If the target entry does not satisfy the conditions for issuing a prefetch request (step S215: negative), the CPU 10 terminates the current prefetch process.

[0158] In response, if the target entry satisfies the conditions for issuing a prefetch request (step S215: affirmative), the state management unit 134 requests the prefetch request generation unit 133 to issue a prefetch request. The prefetch request generation unit 133 receives the request, generates a prefetch request, and issues the generated prefetch request to the lower cache 20 (step S216).

[0159] On the other hand, if a PC error occurs (step S212: negative), the pattern monitoring unit 132 notifies the L1 cache control unit 102 of the PC error. Upon receiving the notification, the L1 cache control unit 102 determines whether the data specified by the requested address of the memory access request is stored in the L1 cache 12, that is, whether it is an L1 cache hit or an L1 cache miss (step S217). If it is an L1 cache hit (step S217: negative), the CPU 10 terminates the current prefetch process.

[0160] In contrast, if an L1 cache miss occurs (step S217: affirmative), the pattern monitoring unit 132 receives notification of the L1 cache miss from the L1 cache control unit 102 and determines whether or not there is an empty entry in the prefetch queue 131 (step S218).

[0161] If there is an empty entry in the prefetch queue 131 (step S218: affirmative), the pattern monitoring unit 132 registers a new entry in the prefetch queue 131 and transitions the state from state #0 to state #1 (step S219).

[0162] Next, the pattern monitoring unit 132 transitions the replacement state information of the newly registered entry from replacement state #R0 to replacement state #R2 (step S220).

[0163] Next, the pattern monitoring unit 132 registers the program counter of the memory access instruction in the newly registered entry (step S221).

[0164] Furthermore, the pattern monitoring unit 132 registers the requested address of the memory access instruction as a predicted address in the address information of the newly registered entry (step S222).

[0165] On the other hand, if there are no available entries in the prefetch queue 131 (step S218: negative), the pattern monitoring unit 132 executes a decrement event that decrements the replace state information of all entries by one (step S223).

[0166] Subsequently, the pattern monitoring unit 132 determines whether or not an entry has become invalid due to a decrement event, resulting in a replacement state #R0 (step S224).

[0167] If an invalid entry occurs (step S224: affirmative), the pattern monitoring unit 132 returns to step S219. Conversely, if no invalid entry occurs (step S224: negative), the pattern monitoring unit 132 terminates the current prefetch process.

[0168] As described above, the arithmetic processing unit according to this embodiment selects entries to be replaced from the prefetch queue using a first condition based on the state and confidence counter used for prefetch control and a second condition based on the state used for replace control. The arithmetic processing unit can invalidate entries that periodically experience address misses and are not used for stride prefetching based on the first condition. Furthermore, the arithmetic processing unit can invalidate entries that have a long period without PC hits and have a low probability of being used for stride prefetching based on the second condition if the first condition is not met.

[0169] Therefore, the arithmetic processing unit according to this embodiment can disable entries that are less likely to be used for stride prefetching, thereby improving the probability of performing stride prefetching. This makes it possible to improve the computational performance of the arithmetic processing unit.

[0170] The arithmetic processing unit with the prefetch mechanism described above can be used in general-purpose computers and can be installed in, for example, servers and computers used in HPC (High Performance Computing). In particular, prefetching by this arithmetic processing unit is effective in processes with many stride accesses, such as those in data center computers, as well as in cases where repetitive processing is performed in functions and loop processing involving arrays. [Explanation of Symbols]

[0171] 1. Information Processing Device 10 CPU 11 Arithmetic section 12 L1 cache 13 Lower cache 14 Main memory 15 Auxiliary storage 16 Display device 17 Input devices 101 Order Issuing Department 102 L1 Cache Control Unit 103 Stride Prefetch Control Unit 131 Prefetch Queue 132 Pattern Monitoring Unit 133 Prefetch Request Generation Unit 134 State Management Department

Claims

1. A prefetch queue, A monitoring unit registers the predetermined entry containing the program counter information into the prefetch queue if a cache miss occurs in the first memory access instruction indicated by a predetermined program counter, and a predetermined entry containing the program counter information does not exist in the prefetch queue. A management unit that calculates the stride width based on the request address of the first memory access instruction and the request addresses of each of the multiple second memory access instructions indicated by the predetermined program counter following the predetermined entry, and registers this stride width in the predetermined entry, and registers a predicted address calculated by adding the stride width to the request address of the second memory access instruction in the predetermined entry, sequentially updates the predicted address with a value calculated by adding the stride width to each of the request addresses of the multiple third memory access instructions indicated by the predetermined program counter following the second memory access instruction, and detects the occurrence of a stride access by comparing the request address of each of the third memory access instructions with the predicted address registered in the predetermined entry, When the management unit detects the stride access, a prefetch request generation unit issues a prefetch request based on the stride width. A processing unit characterized by comprising:

2. The arithmetic processing apparatus according to claim 1, characterized in that the management unit increases the confidence counter when the requested address of the third memory access instruction matches the predicted address registered in the predetermined entry, decreases the confidence counter when the requested address of the third memory access instruction matches the predicted address registered in the predetermined entry, and detects the stride access based on the stride width registered in the predetermined entry when the confidence counter exceeds an upper limit value.

3. The arithmetic processing apparatus according to claim 1, characterized in that when the prefetch request generation unit detects the occurrence of the stride access by the management unit, it issues a prefetch request at an address obtained by adding a value obtained by a predetermined number of times the stride width to the request address of the memory access instruction indicated by the predetermined program counter.

4. The arithmetic processing device according to claim 1, characterized in that, if there is no available space in the prefetch queue to register the predetermined entry, the monitoring unit selects one entry from a plurality of entries stored in the prefetch queue, invalidates it, and then registers the predetermined entry.

5. The arithmetic processing unit according to claim 4, characterized in that the monitoring unit selects entries to be disabled based on the issuance frequency of memory access instructions indicated by the program counter included in each of the entries stored in the prefetch queue.

6. If a cache miss occurs in the first memory access instruction indicated by a predetermined program counter, and a predetermined entry containing the information of the predetermined program counter does not exist in the prefetch queue, the predetermined entry containing the information of the predetermined program counter is registered in the prefetch queue. The stride width is calculated based on the request address of the first memory access instruction and the request addresses of each of the multiple second memory access instructions indicated by the predetermined program counter following the predetermined entry, and registered in the predetermined entry; the predicted address calculated by adding the stride width to the request address of the second memory access instruction is registered in the predetermined entry; the predicted address is sequentially updated with a value calculated by adding the stride width to each of the request addresses of the multiple third memory access instructions indicated by the predetermined program counter following the second memory access instruction; and the occurrence of a stride access is detected by comparing the request address of each of the third memory access instructions with the predicted address registered in the predetermined entry. When the stride access is detected, a prefetch request based on the stride width is issued. A method for performing arithmetic processing, characterized in that the processing is carried out by an arithmetic processing unit.

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