Control device, image processing device, and control program

Abstract

To prevent conflict of notifications by a plurality of processor cores.SOLUTION: A controller 30 comprises a plurality of CPU cores 0-3. The plurality of CPU cores 0-3 are connected with a WDT 21 which monitors that the CPU core 0 is normally operating, and a RAM 13 which has a plurality of storage regions associated with each of the plurality of CPU cores 0-3 in advance. Each of the plurality of CPU cores 0-3 periodically writes information indicating normal operation, with respect to the storage region of the corresponding RAM 13, to update it. The CPU core 0 determines whether or not the information is updated by each of the plurality of CPU cores 0-3, with respect to each storage region of the RAM 13, and controls the WDT 21, on the basis of a determination result.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a control device, an image processing device, and a control program.

Background Art

[0002] For example, Patent Document 1 describes a control device including a multi-core CPU having at least a first core and a second core that execute pre-assigned processes. This control device includes, in the second core, first core monitoring means for detecting an abnormality in the first core, and, in the first core, second core monitoring means for detecting an abnormality in the second core. When the first core detects an abnormality in the second core via the second core monitoring means, the first core executes first substitution processing for substituting the process executed by the second core. When the second core detects an abnormality in the first core via the first core monitoring means, the second core executes second substitution processing for substituting the process executed by the first core.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Processors mounted on a controller are mounted with a plurality of processor cores to improve performance. On the other hand, for example, in a device that uses high temperature and high voltage, a WDT (Watch Dog Timer) is used from the viewpoint of safety, and the system is reset to a safe state when a problem occurs.

[0005] However, when multiple processor cores share a WDT, if the notifications from each of the processor cores that they are continuing to operate normally overlap, a conflict can occur between the multiple processor cores if there is no arbitration function to reconcile the overlapping notifications. When a conflict occurs, the WDT may not receive the notification, mistakenly perceive that the processor core is not operating normally, and may perform unnecessary resets.

[0006] This disclosure aims to provide a control device, an image processing device, and a control program that can prevent notification conflicts between multiple processor cores. [Means for solving the problem]

[0007] To achieve the above objective, the control device according to the first embodiment comprises a monitoring unit that monitors whether a first processor core, which is one of the plurality of processor cores, is operating normally, and a memory having a plurality of storage areas pre-associated with each of the plurality of processor cores, with each of the plurality of processor cores periodically writing and updating information indicating that it is operating normally to the storage area of ​​the memory, the first processor core determines whether the information has been updated by each of the plurality of processor cores for each storage area of ​​the memory, and controls the monitoring unit based on the determination result.

[0008] Furthermore, in the control device according to the second embodiment, the timing at which the first processor core determines whether or not the information has been updated is different from the timing at which each of the plurality of processor cores updates the information.

[0009] Furthermore, in the control device according to the third embodiment, the control device according to the second embodiment determines whether or not the information has been updated between the time the first processor core updates the information and the next update.

[0010] Furthermore, the control device according to the fourth embodiment is a control device according to the first embodiment in which the memory has multiple storage areas for each of the multiple processor cores, each of the multiple processor cores periodically updates the information in the multiple storage areas of the corresponding memory in sequence, and the first processor core determines that the information has been updated when the information in any of the multiple storage areas has been updated.

[0011] Furthermore, the control device according to the fifth embodiment determines that the information has not been updated if, in the control device according to the fourth embodiment, the first processor core has not updated any of the information in the plurality of memory areas.

[0012] Furthermore, in the control device according to the sixth embodiment, if the control device according to the first embodiment has updated the information for each of the plurality of processor cores, the first processor core instructs the monitoring unit to clear the count.

[0013] Furthermore, the control device according to the seventh embodiment determines that an abnormality has occurred if the first processor core has not updated the information for any of the plurality of processor cores, and instructs the monitoring unit to reset all of the plurality of processor cores.

[0014] Furthermore, the control device according to the eighth embodiment determines that an abnormality has occurred if the first processor core has not updated the information for any of the plurality of processor cores, and instructs the monitoring unit to reset only the processor core where the abnormality occurred among the plurality of processor cores.

[0015] Furthermore, in the control device according to the ninth embodiment, if the monitoring unit does not receive instructions from the first processor core for a certain period of time or longer, it outputs a reset signal to reset all of the plurality of processor cores.

[0016] Furthermore, the control device according to the tenth embodiment further includes an interrupt unit that receives a reset signal from the monitoring unit and performs an interrupt processing that replaces the first processor core with another predetermined processor core in accordance with the received reset signal, compared to the control device according to the ninth embodiment.

[0017] Furthermore, in order to achieve the above objective, the image processing apparatus according to the 11th embodiment includes a control device described in any one of the first to tenth embodiments, and an image processing unit controlled by the control device.

[0018] Furthermore, in order to achieve the above objective, the control program according to the 12th embodiment is a control program for the first processor core among the plurality of processor cores connected to a monitoring unit that monitors whether a first processor core, which is one of the plurality of processor cores, is operating normally, and a memory having a plurality of storage areas pre-associated with each of the plurality of processor cores, wherein the control program periodically writes and updates information indicating that the first processor core is operating normally to the storage area of ​​the memory corresponding to the first processor core, and controls the monitoring unit based on whether the information has been updated by each of the plurality of processor cores for each storage area of ​​the memory, causing the computer to perform these actions. [Effects of the Invention]

[0019] According to the first, eleventh, and twelfth embodiments, there is an effect that it is possible to prevent notification conflicts between multiple processor cores.

[0020] According to the second embodiment, compared to the case where the updates are performed at the same time, it has the effect of being able to determine whether or not the information has been updated at an appropriate time.

[0021] According to the third embodiment, it has the effect of being able to determine whether or not the information has been updated between updates.

[0022] According to the fourth aspect, even when the memory update timings are shifted among a plurality of processor cores as compared with the case where each of the plurality of processor cores has one memory area, it is possible to appropriately determine that the information has been updated, and thus has an effect.

[0023] According to the fifth aspect, even when the memory update timings are shifted among a plurality of processor cores as compared with the case where each of the plurality of processor cores has one memory area, it is possible to appropriately determine that the information has not been updated, and thus has an effect.

[0024] According to the sixth aspect, as compared with the case where the presence or absence of information update for each of the plurality of processor cores is not considered, it is possible to appropriately clear the count of the monitoring unit, and thus has an effect.

[0025] According to the seventh aspect, as compared with the case where the presence or absence of information update for each of the plurality of processor cores is not considered, it is possible to appropriately reset all of the plurality of processor cores, and thus has an effect.

[0026] According to the eighth aspect, as compared with the case where the presence or absence of information update for each of the plurality of processor cores is not considered, it is possible to appropriately reset only the processor core in which an abnormality has occurred, and thus has an effect.

[0027] <00,00098>According to the ninth aspect, even when an abnormality occurs in the first processor core, it is possible to output a reset signal, and thus has an effect.

[0028] According to the tenth aspect, even when an abnormality occurs in the first processor core, it is possible to replace it with another processor core, and thus has an effect.

Brief Description of Drawings

[0029] [Figure 1] It is a diagram showing an example of the configuration of an image processing system according to the first embodiment. [Figure 2] This is a block diagram showing an example of the electrical configuration of an image processing apparatus according to the first embodiment. [Figure 3] This is a block diagram showing the configuration of a control device related to a comparative example. [Figure 4] This is a block diagram showing an example of the configuration of a control device according to the first embodiment. [Figure 5] This figure shows an example of the RAM configuration according to the first embodiment. [Figure 6] This is a sequence diagram showing an example of the operation of the control device according to the first embodiment. [Figure 7] This flowchart shows an example of the processing flow by the control program for the first CPU core according to the first embodiment. [Figure 8] This figure shows an example of the RAM configuration according to the second embodiment. [Figure 9] This is a sequence diagram showing an example of the operation of the control device according to the second embodiment. [Figure 10] Figure 9 shows an example of the RAM update state corresponding to the operation of the control device. [Figure 11] This flowchart shows an example of the processing flow by a control program for multiple CPU cores according to the second embodiment. [Figure 12] This is a block diagram showing an example of the configuration of a control device according to the third embodiment. [Figure 13] This is a sequence diagram showing an example of the operation of the control device according to the third embodiment. [Modes for carrying out the invention]

[0030] Hereinafter, an example of an embodiment for carrying out the technology of this disclosure will be described in detail with reference to the drawings. Components and processes that perform the same operation, action, or function are given the same reference numerals throughout the drawings, and redundant explanations may be omitted as appropriate. Each drawing is only a schematic representation to the extent that the technology of this disclosure can be fully understood. Therefore, the technology of this disclosure is not limited to the illustrated examples. Furthermore, in this embodiment, explanations of configurations not directly related to the technology of this disclosure or well-known configurations may be omitted.

[0031] [First Embodiment] Figure 1 shows an example of the configuration of the image processing system 100 according to the first embodiment.

[0032] As shown in Figure 1, the image processing system 100 according to this embodiment comprises an image processing device 10 and a terminal device 50. In the example in Figure 1, one terminal device is shown, but the number is arbitrary.

[0033] The image processing device 10 is a device that performs image-related functions according to user instructions. The image processing device 10 is connected to the user's terminal device 50 via a network N. Network N can be the Internet, LAN (Local Area Network), WAN (Wide Area Network), etc. There are no restrictions on the connection method of network N; it may be wired, wireless, or a combination of wired and wireless.

[0034] The image processing device 10, as an example, has a scanning function that reads an image written on a recording medium such as paper as image data, a printing function that forms an image represented by the image data on a recording medium, and a copying function that forms an image identical to the image formed on the recording medium on another recording medium. The copying function, printing function, and scanning function are examples of image processing in the image processing device 10.

[0035] The terminal device 50 can include various devices such as a personal computer (PC), smartphone, or tablet used by the user.

[0036] The user sends image data generated by the terminal device 50 to the image processing device 10 via the network N, thereby causing the image processing device 10 to perform the desired image processing. Alternatively, the user may store the image data on a portable storage medium such as a USB (Universal Serial Bus) memory or memory card, move it to the image processing device 10, and connect the portable storage medium to the image processing device 10, thereby causing the image processing device 10 to perform the desired image processing. Furthermore, the user may move a document containing at least one of text and / or an image to the image processing device 10, and have the image processing device 10 read the document, thereby causing the image processing device 10 to perform the desired image processing.

[0037] Figure 2 is a block diagram showing an example of the electrical configuration of the image processing apparatus 10 according to the first embodiment.

[0038] As shown in Figure 2, the image processing apparatus 10 according to this embodiment includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, an input / output interface (I / O) 14, a storage unit 15, a display unit 16, an operation unit 17, a document reading unit 18, an image forming unit 19, and a communication unit 20. The CPU 11 is an example of a processor.

[0039] The CPU 11, ROM 12, RAM 13, and I / O 14 are connected to each other via a bus. The I / O 14 is connected to various functional units, including a storage unit 15, a display unit 16, an operation unit 17, a document reading unit 18, an image forming unit 19, and a communication unit 20. These functional units are capable of communicating with the CPU 11 via the I / O 14.

[0040] A control device 30, which functions as a controller, is configured by a CPU 11, ROM 12, RAM 13, and I / O 14. The control device 30 may be configured as a sub-control unit that controls the operation of a part of the image processing device 10, or as part of a main control unit that controls the operation of the entire image processing device 10. Some or all of the blocks of the control device 30 may use integrated circuits such as LSIs (Large Scale Integration) or ICs (Integrated Circuit) chipsets. Individual circuits may be used for each of the above blocks, or circuits that integrate some or all of them may be used. The above blocks may be provided as a single unit, or some of the blocks may be provided separately. In addition, parts of each of the above blocks may be provided separately. For integration of the control device 30, dedicated circuits or general-purpose processors may be used, not limited to LSIs. Note that the control device 30 may consist only of the CPU 11.

[0041] ROM12 stores a control program that controls the operation of CPU11. The control program may be pre-installed on the control device 30, for example. The control program may also be stored on a non-volatile storage medium or distributed via the network N and installed on the control device 30 as appropriate. Examples of non-volatile storage media include CD-ROM (Compact Disc Read Only Memory), magneto-optical disk, HDD, DVD-ROM (Digital Versatile Disc Read Only Memory), flash memory, and memory cards.

[0042] For the memory unit 15, for example, an HDD (Hard Disk Drive), SSD (Solid State Drive), flash memory, etc., can be used.

[0043] The display unit 16 may be, for example, a liquid crystal display (LCD), an organic EL (Electro-Luminescence) display, or the like. The display unit 16 may also have an integrated touch panel. The operation unit 17 is provided with various operation keys, such as a numeric keypad and a start key. The display unit 16 and the operation unit 17, as an operation panel, receive instructions from the user of the image processing device 10 regarding various image processing functions and settings. These instructions include, for example, instructions to start scanning a document, instructions to start copying a document, and instructions to print print data held in the image processing device 10. The display unit 16 displays various information such as the results of processing performed in response to instructions received from the user, and notifications regarding processing.

[0044] The document reading unit 18 takes in documents one by one from the paper feed tray of an automatic document feeder (not shown) located at the top of the image processing device 10, and obtains image data by optically reading the taken documents. Alternatively, the document reading unit 18 obtains image data by optically reading a document placed on a platen glass or the like.

[0045] The image forming unit 19 forms an image on paper, which is an example of a recording medium, based on image data obtained by reading by the document reading unit 18, or image data obtained by a print instruction from the terminal device 50. The image forming unit 19 is an example of an image processing unit. In the following description, the electrophotographic method is used as an example of the method for forming images, but other methods such as the inkjet method may also be used.

[0046] When the image formation method is electrophotography, the image forming unit 19 includes a photoreceptor drum, a charging device, an exposure device, a developing device, a transfer device, and a fixing device. The charging device charges the surface of the photoreceptor drum by applying a voltage to it. The exposure device forms an electrostatic latent image on the photoreceptor drum by exposing the photoreceptor drum, which has been charged by the charging device, with light corresponding to the image data. The developing device forms a toner image on the photoreceptor drum by developing the electrostatic latent image formed on the photoreceptor drum with toner. The transfer device transfers the toner image formed on the photoreceptor drum to paper. The fixing device fixes the toner image transferred to the paper by heating and pressurizing.

[0047] The communication unit 20 is a communication interface for connecting to a network N such as the Internet, LAN, or WAN, and enables communication with the terminal device 50 via the network N.

[0048] Figure 3 is a block diagram showing the configuration of the control device 200 according to the comparative example.

[0049] As shown in Figure 3, the control device 200 is equipped with a CPU 201. The CPU 201 is equipped with multiple CPU cores 0 to 3 and an input / output interface (I / F) 202. The I / F 202 can be configured with, for example, GPIO (General Purpose Input Output) or I2C (Inter Integrated Circuit). The multiple CPU cores 0 to 3 are connected to the WDT 203 via the I / F 202.

[0050] CPU201 features multiple CPU cores (0-3) to improve performance. Meanwhile, WDT203 is used to reset the system to a safe state in the event of a malfunction. When multiple CPU cores (0-3) are activated, WDT203 enters a monitoring state. Programs running on these cores perform specific operations at regular intervals to notify WDT203 that they are functioning correctly. If no notification is received by WDT203 after a certain period, it is assumed that a problem has occurred, and WDT203 executes predetermined abnormality handling procedures (such as a reset).

[0051] When multiple CPU cores 0-3 share the WDT203, if the notifications for each of the CPU cores 0-3 operating normally overlap, a conflict will occur among the CPU cores 0-3 if there is no arbitration function to resolve the overlapping notifications. When a conflict occurs, the WDT203 may not receive the notification, mistakenly perceive that CPU cores 0-3 are not operating normally, and may perform unnecessary resets.

[0052] Therefore, the control device 30 according to this embodiment includes a plurality of processor cores, each of which updates the corresponding memory storage area by writing information indicating that it is operating normally, and the first processor core, which is one of the plurality of processor cores, determines whether the information has been updated by each of the plurality of processor cores for each memory storage area, and controls the monitoring unit based on the determination result.

[0053] Figure 4 is a block diagram showing an example of the configuration of the control device 30 according to the first embodiment. In this embodiment, a CPU 11 is used as an example of a processor, CPU cores 0 to 3 are used as examples of processor cores, RAM 13 is used as an example of memory, and WDT 21 is used as an example of a monitoring unit.

[0054] As shown in Figure 4, the control device 30 includes a CPU 11. The CPU 11 includes multiple CPU cores 0 to 3, a RAM controller 11A, and an input / output interface 11B. For example, GPIO, I2C, etc., can be applied to the input / output interface 11B. The multiple CPU cores 0 to 3 are connected to RAM 13 via RAM controller 11A and to WDT 21 via input / output interface 11B. In the example in Figure 4, there are four CPU cores, but any two or more CPU cores are acceptable. Furthermore, the control device 30 may consist only of the CPU 11, or it may consist of the CPU 11, RAM 13, and WDT 21.

[0055] WDT21 is a timer similar to WDT203 described above, but in this embodiment, it monitors whether the first CPU core, which is one of the multiple CPU cores 0 to 3, is operating normally. Here, the first CPU core is, for example, CPU core 0 among the multiple CPU cores 0 to 3.

[0056] The RAM controller 11A has an arbitration function that arbitrates access timing so that access from multiple CPU cores 0 to 3 does not conflict when multiple CPU cores 0 to 3 access RAM 13.

[0057] Figure 5 shows an example of the configuration of the RAM 13 according to the first embodiment.

[0058] As shown in Figure 5, RAM 13 has multiple memory areas 130 to 133, each pre-associated with one of the multiple CPU cores 0 to 3. In the example in Figure 5, memory area 130 for core 0 corresponds to CPU core 0, memory area 131 for core 1 corresponds to CPU core 1, memory area 132 for core 2 corresponds to CPU core 2, and memory area 133 for core 3 corresponds to CPU core 3. These memory areas 130 for core 0, 131 for core 1, 132 for core 2, and 133 for core 3 are collectively referred to as memory areas 130 to 133.

[0059] As shown in Figures 4 and 5, each of the multiple CPU cores 0 to 3 executes a control program stored in ROM 12 (Figure 2) to periodically write and update information indicating that it is operating normally (hereinafter referred to as "normal operation information") to the corresponding memory areas 130 to 133 of RAM 13. Specifically, CPU core 0 periodically writes normal operation information to memory area 130 for core 0, CPU core 1 periodically writes normal operation information to memory area 131 for core 1, CPU core 2 periodically writes normal operation information to memory area 132 for core 2, and CPU core 3 periodically writes normal operation information to memory area 133 for core 3. Note that the writing timing for each of the CPU cores 0 to 3 is allowed to change depending on the processing content of each CPU core.

[0060] The first CPU core, CPU core 0, executes a control program stored in ROM 12 (Figure 2) to determine whether normal operation information has been updated by each of the multiple CPU cores 0 to 3 in each of the memory areas 130 to 133 of RAM 13, and controls the WDT 21 based on the determination result.

[0061] Specifically, the timing at which CPU core 0 determines whether or not the normal operation information has been updated is different from the timing at which each of the multiple CPU cores 0-3 updates the normal operation information. CPU core 0 determines whether or not the normal operation information has been updated between updates.

[0062] CPU core 0 instructs WDT21 to clear (release) the count if the normal operation information has been updated for each of the multiple CPU cores 0-3. On the other hand, if the normal operation information has not been updated for any of the multiple CPU cores 0-3, CPU core 0 determines that an abnormality has occurred and instructs WDT21 to reset all of the multiple CPU cores 0-3. Alternatively, if the normal operation information has not been updated for any of the multiple CPU cores 0-3, CPU core 0 may determine that an abnormality has occurred and instruct WDT21 to reset only the CPU core among the multiple CPU cores 0-3 that has experienced an abnormality.

[0063] Figure 6 is a sequence diagram showing an example of the operation of the control device 30 according to the first embodiment.

[0064] In Figure 6 (S1), each of the CPU cores 0 to 3 writes and updates normal operation information to the corresponding memory areas 130 to 133 of RAM 13, as shown in Figure 5 above, for example.

[0065] In (S2), CPU core 0 checks whether the normal operation information has been updated for each of the multiple CPU cores 0 to 3 in each of the memory areas 130 to 133 of RAM 13.

[0066] In (S3), if CPU core 0 confirms that the normal operation information has been updated by each of the multiple CPU cores 0 to 3, it instructs WDT21 via the input / output interface 11B to clear the timer count.

[0067] In (S4), WDT21 clears the timer count and starts a new timer count in response to a clear command from CPU core 0.

[0068] In (S5), each of the CPU cores 0 to 3 updates the corresponding memory areas 130 to 133 of RAM 13 by writing normal operation information, similar to (S1).

[0069] In (S6), CPU core 0 checks whether the normal operation information has been updated for each of the multiple CPU cores 0 to 3 in each of the memory areas 130 to 133 of RAM 13.

[0070] In (S7), if CPU core 0 confirms that the normal operation information has been updated by each of the multiple CPU cores 0 to 3, it instructs WDT21 to clear the timer count via the input / output interface 11B.

[0071] In (S8), WDT21 clears the timer count and starts a new timer count in response to a clear command from CPU core 0.

[0072] In (S9), CPU cores 0, 2, and 3 each write and update normal operation information to the corresponding memory areas 130, 132, and 133 of RAM 13. On the other hand, CPU core 1 does not write normal operation information to the memory area 131 of RAM 13 designated for core 1, and therefore it is not updated.

[0073] In (S10), CPU core 0 checks whether the normal operation information for each of the multiple CPU cores 0 to 3 has been updated for each of the memory areas 130 to 133 of RAM 13. Here, since the normal operation information for the memory area 131 corresponding to CPU core 1 has not been updated, it is detected as some kind of abnormality in CPU core 1. When a core abnormality is detected, recovery is performed to return the system to a safe state, for example, by resetting only the abnormal core. Alternatively, instead of clearing WDT21, the entire CPU core may be reset from WDT21 and recovery may be performed by restarting.

[0074] Next, with reference to Figure 7, the operation of the control device 30 according to the first embodiment will be described.

[0075] Figure 7 is a flowchart showing an example of the processing flow by the control program for the first CPU core according to the first embodiment.

[0076] First, the control program is started by CPU core 0, which is an example of the first CPU core, and the following steps are executed.

[0077] In step S101 of Figure 7, CPU core 0 updates the memory area 130 for core 0 in RAM 13 by writing normal operation information. At this time, if the other CPU cores 1 to 3 are also operating normally, they update the memory areas 131 to 133 in RAM 13 by writing normal operation information in the same way as CPU core 0.

[0078] In step S102, CPU core 0 determines whether the normal operation information has been updated for each of the multiple CPU cores 0 to 3 in each of the memory areas 130 to 133 of RAM 13, that is, whether an abnormality has occurred. If it is determined that no abnormality has occurred, that is, that it is normal (negative determination), the process proceeds to step S103. If it is determined that an abnormality has occurred (positive determination), the process proceeds to step S105.

[0079] In step S103, CPU core 0 instructs WDT21 to clear the count. WDT21 clears the timer count in response to the clear instruction from CPU core 0 and starts a new timer count.

[0080] In step S104, CPU core 0 determines whether a certain amount of time has passed since the last update. If it determines that a certain amount of time has passed (positive determination), the process returns to step S101 and is repeated. If it determines that a certain amount of time has not passed (negative determination), the process waits in step S104.

[0081] Meanwhile, in step S105, CPU core 0 instructs WDT21 to reset all of the multiple CPU cores 0 to 3, or the CPU core among the multiple CPU cores 0 to 3 that has malfunctioned, and terminates the series of processes by this control program.

[0082] As described above, according to this embodiment, each of the multiple processor cores updates the corresponding memory storage area by writing normal operation information, and the first processor core determines whether the normal operation information has been updated in each memory storage area by each of the multiple processor cores, and controls the monitoring unit based on the determination result. This prevents conflicts in notifications from the multiple processor cores. As a result, the monitoring unit is prevented from mistakenly recognizing that multiple processor cores are not operating normally and performing unnecessary resets.

[0083] [Second Embodiment] In the first embodiment described above, each processor core performs a separate high-priority process, which may cause a delay in memory update timing. Therefore, the second embodiment describes a configuration that allows memory updates even when there is a delay in memory update timing among multiple processor cores.

[0084] Figure 8 shows an example of the configuration of RAM 13A according to the second embodiment. The control device according to this embodiment (hereinafter referred to as "control device 30A") differs from the control device 30 shown in Figure 4 above in that it is equipped with RAM 13A instead of RAM 13, and has the same configuration in all other respects.

[0085] As shown in Figure 8, RAM 13A has multiple memory areas for each of the multiple CPU cores 0 to 3. That is, memory area 130 for core 0 includes memory area 0 and memory area 1 for core 0. Memory area 131 for core 1 includes memory area 0 and memory area 1 for core 1. Memory area 132 for core 2 includes memory area 0 and memory area 1 for core 2. Memory area 133 for core 3 includes memory area 0 and memory area 1 for core 3. In the example in Figure 8, two memory areas are shown corresponding to each CPU core, but there may be three or more. Furthermore, these memory areas 0 and 1 for core 0, memory areas 0 and 1 for core 1, memory areas 0 and 1 for core 2, and memory areas 0 and 1 for core 3 are collectively referred to as memory areas 0 and 1.

[0086] Each of the multiple CPU cores 0 through 3 sequentially writes and updates normal operation information to multiple memory areas 0 and 1 of the corresponding RAM 13A. In other words, CPU core 0 sequentially writes normal operation information to memory area 0 for core 0 and memory area 1 for core 0, CPU core 1 sequentially writes normal operation information to memory area 0 for core 1 and memory area 1 for core 1, CPU core 2 sequentially writes normal operation information to memory area 0 for core 2 and memory area 1 for core 2, and CPU core 3 sequentially writes normal operation information to memory area 0 for core 3 and memory area 1 for core 3.

[0087] The first CPU core, CPU core 0, determines that the normal operation information has been updated if the normal operation information of any of the multiple memory areas 0 and 1 for each of the multiple CPU cores 0 to 3 has been updated. On the other hand, CPU core 0 determines that the normal operation information has not been updated if the normal operation information of all of the multiple memory areas 0 and 1 has not been updated.

[0088] Figure 9 is a sequence diagram showing an example of the operation of the control device 30A according to the second embodiment. Figure 10 is a diagram showing an example of the update state of the RAM 13A corresponding to the operation of the control device 30A shown in Figure 9.

[0089] In (S11) of Figure 9, each of the CPU cores 0 to 3 updates the corresponding memory area 0 of RAM 13A, as shown in Figure 8 above, by writing normal operation information. However, it is assumed that normal operation information has already been written to memory area 1 of RAM 13A.

[0090] In (S12), CPU core 0 checks whether the normal operation information for one of the multiple memory areas 0 and 1 of the corresponding RAM 13A for each of CPU cores 0 to 3 has been updated. In (S12) of Figure 10, both memory areas 0 and 1 for core 0 corresponding to CPU core 0 have been updated, and both memory areas 0 and 1 for core 1 corresponding to CPU core 1 have been updated. Similarly, both memory areas 0 and 1 for core 2 corresponding to CPU core 2 have been updated, and both memory areas 0 and 1 for core 3 corresponding to CPU core 3 have been updated. Note that, chronologically, memory area 1 is earlier than memory area 0. In this case, it is sufficient to check only memory area 1.

[0091] In (S13), if CPU core 0 confirms that the normal operation information for one of the multiple memory areas 0, 1 of the corresponding RAM 13A has been updated for each of the multiple CPU cores 0 to 3, it instructs WDT21 via I / F 11B to clear the timer count.

[0092] In (S14), WDT21 clears the timer count and starts a new timer count in response to a clear command from CPU core 0.

[0093] In (S15), each of the CPU cores 0 to 3 writes and updates normal operation information to the corresponding memory area 1 of RAM 13A.

[0094] In (S16), CPU core 0 checks whether the normal operation information for one of the multiple memory areas 0 and 1 of the corresponding RAM 13A has been updated for each of the CPU cores 0 to 3. In (S16) of Figure 10, both memory areas 0 and 1 corresponding to each of the CPU cores 0 to 3 have been updated. Note that, chronologically, memory area 0 is updated before memory area 1. In this case, it is sufficient to check only memory area 0.

[0095] In (S17), if CPU core 0 confirms that the normal operation information for one of the multiple memory areas 0, 1 of the corresponding RAM 13A has been updated for each of the multiple CPU cores 0 to 3, it instructs WDT21 via I / F 11B to clear the timer count.

[0096] In (S18), WDT21 clears the timer count and starts a new timer count in response to a clear command from CPU core 0.

[0097] In (S19), CPU cores 0, 2, and 3 each write and update normal operation information to memory area 0 of their respective RAM 13A. On the other hand, CPU core 1 does not write normal operation information to memory area 0 of its corresponding RAM 13A, and therefore it is not updated.

[0098] In (S20), CPU core 0 checks whether the normal operation information for one of the multiple memory areas 0 and 1 of the corresponding RAM 13A for each of CPU cores 0 to 3 has been updated. In (S20) of Figure 10, both memory areas 0 and 1 corresponding to CPU cores 0, 2, and 3 have been updated. On the other hand, for the multiple memory areas 0 and 1 corresponding to CPU core 1, only memory area 1 is updated, and memory area 0 is not updated. Note that in this case, memory area 1 is chronologically earlier than memory area 0. In this case, it would be sufficient to check only memory area 1.

[0099] In (S21), if CPU core 0 confirms that the normal operation information for one of the multiple memory areas 0, 1 of the corresponding RAM 13A has been updated for each of the multiple CPU cores 0 to 3, it instructs WDT21 via I / F 11B to clear the timer count. Note that the description of the "timer count" step of WDT21 is omitted.

[0100] In (S22), CPU cores 0, 2, and 3 each write and update normal operation information to the corresponding memory area 1 of RAM 13A. On the other hand, CPU core 1 does not write normal operation information to the corresponding memory area 1 of RAM 13A, and therefore is not updated.

[0101] In (S23), CPU core 0 checks whether the normal operation information for one of the multiple memory areas 0 and 1 of the corresponding RAM 13A has been updated for each of CPU cores 0 to 3. In (S23) of Figure 10, both of the multiple memory areas 0 and 1 corresponding to CPU cores 0, 2, and 3 have been updated, while the multiple memory areas 0 and 1 corresponding to CPU core 1 have not been updated. In other words, since the normal operation information for all of the multiple memory areas 0 and 1 for CPU core 1 has not been updated, this is detected as some kind of abnormality in CPU core 1. When a core abnormality is detected, recovery is performed to return the system to a safe state, for example, by resetting only the abnormal core. Alternatively, instead of clearing WDT21, the entire CPU core may be reset from WDT21 and recovery may be performed by restarting.

[0102] Next, with reference to Figure 11, the operation of the control device 30A according to the second embodiment will be described.

[0103] Figure 11 is a flowchart showing an example of the processing flow by a control program for multiple CPU cores 0 to 3 according to the second embodiment.

[0104] First, a control program is launched by each of the multiple CPU cores 0-3, and the following steps are executed.

[0105] In step S111 of Figure 11, each of the CPU cores 0 to 3 updates the corresponding memory area 0 for core n (n=0 to 3) of RAM 13A, as shown in Figure 8 above, by writing normal operation information.

[0106] In step S112, each of the CPU cores 0 to 3 writes and updates normal operation information to the corresponding memory area 1 for core n (n=0 to 3) of RAM 13A, and the process returns to step S111 and is repeated.

[0107] Thus, according to this embodiment, even if the memory update timing is out of sync among multiple processor cores, conflicts in notifications from the multiple processor cores are prevented. As a result, the monitoring unit is prevented from mistakenly recognizing that multiple processor cores are not functioning correctly and performing unnecessary resets.

[0108] [Third Embodiment] In the third embodiment, a configuration is described in which, if an abnormality occurs in the first processor core, another processor core is used as a replacement.

[0109] Figure 12 is a block diagram showing an example of the configuration of the control device 30B according to the third embodiment.

[0110] As shown in Figure 12, the control device 30B includes a CPU 11. The CPU 11 includes a plurality of CPU cores 0 to 3, a RAM controller 11A, an input / output interface 11B, and an interrupt unit 11C. Except for the inclusion of the interrupt unit 11C, the configuration is the same as the control device 30 described in the first embodiment or the control device 30A described in the second embodiment.

[0111] The WDT21 outputs a reset signal that resets all of the CPU cores 0 through 3 if no instructions are received from the first CPU core (CPU core 0) for a certain period of time.

[0112] The interrupt unit 11C receives a reset signal from the WDT21 and performs an interrupt process to replace CPU core 0 with another predetermined CPU core (CPU core 1 in the example in Figure 12) according to the received reset signal.

[0113] In other words, if an error occurs in CPU core 0, which is checking for updates to RAM13 or RAM13A, it is not possible to recover by simply resetting that core alone. Therefore, a reset request from WDT21 is received as an interrupt by another core, for example, CPU core 1, and CPU core 1 then resets and recovers only CPU core 0, which is checking for updates to RAM13 or RAM13A.

[0114] Figure 13 is a sequence diagram showing an example of the operation of the control device 30B according to the third embodiment. In this example, the case in which the RAM 13A shown in Figure 8 above is applied will be described.

[0115] In (S31) of Figure 13, each of CPU cores 1 to 3 updates the corresponding memory area 0 of RAM 13A by writing normal operation information, as shown in Figure 8 above. On the other hand, CPU core 0, which is the first CPU core, does not write normal operation information to the corresponding memory area 0 of RAM 13A and therefore is not updated.

[0116] In (S32), each of the CPU cores 1 to 3 updates the corresponding memory area 1 of RAM 13A by writing normal operation information. On the other hand, CPU core 0 does not write normal operation information to the corresponding memory area 1 of RAM 13A, and therefore it is not updated.

[0117] In (S33), WDT21 experiences a timer count-over because it has not received any instructions from CPU core 0 for a certain period of time.

[0118] In (S34), the WDT21 sends a reset signal to the interrupt unit 11C, and the interrupt unit 11C sends a reset signal to another predetermined CPU core, which is CPU core 1.

[0119] In (S35), CPU core 1 sends a reset signal to CPU core 0, where the anomaly occurred.

[0120] In (S36), CPU core 1 instructs CPU cores 2 and 3 to stop updating RAM 13A.

[0121] In (S37), CPU core 0 restarts in response to a reset signal from CPU core 1.

[0122] In (S38), the restarted CPU core 0 requests WDT21 to restart the timer count.

[0123] In (S39), WDT21 restarts the timer count in response to a restart request from CPU core 0.

[0124] In (S40), CPU core 0 instructs each of CPU cores 0 through 3 to start updating RAM 13A.

[0125] In (S41), each of the CPU cores 0 to 3 writes and updates normal operation information to memory area 0 of the corresponding RAM 13A.

[0126] In (S42), each of the CPU cores 0 to 3 writes and updates normal operation information to the corresponding memory area 1 of RAM 13A.

[0127] In (S43), CPU core 0 checks whether the normal operation information of one of the multiple memory areas 0 and 1 of the corresponding RAM 13A has been updated for each of CPU cores 0 to 3. At this time, it is also acceptable to check only the memory area that was previously updated in chronological order.

[0128] In (S44), if CPU core 0 confirms that the normal operation information for one of the multiple memory areas 0, 1 of the corresponding RAM 13A has been updated for each of the multiple CPU cores 0 to 3, it instructs WDT21 via I / F 11B to clear the timer count.

[0129] In (S45), WDT21 clears the timer count and starts a new timer count in response to a clear command from CPU core 0.

[0130] Thus, according to this embodiment, even if an abnormality occurs in the first processor core, it is possible to have another processor core take over. This prevents conflicts in notifications from multiple processor cores. As a result, the monitoring unit is prevented from mistakenly recognizing that multiple processor cores are not functioning properly and performing unnecessary resets.

[0131] In each of the above embodiments, the term "processor" refers to a processor in a broad sense, and includes general-purpose processors (e.g., CPU: Central Processing Unit, etc.) and dedicated processors (e.g., GPU: Graphics Processing Unit, ASIC: Application Specific Integrated Circuit, FPGA: Field Programmable Gate Array, programmable logic device, etc.).

[0132] Furthermore, the processor operations in each of the above embodiments may not be performed by a single processor, but may also be performed by multiple processors located in physically separate locations working together. Also, the order of the processor operations is not limited to the order described in each of the above embodiments, but may be changed as appropriate.

[0133] The embodiments described above may take the form of a program that causes a computer to execute the functions of each part of the control device. The embodiments may also take the form of a non-temporary storage medium that is readable by a computer and stores these programs.

[0134] Furthermore, the configuration of the control device described in the above embodiment is merely an example, and may be modified as needed without departing from the main purpose.

[0135] Furthermore, the program processing flow described in the above embodiment is just one example, and unnecessary steps may be deleted, new steps added, or the processing order rearranged, as long as it does not deviate from the main purpose.

[0136] Furthermore, although the above embodiment describes a case in which the process according to the embodiment is realized by a software configuration using a computer by executing a program, the embodiment is not limited to this. The embodiment may also be realized by a hardware configuration or a combination of a hardware configuration and a software configuration.

[0137] The following is further disclosed regarding the embodiments described above.

[0138] The control device relating to (((1))) comprises a monitoring unit that monitors whether a first processor core, which is one of the multiple processor cores, is operating normally, and a memory having a plurality of storage areas pre-associated with each of the plurality of processor cores, with each of the plurality of processor cores periodically writing and updating information indicating that it is operating normally to the storage area of ​​the memory corresponding to it, and the first processor core determines whether the information has been updated by each of the plurality of processor cores for each storage area of ​​the memory, and controls the monitoring unit based on the determination result.

[0139] The control device relating to (((2))) is such that, in the control device relating to (((1))) the timing at which the first processor core determines whether or not the information has been updated is different from the timing at which each of the plurality of processor cores updates the information.

[0140] The control device relating to (((3))) determines whether or not the information has been updated between the time the first processor core updates the information and the next update, in the control device relating to (((2)))

[0141] The control device relating to (((4))) is a control device relating to any one of (((1))) to (((3))) in which the memory has multiple storage areas for each of the multiple processor cores, each of the multiple processor cores periodically updates the information in the corresponding multiple storage areas of the memory in sequence, and the first processor core determines that the information has been updated when the information in any of the multiple storage areas has been updated.

[0142] The control device relating to (((5))) determines that the information has not been updated if the first processor core has not updated all of the information in the plurality of memory areas.

[0143] The control device relating to (((6))) in any one of the control devices relating to (((1))) to (((3))) instructs the monitoring unit to clear the count when the first processor core has updated the information for each of the plurality of processor cores.

[0144] The control device relating to (((7))) determines that an abnormality has occurred if the first processor core has not updated the information for any of the plurality of processor cores, and instructs the monitoring unit to reset all of the plurality of processor cores.

[0145] The control device relating to (((8))) determines that an abnormality has occurred if the first processor core has not updated the information for any of the plurality of processor cores, and instructs the monitoring unit to reset only the processor core where the abnormality occurred among the plurality of processor cores.

[0146] The control device relating to (((9))) is a control device relating to any one of (((1))) to (((8))) in which the monitoring unit outputs a reset signal to reset all of the plurality of processor cores if there is no instruction from the first processor core for a certain period of time or longer.

[0147] The control device relating to (((10))) further includes an interrupt unit which receives a reset signal from the monitoring unit and performs an interrupt processing that replaces the first processor core with another predetermined processor core in accordance with the received reset signal.

[0148] The image processing device relating to (((11))) includes a control device described in any one of (((1))) to (((10))) and an image processing unit controlled by the control device.

[0149] The control program relating to (((12))) is a control program for the first processor core among the plurality of processor cores connected to a monitoring unit that monitors whether a first processor core, which is one of the plurality of processor cores, is operating normally, and a memory having a plurality of storage areas pre-associated with each of the plurality of processor cores, wherein the program periodically writes and updates information indicating that the first processor core is operating normally to the storage area of ​​the memory corresponding to the first processor core, and causes the computer to control the monitoring unit based on whether the information has been updated by each of the plurality of processor cores for each storage area of ​​the memory.

[0150] According to (((1))), (((11))), and (((12))), this has the effect of preventing notification conflicts between multiple processor cores.

[0151] According to (((2))), this has the effect of being able to determine whether or not the information has been updated at an appropriate time, compared to doing it at the same time.

[0152] According to (((3))), this has the effect of being able to determine whether or not the information has been updated between updates.

[0153] According to (((4))), compared to the case where each of the multiple processor cores has one memory area, this has the effect of being able to appropriately determine that information has been updated even if the memory update timing is staggered among the multiple processor cores.

[0154] According to (((5))), compared to the case where each of the multiple processor cores has one memory area, this has the effect of being able to appropriately determine that information has not been updated even if the memory update timing is staggered among the multiple processor cores.

[0155] According to (((6))), this has the effect of being able to properly clear the monitoring unit's count compared to not considering whether or not information has been updated for each of the multiple processor cores.

[0156] According to (((7))), this has the effect of being able to properly reset all of the multiple processor cores compared to not considering whether or not information has been updated for each of the multiple processor cores.

[0157] According to (((8))), this has the effect of being able to properly reset only the processor core where an anomaly occurred, compared to not considering whether or not information has been updated for each of the multiple processor cores.

[0158] According to (((9))), this has the effect of being able to output a reset signal even if an abnormality occurs in the first processor core.

[0159] According to (((10))), even if a malfunction occurs in the first processor core, it has the effect of being able to be replaced by another processor core. [Explanation of Symbols]

[0160] 10 Image Processing Device 11 CPU 11A RAM controller 11B input / output I / F 11C Interrupt section 12 ROM 13, 13A RAM 14 I / O 15 Storage section 16 Display 17 Control section 18 Manuscript Reading Section 19 Image forming unit 20 Communications Department 30, 30A, 30B control devices 50 Terminal devices 100 Image Processing Systems

Claims

1. A monitoring unit that monitors whether the first processor core, which is one of the multiple processor cores, is operating normally, A memory having multiple storage areas pre-associated with each of the multiple processor cores, The plurality of processor cores connected to the above, Each of the plurality of processor cores periodically writes and updates information indicating that it is operating normally to the corresponding memory storage area. The first processor core controls the monitoring unit based on whether the information has been updated by each of the plurality of processor cores for each storage area of ​​the memory. Control device.

2. The timing at which the first processor core determines whether or not the information has been updated is different from the timing at which each of the plurality of processor cores updates the information. The control device according to claim 1.

3. The first processor core determines whether or not the information has been updated between the time the information was updated and the next update. The control device according to claim 2.

4. The memory has multiple storage areas for each of the multiple processor cores, Each of the plurality of processor cores periodically updates the information in the corresponding memory's memory area in sequence. The first processor core determines that the information has been updated if the information in any of the plurality of memory areas has been updated. The control device according to claim 1.

5. The first processor core determines that the information has not been updated if none of the information in the plurality of storage areas has been updated. The control device according to claim 4.

6. The first processor core, when the information has been updated for each of the plurality of processor cores, instructs the monitoring unit to clear the count. The control device according to claim 1.

7. The first processor core determines that an abnormality has occurred if the information has not been updated for any of the plurality of processor cores, and instructs the monitoring unit to reset all of the plurality of processor cores. The control device according to claim 6.

8. The first processor core determines that an abnormality has occurred if the information has not been updated for any of the plurality of processor cores, and instructs the monitoring unit to reset only the processor core where the abnormality occurred among the plurality of processor cores. The control device according to claim 6.

9. The monitoring unit outputs a reset signal to reset all of the multiple processor cores if no instructions are received from the first processor core for a certain period of time or longer. The control device according to claim 1.

10. The system further includes an interrupt unit that receives a reset signal from the monitoring unit and performs an interrupt process to replace the first processor core with another predetermined processor core in accordance with the received reset signal. The control device according to claim 9.

11. A control device according to any one of claims 1 to 10, An image processing unit controlled by the aforementioned control device, Image processing device including

12. A monitoring unit that monitors whether the first processor core, which is one of the multiple processor cores, is operating normally, A memory having multiple storage areas pre-associated with each of the multiple processor cores, A control program for the first processor core among the plurality of processor cores connected, The memory storage area corresponding to the first processor core is periodically updated by writing information indicating that it is operating normally. The monitoring unit is controlled based on whether or not the information has been updated by each of the plurality of processor cores for each storage area of ​​the memory. A control program designed to be executed by a computer.

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