Arithmetic processing unit and arithmetic processing method

Abstract

To output an instruction refetch request by an out-of-order without deteriorating prediction accuracy of a conditional branch instruction.SOLUTION: A branch prediction part has a prediction holding part for holding prediction values of the continuous number of establishing times of each conditional branch instruction, the current number of establishing times of each conditional branch instruction and the remaining number of establishing times of each conditional branch instruction. A branch instruction issue scheduler outputs an instruction refetch request, and outputs a repair request to the branch prediction part in accordance with conditional branch instructions held between a position of determining a branch prediction error and a beginning in the case of determining the branch prediction errors of conditional branch instructions held other than the beginning of a branch instruction completion queue holding a completion waiting branch instruction. The branch prediction part sets a prediction value of the remaining number of establishing times to difference between the continuous number of establishing times and the current number of establishing times on the basis of the instruction refetch request, and further subtracts the number of conditional branch instructions corresponding to the repair request from the prediction value of the remaining number of establishing times.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an arithmetic processing unit and an arithmetic processing method.

Background Art

[0002] An arithmetic processing unit such as a CPU has a pipeline that divides and executes instructions, and improves processing performance by enabling parallel execution of instructions. Further, when a branch prediction mechanism for predicting the presence or absence of a branch of a conditional branch instruction is provided in this type of arithmetic processing unit, the processing performance is further improved.

[0003] For example, for each conditional branch instruction with the same address, the number of times the branch continuously holds and the number of times the branch continuously does not hold are stored as patterns, and a branch prediction method for predicting whether the conditional branch instruction holds or does not hold is known (see, for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] For example, a reservation station for branch instructions performs processing of branch instructions in order, and sequentially reports completion of branch instructions from the head of a queue that holds information on branch instructions. For example, when a reservation station for branch instructions determines a branch prediction miss based on the execution result of a conditional branch instruction, it waits until the determined conditional branch instruction becomes the head of the queue, and then outputs an instruction re-fetch request in response to the branch prediction miss.

[0006] Thus, when instruction refetch requests are output in order, the fetch process for the instruction refetch request cannot be performed until the conditional branch instruction that has detected a branch prediction error reaches the top of the queue. In this case, the processing time of the instruction fetch pipeline that performs the fetch process for the instruction refetch request cannot be hidden, and the processing performance of the arithmetic unit is reduced.

[0007] If an instruction refetch request can be issued out of order without waiting for a conditional branch instruction with a confirmed misprediction to reach the top of the queue, the processing time of the instruction fetch pipeline that performs the fetching operation for the instruction refetch request can be hidden. However, no method has been proposed to issue an instruction refetch request out of order without reducing the prediction accuracy of conditional branch instructions.

[0008] In one aspect, the present invention aims to output instruction refetch requests out of order without reducing the prediction accuracy of conditional branch instructions. [Means for solving the problem]

[0009] From one perspective, the arithmetic processing unit is an arithmetic processing unit that executes instructions by pipeline processing, and has a prediction holding unit that holds prediction information including a predicted value for the number of consecutive executions of each conditional branch instruction, the current number of executions of each conditional branch instruction, and a predicted value for the remaining number of executions of each conditional branch instruction; a branch prediction unit that predicts the number of consecutive executions of each conditional branch instruction based on the prediction values; an address generation unit that generates a fetch address for the next instruction based on the prediction result by the branch prediction unit or an address included in an instruction refetch request; and a branch instruction completion queue that sequentially holds branch instructions fetched based on the fetch address, and completes branch instructions held in the branch instruction completion queue in order, and conditional branch instructions The branch instruction issuance scheduler includes: a branch instruction issuance scheduler which, when the branch prediction unit determines a branch prediction error based on the execution result, outputs an instruction refetch request; and when it determines a branch prediction error for a conditional branch instruction held anywhere other than the head of the branch instruction completion queue, outputs a repair request to the branch prediction unit corresponding to the conditional branch instructions held between the position where the branch prediction error was determined and the head of the branch instruction completion queue, wherein the branch prediction unit sets the predicted value of the remaining number of successful executions to the difference between the predicted value of the consecutive number of successful executions and the current number of successful executions based on the instruction refetch request from anywhere other than the head of the branch instruction completion queue, and further subtracts the number of conditional branch instructions corresponding to the repair request from the predicted value of the remaining number of successful executions. [Effects of the Invention]

[0010] It is possible to output instruction refetch requests out of order without reducing the prediction accuracy of conditional branch instructions. [Brief explanation of the drawing]

[0011] [Figure 1] Block diagram showing an example of a processing unit in one embodiment. [Figure 2] Figure 1 is an explanatory diagram showing an example of the operation of the arithmetic processing unit when a branch instruction is executed. [Figure 3]Figure 1 is an explanatory diagram illustrating an example where the branch instruction issuing scheduler outputs an instruction refetch request either in order or out of order. [Figure 4] This diagram illustrates an example of an instruction loop containing a conditional branch instruction, and an example of the operation of the branch instruction issuing scheduler when the instruction loop is processed. [Figure 5] Block diagram showing an example of a processing unit in another embodiment. [Figure 6] Figure 5 is a block diagram showing an example of an RSBR. [Figure 7] Figure 5 is a block diagram showing an example of a branching prediction mechanism. [Figure 8] Figure 7 is an explanatory diagram illustrating an example of how the current count value of the LPT is updated. [Figure 9] Figure 7 is a flowchart showing an example of the operation of the RSBR, LPT section, and instruction fetch address generation section. [Figure 10] This flowchart shows a continuation of Figure 9. [Figure 11] This is a block diagram showing an example of an information processing system including the arithmetic processing unit shown in Figure 1 or the arithmetic processing unit shown in Figure 5. [Modes for carrying out the invention]

[0012] The embodiments will be described below with reference to the drawings. In the following, the same symbols as the signal names will be used for the signal lines through which signals are transmitted. The arithmetic processing unit described below is a superscalar processor that executes instructions in parallel by pipeline processing, although it is not particularly limited. The arithmetic processing unit described below may also be a scalar processor.

[0013] Figure 1 shows an example of an arithmetic processing unit in one embodiment. The arithmetic processing unit 100 shown in Figure 1 includes an address generation unit 1, a memory 2, a branch instruction issuance scheduler 3, and a branch prediction unit 5.

[0014] The arithmetic processing unit 100 may include an instruction buffer unit that holds instructions, an instruction decoder that decodes instructions, an arithmetic instruction issue scheduler that schedules the output of arithmetic instructions, an arithmetic unit that executes arithmetic instructions, a register file that holds operand data, and the like.

[0015] The address generation unit 1 outputs the value of the program counter PC or the address output from the branch prediction unit 5 to the memory 2, and fetches an instruction from the memory 2. The instruction fetched from the memory 2 is supplied to a branch instruction issue scheduler 3, a branch prediction unit 5, an arithmetic instruction issue scheduler (not shown), and the like. For example, the address generation unit 1 detects a branch prediction miss based on an instruction re-fetch request (including the re-instruction fetch address) notified from the branch instruction issue scheduler 130. In this case, the address generation unit 1 fetches an instruction using the re-instruction fetch address. When the address generation unit 1 clears the pipeline to cancel the execution of an instruction due to the occurrence of various errors, it fetches an instruction using the value of the program counter PC.

[0016] [[ID=X]] [[ID=X]]

[0017] [[ID=X]] In the branch instruction completion queue 4, the information of the uncompleted branch instructions is held in the order of program description from the entry indicated by the output pointer (not shown) to the entry indicated by the input pointer (not shown) from the TOQ entry. The information of the branch instruction whose processing has been completed is waited until it becomes the TOQ and then taken out from the TOQ. That is, the completion processing of the branch instruction by the branch instruction issue scheduler 3 is performed in order. Hereinafter, the information of the branch instruction held in the branch instruction completion queue 4 is simply referred to as a branch instruction.

[0018] ​The branch instruction issuance scheduler 3 outputs a completion report to the branch prediction unit 5 when it determines, based on calculation results, whether a branch instruction held in TOQ is taken or not. If the branch instruction issuance scheduler 3 detects a branch prediction error for an incomplete conditional branch instruction, it outputs an instruction refetch request to the address generation unit 1 and the branch prediction unit 5. The instruction refetch request is output not only for conditional branch instructions in TOQ, but also for conditional branch instructions outside of TOQ.

[0019] The branch instruction issuing scheduler 3 invalidates branch instructions held in entries after the entry that output the instruction refetch request (entries opposite to TOQ). If the branch instruction issuing scheduler 3 outputs an instruction refetch request from an entry other than TOQ, it outputs a repair request to the branch prediction unit 5 corresponding to conditional branch instructions held between TOQ and the entry where the branch prediction error was detected.

[0020] The branch prediction unit 5 has a prediction holding unit 6. The branch prediction unit 5 uses the information held in the prediction holding unit 6 to predict whether a branch due to a conditional branch instruction will occur based on the address generated by the address generation unit 1. If it predicts that a branch will occur, it outputs the address indicating the branch destination to the address generation unit 1.

[0021] The prediction and holding unit 6 has multiple entries, each holding information for a single conditional branch instruction. Each entry holds prediction information including a predicted number of consecutive executions of the conditional branch instruction, the current number of executions of the conditional branch instruction, and a predicted number of remaining executions of the conditional branch instruction. The branch prediction unit 5 then uses the prediction and holding unit 6 to predict the number of consecutive executions of the conditional branch instruction and the transition from execution to non-execution.

[0022] Furthermore, the prediction storage unit 6 may store only a portion of the address of the conditional branch instruction, with the remaining address being used as an index to identify entries in the prediction storage unit 6. Also, when predicting the number of consecutive failures, the prediction storage unit 6 stores the current number of successes, the predicted number of consecutive failures, and the predicted number of remaining failures, instead of the current number of successes, the predicted number of consecutive successes, and the predicted number of remaining successes.

[0023] The current count of successful executions indicates the number of consecutive successful executions since the conditional branch instruction failed, and is incremented each time the branch instruction issuing scheduler 3 reports the completion of the conditional branch instruction's execution. The current count of successful executions is reset to "0" when the completion report for the conditional branch instruction is failed. When predicting the number of consecutive failures of a conditional branch instruction and the transition from failure to success, the current count of failures is incremented each time the completion report for the failure of a conditional branch instruction is reported, and reset to "0" when the completion report for the conditional branch instruction is successful.

[0024] The predicted number of consecutive fulfillments indicates the predicted number of remaining branches in which the conditional branch instruction will be successfully executed consecutively. For example, if the predicted number of consecutive fulfillments is "30", the branch prediction unit 5 predicts that the next conditional branch instruction will be successful if the predicted number of remaining fulfillments is between "0" and "29". If the predicted number of remaining fulfillments is "30", the branch prediction unit 5 predicts that the next conditional branch instruction will not be successful.

[0025] Before starting branch prediction, the branch prediction unit 5 obtains the number of consecutive fulfillments (e.g., loop count) until a conditional branch instruction fails, based on the completion report for each conditional branch instruction. If, for example, the number of consecutive fulfillments is the same for two consecutive times, the branch prediction unit 5 sets the number of consecutive fulfillments as the predicted value for the number of consecutive fulfillments and starts branch prediction for the conditional branch instruction for which the predicted value for the number of consecutive fulfillments has been set.

[0026] When predicting the number of consecutive failures, the predicted number of consecutive failures used instead of the predicted number of consecutive successes indicates the predicted number of remaining failures for the conditional branch instruction. For example, if the predicted number of consecutive failures is "30", the branch prediction unit 5 predicts that the next conditional branch instruction will fail if the predicted number of remaining failures is between "0" and "29". The branch prediction unit 5 predicts that the next conditional branch instruction will succeed if the predicted number of remaining failures is "30".

[0027] The predicted number of remaining fulfillments is updated when a conditional branch instruction is fetched, when an instruction refetch request occurs, or when a repair request occurs. Based on the reception of the fetch address of the conditional branch instruction, the branch prediction unit 5 decrements the predicted number of remaining fulfillments in the corresponding entry if it is not "0". Based on the reception of the fetch address of the conditional branch instruction, the branch prediction unit 5 sets the predicted number of consecutive fulfillments to the predicted number of remaining fulfillments if it is "0". Then, the branch prediction unit 5 uses the predicted number of consecutive fulfillments, which is updated when the instruction is fetched, to predict whether the conditional branch instruction will be fulfilled or not.

[0028] When the branch prediction unit 5 receives an instruction refetch request for a conditional branch instruction held outside of the TOQ of the branch instruction completion queue 4, it sets the predicted number of remaining executions to a value obtained by subtracting the current execution count from the predicted number of consecutive executions for the entry holding the incomplete conditional branch instruction in the instruction loop. The instruction loop is explained in Figure 4. Furthermore, in response to a repair request from the branch instruction issuance scheduler 3, the branch prediction unit 5 decrements the predicted number of remaining executions for each incomplete conditional branch instruction in the instruction loop. Note that when processing a repair request, if the predicted number of remaining executions for an incomplete conditional branch instruction in the instruction loop is "0", the branch prediction unit 5 sets the predicted number of consecutive executions to the predicted number of remaining executions.

[0029] This allows the predicted number of remaining fulfillments for an incomplete conditional branch instruction to be updated to an appropriate value, even when an instruction refetch request is output out of order from an entry other than TOQ. Therefore, it is possible to suppress the decrease in prediction accuracy of the predicted number of remaining fulfillments for conditional branch instructions within an instruction loop after an instruction refetch outside of TOQ for a conditional branch instruction where a branch prediction error occurred. An example of updating the predicted number of remaining fulfillments when an instruction refetch request is output in response to an entry other than TOQ is illustrated in Figures 3 and 4.

[0030] Furthermore, when the branch prediction unit 5 predicts the number of consecutive failures, and receives an instruction refetch request for a conditional branch instruction held outside of TOQ, it sets the predicted number of remaining failures for the incomplete conditional branch instruction to the predicted number of consecutive failures minus the current number of failures. However, if the predicted number of remaining failures for an incomplete conditional branch instruction is "0", the branch prediction unit 5 sets the predicted number of consecutive failures to the predicted number of remaining failures.

[0031] Figure 2 shows an example of the operation of the arithmetic processing unit 100 in Figure 1 when a branch instruction is executed. In the branch instruction completion process, the branch instruction issue scheduler 3 waits until the entry holding the branch instruction becomes TOQ (Time Out of Quotient) if the processing of a branch instruction held in any of the entries of the branch instruction completion queue 4 is confirmed, and then performs the branch instruction completion process. In the example shown in Figure 2, a branch prediction error for a conditional branch instruction held in the second entry of the branch instruction completion queue 4 is detected before the processing of the branch instruction held in TOQ of the branch instruction completion queue 4 is confirmed.

[0032] In the upper part of Figure 2, the branch instruction issuance scheduler 3, upon detecting a branch prediction error for a branch instruction held in any entry of the branch instruction completion queue 4, outputs an instruction refetch request without waiting for the entry holding the branch instruction to become the TOQ (Time Out of Quotient). Then, when the entry holding the branch instruction becomes the TOQ, it performs the branch instruction completion process.

[0033] This allows instruction fetching in response to an instruction refetch request to be performed and the fetched instruction decoded without waiting for the entry holding the conditional branch instruction with the branch prediction error to become the TOQ (Time Out of Q). As a result, the processing of the instruction fetch pipeline in response to instruction refetch requests can be hidden, improving the processing efficiency of the pipeline.

[0034] If a branch prediction error is confirmed, the arithmetic processing unit 100 outputs a request for instruction refetching of a conditional branch instruction at the correct address from the branch instruction issuance scheduler 3 to the address generation unit 1, and clears the pipeline stage that was performed in response to the branch prediction error.

[0035] The lower brackets in Figure 2 illustrate the operation of other arithmetic processing units that perform instruction refetching in order according to the order in which instructions are written in the program. For example, if a branch prediction error is confirmed, other arithmetic processing units will output an instruction refetch request after the entry holding the conditional branch instruction with the branch prediction error becomes TOQ.

[0036] In this case, the timing of the instruction fetch in response to the instruction refetch request is delayed compared to the timing shown in the upper part of Figure 2, resulting in a performance degradation due to the waiting time between the confirmation of a branch prediction error and the output of the instruction refetch request.

[0037] Figure 3 shows an example where the branch instruction issue scheduler 3 in Figure 1 outputs an instruction refetch request either in order or out of order. In order means that the instruction refetch request is output in response to a conditional branch instruction held in the TOQ of the branch instruction completion queue 4. Out of order means that the instruction refetch request is output in response to a conditional branch instruction held in an entry other than TOQ of the branch instruction completion queue 4. Entries shown in diagonal lines indicate that they hold a conditional branch instruction for which an instruction refetch request is output. Entries shown in shaded areas indicate that they hold a conditional branch instruction awaiting completion.

[0038] In Figure 3(A), where an instruction refetch request for a conditional branch instruction held in TOQ is output, conditional branch instructions prior to the conditional branch instruction targeted by the instruction refetch request have already been reflected in the prediction holding unit 6. This allows for the appropriate updating of the predicted number of remaining fulfillments, thereby suppressing a decrease in prediction accuracy.

[0039] On the other hand, in Figure 3(B), where an instruction refetch request for a conditional branch instruction held outside of TOQ is output, at least one of the entries prior to the conditional branch instruction targeted by the instruction refetch request (on the TOQ side) may hold a conditional branch instruction awaiting completion. Furthermore, the information in the prediction holding unit 6 corresponding to the conditional branch instruction awaiting completion has not been updated.

[0040] Therefore, as described above, the instruction issuing scheduler 3 outputs a repair request corresponding to the conditional branch instruction awaiting completion, and the branch prediction unit 5 updates the predicted value of the remaining number of conditions to be met in the prediction holding unit 6 corresponding to the conditional branch instruction awaiting completion based on the repair request.

[0041] In Figures 3(A) and 3(B), branch instructions held in entries after the entry holding the conditional branch instruction that is the target of the instruction refetch request (on the opposite side of TOQ) are invalidated.

[0042] Figure 4 shows an example of an instruction loop containing a conditional branch instruction and an example of the operation of the branch instruction issuing scheduler 3 when the instruction loop is processed. In Figure 4, it is assumed that only conditional branch instructions A and B shown in the instruction sequence are executed.

[0043] Furthermore, in Figure 4, it is assumed that conditional branch instruction B is either not registered in the prediction storage unit 6's entry, or the entry in the prediction storage unit 6 corresponding to conditional branch instruction B is not valid. Here, if conditional branch instruction B has never been completed, conditional branch instruction B is not registered in the prediction storage unit 6. Also, if the number of consecutive fulfillment counts for conditional branch instruction B has not been repeated multiple times, the information for conditional branch instruction B held in the prediction storage unit 6 is not valid.

[0044] The instruction sequence shown in Figure 4 has an instruction loop with conditional branch instruction A, and a conditional branch instruction B that determines whether to skip a predetermined number of instructions in the forward direction during the instruction loop with conditional branch instruction A. When processing an instruction sequence within such an instruction loop, conditional branch instructions A and B are alternately held in the branch instruction completion queue 4 of the branch instruction issuance scheduler 3.

[0045] In conditional branch instruction B(5), the execution result of conditional branch instruction B(5) is true, contrary to the branch prediction unit 5's prediction that it would not be true, resulting in a branch prediction error. Assume that in conditional branch instruction A, which was completed just before the instruction refetch request was output, the remaining number of true conditions on a completion basis is 10. Here, the remaining number of true conditions on a completion basis is shown as the difference between the predicted number of consecutive true conditions and the current number of true conditions.

[0046] At the point when the instruction refetch request is issued, the remaining number of fulfilled conditions for conditional branch instruction A(2) on a completion basis is 9, and the remaining number of fulfilled conditions for conditional branch instruction A(4) on a completion basis is 8. The remaining number of fulfilled conditions on a completion basis is usually greater than the predicted number of fulfilled conditions that is updated on a fetch basis.

[0047] As described above, when the address generation unit starts refetching instructions from the jump destination of conditional branch instruction B(5) based on the instruction refetch request, the remaining number of fulfilled conditions for conditional branch instruction A on a completion basis is 10. However, between the TOQ and the entry holding conditional branch instruction B(5), there are incomplete entries for conditional branch instruction A(2) and conditional branch instruction A(4). Therefore, in order to avoid reducing the branch prediction accuracy of conditional branch instruction A, it is preferable that the predicted value of the remaining number of fulfilled conditions for conditional branch instruction A be set to 8 when the prediction holding unit 6 is updated based on the instruction refetch request for conditional branch instruction B.

[0048] If conditional branch instructions A(2) and A(4) are ignored and the predicted number of remaining successful occurrences is set to 10, the predicted number of remaining successful occurrences will be 2 more than the number that should be updated. In this case, the branch prediction unit 5 predicts a successful occurrence when it should predict a non-successful occurrence, resulting in a branch prediction error.

[0049] To reduce the frequency of branch prediction errors and suppress the decline in prediction accuracy, the branch instruction issuing scheduler 3 outputs a repair request to the branch prediction unit 5 when a branch prediction error occurs in an entry other than TOQ and outputs an instruction refetch request, causing the predicted value of the remaining number of fulfilled conditions to be corrected. For example, the repair request is output in a way that identifies the conditional branch instruction for each incomplete conditional branch instruction held in the entry between TOB and the entry holding the conditional branch instruction that is the target of the instruction refetch request.

[0050] The branch prediction unit 5 updates the predicted value of the remaining number of fulfilled conditions if the entry in the prediction holding unit 6, which holds information on conditional branch instructions corresponding to the repair request, is valid. This suppresses a decrease in the branch prediction accuracy by the branch prediction unit 5 even when an instruction refetch request is output for conditional branch instructions held in entries other than TOQ.

[0051] Note that there may be multiple conditional branch instructions with different addresses between the TOB (Takeover Bid) and the entry that holds the conditional branch instruction that is the target of the instruction refetch request. In this case, the branch instruction issue scheduler 3 outputs a repair request corresponding to the number of conditional branch instructions for each conditional branch instruction with a different address.

[0052] In this embodiment, even when an instruction refetch request is output out of order from an entry other than TOQ, the predicted value of the remaining number of fulfilled conditional branch instructions in an incomplete conditional branch instruction can be updated to an appropriate value. Therefore, it is possible to suppress the decrease in prediction accuracy of the predicted value of the remaining number of fulfilled conditional branch instructions in the instruction loop after instruction refetching of a conditional branch instruction outside of TOQ where a branch prediction error occurred. As a result, the processing efficiency of the pipeline can be improved, and the processing performance of the arithmetic processing unit 100 can be improved.

[0053] By improving the processing performance of the arithmetic processing unit 100, the processing performance of systems such as servers equipped with the arithmetic processing unit 100 can be improved, thereby reducing the time required for scientific and technical calculations, deep learning, or various simulations.

[0054] In the branch instruction completion queue 4, instruction fetching in response to an instruction refetch request can be performed and the fetched instruction decoded without waiting for the entry holding the conditional branch instruction that caused the branch prediction error to become the TOQ. As a result, the instruction fetch pipeline processing for instruction refetch requests can be hidden, improving the processing efficiency of the pipeline.

[0055] The branch prediction unit 5 decrements the predicted value of the remaining number of fulfilled conditions for the entry corresponding to the incomplete conditional branch instruction that corresponds to the repair request from the branch instruction issuing scheduler 3, or sets it to the predicted value of consecutive fulfilled conditions. This allows the predicted value of the remaining number of fulfilled conditions for the incomplete conditional branch instruction to be updated to an appropriate value even when the instruction refetch request is output out of order from an entry other than TOQ. Therefore, it is possible to suppress the decrease in the prediction accuracy of the predicted value of the remaining number of fulfilled conditions for the conditional branch instruction after instruction refetching of a conditional branch instruction in which a branch prediction error occurred.

[0056] The prediction and holding unit 6 can store the current number of failures, past failures, and remaining failures, instead of the current number of successes, the predicted number of consecutive successes, and the predicted number of remaining successes. This allows the prediction and holding unit 6 to be used not only to predict the number of consecutive successes of a conditional branch instruction, but also to predict the number of consecutive failures of a conditional branch instruction.

[0057] Figure 5 shows an example of a processing unit in another embodiment. Detailed explanations of elements and functions that are the same as or similar to those described in Figures 1 to 4 are omitted.

[0058] The arithmetic processing unit 102 shown in Figure 5 includes an instruction fetch address generation unit 10, a branch prediction mechanism 12, a primary instruction cache 14, a secondary instruction cache 16, an instruction buffer unit 18, an instruction decoding unit 20, and a register renaming unit 22. The instruction fetch address generation unit 10 is an example of an address generation unit that generates the fetch address of an instruction.

[0059] The arithmetic processing unit 102 also includes a reservation station RS, a commit control unit 34, and a program counter 36. Hereinafter, the commit control unit 34 will also be referred to as the CSE (Commit Stack Entry) 34. The reservation station RS includes an RSA (Reservation Station for Address generation) 24, an RSE (Reservation Station for Execution) 26, an RSF (Reservation Station for Floating point) 28, and an RSBR (Reservation Station for Branch) 30. Hereinafter, when RSA 24, RSE 26, RSF 28, and RSBR 30 are not distinguished, they will also be referred to as the reservation station RS.

[0060] Furthermore, the arithmetic processing unit 102 includes an operand address generation unit 38, a primary data cache 40, arithmetic units 42 and 44, a fixed-point update buffer 46, a floating-point update buffer 48, a fixed-point register 50, and a floating-point register 52. Hereafter, the fixed-point update buffer 46 and the floating-point update buffer 48 will also be referred to as update buffers 46 and 48. The fixed-point register 50 and the floating-point register 52 will also be referred to as registers 50 and 52.

[0061] The instruction fetch address generation unit 10 generates the fetch address of the next instruction based on the value of the program counter 36, the prediction result from the branch prediction mechanism 12, or the address included in the instruction refetch request from the RSBR 30. The instruction fetch address generation unit 10 outputs the generated fetch address of the next instruction to the primary instruction cache 14 and fetches the instruction from the primary instruction cache 14.

[0062] The branch prediction mechanism 12 has an LPT (Local Pattern Table) 125. Based on the address generated by the instruction fetch address generation unit 10, the branch prediction mechanism 12 uses the LPT 125 to predict whether or not a branch will be executed by a conditional branch instruction. If the branch prediction mechanism 12 predicts a branch (successful), it outputs the branch destination address (target address) to the instruction fetch address generation unit 10. An example of the branch prediction mechanism 12 is illustrated in Figure 7.

[0063] The primary instruction cache 14 retrieves an instruction from the area indicated by the address from the instruction fetch address generation unit 10 and outputs the retrieved instruction to the instruction buffer unit 18. The instructions held by the primary instruction cache 14 include arithmetic instructions that perform calculations using the arithmetic units 42 and 44, memory access instructions, or branch instructions. If the primary instruction cache 14 does not hold an instruction in the area indicated by the address, it outputs an access request to the secondary cache 16 and retrieves an instruction from the secondary cache 16.

[0064] The secondary cache 16 retrieves an instruction from the area indicated by the address included in the access request and outputs the retrieved instruction to the primary instruction cache 14. If the secondary cache 16 does not hold an instruction in the area indicated by the address, it outputs an access request to the main memory 210 and retrieves an instruction from the main memory 210. For example, the main memory 210 is located on a semiconductor chip separate from the semiconductor chip containing the arithmetic processing unit 102. Note that the secondary cache may hold data as well as instructions.

[0065] The instruction buffer unit 18 holds multiple instructions output from the primary instruction cache 14 in parallel and outputs the held instructions to the instruction decode unit 20 in parallel. For example, the instruction buffer unit 18 outputs four instructions to the instruction decode unit 20 in parallel. Note that the number of instructions output in parallel from the primary instruction cache 14 to the instruction buffer unit 18 is more than four.

[0066] The instruction decoding unit 20 has multiple decoding slots that decode multiple instructions output from the instruction buffer unit 18 in parallel. The number of decoding slots is four, although not particularly limited. Each decoding slot determines the reservation station RS (RSA24, RSE26, RSF28, or RSBR30) corresponding to the arithmetic units 42, 44, etc. that execute each instruction. Each decoding slot adds information to the instruction indicating the reservation station RS to which the instruction is output, and outputs the instruction with the added information to the register renaming unit 22.

[0067] Furthermore, the instruction decoding unit 20 assigns an instruction identifier (IID) to each instruction according to the order in which they are described in the program executed by the arithmetic processing unit 102, and outputs the assigned instruction identifier along with the decoded instruction (decode result) to the CSE 34. Note that the instruction buffer unit 18 and the instruction decoding unit 20 process multiple instructions in parallel (in order) without changing the order in which they are described in the program.

[0068] The register renaming unit 22, in order to enable out-of-order execution, allocates an entry in the update buffer 46 (or 48) to be used in place of the register 50 (or 52) specified in the instruction operand when the instruction is executed. The register renaming unit 22 outputs the instruction output from the instruction decoding unit 20 to the reservation station RS that will execute the instruction, along with information indicating the allocated entry in the update buffer 46 (or 48). The instruction output from the instruction decoding unit 20 includes information indicating which reservation station RS the instruction should be output to.

[0069] For example, if the instruction decoded by the instruction decoding unit 20 is a memory access instruction (load instruction or store instruction), the instruction is output to RSA24. If the instruction decoded by the instruction decoding unit 20 is a fixed-point arithmetic instruction, the instruction is output to RSE26. If the instruction decoded by the instruction decoding unit 20 is a floating-point arithmetic instruction, the instruction is output to RSF28. If the instruction decoded by the instruction decoding unit 20 is a branch instruction, the instruction is output to RSBR30.

[0070] RSA24 holds memory access instructions received sequentially from the instruction decoding unit 20 and outputs the held memory access instructions to the operand address generation unit 38 in the order in which they can be executed (out of order). The operand address generation unit 38 generates addresses based on the memory access instructions received from the reservation station RSA and outputs the generated addresses to the primary data cache 40. In Figure 5, the arithmetic processing unit 102 has multiple operand address generation units 38, but the number of operand address generation units 38 may be as few as one.

[0071] For example, when a load instruction is executed, the primary data cache 40 retrieves data held in the area indicated by the address from the operand address generation unit 38 and outputs the retrieved data to the update buffer 46 or update buffer 48. Similar to the primary instruction cache 14, if the primary data cache 40 does not hold data in the area indicated by the address, it outputs an access request to the secondary cache 16 and retrieves data from the secondary cache 16.

[0072] RSE26 holds fixed-point arithmetic instructions received sequentially from the instruction decoding unit 20 and outputs the held arithmetic instructions to the arithmetic unit 42 in the order in which they can be executed (out of order). RSF28 holds floating-point arithmetic instructions received sequentially from the instruction decoding unit 20 and outputs the held arithmetic instructions to the arithmetic unit 44 in the order in which they can be executed (out of order).

[0073] The RSBR30 holds branch instructions received sequentially from the instruction decoding unit 20 until it determines whether the branch is successful or unsuccessful and outputs a completion report. The RSBR30 performs the completion processing of branch instructions in order, notifies the CSE34 of the completion signal, and causes the CSE34 to commit the branch instruction. If a branch prediction error is confirmed, the RSBR30 outputs an instruction refetch request to the instruction fetch address generation unit 10 and the branch prediction mechanism 12. An example of the RSBR30 is shown in Figure 6.

[0074] The CSE34 has a queue that stores instructions received via the register renaming unit 22 in the order described in the program, and a completion processing unit that performs instruction completion processing. The completion processing unit performs instruction completion processing in order according to the order described in the program, based on the instruction completion reports from each reservation station RS and the queue information. In the completion processing, the completion processing unit commits (terminates) the instructions corresponding to the completion reports from the instructions waiting for completion reports stored in the CSE34 queue, and updates the resources.

[0075] The program counter 36 updates the memory address indicating the location where the instruction is stored based on instructions from the commit control unit 34, and outputs the updated memory address as the program counter PC to the instruction fetch address generation unit 10.

[0076] The arithmetic unit 42 is an arithmetic unit for fixed-point numbers. The arithmetic processing unit 102 may have multiple arithmetic units 42 in order to execute fixed-point number arithmetic instructions decoded in parallel by the instruction decoding unit 20 in parallel. The arithmetic unit 42 obtains the data to be used for calculation from the update buffer 46 or register 50 and stores the calculation result in the update buffer 46.

[0077] The arithmetic unit 44 is an arithmetic unit for floating-point numbers. For example, the arithmetic processing unit 102 may have multiple arithmetic units 44 in order to execute floating-point arithmetic instructions decoded in parallel by the instruction decoding unit 20 in parallel. The arithmetic unit 44 obtains the data to be used for calculation from the update buffer 48 or register 52 and stores the calculation result in the update buffer 48. The arithmetic unit 44 may also include arithmetic units that perform multiply-accumulate operations, integer operations, logical operations, etc.

[0078] The update buffer 46 has multiple entries that hold data used for calculations performed by the arithmetic unit 42, and a management unit that manages the correspondence between the entries and the registers in register 50. The update buffer 48 has multiple entries that hold data used for calculations performed by the arithmetic unit 44, and a management unit that manages the correspondence between the entries and the registers in register 52.

[0079] Register 50 has multiple entries that hold data used for calculations performed by the arithmetic unit 42 and the results of calculations performed by the arithmetic unit 42. Register 52 has multiple entries that hold data used for calculations performed by the arithmetic unit 44 and the results of calculations performed by the arithmetic unit 44.

[0080] For example, register 50 contains 32 fixed-point registers with a 64-bit configuration, and register 52 contains 32 floating-point registers with a 512-bit configuration. Note that the number of registers and the bit configuration of registers 50 and 52 may be other than those described above. Also, the bit configuration of register 52 for floating-point numbers may be variable.

[0081] The circuit elements of the arithmetic processing unit 102 shown in Figure 5 are divided into multiple stages by flip-flops (not shown), and the arithmetic processing unit 102 executes instructions by pipeline processing. For example, the pipeline stages include a decode stage, a decode transfer stage, a priority stage, a priority transfer stage, a buffer stage, an execution stage, and a write-back stage.

[0082] In the decoding stage, the instruction decoding unit 20 decodes the instruction. In the decode transfer stage, the instruction decoded by the instruction decoding unit 20 is output to RSE26, RSF28, etc. In the priority stage, for example, RSE26 determines which instruction to output to the arithmetic unit 42.

[0083] In the priority transfer stage, for example, an instruction is output from RSE26 to arithmetic unit 42. In the buffer stage, operands to be used in the calculation are read from update buffers 46, 48 or registers 50, 52, etc. In the execution stage, the calculation is performed by arithmetic unit 42 or arithmetic unit 44. In the write-back stage, the result of the calculation by arithmetic unit 42 or arithmetic unit 44 is stored in update buffer 46 or update buffer 48.

[0084] Figure 6 shows an example of the RSBR30 in Figure 5. The RSBR30 has a FIFO-type branch instruction completion queue 301, a branch control unit 302, a repair pointer 303, and a repair end pointer 304. The branch instruction completion queue 301 has multiple entries, each holding a valid flag VLD, the branch prediction result (true / false) predicted by the branch prediction mechanism 12, the predicted address, the prediction result flag, the program counter PC, and the conditional branch instruction flag. The branch instruction completion queue 301 is managed by the branch control unit 302 using an output pointer OUTP and an input pointer INP.

[0085] The branch instruction completion queue 301 holds information about branch instructions from the time they are decoded until processing is complete, in the order they are written in the program, in entries ranging from the input pointer INP to the output pointer OUTP. The valid flag VLD is set for valid entries. Information about branch instructions that have been processed is retrieved only from the entry pointed to by the output pointer OUTP. In other words, branch instruction completion processing in RSBR30 is performed in order. The branch instruction held in the entry pointed to by the output pointer OUTP is the first branch instruction that has not yet been processed. Hereafter, the entry pointed to by the output pointer OUTP will also be referred to as TOQ.

[0086] The prediction result area stores information indicating that a branch has been established if the branch prediction mechanism 12 predicts that a branch has been established (when the address indicated by the program counter PC is changed to the jump destination). The prediction result area also stores information indicating that a branch has not been established if the branch prediction mechanism 12 predicts that a branch has not been established (when the address indicated by the program counter PC is incremented).

[0087] The predicted address area holds the jump destination address predicted by the branch prediction mechanism 12. The prediction result flag area holds information indicating whether the branch prediction mechanism 12's prediction was correct or incorrect. The program counter PC area holds the address where the conditional branch instruction is stored as the program counter PC. The conditional branch instruction flag area is set to, for example, "1" when a conditional branch instruction is stored.

[0088] The branch control unit 302 outputs a completion report to the branch prediction mechanism 12, along with the program counter PC and conditional branch instruction flag held in the branch instruction completion queue 301. The branch prediction mechanism 12 updates the LPT 125 based on the completion report from RSBR 30, the program counter PC, and the conditional branch instruction flag.

[0089] In this embodiment, the branch control unit 302 performs the completion processing of branch instructions in order, but can perform instruction refetch requests due to branch prediction errors out of order. That is, the branch control unit 302 can output an instruction refetch request without waiting for the entry holding the conditional branch instruction that is the target of the instruction refetch request to become TOQ. This improves the processing performance of the arithmetic processing unit 102.

[0090] The branch control unit 302 compares the prediction result from the branch prediction mechanism 12 with the execution result of the conditional branch instruction for each entry in the branch instruction completion queue 301 to determine whether the prediction was correct or not. For example, the branch control unit 302 determines the execution result of the conditional branch instruction based on the calculation result of the instruction that determines the condition code flag NZCV of the ARM instruction set received from the arithmetic unit or the target address of the indirect branch instruction, and determines the target address.

[0091] The branch control unit 302 sets the prediction result flag to "1" if the branch prediction mechanism 12's prediction is incorrect, and sets the prediction result flag to "0" if the branch prediction mechanism 12's prediction is correct.

[0092] If the branch control unit 302 detects that the branch prediction mechanism 12 has failed to predict the branch of a conditional branch instruction, it outputs an instruction refetch request corresponding to the correct address to the instruction fetch address generation unit 10 and the branch prediction mechanism 12. The branch prediction mechanism 12 updates the LPT 125 based on the instruction refetch request.

[0093] The branch control unit 302 clears the valid flag VLD of the entry on the input pointer INP side of the entry holding the conditional branch instruction that is the target of the instruction refetch request, and further suppresses the creation of new entries. The branch control unit 302 outputs an instruction to the pipeline to be cleared to clear the pipeline that has executed an incorrect path due to a conditional branch instruction whose branch prediction was incorrect.

[0094] The branch control unit 302 stores the entry number holding the conditional branch instruction that is the target of the refetch request as the repair end pointer 304, based on the output of the instruction refetch request for the conditional branch instruction held in addition to the TOQ, and sets the repair trigger. The repair pointer 303 is updated sequentially from the TOQ identification number to the identification number of the entry holding the conditional branch instruction that is the target of the refetch request.

[0095] The repair trigger is notified to the instruction fetch address generation unit 10. A set repair trigger indicates that the LPT125 is in the process of repair. While the repair trigger is set, the instruction fetch address generation unit 10 suppresses instruction refetching based on instruction refetch requests. This prevents the refetching of conditional branch instructions that have experienced branch prediction errors from starting before the repair process is complete, thereby preventing the LPT125 entry from being updated and suppressing malfunctions of the LPT125.

[0096] The branch control unit 302 sequentially updates the repair pointer 303 from the TOQ to the entry indicated by the repair end pointer. The branch control unit 302 sequentially reads the conditional branch instruction flag and program counter PC held in the entry indicated by the repair pointer 303 in the branch instruction completion queue 301 until the repair pointer 303 matches the repair end pointer 304.

[0097] Each time the branch control unit 302 reads the conditional branch instruction flag and the program counter PC, it outputs a repair request to the LPT unit 123 of the branch prediction mechanism 12. If the LPT unit 123 contains an entry in the program counter PC that holds a conditional branch instruction in the repair request, it decrements the current count value CURR-CNT of that entry, or sets the current count value CURR-CNT to the loop count LP-NUM.

[0098] The current count value CURR-CNT and loop count LP-NUM correspond to the predicted values ​​for the remaining number of occurrences and the predicted values ​​for consecutive occurrences, respectively, in Figure 1. The current count value CURR-CNT and loop count LP-NUM are explained in Figure 7.

[0099] This allows the current count value CURR-CNT, corresponding to conditional branch instructions held in entries from TOQ to repair end pointer 304, to be corrected to its original value even when an instruction refetch request is output from an entry other than TOQ. Here, the original value is the value that is updated when an instruction refetch request is output from TOQ.

[0100] Furthermore, if an instruction refetch request for a conditional branch instruction held in TOQ is output, the repair process described below is not performed, and the repair trigger remains in a reset state. When the repair trigger is in a reset state, the instruction fetch address generation unit 10 outputs the address to which the instruction is refetched based on the instruction refetch request.

[0101] Furthermore, when the branch control unit 302 determines that it should output an instruction refetch request for a conditional branch instruction held in an entry of the branch instruction completion queue 301, it searches for an entry closer to the TOQ to output an instruction refetch request. If there are multiple entries that can output an instruction refetch request, the branch control unit 302 decides to output the instruction refetch request from the entry closest to the TOQ.

[0102] Figure 7 shows an example of the branch prediction mechanism 12 of Figure 5. The branch prediction mechanism 12 includes a branch prediction unit 121, which includes a bimodal predictor 122 and an LPT unit 123, a branch command information holding unit 126, and a branch determination unit 127. The LPT unit 123 includes an LPT control unit 124 and an LPT 125. The LPT 125 is an example of a prediction holding unit.

[0103] The LPT unit 123 is a mechanism for predicting the pattern of consecutive fulfillment or failure of conditional branch instructions for a specific program counter PC. For example, if the loop is executed by fulfilling branches, the LPT unit 123 stores the number of fulfillment counts included in the loop and predicts whether to continue the loop when the branch is fulfilled or to exit the loop when the branch is not fulfilled. If the loop is executed by failing branches, the LPT unit 123 stores the number of failing branches included in the loop and predicts whether to continue the loop when the branch is not fulfilled or to exit the loop when the branch is fulfilled. In the following, unless otherwise specified, examples of predicting consecutive fulfillment patterns will be described. However, the LPT unit 64 can also be applied to predict consecutive failure patterns.

[0104] The LPT control unit 124 updates the contents of the LPT 125 based on the branch instruction completion report, repair request, and instruction refetch request received from the RSBR 30, and the instruction fetch address received from the instruction fetch address generation unit 10.

[0105] The LPT control unit 124 performs branch prediction for the conditional branch instruction indicated by the instruction fetch address based on the updated LPT 125, and outputs the prediction result (hit, true / fail) of the conditional branch instruction to the branch determination unit 127. A hit is set when branch prediction is valid and reset when branch prediction is invalid.

[0106] The LPT control unit 124 outputs information indicating that the conditional branch instruction is successful when the branch is successful (the program counter PC is changed to the jump destination) along with a hit. The LPT control unit 124 outputs information indicating that the conditional branch instruction is unsuccessful when the branch is not successful (the program counter PC is incremented by "1") along with a hit.

[0107] The LPT125 has multiple entries, each corresponding to a single conditional branch instruction. The lower bits of the program counter PC are assigned as indices to each entry, and each entry is identified by the lower bits of the program counter PC. For simplicity, only four entries are shown in Figure 7, but a number of entries corresponding to the number of lower bits is provided.

[0108] Each entry in LPT125 has a region that holds the valid flag VLD, tag TAG, confidence CONF, completion count value CMPT-CNT, loop count LP-NUM, and current count value CURR-CNT. The completion count value CMPT-CNT is an example of the current number of times the conditional branch instruction has been executed. The loop count LP-NUM is an example of the predicted number of consecutive times the conditional branch instruction has been executed. The current count value CURR-CNT is an example of the predicted number of remaining times the conditional branch instruction has been executed.

[0109] The valid flag VLD is set when an entry is valid and reset when an entry is invalid. Below, entries with the valid flag VLD set are also referred to as valid entries, and entries with the valid flag VLD reset are also referred to as invalid entries. The tag TAG indicates the upper bits of the program counter PC for the conditional branch instruction. Each conditional branch instruction is identified by the tag TAG and the index in LPT125.

[0110] Confidence CONF is a numerical value that indicates the accuracy of branch prediction. Entries with a Confidence CONF of 1 or higher than a predetermined accuracy (threshold) are used for branch prediction. Entries with a Confidence CONF below the predetermined accuracy and invalid entries are not used for branch prediction. The updating of Confidence CONF will be described later.

[0111] The completion count value CMPT-CNT is incremented each time a conditional branch instruction is completed when the conditional branch instruction is successfully executed consecutively. When predicting the number of consecutive failures, the completion count value CMPT-CNT is incremented each time a conditional branch instruction is successfully executed when the conditional branch instruction is successfully executed consecutively. Although not shown in the diagram, each entry in LPT125 has a usage flag that is set, for example, when counting the number of consecutive successful executions and reset when counting the number of consecutive failures. The LPT unit 123 then uses the entries with the usage flag set to predict the number of consecutive successful executions and uses the entries with the usage flag reset to predict the number of consecutive failures.

[0112] The loop count LP-NUM indicates the predicted number of consecutive successful executions and is updated based on the completion report of the conditional branch instruction. For example, if the loop count LP-NUM is "5", the LPT control unit 124 predicts that the next conditional branch instruction will be successful if the completion count value CMPT-CNT is between "1" and "4". The LPT control unit 124 predicts that the next conditional branch instruction will not be successful if the completion count value CMPT-CNT is "5".

[0113] When predicting the number of consecutive failures, the loop count LP-NUM of a valid entry indicates the predicted number of consecutive failures. For example, if the loop count LP-NUM is "5", the LPT control unit 124 predicts that the next conditional branch instruction will fail if the completion count CMPT-CNT is between "1" and "4". The LPT control unit 124 predicts that the next conditional branch instruction will succeed if the completion count CMPT-CNT is "5".

[0114] The current count value CURR-CNT is updated when a conditional branch instruction is fetched, when an instruction refetch request occurs, or when a repair request occurs. An example of the update process for the current count value CURR-CNT is explained in Figure 8. The current count value CURR-CNT indicates the predicted number of remaining successful executions. When predicting the number of consecutive unsuccessful executions, the current count value CURR-CNT indicates the predicted number of remaining unsuccessful executions.

[0115] When the LPT unit 123 receives a branch instruction completion report from the RSBR 30, along with a program counter PC that identifies a conditional branch instruction, it searches for an entry that matches the program counter PC. For example, the LPT unit 123 uses the lower bits of the program counter PC as an index and compares the upper bits of the program counter PC with the tag TAG of each entry.

[0116] The LPT control unit 124 performs an entry update process when it detects an entry that matches the program counter PC. If there is no entry that matches the program counter PC, the LPT control unit 124 determines that there is no entry for the corresponding conditional branch instruction and creates an entry. If there is an invalid entry or a replaceable entry, the LPT control unit 124 creates an entry based on the program counter PC included in the completion report. The LPT control unit 124 may also create an entry by overwriting the information of the conditional branch instruction that received the completion report for entries where the confidence CONF value is lower than a threshold.

[0117] When the LPT control unit 124 creates an entry, it overwrites the upper bits of the program counter PC of the conditional branch instruction to be created with the tag TAG of the created entry, and sets the completion count value CMPT-CNT to "1".

[0118] If the LPT control unit 124 receives a completion report from the RSBR 30 for a conditional branch instruction entry, it increments the completion count value CMPT-CNT of that entry by "1". If the LPT control unit 124 receives a completion report from the RSBR 30 for a conditional branch instruction entry, it copies the completion count value CMPT-CNT of that entry to the loop count LP-NUM and clears the completion count value CMPT-CNT to "0". This allows the LPT unit 123 to predict the number of consecutive completions using the loop count LP-NUM.

[0119] The LPT control unit 124 compares the completion count value CMPT-CNT with the loop count LP-NUM based on the failure completion report from RSBR30. If the count value CMPT-CNT is the same as the loop count LP-NUM, the LPT control unit 124 determines that the same loop pattern has occurred repeatedly and increments the confidence CONF by "1". Then, the LPT unit 123 removes entries where the confidence CONF is above a predetermined threshold (for example, "2") from the replacement target and uses them for branch prediction in conditional branch instructions.

[0120] Furthermore, when predicting the number of consecutive failures, the LPT control unit 124 increments the completion count value CMPT-CNT of an entry for a conditional branch instruction that has received a failure completion report from RSBR30 by "1". If the LPT control unit 124 has received a success completion report from RSBR30 for an entry for a conditional branch instruction, it copies the completion count value CMPT-CNT of that entry to the loop count LP-NUM and clears the completion count value CMPT-CNT to "0".

[0121] This allows the LPT unit 123 to predict the number of consecutive failures using the loop count LP-NUM. Additionally, when the RSBR 30 reports completion of a successful connection, the LPT control unit 124 determines that the same loop pattern has occurred repeatedly if the count value CMPT-CNT is the same as the loop count LP-NUM, and increments the confidence CONF by "1".

[0122] For example, the bimodal predictor 122 has a 2-bit saturation counter for each index. When the bimodal predictor 122 receives a completion report indicating that a conditional branch instruction has been fulfilled, it increments the saturation counter by "1", and when it receives a completion report indicating that a conditional branch instruction has not been fulfilled, it decrements the saturation counter by "1". The bimodal predictor 122 selects the saturation counter to be used for prediction using the lower bit of the instruction fetch address received from the instruction fetch address generation unit 10 as the index.

[0123] The bimodal predictor 122 predicts that the condition is met if the upper bit of the selected saturation counter is "1", and predicts that it is not met if the upper bit of the selected saturation counter is "0". The bimodal predictor 122 outputs the prediction result (met / not met) to the branch determination unit 127. Alternatively, a piecewise predictor or a TAGE (TAgged GEometric history length predictor) predictor with higher prediction accuracy than the bimodal predictor 122 may be provided.

[0124] The branch instruction information storage unit 126 has multiple entries, each holding a target address, a branch instruction flag, and a tag, respectively, and stores information on branch instructions that have been completed in the past. The branch instruction information storage unit 126 is updated based on branch instruction completion reports from the RSBR 30 and is searched based on instruction fetch addresses from the instruction fetch address generation unit 10.

[0125] The target address indicates the instruction fetch address to which the branch instruction will branch. The branch instruction flag indicates whether it is a conditional branch instruction or an unconditional branch instruction. The tag TAG indicates the upper bits of the program counter PC of the branch instruction.

[0126] If there is no entry corresponding to the program counter PC included in the completion report indicating the fulfillment of a conditional branch instruction, the branch instruction that received the completion report is registered in one of the entries. Furthermore, if the target address held in the entry is incorrect, or if the branch instruction flag is incorrect, the branch instruction information holding unit 126 overwrites the entry with the correct information.

[0127] The branch instruction information holding unit 126 searches for an entry based on the instruction fetch address from the instruction fetch address generation unit 10. The branch instruction information holding unit 126 determines a hit if there is an entry that holds the lower bits of the instruction fetch address as an index and the upper bits of the instruction fetch address as a tag TAG. The branch instruction information holding unit 126 then outputs the hit / miss information (hit) and the branch instruction flag to the branch determination unit 127 and outputs the target address to the instruction fetch address generation unit 10.

[0128] The branch determination unit 127 outputs the branch prediction result it ultimately determined as the branch prediction mechanism 12 to the instruction fetch address generation unit 10, based on the prediction result from the LPT unit 123, the prediction result from the bimodal predictor 122, and the information from the branch instruction information holding unit 126. The information from the branch instruction information holding unit 126 includes hit and branch instruction flags. For example, if the branch determination unit 127 receives the information hit and a branch instruction flag indicating an unconditional branch instruction from the branch instruction information holding unit 126, it outputs the branch prediction result indicating the establishment of a conditional branch instruction to the instruction fetch address generation unit 10.

[0129] When the branch determination unit 127 receives information hit and a branch instruction flag indicating a conditional branch instruction from the branch instruction information holding unit 126, it first refers to the prediction result from the LPT unit 123. If the prediction result from the LPT unit 123 indicates a hit and is successful, the branch determination unit 127 outputs a branch prediction result indicating the success of the conditional branch instruction to the instruction fetch address generation unit 10. If the prediction result from the LPT unit 123 indicates a hit and is not successful, the branch determination unit 127 outputs a branch prediction result indicating the failure of the conditional branch instruction to the instruction fetch address generation unit 10.

[0130] The branch determination unit 127 receives information hit and a branch instruction flag indicating a conditional branch instruction from the branch instruction information holding unit 126. If the prediction result from the LPT unit 123 is not a hit (miss), it adopts the prediction result from the bimodal predictor 122. The branch determination unit 127 then outputs the branch prediction result from the bimodal predictor 122, indicating whether the conditional branch instruction is fulfilled or not, to the instruction fetch address generation unit 10.

[0131] If the branch determination unit 127 does not receive an information hit from the branch instruction information holding unit 126 (miss), it determines whether the branch instruction or conditional branch instruction is not fulfilled and outputs information indicating the failure to the instruction fetch address generation unit 10. If the branch determination unit 127 receives an information hit and a branch instruction flag indicating an unconditional branch instruction from the branch instruction information holding unit 126, it outputs a branch prediction result indicating fulfillment to the instruction fetch address generation unit 10.

[0132] If the instruction fetch address generation unit 10 receives a branch prediction result indicating success from the branch determination unit 127, it sets the target address received from the branch instruction information holding unit 126 as the next instruction fetch address. If the instruction fetch address generation unit 10 receives a branch prediction result indicating failure from the branch determination unit 127, it sets the address generated by updating the current program counter PC as the next instruction fetch address. The amount by which the program counter PC is updated depends on the number of instructions to be fetched at one time. For example, if the instruction fetch address generation unit 10 fetches four instructions at one time, it advances the program counter PC by "4".

[0133] Figure 8 shows an example of the update operation of the current count value CURR-CNT of LPT125 in Figure 7. As described above, the current count value CURR-CNT is updated when a conditional branch instruction is fetched, when an instruction refetch request occurs, or when a repair request occurs.

[0134] In (A1), if the fetched conditional branch instruction hits any of the entries in LPT125 and the current count value CURR-CNT is not "0", LPT unit 123 decrements the current count value CURR-CNT by "1". For example, if the loop count LP-NUM is 5 times, LPT unit 123 decrements the loop count LP-NUM if the prediction of the conditional branch instruction being fulfilled is any of the 1st to 4th times. This allows branch prediction by LPT125 to continue.

[0135] In (A2), if a conditional branch instruction corresponding to the program counter PC included in the repair request hits any of the entries in LPT125, and the current count value CURR-CNT is not "0", LPT123 decrements the current count value CURR-CNT by "1". When a repair request hits an entry in LPT125, it indicates that there is a conditional branch instruction between TOQ and the entry that output the instruction refetch request that requires a decrement of the current count value CURR-CNT. Therefore, by decrementing the current count value CURR-CNT based on the determination in (A2), it is possible to suppress a decrease in the prediction accuracy of the predicted number of remaining fulfillments after the refetching of the conditional branch instruction.

[0136] In (B1), if the conditional branch instruction targeted by the instruction refetch request from the RSBR30's TOQ does not hit any of the entries in LPT125, the LPT unit 123 updates the current count value CURR-CNT of the conditional branch instruction present in the instruction loop of the target conditional branch instruction as follows: The LPT unit 123 sets the current count value CURR-CNT to the value obtained by subtracting the completion count value CMPT-CNT from the loop count LP-NUM.

[0137] In (B2), when an instruction refetch request is received from an entry other than TOQ in RSBR30, the LPT unit 123 sets the current count value CURR-CNT to the loop count LP-NUM minus the completion count value CMPT-CNT. This allows the current count value CURR-CNT to be updated in the same way as when an instruction refetch request is received from TOQ, even if the instruction refetch request is output out of order from an entry other than TOQ.

[0138] In (C1), if the LPT unit 123 receives a valid instruction refetch request from the RSBR 30 and hits one of the entries in the LPT 125, it sets the current count value CURR-CNT to the loop count LP-NUM minus the completion count value CMPT-CNT. Furthermore, the LPT unit 123 subtracts "1" from the current count value CURR-CNT.

[0139] For example, in the (C1) judgment, when the loop count LP-NUM is 5 and the completion count value CMPT-CNT is 0, the LPT unit 123 predicts that the instruction loop will not be executed and the instruction will be exited. However, in reality, the instruction is executed, and the prediction is wrong, the LPT unit 123 determines that the first execution of the instruction loop of the conditional branch instruction, which is repeated 5 times, has been executed. In this case, the predicted number of remaining executions is 4, so the current count value CURR-CNT is set to "4", which is "loop count LP-NUM" - "completion count value CMPT-CNT" - "1". In this way, the LPT unit 123 can set the current count value CURR-CNT to the predicted value after the conditional branch instruction has been executed once, similar to the normal operation of using LPT 125 to predict the remaining number of executions.

[0140] Furthermore, in the determination of (C1), conditional branch instructions held in LPT125 in entries where confidence CONF is lower than the threshold are predicted by the bimodal predictor 122, not the LPT unit 123. In this state, the information held in LPT125 predicts that the conditional branch instruction will be fulfilled, the bimodal predictor 122 predicts that it will not be fulfilled, and the bimodal predictor 122's prediction is incorrect. At this time, RSBR30 outputs an instruction refetch request (fulfilled) from the program counter PC when the condition is fulfilled.

[0141] For example, when the loop count LP-NUM is 5 and the completion count value CMPT-CNT is 3, the remaining number of completed branches (fulfilled) is 2, regardless of the current count value CURR-CNT. If the instruction refetch request (fulfilled) (C1) is output in this state, the LPT unit 123 sets the current count value CURR-CNT to "1", which is "loop count LP-NUM" - "completion count value CMPT-CNT" - "1". In this way, the LPT unit 123 can make the current count value CURR-CNT the predicted value after the conditional branch instruction has been fulfilled 3 times in a row, similar to the normal operation of predicting the remaining number of fulfilled conditions using LPT 125.

[0142] In (D1), if the fetched conditional branch instruction hits any of the entries in LPT125 and the current count value CURR-CNT is "0", LPT unit 123 sets the loop count LP-NUM to the current count value CURR-CNT. For example, in the determination in (D1), if the loop count LP-NUM is 5 and the prediction of fulfilling the conditional branch instruction hits 5 times in a row, and the current count value CURR-CNT becomes "0", LPT unit 123 resets the loop count LP-NUM to 5. This allows branch prediction by LPT125 to continue.

[0143] In (D2), the LPT unit 123 sets the loop count LP-NUM to the current count CURR-CNT if a conditional branch instruction corresponding to the program counter PC included in the repair request hits any entry in LPT 125 and the current count value CURR-CNT is "0". In the determination in (D2), similar to (A2) above, if a repair request hits an entry in LPT 125, it indicates that there is a conditional branch instruction between TOQ and the entry that output the instruction refetch request that requires a decrement of the current count value CURR-CNT. Therefore, by setting the loop count LP-NUM to the current count value CURR-CNT based on the determination in (D2), it is possible to suppress the decrease in the prediction accuracy of the remaining number of fulfilled conditions after the conditional branch instruction has been refetched.

[0144] In (D3), if the LPT unit 123 receives an instruction refetch request from RSBR 30 indicating failure and hits one of the entries in LPT 125, it sets the loop count LP-NUM to the current count value CURR-CNT.

[0145] For example, in the (D3) judgment, when the loop count LP-NUM is 5 and the completion count value CMPT-CNT is 3, regardless of the current count value CURR-CNT, the remaining number of completed branches (fulfilled) is 2. If the branch prediction is wrong (actually not fulfilled) when the fulfillment of a conditional branch instruction is predicted in this state, the LPT unit 123 determines that a new instruction loop is starting and resets the loop count LP-NUM to 5. This allows the branch prediction by LPT 125 to be restarted.

[0146] Furthermore, in the determination of (D3), the bimodal predictor 122 predicts that the condition is met when the LPT unit 123 is collecting information on whether the condition is met or not for entries with a low confidence value CONF. Then, the bimodal predictor 122's prediction is wrong, and an instruction refetch request is output. For example, when the loop count LP-NUM is 5 and the completion count value CMPT-CNT is 0, regardless of the current count value CURR-CNT, the remaining number of completed branches (met) is 5. Therefore, the LPT unit 123 determines that a new instruction loop is starting and resets the loop count LP-NUM to 5. This is the same as the branch prediction operation in (D1) using the entry of LPT 125.

[0147] Figures 9 and 10 show an example of the operation of the RSBR 30, LPT unit 123, and instruction fetch address generation unit 10 in Figure 7. In other words, Figures 9 and 10 show an example of the arithmetic processing method of the arithmetic processing unit 102. The operations shown in Figures 9 and 10 are performed repeatedly.

[0148] The RSBR30, LPT unit 123, and instruction fetch address generation unit 10 correspond to the branch instruction issuance scheduler 3, branch prediction unit 5, and address generation unit 1 shown in Figure 1. Furthermore, the completion count value CMPT-CNT, loop count LP-NUM, and current count value CURR-CNT correspond to the current execution count, the predicted value of consecutive execution counts, and the predicted value of remaining execution counts, respectively, as explained in the embodiments shown in Figures 1 to 4.

[0149] Therefore, the operations described in Figures 1 to 4 are also applicable to the operations of the arithmetic processing unit 102 in Figure 5. For example, the explanation of the instruction refetch request output by the branch instruction issuing scheduler 3 in Figure 3 is also applicable to the explanation of the RSBR 30. The operation of the branch instruction issuing scheduler when the instruction loop is processed in Figure 4 is also applicable to the operation of the RSBR 30.

[0150] RSBR30 determines whether a branch prediction error has occurred for each entry in the branch instruction completion queue 301. RSBR30 sets the prediction result flag of the entry in which a branch prediction error has occurred to "1", indicating that a branch prediction error has occurred. If no branch prediction error has been detected, RSBR30 continues the normal completion process of the branch instruction.

[0151] First, in step S10, the RSBR30 repeatedly checks whether there is an entry in the branch instruction completion queue 301 that has a branch prediction error (the prediction result flag is set). If there is an entry with a branch prediction error, the RSBR30 performs step S12. In step S12, if the branch prediction error occurred in TOQ, the RSBR30 performs step S14, and if the branch prediction error occurred in an entry other than TOQ, it performs step S18.

[0152] In step S14, the RSBR 30 invalidates the information held in all entries except TOQ and outputs an instruction refetch request for the conditional branch instruction held in TOQ. Next, in step S16, the LPT unit 123 updates the current LPT count value CURR-CNT according to the algorithm shown in Figure 8, based on the instruction refetch request LPT unit output from the RSBR 30. The instruction fetch address generation unit 10 resumes instruction fetching based on the instruction refetch request output from the RSBR 30. After the operation of step S16, step S10 is performed.

[0153] In step S18, the RSBR 30 searches for entries in the branch instruction completion queue 301 with the prediction result flag set, and confirms the entry with the closest branch prediction miss to the TOQ. The RSBR 30 invalidates the information held in entries after the confirmed entry and outputs an instruction refetch request for the conditional branch instruction held in the confirmed entry.

[0154] Next, in step S20, the RSBR 30 sets a repair trigger that suppresses the re-fetching of conditional branch instructions by the instruction fetch address generation unit 10. The RSBR 30 also sets the entry number determined in step S18 to the repair end pointer 304 and sets the value of the output pointer OUTP to the repair pointer 303. The repair end pointer 304 and the repair pointer 303 are used in the operation shown in Figure 10.

[0155] Next, in step S22, the LPT unit 123 updates the current LPT count value CURR-CNT according to the algorithm shown in Figure 8, based on the instruction refetch request LPT output from the RSBR 30. In this case, since it corresponds to "an instruction refetch request was received from a source other than TOQ" in Figure 8, the LPT unit 123 sets the current count value CURR-CNT to the value obtained by subtracting the completion count value CMPT-CNT from the loop count LP-NUM. The instruction fetch address generation unit 10 receives the instruction refetch request, but does not resume instruction fetching because the repair trigger is set, and waits for the repair trigger to be reset.

[0156] Next, in step S24 of Figure 10, the RSBR 30 outputs the conditional branch instruction flag and the program counter PC held in the entry indicated by the repair pointer to the LPT unit 123, and increments the repair pointer 303.

[0157] Next, in step S26, the LPT unit 123 updates the current LPT count value CURR-CNT according to the algorithm shown in Figure 8, based on the instruction refetch request LPT unit output from the RSBR 30.

[0158] Next, in step S28, if the repair pointer 303 exceeds the repair end pointer 304, the RSBR 30 determines that the update of the current count value CURR-CNT corresponding to the entry to be repaired is complete and executes step S30. On the other hand, if the repair pointer 303 does not exceed the repair end pointer 304, the RSBR 30 returns to step S24 in order to continue updating the current count value CURR-CNT corresponding to the entry to be repaired.

[0159] In step S30, the RSBR 30 resets the repair trigger because it has completed updating the current count value CURR-CNT corresponding to the entry to be repaired. Next, in step S32, the instruction fetch address generation unit 10 resumes instruction fetching in response to the instruction refetch request based on the reset of the repair trigger. After this, the operation returns to step S10 in Figure 9.

[0160] As described above, the same effects as those of the embodiments described can be obtained in this embodiment as well. For example, even when an instruction refetch request is output out of order from an entry other than TOQ, the current count value CURR-CNT, which is the predicted value of the remaining number of times an incomplete conditional branch instruction is fulfilled, can be updated to an appropriate value. Therefore, it is possible to suppress a decrease in the prediction accuracy of the predicted value of the remaining number of times a conditional branch instruction in the instruction loop is fulfilled. As a result, the processing efficiency of the pipeline can be improved, and the processing performance of the arithmetic processing unit 102 can be improved.

[0161] Furthermore, in this embodiment, by suppressing instruction refetching while the repair trigger is set, it is possible to prevent instruction refetching from starting before the repair process is complete and updating the entry in LPT125, thereby preventing malfunction of LPT125.

[0162] Figure 11 shows an example of an information processing system including the arithmetic processing unit 100 of Figure 1 or the arithmetic processing unit 102 of Figure 5. Figure 11 shows an example in which the arithmetic processing unit 100 is installed in the information processing system.

[0163] For example, the information processing system shown in Figure 11 is a server 200. The server 200 has multiple arithmetic processing units 100, multiple main memory units 210, and an interconnect control unit 220. For example, the arithmetic processing unit 100 is a processor such as a central processing unit (CPU) and is connected to the interconnect control unit 220. Each main memory unit 210 is connected to the corresponding arithmetic processing unit 100. The interconnect control unit 220 is connected to an external device such as a hard disk drive or a communication device and performs input / output control to the external device.

[0164] The following additional information is disclosed regarding the embodiments described above. (Note 1) An arithmetic processing unit that executes instructions by pipeline processing, It has a prediction holding unit that holds prediction information including a predicted value for the number of consecutive executions of each conditional branch instruction, the current number of executions of each conditional branch instruction, and a predicted value for the remaining number of executions of each conditional branch instruction, and a branch prediction unit that predicts the number of consecutive executions of each conditional branch instruction based on the predicted value, An address generation unit generates the fetch address of the next instruction based on the prediction result from the branch prediction unit or the address included in the instruction refetch request, A branch instruction issuance scheduler has a branch instruction completion queue that sequentially holds branch instructions fetched based on the fetch address, completes branch instructions held in the branch instruction completion queue in order, outputs a request for the instruction re-fetch if the branch prediction unit determines a branch prediction error based on the execution result of a conditional branch instruction, and outputs a repair request to the branch prediction unit corresponding to the conditional branch instructions held between the position where the branch prediction error was determined and the beginning of the branch instruction completion queue if a branch prediction error is determined for a conditional branch instruction held anywhere other than the beginning of the branch instruction completion queue. The branch prediction unit sets the predicted value of the remaining number of successful executions to the difference between the predicted value of the consecutive number of successful executions and the current number of successful executions, based on the instruction refetch request from a source other than the head of the branch instruction completion queue, and further subtracts the number of conditional branch instructions corresponding to the repair request from the predicted value of the remaining number of successful executions. Processing unit. (Note 2) If multiple conditional branch instructions that have been determined to have a branch prediction error exist in the branch instruction completion queue, the branch instruction issuance scheduler outputs a request for the instruction refetch for the conditional branch instruction that has been determined to have a branch prediction error closest to the beginning of the branch instruction completion queue, and invalidates branch instructions held after the conditional branch instruction that has been determined to have a branch prediction error in the branch instruction completion queue. The arithmetic processing unit described in Appendix 1. (Note 3) After the branch instruction issuance scheduler outputs the repair request to the branch prediction unit, it suppresses the generation of the fetch address by the address generation unit while the predicted value of the remaining number of executions is updated based on the repair request. The arithmetic processing unit described in Appendix 1 or Appendix 2. (Note 4) The prediction and holding unit further holds a predicted value for the number of consecutive failures of each conditional branch instruction, the current number of failures of each conditional branch instruction, and a predicted value for the remaining number of failures of each conditional branch instruction, thereby enabling the prediction of the number of consecutive failures of each conditional branch instruction. The branch prediction unit sets the predicted number of remaining failures to the difference between the predicted number of consecutive failures and the current number of failures, based on the instruction refetch request from a branch instruction completion queue other than the head of the queue, and further subtracts the number of conditional branch instructions corresponding to the repair request from the predicted number of remaining failures. The arithmetic processing unit described in Appendix 1 or Appendix 2. (Note 5) The branch prediction unit, when it receives the repair request, subtracts the predicted value of the remaining number of successful executions if the predicted value of the remaining number of successful executions is not "0", and sets the predicted value of the consecutive number of successful executions to the predicted value of the remaining number of successful executions if the predicted value of the remaining number of successful executions is "0" when it receives the repair request. The arithmetic processing unit described in Appendix 1 or Appendix 2. (Note 6) The branch prediction unit decrements the predicted value of the remaining number of executions if the predicted value of the remaining number of executions is not "0" when an instruction is fetched using the fetch address generated by the address generation unit, and sets the predicted value of consecutive executions to the predicted value of the remaining number of executions if the predicted value of the remaining number of executions is "0" when an instruction is fetched using the fetch address generated by the address generation unit. The arithmetic processing unit described in Appendix 1 or Appendix 2. (Note 7) If the branch prediction unit does not hold prediction information for the conditional branch instruction corresponding to the instruction refetch request output in response to the conditional branch instruction held at the head of the branch instruction completion queue, it sets the remaining prediction value for the number of successful branches to be the predicted value obtained by subtracting the number of successful branches from the predicted value for the number of consecutive successful branches. The arithmetic processing unit described in Appendix 1 or Appendix 2. (Note 8) The branch prediction unit, when it receives an instruction refetch request due to a branch prediction error resulting in a failed branch for a conditional branch instruction held at the head of the branch instruction completion queue, and the prediction holding unit holds the prediction information for the outputted conditional branch instruction, sets the remaining predicted number of successful branches to a value obtained by subtracting "1" from the value obtained by subtracting the current number of successful branches from the predicted number of successful branches. The arithmetic processing unit described in Appendix 1 or Appendix 2. (Note 9) An arithmetic processing method for an arithmetic processing unit having a branch prediction unit, an address generation unit, and a branch instruction issuance scheduler, which executes instructions by pipeline processing, The branch prediction unit has a prediction holding unit that holds prediction information including a predicted value for the number of consecutive executions of each conditional branch instruction, the current number of executions of each conditional branch instruction, and a predicted value for the remaining number of executions of each conditional branch instruction, and predicts the number of consecutive executions of each conditional branch instruction based on the prediction values. The address generation unit generates the fetch address of the next instruction based on the prediction result by the branch prediction unit or the address included in the instruction refetch request. The branch instruction issuance scheduler has a branch instruction completion queue that sequentially holds branch instructions fetched based on the fetch address, completes the branch instructions held in the branch instruction completion queue in order, outputs a request for instruction re-fetching if the branch prediction unit determines a branch prediction error based on the execution result of a conditional branch instruction, and if it determines a branch prediction error for a conditional branch instruction held anywhere other than the beginning of the branch instruction completion queue, outputs a repair request to the branch prediction unit corresponding to the conditional branch instructions held between the position where the branch prediction error was determined and the beginning of the branch instruction completion queue. The branch prediction unit sets the predicted value of the remaining number of successful executions to the difference between the predicted value of the consecutive number of successful executions and the current number of successful executions, based on the instruction refetch request from a source other than the head of the branch instruction completion queue, and further subtracts the number of conditional branch instructions corresponding to the repair request from the predicted value of the remaining number of successful executions. Calculation processing method.

[0165] The features and advantages of the embodiments will become clear from the detailed description above. This is intended to be so as not to deviate from the spirit and scope of the claims, that the features and advantages of the embodiments described above are included. Furthermore, any improvement and modification should be readily conceivable to a person with ordinary skill in the art. Therefore, there is no intention to limit the scope of inventive embodiments to those described above, and it is also possible to rely on appropriate improvements and equivalents that fall within the scope disclosed in the embodiments. [Explanation of Symbols]

[0166] 1. Address generation unit 2 memory 3. Branch Instruction Issuance Scheduler 4 Branch instruction completion queue 5. Branch prediction section 6. Prediction Holding Unit 10 Instruction fetch address generation unit 12 Branch Prediction Mechanism 121 Branch prediction section 122 bimodal predictors 123 LPT section 124 LPT Control Unit 125 LPT 126 Branch instruction information holding unit 127 Branch determination unit 14. Primary Instruction Cache 16. Secondary cache 18. Instruction Buffer Section 20 Instruction Decode Unit 22 Register Renaming Department 30 RSBR 301 Branch instruction completion queue 302 Branch Control Unit 303 Repair Pointer 304 Repair End Pointer 34. Commitment Control Unit 36 Program Counter 38 Operand Address Generation Unit 40 Primary Data Cache 42, 44 Arithmetic unit 46 Fixed-point update buffer 48 Floating-point update buffer 50 fixed-point registers 52 floating-point registers 100, 102 Arithmetic Processing Units CMPT-CNT completion count value CONF Confidence CURR-CNT Current Count Value LP-NUM Loop count RS Reservation Station TAG VLD Valid Flag

Claims

1. An arithmetic processing unit that executes instructions by pipeline processing, It has a prediction holding unit that holds prediction information including a predicted value for the number of consecutive executions of each conditional branch instruction, the current number of executions of each conditional branch instruction, and a predicted value for the remaining number of executions of each conditional branch instruction, and a branch prediction unit that predicts the number of consecutive executions of each conditional branch instruction based on the predicted value, An address generation unit generates the fetch address of the next instruction based on the prediction result from the branch prediction unit or the address included in the instruction refetch request, A branch instruction issuance scheduler has a branch instruction completion queue that sequentially holds branch instructions fetched based on the fetch address, completes branch instructions held in the branch instruction completion queue in order, outputs a request for the instruction re-fetch if the branch prediction unit determines a branch prediction error based on the execution result of a conditional branch instruction, and outputs a repair request to the branch prediction unit corresponding to the conditional branch instructions held between the position where the branch prediction error was determined and the beginning of the branch instruction completion queue if a branch prediction error is determined for a conditional branch instruction held anywhere other than the beginning of the branch instruction completion queue. The branch prediction unit sets the predicted value of the remaining number of successful executions to the difference between the predicted value of the consecutive number of successful executions and the current number of successful executions, based on the instruction refetch request from a source other than the head of the branch instruction completion queue, and further subtracts the number of conditional branch instructions corresponding to the repair request from the predicted value of the remaining number of successful executions. Processing unit.

2. If multiple conditional branch instructions that have been determined to have a branch prediction error exist in the branch instruction completion queue, the branch instruction issuance scheduler outputs a request for the instruction refetch for the conditional branch instruction that has been determined to have a branch prediction error closest to the beginning of the branch instruction completion queue, and invalidates branch instructions held after the conditional branch instruction that has been determined to have a branch prediction error in the branch instruction completion queue. The arithmetic processing device according to claim 1.

3. After the branch instruction issuance scheduler outputs the repair request to the branch prediction unit, it suppresses the generation of the fetch address by the address generation unit while the predicted value of the remaining number of executions is updated based on the repair request. The arithmetic processing device according to claim 1 or claim 2.

4. The prediction and holding unit further holds a predicted value for the number of consecutive failures of each conditional branch instruction, the current number of failures of each conditional branch instruction, and a predicted value for the remaining number of failures of each conditional branch instruction, thereby enabling the prediction of the number of consecutive failures of each conditional branch instruction. The branch prediction unit sets the predicted number of remaining failures to the difference between the predicted number of consecutive failures and the current number of failures, based on the instruction refetch request from a branch instruction completion queue other than the head of the queue, and further subtracts the number of conditional branch instructions corresponding to the repair request from the predicted number of remaining failures. The arithmetic processing device according to claim 1 or claim 2.

5. The branch prediction unit, when it receives the repair request, subtracts the predicted value of the remaining number of successful executions if the predicted value of the remaining number of successful executions is not "0", and sets the predicted value of consecutive successful executions to the predicted value of the remaining number of successful executions if the predicted value of the remaining number of successful executions is "0" when it receives the repair request. The arithmetic processing device according to claim 1 or claim 2.

6. An arithmetic processing method for an arithmetic processing unit having a branch prediction unit, an address generation unit, and a branch instruction issuance scheduler, which executes instructions by pipeline processing, The branch prediction unit has a prediction holding unit that holds prediction information including a predicted value for the number of consecutive executions of each conditional branch instruction, the current number of executions of each conditional branch instruction, and a predicted value for the remaining number of executions of each conditional branch instruction, and predicts the number of consecutive executions of each conditional branch instruction based on the prediction values. The address generation unit generates the fetch address of the next instruction based on the prediction result by the branch prediction unit or the address included in the instruction refetch request. The branch instruction issuance scheduler has a branch instruction completion queue that sequentially holds branch instructions fetched based on the fetch address, completes the branch instructions held in the branch instruction completion queue in order, outputs a request for instruction re-fetching if the branch prediction unit determines a branch prediction error based on the execution result of a conditional branch instruction, and if it determines a branch prediction error for a conditional branch instruction held anywhere other than the beginning of the branch instruction completion queue, outputs a repair request to the branch prediction unit corresponding to the conditional branch instructions held between the position where the branch prediction error was determined and the beginning of the branch instruction completion queue. The branch prediction unit sets the predicted value of the remaining number of successful executions to the difference between the predicted value of the consecutive number of successful executions and the current number of successful executions, based on the instruction refetch request from a source other than the head of the branch instruction completion queue, and further subtracts the number of conditional branch instructions corresponding to the repair request from the predicted value of the remaining number of successful executions. Calculation processing method.

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