Switching power supply

Abstract

To provide a switching power source device capable of stably charging a boosting capacitor.SOLUTION: In a switching power source device 1, a high side switch 2 and a low side switch 3 of an N channel MOSFET generate an output voltage VOUT from an input voltage VIN. An LDO 9 generates a power source for driving the switches by charging a boosting capacitor 11. An off time generation unit 17 brings the gate voltage of the switch 2 to a high level when a divided voltage signal FB becomes lower than a target voltage VREF. A Ton calculation unit 12 has a current source circuit in which the value of a constant current is controlled in accordance with the input voltage VIN, and brings the gate voltage of the high side switch to a low level according to a comparison result of a terminal voltage of the capacitor charged with the constant current with a voltage obtained by multiplying the output voltage by α. An RS latch 14 keeps the gate voltage at a high level in a state where the off time generation unit is outputting a signal for bringing the gate voltage to the high level.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0001] The present invention relates to a switching power supply device that generates an output voltage obtained by switching and transforming an input voltage using a switching element.

Background Art

[0002] In a step-down DCDC converter, which is a type of switching power supply device, when the input voltage Vin drops near the output voltage VOUT, in order to suppress the drop in the output voltage as much as possible, it is desirable to drive the high-side switch by increasing the duty ratio of the PWM signal as much as possible.

[0003] On the other hand, when an N-channel MOSFET is used for the high-side switch and its gate drive voltage is generated by a bootstrap circuit, in order to charge the capacitor of the bootstrap circuit, it is necessary to periodically lower the source potential of the high-side FET to a low level, that is, turn off the high-side FET. If the charging of the bootstrap capacitor, that is, the boost capacitor, cannot be performed periodically, the voltage required to drive the high-side FET cannot be obtained and the half-on state will occur.

[0004] To address the above problems, a technique is generally used in which, when the input voltage drops, the high-side FET is operated at a constant high duty ratio to minimize the drop in the output voltage while periodically charging the boost capacitor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In COT (Constant On Time) control, a control method used in switching power supplies, the output voltage is controlled by fixing the ON time and determining the OFF time through feedback control. As a result, the ON / OFF timing of the switch is not determined at a constant cycle, making it difficult to stably charge the boost capacitor. Furthermore, when the output voltage drops, the ON time is shortened, which presents a challenge in obtaining a sufficiently high duty cycle.

[0007] The present invention has been made in view of the above circumstances, and its objective is to provide a switching power supply that can stably charge a boost capacitor even when an N-channel MOSFET is used as the high-side switch. [Means for solving the problem]

[0008] According to the switching power supply device of claim 1, an output voltage is generated by switching the input voltage using a high-side switch which is at least an N-channel MOSFET. The bootstrap circuit has a boost capacitor, one end of which is connected to the low-potential conductive terminal of the high-side switch, and generates a drive power supply to drive the high-side switch.

[0009] The off-time generation unit raises the gate voltage of the high-side switch to a high level when the voltage divider signal of the output voltage falls below the target voltage. The on-time calculation unit has a current source circuit whose constant current value is adjusted depending on the input voltage, and lowers the gate voltage of the high-side switch to a low level according to the result of comparing the terminal voltage of the capacitor charged by the constant current with the voltage obtained by gain-multiplying the output voltage. The high-level priority unit raises the gate voltage to a high level preferentially when the off-time generation unit is outputting a signal that raises the gate voltage to a high level.

[0010] With this configuration, even if the off-time generation unit controls the gate voltage of the high-side switch to a high level and the on-time calculation unit controls the gate voltage to a low level, the gate voltage will remain at a high level due to the high-level priority unit. Therefore, the boost capacitor of the bootstrap circuit can be charged for a longer period of time.

[0011] Also, Claim 1 According to the switching power supply described, the low-level setting unit forces the gate voltage to a low level when the time the gate voltage remains at a high level exceeds a threshold. As a result, even if the time the gate voltage remains at a high level increases due to a decrease in the input voltage, the low-level setting unit can reliably charge the boost capacitor by turning off the high-side switch. [Brief explanation of the drawing]

[0012] [Figure 1] This is a diagram showing the configuration of a switching power supply, representing the first embodiment. [Figure 2] Diagram showing the configuration of the Ton time generation circuit. [Figure 3] Circuit diagram showing the detailed configuration of the ON time counter. [Figure 4] Timing chart showing the operation of the ON time counter. [Figure 5] This diagram shows a PWM signal output when the input voltage VIN is higher than the output voltage VOUT. [Figure 6] This diagram shows the PWM signal output when the input voltage VIN gradually decreases from a state where it is higher than the output voltage VOUT. [Figure 7] A magnified view of a portion of Figure 6. [Figure 8] This is a second embodiment, and the diagram shows the configuration of the switching power supply. [Figure 9] This is a third embodiment, and is a circuit diagram showing the detailed configuration of the ON time counter. [Figure 10] Timing chart showing the operation of the ON time counter. [Figure 11] Embodiment 4, a diagram showing the configuration of a switching power supply device [Figure 12] Circuit diagram showing the detailed configuration of the voltage detection unit between BT and SW [Figure 13] Timing chart showing the operation of the voltage detection unit between BT and SW [Figure 14] Diagram showing another configuration example of the power stage

Mode for Carrying Out the Invention

[0013] (First Embodiment) Hereinafter, the first embodiment will be described. The switching power supply device 1 of the present embodiment shown in FIG. 1 is a step-down switching power supply by COT control. A series circuit of a high-side switch 2 and a low-side switch 3, both of which are N-channel MOSFETs, is connected between the power supply VIN and the ground. A series circuit of an inductor 4 and a capacitor 5 is connected between the common connection point of the switches 2 and 3 and the ground.

[0014] Gate drive signals are applied to the gates of the high-side switch 2 and the low-side switch 3 via a driver 6 and an inverter driver 7, respectively. The output terminal of an AND gate 8 is connected to the input terminals of the drivers 6 and 7, and a PWM (Pulse Width Modulation) signal is input from the output terminal.

[0015] An LDO (Low Drop Out) 9 boosts the input voltage VIN to generate a drive power supply for the drivers 6 and 7 and supplies it to them. The output terminal of the LDO 9 is directly connected to the power supply terminal of the driver 7 and is also connected to the power supply terminal of the driver 6 via a diode 10. A boosting capacitor 11 is connected between the cathode of the diode 10 and the common connection point of the switches 2 and 3. The source, which is the low-potential side conduction terminal of the high-side switch 2, is connected to the above common connection point. The LDO 9 and the boosting capacitor 11 correspond to a bootstrap circuit.

[0016] The Ton calculation unit 12 receives the input voltage VIN, the output voltage VOUT, and the duty cycle control signal D via the NOT gate 13. Based on these input signals, the Ton calculation unit 12 generates a reset signal R for the RS latch 14 and outputs it to the reset terminal R.

[0017] A series circuit of resistors 15a and 15b is connected to capacitor 5. The common connection point of resistors 15a and 15b is connected to the non-inverting input terminal of comparator 16. A reference voltage or target voltage VREF is applied to the inverting input terminal of comparator 16, and the output terminal of comparator 16 is connected to the set terminal S of RS latch 14. The resistors 15 and comparator 16 constitute the off-time generation unit 17.

[0018] The RS latch 14 generates the duty cycle control signal D from its output terminal Q and outputs it to one of the input terminals of the AND gate 8. The input terminal of the ON time counter 18 is connected to the common connection point of switches 2 and 3, and its output terminal is connected to the other input terminal of the AND gate 8. The RS latch 14 is a latch that, when a set signal and a reset signal are input simultaneously, prioritizes the set signal and raises the output terminal Q to a high level, and corresponds to the high-level priority section.

[0019] As shown in Figure 2, the Ton calculation unit 12 consists of a series circuit of a current source circuit 21 and a capacitor 22 connected between the power supply VIN and ground, a comparator circuit 24 to which an α multiple of the output voltage VOUT is input at the inverting input terminal, and the non-inverting input terminal is connected to the common connection point of the current source circuit 21 and the capacitor 22, and also connected to ground via a switch circuit 23. The current source circuit 21 supplies a constant current I (=G × VIN) proportional to the input voltage VIN.

[0020] The switch circuit 23 is turned ON by signal DB, which is the inverse of the duty cycle control signal D. The off-time generation unit 17 sets the RS flip-flop 14 according to the result of comparing the voltage FB, obtained by dividing the output voltage VOUT, with the reference voltage VREF, thereby raising the duty cycle control signal D to a high level. Ton is the time that signal D remains at a high level and is determined by constant current charging of capacitor 22. If the capacitance of capacitor 22 is C, Ton = (VOUT × C) / (G × VIN) Therefore, time Ton is inversely proportional to the input voltage VIN.

[0021] The ON time counter 18, which corresponds to the low-level setting section, is a counter that counts the time the high-side switch 2 remains in the ON state. As shown in Figure 3, the ON time counter 18 includes eight D flip-flops 25a to 25h connected in series, a buffer 26, a selector 27, and a NOT gate 28. The inverted output terminal of each D flip-flop 25 is connected to its respective input terminal D.

[0022] The clock signal CLK is input from the CLK generation circuit 19 to the clock terminal of the first-stage D flip-flop 25a and the "1" side of the selector 27. If the voltage at the common connection point of switches 2 and 3 is denoted as SW, the voltage SW is input to the "0" side of the selector 27 via the buffer 26. The output terminal of the selector 27 is connected to the negative logic reset terminal R of each D flip-flop 25. The switching control of the "1" and "0" of the selector 27 is performed by the non-inverting output of the final-stage D flip-flop 25h. The non-inverting output terminal of the D flip-flop 25h is also supplied to the input terminal of the AND gate 8 via the NOT gate 28.

[0023] As shown in Figure 4, the output signal MAXon of the NOT gate 28 is at a high level until the pulse count of the clock signal CLK reaches "8". When the count reaches "8", the signal MAXon changes to a low level for half a cycle of the clock signal CLK.

[0024] Next, the operation of this embodiment will be described. As shown in Figure 5, when the voltage FB falls below the reference voltage VREF, the RS latch 14 is set and the PWM signal rises. At the same time, the switch circuit 23 of the Ton calculation unit 12 turns OFF, and the capacitor 22 is charged with a constant current I. When the terminal voltage of the capacitor 22 reaches α times the output voltage VOUT, the output signal of the comparator 24 changes from a low level to a high level, and the RS latch 14 is reset. The time from when the RS latch 14 is set until it is reset is the time Ton. This is normal COT control.

[0025] On the other hand, as shown in Figures 6 and 7, as the input voltage VIN gradually decreases from a state where it is higher than the output voltage VOUT, the on-time of the high-side switch 2 gradually increases to prevent the output voltage VOUT from decreasing accordingly. When the input voltage VIN becomes lower than the output voltage VOUT, the on-time becomes even longer, which may lead to the depletion of the charge in the boost capacitor 11.

[0026] In this embodiment, the ON time counter 18 monitors the voltage SW to measure the time that the high-side switch 2 remains in the ON state. When this time reaches a threshold corresponding to the number of clock pulses "8", the signal MAXon is set to a low level, forcibly turning the high-side switch 2 OFF via the AND gate 8. At this timing, the boost capacitor 11 is charged.

[0027] As described above, according to this embodiment, the switching power supply 1 generates a stepped-down output voltage VOUT by switching the input voltage VIN using the high-side switch 2 and low-side switch 3, which are N-channel MOSFETs. The LDO 9 generates a drive power supply to drive switches 2 and 3 by charging the boost capacitor 11.

[0028] The off-time generation unit 17 raises the gate voltage of the high-side switch 2 when the voltage divider signal FB falls below the target voltage VREF. The Ton calculation unit 12 has a current source circuit 21 in which the value of the constant current I is adjusted depending on the input voltage VIN, and lowers the gate voltage of the high-side switch 2 according to the result of comparing the terminal voltage of the capacitor 22 charged by the constant current I with a voltage obtained by multiplying the output voltage by α. The RS latch 14 preferentially raises the gate voltage when the off-time generation unit 17 is outputting a signal that raises the gate voltage.

[0029] With this configuration, even if the off-time generation unit 17 controls the gate voltage of the high-side switch 2 to a high level and the Ton calculation unit 12 controls the gate voltage to a low level, the gate voltage will remain at a high level due to the RS latch 14. Therefore, even in COT control, the boost capacitor 11 can be charged for a longer period of time.

[0030] The ON time counter 18 then forces the gate voltage of the high-side switch 2 to a low level when the time during which the gate voltage of the high-side switch 2 is at a high level exceeds a threshold. This ensures that even if the time during which the gate voltage is at a high level increases due to a decrease in the input voltage VIN, the Ton calculation unit 12 can reliably charge the boost capacitor 11 by turning off the high-side switch 2.

[0031] (Second Embodiment) In the following description, parts identical to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted, while the differences are described. As shown in Figure 8, the only difference between the switching power supply 1A of the second embodiment and the second embodiment is that the input terminal of the ON time counter 18 is connected to the gate of the high-side switch 2 instead of the common connection point of switches 2 and 3.

[0032] (Third embodiment) As shown in Figure 9, the third embodiment uses an ON time counter 30 instead of the ON time counter 18. The ON time counter 30 has a similar configuration to the Ton calculation unit 12, and consists of a series circuit of a current source circuit 31 and a capacitor 32 connected between the power supply VDD and ground, a comparator 34 to which a reference voltage is input at the non-inverting input terminal and which is connected to the common connection point of the current source circuit 31 and the capacitor 32, and also connected to ground via a switch circuit 33. The ON / OFF state of the switch circuit 33 is controlled by a NOT gate 13, similar to the Ton calculation unit 12.

[0033] As shown in Figure 10, the ON time counter 30 operates by having the comparator 34 compare the terminal voltage Vcount of capacitor 32 with a reference voltage. When the former level exceeds the latter level, the signal MAXon is lowered to a low level. This turns off the high-side switch 2 and charges the boost capacitor 11.

[0034] (Fourth Embodiment) As shown in Figure 11, the switching power supply 41 of the fourth embodiment uses a BT-SW voltage detection unit 42 instead of an ON time counter 18. The BT-SW voltage detection unit 42 is connected between the cathode BT of the diode 10 and the source SW of the high-side switch 2. The power supply for driving the inverting driver 7 is also supplied from the cathode of the diode 10.

[0035] As shown in Figure 12, the BT-SW voltage detection unit 42 includes a series circuit of resistors 43a and 43b connected between terminals BT and SW, an N-channel MOSFET 44, a series circuit of resistors 45a and 45b, and a buffer 46. The gate of the FET 44 is connected to the common connection point of resistors 43a and 43b. The input terminal of the NOT gate 46 is connected to the common connection point of resistors 45a and 45b. The output terminal of the NOT gate 46 is connected to the input terminal of the AND gate 8.

[0036] As shown in Figure 13, in the BT-SW voltage detection unit 42, if the BT-SW voltage is high and the gate voltage of FET 44 exceeds the threshold, FET 44 is ON, and the signal BT-POR output via buffer 46 shows a high level. When the BT-SW voltage drops and the gate voltage of FET 44 falls below the threshold, FET 44 turns OFF. As a result, the signal BT-POR changes to a low level.

[0037] (Other embodiments) Figure 14 shows another configuration example for the power stage that performs switching, in which diode 47 is placed in place of the low-side switch 3. The count of the Ton time calculation unit 18 is not limited to "8". This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of Symbols]

[0038] In the diagram, 1 is a switching power supply, 2 is a high-side switch, 3 is a low-side switch, 8 is an AND gate, 9 is an LDO, 11 is a boost capacitor, 12 is a Ton calculation unit, 14 is an RS latch, 17 is an off-time generation unit, 18 is an ON-time counter, 21 is a current source circuit, 23 is a switch circuit, and 24 is a comparator.

Claims

1. The high-side switch (2), which is at least an N-channel MOSFET, switches the input voltage to generate a transformed output voltage. A bootstrap circuit (9) has a boost capacitor (11) at one end connected to the low-potential conductive terminal of the high-side switch, which generates a drive power supply to drive the high-side switch, An off-time generation unit (17) that raises the gate voltage of the high-side switch to a high level when the voltage divider signal of the output voltage falls below the target voltage, The circuit includes a current source circuit (21) whose constant current value is adjusted depending on the input voltage, and an on-time calculation unit (12) which lowers the gate voltage of the high-side switch to a low level according to the result of comparing the terminal voltage of a capacitor (22) charged by the constant current with a voltage obtained by gain multiplying the output voltage, When the off-time generation unit outputs a signal that raises the gate voltage to a high level, the high-level priority unit (14) prioritizes raising the gate voltage to a high level, A switching power supply device comprising: low-level setting units (18, 30, 42) that forcibly lower the gate voltage to a low level when the time during which the gate voltage is at a high level exceeds a threshold.

2. The switching power supply device according to claim 1, wherein the low-level setting unit (18) is equipped with a counter for measuring the time during which the gate voltage is at a high level.

3. The low-level setting unit (30) includes a ramp wave signal generation unit that generates a ramp wave signal by combining a current source (31), a capacitor (32) charged by the current from the current source, and a discharge switching element (33) that discharges the capacitor during the period when the gate voltage is at a low level. The switching power supply device according to claim 1, further comprising a comparison circuit (34) for comparing the ramp wave signal with a reference voltage.

4. The switching power supply device according to claim 1, wherein the low-level setting unit (42) includes a voltage detection unit (43) for detecting the terminal voltage of the boost capacitor, and when the terminal voltage falls below a threshold, the gate voltage is forcibly set to a low level.

5. The on-time calculation unit (12) includes a ramp wave signal generation unit that generates a ramp wave signal by combining the current source circuit and a discharge switching element (23) that discharges the capacitor during the period when the gate voltage is at a low level, A switching power supply device according to any one of claims 1 to 4, further comprising a comparison circuit (24) for comparing the output voltage and the ramp wave signal.

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