Manufacturing method for semiconductor devices

Abstract

To provide a technique of suppressing collapse of a charge balance between an n-type column and a p-type column in a semiconductor device with a super junction structure.SOLUTION: A manufacturing method for a semiconductor device 1 including a semiconductor layer 10 with a super junction structure in which n-type columns 14a and p-type columns 14b are alternately disposed repeatedly in at least one direction includes a step of forming the super junction structure on the basis of pattern displacement expressing displacement, from a design pattern, of shielding layers 52, 54, 62, and 64 that are formed on a surface of the semiconductor layer and are open corresponding to a formation range of at least one of the n-type column and the p-type column.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

Background Art

[0002] As a structure that achieves both low on-resistance and high breakdown voltage, a super junction structure in which n-type columns and p-type columns are alternately and repeatedly arranged along at least one direction has been proposed. Patent Documents 1 to 3 disclose an example of a semiconductor device having such a super junction structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to further improve the compatibility between low on-resistance and high breakdown voltage, it is necessary to increase the impurity concentration of each of the n-type columns and p-type columns constituting the super junction structure. When the impurity concentration of each of the n-type columns and p-type columns increases, for example, it becomes difficult to form the n-type columns and p-type columns by counter-doping p-type impurity ions in the n-type semiconductor layer. This is because a large amount of p-type impurity ions must be ion-implanted into the high-concentration n-type semiconductor layer, and problems such as defects occur. Therefore, in order to manufacture a semiconductor device that highly achieves both low on-resistance and high breakdown voltage, each of the n-type columns and p-type columns must be formed by ion implantation.

[0005] <00000...When forming n-type and p-type columns by ion implantation, there is a need for a technique that can control the impurity concentration and / or position of each n-type and p-type column to suppress the disruption of the charge balance between the n-type and p-type columns. This specification provides a technique for suppressing the disruption of the charge balance between n-type and p-type columns in a semiconductor device equipped with a superjunction structure. [Means for solving the problem]

[0006] This specification can disclose a method for manufacturing a semiconductor device (1) comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction. This manufacturing method may include a step of forming the superjunction structure based on a pattern deviation indicating a deviation from the design pattern of a shielding layer (52, 54, 62, 66) which is deposited on the surface of the semiconductor layer and opens corresponding to the formation range of at least one of the n-type columns and the p-type columns. Here, the pattern deviation is not particularly limited, but may be, for example, a dimensional deviation of the opening width of the shielding layer or an alignment deviation of the shielding layer. According to this manufacturing method, the superjunction structure can be formed by feedback control based on the pattern deviation of the shielding layer, so that the imbalance in the charge balance of the first column and the second column is suppressed. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic cross-sectional view of the main parts of the semiconductor device of the embodiment disclosed herein is shown. [Figure 2] Figure 1 shows the flow chart of the process for forming a superjunction structure, which is part of the first manufacturing method for producing the semiconductor device shown in Figure 1. [Figure 3] Figure 1 schematically shows a cross-sectional view of a key part in the first manufacturing method for producing the semiconductor device shown in Figure 1. [Figure 4]Figure 1 schematically shows a cross-sectional view of a key part in the first manufacturing method for producing the semiconductor device shown in Figure 1. [Figure 5] Figure 1 schematically shows a cross-sectional view of a key part in the first manufacturing method for producing the semiconductor device shown in Figure 1. [Figure 6] Figure 1 shows a flowchart of the process for forming a superjunction structure, which is a modified example of the first manufacturing method for producing the semiconductor device shown in Figure 1. [Figure 7] Figure 1 shows the flow chart of the process for forming a superjunction structure, which is part of the second manufacturing method for producing the semiconductor device shown in Figure 1. [Figure 8] A schematic cross-sectional view of a key part in the second manufacturing method for producing the semiconductor device shown in Figure 1 is shown. [Figure 9] A schematic cross-sectional view of a key part in the second manufacturing method for producing the semiconductor device shown in Figure 1 is shown. [Figure 10] A schematic cross-sectional view of a key part in the second manufacturing method for producing the semiconductor device shown in Figure 1 is shown. [Figure 11] A schematic cross-sectional view of a key part in the second manufacturing method for producing the semiconductor device shown in Figure 1 is shown. [Figure 12] Figure 1 shows the flowchart for the process of forming a superjunction structure, which is one of the third manufacturing methods for producing the semiconductor device shown in Figure 1. [Modes for carrying out the invention]

[0008] The semiconductor devices disclosed herein will be described below with reference to the drawings. For the purpose of clarity in the illustrations, only one of the repeatedly arranged components will be given a reference numeral.

[0009] Figure 1 schematically shows a cross-sectional view of the main part of the semiconductor device 1. The semiconductor device 1 is a type of power semiconductor device called a MOSFET, and comprises a semiconductor layer 10, a drain electrode 22 covering the lower surface of the semiconductor layer 10, a source electrode 24 covering the upper surface of the semiconductor layer 10, and a plurality of trench gates 30 provided in the upper part of the semiconductor layer 10.

[0010] The semiconductor layer 10 is not particularly limited, and for example, it may be a 4H silicon carbide layer. The crystal plane on the upper surface of the semiconductor layer 10 may be inclined by an off-angle with respect to the (0001) Si plane. The off-angle is not particularly limited, and for example, it may be 4°. Instead of the silicon carbide layer, the semiconductor layer 10 may be a silicon layer, a nitride semiconductor layer, or a gallium oxide layer. The semiconductor layer 10 is n + -type drain region 12, an n-type drift region 14, a p-type body region 16, and n + -type source region 18, and p + -type body contact region 19.

[0011] The drain region 12 is disposed in the lower layer portion of the semiconductor layer 10 and is provided at a position exposed on the lower surface of the semiconductor layer 10. The drain region 12 is in ohmic contact with a drain electrode 22 that coats the lower surface of the semiconductor layer 10.

[0012] The drift region 14 is provided between the drain region 12 and the body region 16 and has a plurality of n-type columns 14a and a plurality of p-type columns 14b. The n-type columns 14a and the p-type columns 14b are arranged to alternately repeat along at least one direction in the cross section of the semiconductor layer 10, constituting a superjunction structure. The direction in which the n-type columns 14a and the p-type columns 14b alternately repeat in the cross section of the semiconductor layer 10 is hereinafter referred to as the "repetition direction". The plurality of n-type columns 14a and the plurality of p-type columns 14b are not particularly limited, and for example, they may be arranged in a stripe shape when viewed from a direction orthogonal to the upper surface of the semiconductor layer 10 (hereinafter referred to as "when viewed in plan view").

[0013] When the drift region 14 is depleted, the n-type columns 14a are positively charged and the p-type columns 14b are negatively charged. When the charge amount of the positive charge of the n-type column 14a and the charge amount of the negative charge of the p-type column 14b are balanced, the drift region 14 is depleted well, and the breakdown voltage of the semiconductor device 1 is improved. In the semiconductor device 1, it is designed so that charge balance is achieved between the n-type columns 14a and the p-type columns 14b.

[0014] The body region 16 is provided on the drift region 14 and is disposed in the upper portion of the semiconductor layer 10. The body region 16 is provided between the n-type column 14a of the drift region 14 and the source region 18, is in contact with both the n-type column 14a and the source region 18, and separates the n-type column 14a and the source region 18. The carrier concentration of the p-type impurities in the body region 16 is adjusted according to a desired gate threshold voltage.

[0015] The source region 18 is provided on the body region 16, is disposed in the upper portion of the semiconductor layer 10, and is provided at a position exposed on the surface of the semiconductor layer 10. The source region 18 is in contact with the side surface of the trench gate 30. The source region 18 makes an ohmic contact with the source electrode 24 that coats the surface of the semiconductor layer 10.

[0016] The body contact region 19 is provided on the body region 16, is disposed in the upper portion of the semiconductor layer 10, and is provided at a position exposed on the surface of the semiconductor layer 10. The body contact region 19 makes an ohmic contact with the source electrode 24 that coats the surface of the semiconductor layer 10.

[0017] The trench gate 30 is filled in a trench formed in the upper part of the semiconductor layer 10, and penetrates the source region 18 and the body region 16 to reach the n-type column 14a of the drift region 14. In this example, the trench gate 30 extends along the longitudinal direction of the n-type column 14a and the p-type column 14b when the semiconductor layer 10 is viewed from above. Alternatively, the trench gate 30 may extend along the repeating direction of the n-type column 14a and the p-type column 14b, i.e., in a direction perpendicular to the longitudinal direction of the n-type column 14a and the p-type column 14b, when the semiconductor layer 10 is viewed from above. The trench gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is formed of polysilicon containing impurities and faces the semiconductor layer 10 via the gate insulating film 34. In particular, the gate electrode 32 faces the body region 16 of the drift region 14, which separates the n-type column 14a and the source region 18, via the gate insulating film 34. The gate insulating film 34 is made of silicon oxide and covers the inner wall of the trench.

[0018] Next, the operation of the semiconductor device 1 will be explained with reference to Figure 1. When the potential of the drain electrode 22 is positive compared to the potential of the source electrode 24, and the potential of the gate electrode 32 of the trench gate 30 is positive compared to the source electrode 24 and controlled to be higher than a threshold, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the body region 16 that separates the source region 18 and the n-type column 14a of the drift region 14. Electrons supplied from the source region 18 reach the n-type column 14a of the drift region 14 via the channel of the inversion layer. Electrons that reach the n-type column 14a flow through the n-type column 14a to the drain region 12. Since the n-type column 14a has a high carrier concentration of n-type impurities, the semiconductor device 1 can have the characteristic of low on-resistance.

[0019] When the potential of the gate electrode 32 of the trench gate 30 is controlled to be the same as the potential of the source electrode 24, the channel in the inversion layer disappears, and the semiconductor device 1 turns off. The multiple n-type columns 14a and multiple p-type columns 14b constituting the superjunction structure are substantially completely depleted, and a wide area of ​​the drift region 14 is depleted. Furthermore, because the drift region 14 has a superjunction structure, the electric field distribution of the drift region 14 is leveled in the thickness direction. As a result, the drift region 14 can bear a large potential difference, and the semiconductor device 1 can have the characteristic of high breakdown voltage.

[0020] (First method for manufacturing a semiconductor device) Next, with reference to Figures 2 to 5, the step of forming the superjunction structure, which is part of the first manufacturing method of the semiconductor device 1, will be described. For the other steps for manufacturing the semiconductor device 1, known manufacturing techniques can be used.

[0021] First, as shown in Figure 3, n + A drain region 12, which is a silicon carbide substrate of type n, is prepared. Next, an n-type epitaxial layer 140 of silicon carbide is grown from the surface of the drain region 12 using an epitaxial growth technique such as CVD (Chemical Vapor Deposition), although this technique is not particularly limited. The epitaxial layer 140 constitutes at least a part of the semiconductor layer 10 and is sometimes referred to as the semiconductor layer.

[0022] Next, as shown in Figure 4, a shielding layer 52 for the n-type column is deposited on the epitaxial layer 140 using photolithography (i.e., step S1 in Figure 2). The shielding layer 52 for the n-type column is patterned to have openings corresponding to the formation area of ​​the n-type column 14a.

[0023] Next, the opening width 52W of the n-type column shielding layer 52 is measured (i.e., step S2 in Figure 2). The opening width 52W of the n-type column shielding layer 52 is the width of the opening of the n-type column shielding layer 52 in the short-side direction, and is the width in the repeating direction of the superjunction structure.

[0024] Next, using ion implantation technology, n-type impurity ions are implanted into the epitaxial layer 140 through the opening in the n-type column shielding layer 52 to form the n-type column 14a (i.e., step S3 in Figure 2). The n-type impurity ions are not particularly limited, but for example, nitrogen ions may be used. Here, the conditions for implanting the n-type impurity ions are set based on the measured opening width 52W of the n-type column shielding layer 52. If the measured opening width 52W is narrower than the opening width of the design pattern, the ion implantation process for n-type impurity ions is carried out under conditions where the amount of n-type impurity ions implanted is greater than the design condition (i.e., the baseline condition). Conversely, if the measured opening width 52W is wider than the opening width of the design pattern, the n-type impurity ion implantation process is carried out under conditions where the amount of n-type impurity ions implanted is less than the design condition. In this way, by feedback-controlling the amount of n-type impurity ions implanted based on the pattern shift of the aperture width 52W of the n-type column shielding layer 52, the concentration of n-type impurities in the n-type column 14a can be set to a desired value. The set amount of n-type impurity ions implanted may be adjusted continuously or in multiple stages based on the aperture width 52W. After ion implantation, the n-type column shielding layer 52 is removed.

[0025] Next, as shown in Figure 5, a p-type column shielding layer 54 is deposited on the epitaxial layer 140 using photolithography (i.e., step S4 in Figure 2). The p-type column shielding layer 54 is patterned to have openings corresponding to the formation area of ​​the p-type column 14b.

[0026] Next, the opening width 54W of the p-type column shielding layer 54 is measured (i.e., step S5 in Figure 2). The opening width 54W of the p-type column shielding layer 54 is the width of the opening of the p-type column shielding layer 54 in the short-side direction, and is the width in the repeating direction of the superjunction structure.

[0027] Next, using ion implantation technology, p-type impurity ions are implanted into the epitaxial layer 140 through the opening of the p-type column shielding layer 54 to form the p-type column 14b (i.e., step S6 in Figure 2). The p-type impurity ions are not particularly limited, but for example, aluminum ions may be used. Here, the conditions for implanting the p-type impurity ions are set based on the measured opening width 54W of the p-type column shielding layer 54. If the measured opening width 54W is narrower than the opening width of the design pattern, the ion implantation process for p-type impurity ions is carried out under conditions where the amount of p-type impurity ions implanted is greater than the design condition (i.e., the reference condition). Conversely, if the measured opening width 54W is wider than the opening width of the design pattern, the p-type impurity ion implantation process is carried out under conditions where the amount of p-type impurity ions implanted is less than the design condition. In this way, by feedback-controlling the amount of p-type impurity ions implanted based on the pattern shift of the aperture width 54W of the p-type column shielding layer 54, the concentration of p-type impurities in the p-type column 14b can be set to a desired value. The set amount of p-type impurity ions implanted may be adjusted continuously or in multiple stages based on the aperture width 54W. After ion implantation, the p-type column shielding layer 54 is removed.

[0028] Through these processes, a superjunction structure can be formed in which n-type columns 14a and p-type columns 14b are alternately and repeatedly arranged within the semiconductor layer 10. According to the above manufacturing method, the impurity concentrations of the n-type columns 14a and p-type columns 14b are adjusted to desired values ​​by feedback control. Therefore, when the semiconductor device 1 is turned off, the amount of positive charge in the n-type columns 14a and the amount of negative charge in the p-type columns 14b are balanced, and the drift region 14 is well depleted. As a result, the semiconductor device 1 can have high breakdown voltage characteristics.

[0029] (Modified example of the first method for manufacturing a semiconductor device) The above manufacturing method is an example in which one ion implantation step is performed for each of the n-type column 14a and the p-type column 14b, and the amount of impurity ions implanted in the ion implantation step is adjusted. Alternatively, the first ion implantation step may be performed under predetermined conditions, and additional ion implantation steps may be performed only if additional ion implantation is necessary. The manufacturing flow for this example is shown in Figure 6. In the manufacturing flow of Figure 6, steps common to both Figure 2 and Figure 2 are denoted by the same reference numerals.

[0030] As shown in Figure 6, steps S1 and S2 are the same as the manufacturing flow in Figure 2. Next, n-type impurity ions are implanted into the epitaxial layer 140 through the opening of the shielding layer 52 for the n-type column using ion implantation technology (i.e., step S11 in Figure 6). The conditions for implanting the n-type impurity ions are predetermined conditions. Here, the predetermined conditions are those in which the amount of n-type impurity ions implanted is set to be less than the desired n-type impurity concentration in the n-type column 14a.

[0031] Next, based on the measured opening width 52W of the n-type column shielding layer 52, it is determined whether additional ion implantation is necessary (i.e., step S12 in Figure 6). In this determination step, if the n-type impurity concentration of the n-type column 14a, estimated from the measured opening width 52W of the n-type column shielding layer 52 and the predetermined conditions of the first ion implantation step, is below the permissible concentration, it is determined that additional ion implantation is necessary. If it is determined that additional ion implantation is necessary, n-type impurity ions are implanted into the epitaxial layer 140 through the opening of the n-type column shielding layer 52 to form the n-type column 14a (i.e., step S13 in Figure 6). The amount of n-type impurity ions to be implanted additionally may be predetermined. If it is not determined that additional ion implantation is necessary, this ion implantation step is skipped. In this way, by feedback-controlling the number of times n-type impurity ions are implanted based on the pattern shift of the opening width 52W of the n-type column shielding layer 52, the concentration of n-type impurities in the n-type column 14a can be set to a desired value. After ion implantation, the n-type column shielding layer 52 is removed.

[0032] As shown in Figure 6, steps S4 and S5 are the same as in the manufacturing flow of Figure 2. Next, p-type impurity ions are implanted into the epitaxial layer 140 through the opening of the shielding layer 54 for the p-type column using ion implantation technology (i.e., step S14 in Figure 6). The conditions for implanting the p-type impurity ions are predetermined conditions. Here, the predetermined conditions are those in which the amount of p-type impurity ions implanted is set to be less than the desired concentration of p-type impurities in the p-type column 14b.

[0033] Next, based on the measured opening width 54W of the p-type column shielding layer 54, it is determined whether additional ion implantation is necessary (i.e., step S15 in Figure 6). In this determination step, if the p-type impurity concentration of the p-type column 14b, estimated from the measured opening width 54W of the p-type column shielding layer 54 and the predetermined conditions of the first ion implantation step, is below the permissible concentration, it is determined that additional ion implantation is necessary. If it is determined that additional ion implantation is necessary, p-type impurity ions are implanted into the epitaxial layer 140 through the opening of the p-type column shielding layer 54 to form the p-type column 14b (i.e., step S16 in Figure 6). The amount of p-type impurity ions to be implanted additionally may be predetermined. If it is not determined that additional ion implantation is necessary, this ion implantation step is skipped. In this way, by feedback-controlling the number of p-type impurity ion implantations based on the pattern shift of the opening width 54W of the p-type column shielding layer 54, the concentration of p-type impurities in the p-type column 14b can be set to a desired value. After ion implantation, the p-type column shielding layer 54 is removed.

[0034] Through these processes, a superjunction structure can be formed in which n-type columns 14a and p-type columns 14b are alternately and repeatedly arranged within the semiconductor layer 10. In the above manufacturing method, the impurity concentrations of the n-type columns 14a and p-type columns 14b are adjusted to desired values ​​by feedback control, and the semiconductor device 1 can have high voltage resistance characteristics.

[0035] (Second method for manufacturing a semiconductor device) The first manufacturing method described above is an example in which the ion implantation process is performed using one shielding layer for each of the n-type column 14a and the p-type column 14b. Alternatively, the ion implantation process may be performed using two shielding layers for each of the n-type column 14a and the p-type column 14b. Referring to Figures 7 to 11, the process of forming the superjunction structure in the second manufacturing method of the semiconductor device 1 will be described. Note that components common to the first manufacturing method are denoted by the same reference numerals, and their descriptions are omitted.

[0036] First, as shown in Figure 8, a shielding layer 62 for the n-type column is deposited on the epitaxial layer 140 using photolithography (i.e., step S21 in Figure 7). The shielding layer 62 for the n-type column is patterned to have openings corresponding to the formation area of ​​the n-type column 14a.

[0037] Next, the opening width 62W of the n-type column shielding layer 62 is measured (i.e., step S22 in Figure 7). The opening width 62W of the n-type column shielding layer 62 is the width of the opening of the n-type column shielding layer 62 in the short-side direction, and is the width in the repeating direction of the superjunction structure.

[0038] Next, using ion implantation technology, n-type impurity ions are implanted into the epitaxial layer 140 through the opening in the n-type column shielding layer 62 (i.e., step S23 in Figure 7). The conditions for implanting the n-type impurity ions are predetermined conditions. Here, the predetermined conditions are those in which the amount of n-type impurity ions implanted is set to a concentration lower than the desired n-type impurity concentration in the n-type column 14a. After ion implantation, the n-type column shielding layer 62 is removed.

[0039] Next, as shown in Figure 9, a p-type column shielding layer 64 is deposited on the epitaxial layer 140 using photolithography (i.e., step S24 in Figure 7). The p-type column shielding layer 64 is patterned to have openings corresponding to the formation area of ​​the p-type column 14b.

[0040] Next, the opening width 64W of the p-type column shielding layer 64 is measured (i.e., step S25 in Figure 7). The opening width 64W of the p-type column shielding layer 64 is the width of the opening of the p-type column shielding layer 64 in the short-side direction, and is the width in the repeating direction of the superjunction structure.

[0041] Next, using ion implantation technology, p-type impurity ions are implanted into the epitaxial layer 140 through the opening in the p-type column shielding layer 64 (i.e., step S26 in Figure 7). The conditions for implanting the p-type impurity ions are predetermined conditions. Here, the predetermined conditions are those in which the amount of p-type impurity ions implanted is set to a concentration lower than the desired p-type impurity concentration in the p-type column 14b. After ion implantation, the p-type column shielding layer 64 is removed.

[0042] Next, based on the opening width 62W of the n-type column shielding layer 62 measured in step S22, it is determined whether additional ion implantation is necessary (i.e., step S27 in Figure 7). In this determination step, if the n-type impurity concentration of the n-type column 14a, estimated from the measured opening width 62W of the n-type column shielding layer 62 and the predetermined conditions of the first ion implantation step, is below the permissible concentration, it is determined that additional ion implantation is necessary.

[0043] As shown in Figure 10, if additional ion implantation is deemed necessary, an additional n-type column shielding layer 66 is deposited on the epitaxial layer 140 using photolithography (i.e., step S28 in Figure 7). The additional n-type column shielding layer 66 is patterned to open in a portion of the inside of the formation area of ​​the n-type column 14a. This ensures that the opening of the additional n-type column shielding layer 66 overlaps with the region where n-type impurity ions were implanted in the first ion implantation step, even if pattern misalignment occurs. Here, several types of photomasks are available for exposing the additional n-type column shielding layer 66, and are appropriately selected according to the measured opening width 62W of the n-type column shielding layer 62 (see Figure 8), i.e., according to the amount of n-type impurity ions implanted in the first ion implantation step. For example, if the measured aperture width 62W of the n-type column shielding layer 62 is wider than the design value, the amount of n-type impurity ions implanted in the first ion implantation step is greater than the design value. Therefore, a photomask with an aperture width 66W narrower than the design value is selected for exposing the additional n-type column shielding layer 66. Conversely, if the measured aperture width 62W of the n-type column shielding layer 62 is narrower than the design value, the amount of n-type impurity ions implanted in the first ion implantation step is less than the design value. Therefore, a photomask with an aperture width 66W wider than the design value is selected for exposing the additional n-type column shielding layer 66.

[0044] Next, using ion implantation technology, n-type impurity ions are implanted into the epitaxial layer 140 through the opening of the additional shielding layer 66 for the n-type column to form the n-type column 14a (i.e., step S29 in Figure 7). The conditions for implanting the n-type impurity ions may be predetermined conditions. In this way, by feedback-controlling the opening width 66W of the additional shielding layer 66 for the n-type column to be deposited based on the pattern misalignment of the opening width 62W of the shielding layer 62 for the n-type column, the concentration of n-type impurities in the n-type column 14a can be set to a desired value. After ion implantation, the additional shielding layer 66 for the n-type column is removed. If it is determined that additional ion implantation is not necessary, these additional ion implantation steps are skipped.

[0045] Next, based on the aperture width 64W of the p-type column shielding layer 64 measured in step S25, it is determined whether additional ion implantation is necessary (i.e., step S30 in Figure 7). In this determination step, if the p-type impurity concentration of the p-type column 14b, estimated from the measured aperture width 64W of the p-type column shielding layer 64 and the predetermined conditions of the first ion implantation step, is below the permissible concentration, it is determined that additional ion implantation is necessary.

[0046] As shown in Figure 11, if it is determined that additional ion implantation is necessary, an additional p-type column shielding layer 68 is deposited on the epitaxial layer 140 using photolithography (i.e., step S31 in Figure 7). The additional p-type column shielding layer 68 is patterned to open in a portion of the inside of the formation range of the p-type column 14b. This ensures that the opening of the additional p-type column shielding layer 68 overlaps with the region where p-type impurity ions were implanted in the first ion implantation step, even if pattern misalignment occurs. Here, several types of photomasks are available for exposing the additional p-type column shielding layer 68, and are appropriately selected according to the measured opening width 64W of the p-type column shielding layer 64 (see Figure 8), i.e., according to the amount of p-type impurity ions implanted in the first ion implantation step. For example, if the measured aperture width 64W of the p-type column shielding layer 64 is wider than the design value, the amount of p-type impurity ions implanted in the first ion implantation step is greater than the design value. Therefore, a photomask with an aperture width 68W narrower than the design value is selected for exposing the additional p-type column shielding layer 68. Conversely, if the measured aperture width 64W of the p-type column shielding layer 64 is narrower than the design value, the amount of p-type impurity ions implanted in the first ion implantation step is less than the design value. Therefore, a photomask with an aperture width 68W wider than the design value is selected for exposing the additional p-type column shielding layer 68.

[0047] Next, using ion implantation technology, p-type impurity ions are implanted into the epitaxial layer 140 through the opening of the additional p-type column shielding layer 68 to form the p-type column 14b (i.e., step S32 in Figure 7). The conditions for implanting the p-type impurity ions may be predetermined conditions. In this way, by feedback-controlling the opening width 68W of the additional p-type column shielding layer 68 to be deposited based on the pattern misalignment of the opening width 64W of the p-type column shielding layer 64, the concentration of p-type impurities in the p-type column 14b can be set to a desired value. After ion implantation, the additional p-type column shielding layer 68 is removed. If it is determined that additional ion implantation is not necessary, these additional ion implantation steps are skipped.

[0048] Through these processes, a superjunction structure can be formed in which n-type columns 14a and p-type columns 14b are alternately and repeatedly arranged within the semiconductor layer 10. In the above manufacturing method, the impurity concentrations of the n-type columns 14a and p-type columns 14b are adjusted to desired values ​​by feedback control, and the semiconductor device 1 can have high voltage resistance characteristics.

[0049] Furthermore, the above manufacturing method allows for individual treatment of each chip within the wafer. The aperture width of the shielding layer for the first ion implantation can be measured for each chip, and the aperture width of the shielding layer for the second ion implantation can be feedback-controlled for each chip. For chips where a second ion implantation is not deemed necessary, the second ion implantation can be skipped by not exposing the shielding layer for the corresponding chip in the shielding layer for the second ion implantation. In this way, the above manufacturing method allows for individual treatment of each chip within the wafer, making it possible to optimize the impurity concentrations of the n-type column 14a and p-type column 14b for each chip.

[0050] (Third method for manufacturing a semiconductor device) The first and second manufacturing methods described above are examples of feedback control of the ion implantation process based on the pattern misalignment of the opening width of the shielding layer for ion implantation. Alternatively, the ion implantation process may be feedback controlled based on the alignment misalignment of the shielding layer for ion implantation. Referring to the manufacturing flow in Figure 12, the step of forming the superjunction structure in the third manufacturing method of the semiconductor device 1 will be described. Cross-sectional views are omitted here, but the cross-sectional views used to explain the third manufacturing method are similar to those for the first manufacturing method, for example.

[0051] First, a shielding layer for the n-type column is deposited on the epitaxial layer using photolithography (i.e., step S41 in Figure 12). The shielding layer for the n-type column is patterned to have openings corresponding to the formation area of ​​the n-type column.

[0052] Next, the alignment misalignment of the shielding layer for the n-type column is measured (i.e., step S42 in Figure 12). Alignment misalignment refers to the positional deviation from the design position in relation to the alignment marks. The alignment misalignment is not particularly limited, but may be described in a coordinate system defined with respect to the alignment marks, for example. For example, if an XY Cartesian coordinate system is defined with respect to the alignment marks, the alignment mark misalignment is described in terms of two component positional deviations in the X and Y directions.

[0053] Next, using ion implantation technology, n-type impurity ions are implanted into the epitaxial layer through the opening in the shielding layer for the n-type column to form an n-type column (i.e., step S43 in Figure 12). The conditions for implanting the n-type impurity ions may be predetermined conditions. After ion implantation, the shielding layer for the n-type column is removed.

[0054] Next, a p-type column shielding layer is deposited on the epitaxial layer using photolithography (i.e., step S44 in Figure 12). Here, the p-type column shielding layer is deposited so that a similar alignment misalignment occurs based on the measured alignment misalignment of the n-type column shielding layer.

[0055] Next, the alignment misalignment of the p-type column shielding layer is measured, and it is determined whether or not it matches the alignment misalignment of the n-type column shielding layer (i.e., step S45 in Figure 12). Here, "matching" does not only mean that the alignment misalignments are perfectly matched, but also that the difference between the alignment misalignment of the p-type column shielding layer and the n-type column shielding layer is within an acceptable range.

[0056] If the alignment misalignment of the p-type column shielding layer matches that of the n-type column shielding layer, ion implantation technology is used to implant p-type impurity ions into the epitaxial layer through the openings in the p-type column shielding layer to form a p-type column (i.e., step S46 in Figure 12). The conditions for implanting the p-type impurity ions may be predetermined conditions. Since the alignment misalignment of the p-type column shielding layer matches that of the n-type column shielding layer, the relative positional relationship between the formed n-type and p-type columns will be close to the design pattern. In this way, by feedback-controlling the pattern of the p-type column shielding layer based on the alignment misalignment of the n-type column shielding layer, the relative positional relationship between the n-type and p-type columns can be made to the desired state. If the alignment misalignment of the n-type column shielding layer does not match that of the n-type column shielding layer, the p-type column shielding layer may be removed and the film deposition process for the p-type column shielding layer may be repeated.

[0057] Furthermore, the process of feeding back the alignment misalignment of the shielding layer may be performed together with the process of feeding back the aperture width of the shielding layer. Alternatively, the shielding layer for the p-type column may be deposited first, and the pattern of the shielding layer for the n-type column may be feedback-controlled based on the alignment misalignment of the shielding layer for the p-type column.

[0058] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0059] (Feature 1) A method for manufacturing a semiconductor device (1) comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, A method for manufacturing a semiconductor device, comprising the step of forming the superjunction structure based on a pattern deviation indicating a deviation from the design pattern of a shielding layer (52, 54, 62, 64) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of at least one of the n-type columns and the p-type columns.

[0060] (Feature 2) The process of forming the superjunction structure is as follows: A step of forming the n-type column based on the pattern misalignment of the n-type column shielding layer (52, 62) that opens up in a manner corresponding to the formation range of the n-type column, A method for manufacturing a semiconductor device according to feature 1, comprising the step of forming the p-type column based on the pattern misalignment of the p-type column shielding layer (54, 64) that opens in a manner corresponding to the formation range of the p-type column.

[0061] (Feature 3) The step of forming the n-type column based on the pattern misalignment of the shielding layer for the n-type column is: The steps include measuring the opening width (52W) of the shielding layer for the n-type column, A method for manufacturing a semiconductor device according to feature 2, comprising the step of forming an n-type column by implanting n-type impurity ions into the semiconductor layer through an opening in the n-type column shielding layer, wherein the amount of n-type impurity ions implanted is adjusted according to the measured opening width.

[0062] (Feature 4) The step of forming the p-type column based on the pattern misalignment of the shielding layer for the p-type column is: The steps include measuring the opening width (54W) of the shielding layer for the p-type column, A method for manufacturing a semiconductor device according to feature 2 or 3, comprising the step of forming a p-type column by implanting p-type impurity ions into the semiconductor layer through an opening in the p-type column shielding layer, wherein the amount of p-type impurity ions implanted is adjusted according to a measured opening width.

[0063] (Feature 5) The step of forming the n-type column based on the pattern misalignment of the shielding layer for the n-type column is: The steps include measuring the opening width (52W) of the shielding layer for the n-type column, A step of implanting n-type impurity ions into the semiconductor layer through an opening in the shielding layer for the n-type column, wherein the n-type impurity ions are implanted according to predetermined conditions. A method for manufacturing a semiconductor device according to feature 2, comprising the steps of: determining whether or not to implant additional n-type impurity ions according to the measured aperture width; and, if it is determined that additional implantation is necessary, implanting additional n-type impurity ions into the semiconductor layer through the opening of the n-type column shielding layer to form the n-type column.

[0064] (Feature 6) The step of forming the p-type column based on the pattern misalignment of the shielding layer for the p-type column is: The steps include measuring the opening width (54W) of the shielding layer for the p-type column, A step of implanting p-type impurity ions into the semiconductor layer through an opening in the shielding layer for the p-type column, wherein the p-type impurity ions are implanted according to predetermined conditions. A method for manufacturing a semiconductor device according to feature 2 or 6, comprising the steps of: determining whether or not to implant additional p-type impurity ions according to the measured aperture width; and, if it is determined that additional implantation is necessary, implanting additional p-type impurity ions into the semiconductor layer through the opening of the p-type column shielding layer to form the p-type column.

[0065] (Feature 7) The step of forming the n-type column based on the pattern misalignment of the shielding layer for the n-type column is: The steps include measuring the opening width (62W) of the shielding layer for the n-type column, The steps include: implanting n-type impurity ions into the semiconductor layer through the opening in the shielding layer for the n-type column; The steps include removing the shielding layer for the n-type column, The process involves determining whether or not to implant additional n-type impurity ions according to the measured aperture width, and if additional implantation is determined to be necessary, forming an additional shielding layer (64) for an additional n-type column on the surface of the semiconductor layer, which opens up in a manner corresponding to at least a portion of the formation range of the n-type column. A method for manufacturing a semiconductor device according to feature 2, comprising the step of implanting n-type impurity ions into the semiconductor layer through an opening in the additional shielding layer for the n-type column to form the n-type column.

[0066] (Feature 8) The step of forming the p-type column based on the pattern misalignment of the shielding layer for the p-type column is: The steps include measuring the opening width (64W) of the shielding layer for the p-type column, The steps include: implanting p-type impurity ions into the semiconductor layer through the opening in the shielding layer for the p-type column; The process involves determining whether or not to implant additional p-type impurity ions based on the measured aperture width, and if additional implantation is determined to be necessary, forming an additional shielding layer (68) for an additional p-type column on the surface of the semiconductor layer, which opens up in a manner corresponding to at least a portion of the p-type column formation range. A method for manufacturing a semiconductor device according to feature 2 or 7, comprising the step of implanting p-type impurity ions into the semiconductor layer through an opening in the additional shielding layer for the p-type column to form the p-type column.

[0067] (Feature 9) The process of forming the superjunction structure is as follows: A step of forming an n-type column shielding layer on the surface of the semiconductor layer, which opens up in a manner corresponding to the formation range of the n-type column, A step of measuring the alignment deviation from the design pattern of the shielding layer for the n-type column, A step of forming the n-type column by implanting n-type impurity ions into the semiconductor layer through the opening of the shielding layer for the n-type column, A step of forming a p-type column shielding layer on the surface of the semiconductor layer, which opens in a manner corresponding to the formation range of the p-type column based on the measured alignment deviation, A method for manufacturing a semiconductor device according to any one of features 1 to 8, comprising the step of implanting p-type impurity ions into the semiconductor layer through an opening in the p-type column shielding layer to form the p-type column.

[0068] (Feature 10) The process of forming the superjunction structure is as follows: A step of forming a p-type column shielding layer on the surface of the semiconductor layer, which opens up in a manner corresponding to the formation range of the p-type column, A step of measuring the alignment deviation from the design pattern of the shielding layer for the p-type column, A step of forming the p-type column by implanting p-type impurity ions into the semiconductor layer through the opening in the shielding layer for the p-type column, A step of forming an n-type column shielding layer on the surface of the semiconductor layer, which opens in a manner corresponding to the formation range of the n-type column based on the measured alignment deviation, A method for manufacturing a semiconductor device according to any one of features 1 to 9, comprising the step of implanting n-type impurity ions into the semiconductor layer through an opening in the shielding layer for the n-type column to form the n-type column.

[0069] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of Symbols]

[0070] 1: Semiconductor device, 10: Semiconductor layer, 12: Drain region, 14: Drift region, 14a: n-type column, 14b: p-type column, 16: Body region, 18: Source region, 19: Body contact region, 22: Drain electrode, 24: Source electrode, 30: Trench gate, 52: Shielding layer for n-type column, 54: Shielding layer for p-type column, 62: Shielding layer for n-type column, 64: Shielding layer for p-type column, 66: Additional shielding layer for n-type column, 68: Additional shielding layer for p-type column

Claims

1. A method for manufacturing a semiconductor device (1), comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the superjunction structure based on a pattern deviation indicating a deviation from the design pattern of a shielding layer (52, 54, 62, 64) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of at least one of the n-type columns and the p-type columns, The process of forming the superjunction structure is as follows: A step of forming the n-type column based on the pattern misalignment of the n-type column shielding layer (52, 62) that opens up in a manner corresponding to the formation range of the n-type column, The process includes forming the p-type column based on the pattern misalignment of the p-type column shielding layers (54, 64) that open in a manner corresponding to the formation range of the p-type column, The step of forming the n-type column based on the pattern misalignment of the shielding layer for the n-type column is: The steps include measuring the opening width (52W) of the shielding layer for the n-type column, A step of implanting n-type impurity ions into the semiconductor layer through an opening in the shielding layer for the n-type column, wherein the n-type impurity ions are implanted according to predetermined conditions. The process includes the steps of determining whether or not to implant additional n-type impurity ions according to the measured aperture width, and if additional implantation is determined to be necessary, implanting additional n-type impurity ions into the semiconductor layer through the opening in the n-type column shielding layer to form the n-type column, The step of forming the p-type column based on the pattern misalignment of the shielding layer for the p-type column is: The steps include measuring the opening width (54W) of the shielding layer for the p-type column, A step of implanting p-type impurity ions into the semiconductor layer through an opening in the p-type column shielding layer, wherein the p-type impurity ions are implanted according to predetermined conditions. A method for manufacturing a semiconductor device, comprising the steps of: determining whether or not to implant additional p-type impurity ions according to the measured aperture width; and, if it is determined that additional implantation is necessary, implanting additional p-type impurity ions into the semiconductor layer through the opening of the p-type column shielding layer to form the p-type column.

2. A method for manufacturing a semiconductor device (1), comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the superjunction structure based on a pattern deviation indicating a deviation from the design pattern of a shielding layer (52, 54, 62, 64) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of at least one of the n-type columns and the p-type columns, The process of forming the superjunction structure is as follows: A step of forming the n-type column based on the pattern misalignment of the n-type column shielding layer (52, 62) that opens up in a manner corresponding to the formation range of the n-type column, The process includes forming the p-type column based on the pattern misalignment of the p-type column shielding layers (54, 64) that open in a manner corresponding to the formation range of the p-type column, The step of forming the n-type column based on the pattern misalignment of the shielding layer for the n-type column is: The steps include measuring the opening width (62W) of the shielding layer for the n-type column, The steps include: implanting n-type impurity ions into the semiconductor layer through the opening in the shielding layer for the n-type column; The steps include removing the shielding layer for the n-type column, The process involves determining whether or not to implant additional n-type impurity ions according to the measured aperture width, and if it is determined that additional implantation is necessary, forming an additional shielding layer (64) for an additional n-type column on the surface of the semiconductor layer, which opens up in a manner corresponding to at least a portion of the formation range of the n-type column. The step of forming the n-type column by implanting n-type impurity ions into the semiconductor layer through the opening of the additional shielding layer for the n-type column, The step of forming the p-type column based on the pattern misalignment of the shielding layer for the p-type column is: The steps include measuring the opening width (64W) of the shielding layer for the p-type column, The steps include: implanting p-type impurity ions into the semiconductor layer through the opening in the shielding layer for the p-type column; The process involves determining whether or not to implant additional p-type impurity ions according to the measured aperture width, and if it is determined that additional implantation is necessary, forming an additional shielding layer (68) for an additional p-type column on the surface of the semiconductor layer, which opens up in a manner corresponding to at least a portion of the p-type column formation range. A method for manufacturing a semiconductor device, comprising the step of implanting p-type impurity ions into the semiconductor layer through an opening in the additional shielding layer for the p-type column to form the p-type column.

3. A method for manufacturing a semiconductor device (1), comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the superjunction structure based on a pattern deviation indicating a deviation from the design pattern of a shielding layer (52, 54, 62, 64) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of at least one of the n-type columns and the p-type columns, The process of forming the superjunction structure is as follows: A step of forming an n-type column shielding layer on the surface of the semiconductor layer, which opens up in a manner corresponding to the formation range of the n-type column, A step of measuring the alignment deviation from the design pattern of the shielding layer for the n-type column, A step of forming the n-type column by implanting n-type impurity ions into the semiconductor layer through the opening of the shielding layer for the n-type column, A step of forming a p-type column shielding layer on the surface of the semiconductor layer, which opens in a position adjusted based on the measured alignment deviation, corresponding to the formation range of the p-type column, A method for manufacturing a semiconductor device, comprising the step of forming a p-type column by implanting p-type impurity ions into the semiconductor layer through an opening in the p-type column shielding layer.

4. A method for manufacturing a semiconductor device (1), comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the superjunction structure based on a pattern deviation indicating a deviation from the design pattern of a shielding layer (52, 54, 62, 64) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of at least one of the n-type columns and the p-type columns, The process of forming the superjunction structure is as follows: A step of forming a p-type column shielding layer on the surface of the semiconductor layer, which opens up in a manner corresponding to the formation range of the p-type column, A step of measuring the alignment deviation from the design pattern of the shielding layer for the p-type column, A step of forming the p-type column by implanting p-type impurity ions into the semiconductor layer through the opening of the p-type column shielding layer, A step of forming an n-type column shielding layer on the surface of the semiconductor layer, which opens in a position adjusted based on the measured alignment deviation, corresponding to the formation range of the n-type column, A method for manufacturing a semiconductor device, comprising the step of forming an n-type column by implanting n-type impurity ions into the semiconductor layer through an opening in the n-type column shielding layer.

5. A method for manufacturing a semiconductor device (1) comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the n-type column based on a pattern deviation indicating a deviation from the design pattern of the n-type column shielding layer (52, 62) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of the n-type column, The step of forming the n-type column based on the pattern misalignment of the shielding layer for the n-type column is: The steps include measuring the opening width (52W) of the shielding layer for the n-type column, A step of implanting n-type impurity ions into the semiconductor layer through an opening in the shielding layer for the n-type column, wherein the n-type impurity ions are implanted according to predetermined conditions. A method for manufacturing a semiconductor device, comprising the steps of: determining whether or not to implant additional n-type impurity ions according to the measured aperture width; and, if it is determined that additional implantation is necessary, implanting additional n-type impurity ions into the semiconductor layer through the opening of the n-type column shielding layer to form the n-type column.

6. A method for manufacturing a semiconductor device (1), comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the p-type column based on a pattern deviation indicating a deviation from the design pattern of the p-type column shielding layer (54, 64) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of the p-type column, The step of forming the p-type column based on the pattern misalignment of the shielding layer for the p-type column is: The steps include measuring the opening width (54W) of the shielding layer for the p-type column, A step of implanting p-type impurity ions into the semiconductor layer through an opening in the p-type column shielding layer, wherein the p-type impurity ions are implanted according to predetermined conditions. A method for manufacturing a semiconductor device, comprising the steps of: determining whether or not to implant additional p-type impurity ions according to the measured aperture width; and, if it is determined that additional implantation is necessary, implanting additional p-type impurity ions into the semiconductor layer through the opening of the p-type column shielding layer to form the p-type column.

7. A method for manufacturing a semiconductor device (1) comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the n-type column based on a pattern deviation indicating a deviation from the design pattern of the n-type column shielding layer (52, 62) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of the n-type column, The step of forming the n-type column based on the pattern misalignment of the shielding layer for the n-type column is: The steps include measuring the opening width (62W) of the shielding layer for the n-type column, The steps include: implanting n-type impurity ions into the semiconductor layer through the opening in the shielding layer for the n-type column; The steps include removing the shielding layer for the n-type column, The process involves determining whether or not to implant additional n-type impurity ions according to the measured aperture width, and if it is determined that additional implantation is necessary, forming an additional shielding layer (64) for an additional n-type column on the surface of the semiconductor layer, which opens up in a manner corresponding to at least a portion of the formation range of the n-type column. A method for manufacturing a semiconductor device, comprising the step of implanting n-type impurity ions into the semiconductor layer through an opening in the additional shielding layer for the n-type column to form the n-type column.

8. A method for manufacturing a semiconductor device (1) comprising a semiconductor layer (10) including a superjunction structure in which n-type columns (14a) and p-type columns (14b) are alternately and repeatedly arranged along at least one direction, The process includes forming the p-type column based on a pattern deviation indicating a deviation from the design pattern of the p-type column shielding layer (54, 64) which is formed on the surface of the semiconductor layer and opens up in a manner corresponding to the formation range of the p-type column, The step of forming the p-type column based on the pattern misalignment of the shielding layer for the p-type column is: The steps include measuring the opening width (64W) of the shielding layer for the p-type column, The steps include: implanting p-type impurity ions into the semiconductor layer through the opening in the shielding layer for the p-type column; The process involves determining whether or not to implant additional p-type impurity ions according to the measured aperture width, and if it is determined that additional implantation is necessary, forming an additional shielding layer (68) for an additional p-type column on the surface of the semiconductor layer, which opens up in a manner corresponding to at least a portion of the p-type column formation range. A method for manufacturing a semiconductor device, comprising the step of implanting p-type impurity ions into the semiconductor layer through an opening in the additional shielding layer for the p-type column to form the p-type column.

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