Semiconductor equipment
The semiconductor device design with a protruding local region addresses electric field concentration issues, enhancing static breakdown voltage performance by dispersing electric fields and preventing device failure.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2023-01-30
- Publication Date
- 2026-07-29
AI Technical Summary
In semiconductor devices with p-type deep regions and p-type RESURF regions, electric field concentration during static breakdown voltage inspection leads to device breakdown and deteriorates inspection performance.
A semiconductor device design incorporating a semiconductor substrate with a deep region and a RESURF region, featuring a local region that protrudes downward from the RESURF region's bottom surface, positioned away from the deep region, to mitigate electric field concentration during static breakdown voltage testing.
The local region effectively disperses electric fields, preventing device failure and improving static breakdown voltage performance by reducing electric field concentration in the deep region.
Smart Images
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Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to semiconductor devices.
Background Art
[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate having an element region and a peripheral region. In this semiconductor device, an inverse-conducting IGBT structure is formed in the element region, and a p-type RESURF region is formed in the peripheral region. Further, a p-type deep region formed deeper than the RESURF region is provided at the boundary between the element region and the peripheral region.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In a semiconductor device having a p-type deep region and a p-type RESURF region, it is known that when inspecting the static breakdown voltage, the electric field concentrates in the deep region in the negative resistance region after breakdown. Such electric field concentration has been found to cause device breakdown during the static breakdown voltage inspection and deteriorate the static breakdown voltage inspection performance. This specification provides a technology for suppressing device breakdown during the static breakdown voltage inspection.
Means for Solving the Problems
[0005] A semiconductor device disclosed herein may include a semiconductor substrate (10) having an element region (10A) on which a device structure is formed and a peripheral region (10B) provided around the element region, an upper electrode (22) provided on the upper surface of the semiconductor substrate, and a lower electrode (24) provided on the lower surface of the semiconductor substrate. Here, the device structure refers to a structure formed on the semiconductor substrate to perform a specific function. The device structure is not particularly limited, but may be, for example, an IGBT structure or MOSFET structure for performing a switching function, a diode structure for performing a rectification function, or a combination thereof. The semiconductor substrate may have: a drift region (12) of a first conductivity type provided in the element region and the peripheral region; a deep region (15) of a second conductivity type provided at the boundary between the element region and the peripheral region and positioned to be exposed on the upper surface of the semiconductor substrate; a resurf region (16) of a second conductivity type provided in the peripheral region and positioned to be exposed on the upper surface of the semiconductor substrate, which extends from the deep region and is shallower than the deep region; and a local region (17) of a second conductivity type provided projecting downward from the bottom surface of the resurf region, which is located away from the deep region and whose bottom surface is located deeper than the deep region.
[0006] In the semiconductor device described above, a local region is provided that is deeper than the deep region and protrudes downward from the bottom surface of the resurf region. Such a local region can bear the electric field during static withstand voltage testing. Therefore, the electric field concentration in the deep region is mitigated during static withstand voltage testing. As a result, element failure during static withstand voltage testing is suppressed in the semiconductor device described above. [Brief explanation of the drawing]
[0007] [Figure 1] A schematic plan view of a semiconductor device is shown. [Figure 2]This is a schematic cross-sectional view of the main part of a semiconductor device, corresponding to the cross-sectional view of the main part along line II-II in Figure 1. [Figure 3] This is an enlarged cross-sectional view of a key part of a semiconductor device, schematically showing an enlarged cross-sectional view of a key part of the peripheral region of the semiconductor substrate. [Modes for carrying out the invention]
[0008] The semiconductor device of this embodiment will be described below with reference to the drawings. For the purpose of clarity in the illustration, only a portion of the repeatedly formed structures may be given reference numerals.
[0009] The semiconductor device 1 shown in Figure 1 has a semiconductor substrate 10. The material of the semiconductor substrate 10 is not particularly limited, but may be silicon, silicon carbide, or nitride semiconductor, for example. Two upper electrodes 22 and a plurality of signal electrodes 26 are provided on the upper surface 10a of the semiconductor substrate 10. Alternatively, one upper electrode 22 may be provided on the upper surface 10a of the semiconductor substrate 10 instead of two upper electrodes 22. Each of the plurality of signal electrodes 26 is an interface for inputting and outputting gate signals and various sensor signals. The semiconductor substrate 10 has an element region 10A in the area below each upper electrode 22, where an IGBT structure that exhibits a switching function is formed. The element region 10A may have a structure that exhibits a specific function, for example, a MOSFET structure that exhibits a switching function may be formed, a diode structure that exhibits a rectification function may be formed, or a reverse conducting IGBT structure that combines an IGBT structure and a diode structure may be formed. The semiconductor substrate 10 further has a peripheral region 10B around each element region 10A. The peripheral region 10B is located between the element region 10A and the outer peripheral end face 10c of the semiconductor substrate 10. As will be described later, the peripheral region 10B is provided with a voltage-resistant structure to improve the voltage resistance of the semiconductor device 1. In the following description, the side closer to the outer peripheral end face 10c is referred to as the outer peripheral side, and the opposite side (the side further from the outer peripheral end face 10c) is referred to as the inner peripheral side.
[0010] As shown in Figure 2, a lower electrode 24 is provided on the lower surface 10b of the semiconductor substrate 10. The lower electrode 24 covers the entire area of the lower surface 10b of the semiconductor substrate 10. Multiple trench gates 30 are formed in the upper layer of the element region 10A of the semiconductor substrate 10. Each of the multiple trench gates 30 has a gate insulating film 32 and a gate electrode 34. The gate insulating film 32 is provided so as to cover the inner surface of the trench formed in the upper layer of the element region 10A of the semiconductor substrate 10. The gate electrode 34 is filled in the trench and is insulated from the semiconductor substrate 10 by the gate insulating film 32.
[0011] The semiconductor substrate 10 is p + A collector region 11 of type n, a drift region 12 of type n, a body region 13 of type p, and multiple n + A p-type emitter region 14, a p-type deep region 15, a p-type resurf region 16, multiple p-type local regions 17, and n + It has a type equipotential ring region 18.
[0012] The collector region 11 is provided in both the element region 10A and the peripheral region 10B of the semiconductor substrate 10, and is located in the lower layer of the semiconductor substrate 10. The collector region 11 is in ohmic contact with the lower electrode 24.
[0013] The drift region 12 is provided in both the element region 10A and the peripheral region 10B of the semiconductor substrate 10 and is located on the collector region 11. The drift region 12 is in contact with the lower surface and the lower side of each of the multiple trench gates 30.
[0014] The body region 13 is located in the element region 10A of the semiconductor substrate 10 and is positioned in the upper layer of the semiconductor substrate 10. The body region 13 is in contact with each side of the multiple trench gates 30 and separates the drift region 12 and the emitter region 14. The body region 13 is in ohmic contact with the upper electrode 22 via a contact region in which p-type impurities are adjusted to a high concentration.
[0015] Each of the multiple emitter regions 14 is located in the element region 10A of the semiconductor substrate 10 and is positioned to be exposed on the upper surface 10a of the semiconductor substrate 10. Each of the multiple emitter regions 14 is in contact with the upper side of the corresponding trench gate 30. Each of the multiple emitter regions 14 is in ohmic contact with the upper electrode 22.
[0016] The deep region 15 is located at the boundary between the device region 10A and the peripheral region 10B of the semiconductor substrate 10, and is positioned to be exposed on the upper surface 10a of the semiconductor substrate 10. When the semiconductor substrate 10 is viewed from above, the deep region 15 is positioned to encircle the body region 13 along the boundary between the device region 10A and the peripheral region 10B. The deep region 15 is a diffusion region formed by introducing p-type impurities into the upper layer of the semiconductor substrate 10 using ion implantation technology. The deep region 15 is in contact with both the adjacent body region 13 and the resurf region 16, and is formed to be deeper than both the body region 13 and the resurf region 16. The deep region 15 is in ohmic contact with the upper electrode 22.
[0017] The resurf region 16 is located in the peripheral region 10B of the semiconductor substrate 10 and is positioned to be exposed on the upper surface 10a of the semiconductor substrate 10. The resurf region 16 is in contact with the deep region 15 and extends from the deep region 15 toward the outer periphery, i.e., away from the element region 10A. When the semiconductor substrate 10 is viewed from above, the resurf region 16 is arranged to encircle the deep region 15. The resurf region 16 is a diffusion region formed by introducing p-type impurities into the upper layer of the semiconductor substrate 10 using ion implantation technology. The concentration of p-type impurities in the resurf region 16 is lower than the concentration of p-type impurities in the deep region 15. Furthermore, the concentration of p-type impurities in the resurf region 16 decreases continuously or in multiple stages toward the outer periphery.
[0018] Each of the multiple local regions 17 is located in the peripheral region 10B of the semiconductor substrate 10 and is positioned in contact with the bottom surface of the resurf region 16. Each of the multiple local regions 17 protrudes downward from the bottom surface of the resurf region 16. Each of the multiple local regions 17 is located away from the deep region 15, and its bottom surface is located deeper than the deep region 15. Each of the multiple local regions 17 is a diffusion region formed by introducing p-type impurities to a predetermined depth from the top surface 10a of the semiconductor substrate 10 using ion implantation technology. The concentration of p-type impurities in each of the multiple local regions 17 is lower than the concentration of p-type impurities in the deep region 15. Alternatively, only one local region 17 may be provided instead of multiple local regions 17.
[0019] Here, with reference to Figure 3, the relative positions and shapes of each region will be explained. The thickness T1 of the semiconductor substrate 10 is the length measured along the thickness direction of the semiconductor substrate 10 between the top surface 10a and the bottom surface 10b of the semiconductor substrate 10. The depth D1 of the deep region 15 is the length measured along the thickness direction of the semiconductor substrate 10 between the top surface 10a of the semiconductor substrate 10 and the deepest part of the deep region 15. In this example, the depth of the deepest part of the deep region 15 is the depth of the bottom surface, which is configured parallel to the plane direction of the semiconductor substrate 10, reflecting the broad ion implantation. The depth D2 of the local region 17 is the length measured between the top surface 10a of the semiconductor substrate 10 and the deepest part of the local region 17. In this example, the depth of the deepest part of the local region 17 is the depth of the downward-facing apex P2, reflecting the local ion implantation. The distance W1 between the local region 17 closest to the element region 10A and the deep region 15 is measured as the shortest distance between the inflection point P1 of the deep region 15 and the downward-facing vertex P2 of the local region 17. The inflection point P1 of the deep region 15 is the junction point between the flat bottom surface and the curved side surface of the deep region 15. The distance W2 between adjacent local regions 17 is measured as the shortest distance between their respective downward-facing vertices P2 and P3. If the local region 17 is formed to have a flat bottom surface, the inflection point of the local region 17 may be used to measure the distances W1 and W2. The length L1 of the resurf region 16 is measured as the shortest distance between the inner-circumferential endpoint P4 and the outer-circumferential endpoint P5 of the resurf region 16. The inner-circumferential endpoint P4 of the resurf region 16 is defined by the contact point where the junction surface of the resurf region 16 and the deep region 15 contacts the upper surface 10a of the semiconductor substrate 10. The outermost endpoint P5 of the resurf region 16 is defined by the contact point where the junction surface of the resurf region 16 and the drift region 12 contacts the upper surface 10a of the semiconductor substrate 10.
[0020] In the semiconductor device 1, the depth D2 of the local region 17 is greater than the depth D1 of the deep region 15. Also, in the semiconductor device 1, the interval W1 is greater than or equal to the thickness T1 of the semiconductor substrate 10, and the interval W2 is less than or equal to the thickness T1 of the semiconductor substrate 10. Further, in the semiconductor device 1, at least one of the plurality of local regions 17 is arranged on the outer peripheral side of the center position 16a of the RESURF region 16, that is, the position where L1 / 2 is located, when observed in the direction away from the element region 10A, that is, along the direction connecting the inner peripheral side and the outer peripheral side. In this example, both of the two local regions 17 are arranged on the outer peripheral side of the center position 16a of the RESURF region 16. Instead of this example, the outer peripheral local region 17 among the plurality of local regions 17 may be arranged on the outer peripheral side of the center position 16a of the RESURF region 16, and the inner peripheral local region 17 may be arranged on the inner peripheral side of the center position 16a of the RESURF region 16.
[0021] Returning to FIG. 2. The equipotential ring region 18 is provided in the peripheral region 10B of the semiconductor substrate 10 and is arranged at a position exposed on the upper surface 10a of the semiconductor substrate 10. The equipotential ring region 18 is arranged so as to go around the element region 10A and the peripheral region 10B along the outer peripheral end of the semiconductor substrate 10 in a plan view. The equipotential ring region 18 is in ohmic contact with an EQR electrode formed on the upper surface 10a of the semiconductor substrate 10. The EQR electrode is fixed to the same potential as the lower electrode 24.
[0022] As described above, in the semiconductor device 1, an IGBT structure composed of a plurality of trench gates 30 and various semiconductor regions is formed in the element region 10A of the semiconductor substrate 10, and a RESURF region 16 is formed as a breakdown voltage structure in the peripheral region 10B of the semiconductor substrate 10. Also, in the semiconductor device 1, a deep region 15 that diffuses deeper than the body region 13 and the RESURF region 16 is formed at the boundary between the element region 10A and the peripheral region 10B.
[0023] In such a semiconductor device 1, a static breakdown test is performed by applying a voltage between the upper electrode 22 and the lower electrode 24 such that the lower electrode 24 is more positive than the upper electrode 22, while the IGBT structure is turned off (i.e., no gate-on voltage is applied to each of the multiple trench gates 30). In the static breakdown test, a breakdown is caused in the semiconductor device 1, and the pass / fail status of the semiconductor device 1 is determined based on the measured breakdown voltage.
[0024] For example, in a comparative example where multiple local regions 17 are not provided, if a static breakdown test is performed, the electric field will concentrate in the deep region 15 in the negative resistance region after breakdown, causing a large current to flow in the deep region 15, raising concerns about device failure.
[0025] On the other hand, in the semiconductor device 1 of this embodiment, since the depth D2 of each of the multiple local regions 17 is greater than the depth D1 of the deep region 15, each of these multiple local regions 17 can bear the electric field during static withstand voltage testing. As a result, electric field concentration in the deep region 15 during static withstand voltage testing is mitigated. Consequently, device failure during static withstand voltage testing is suppressed in the semiconductor device 1.
[0026] In particular, in the semiconductor device 1, the distance W1 between the local region 17 closest to the element region 10A and the deep region 15 is greater than or equal to the thickness T1 of the semiconductor substrate 10. Furthermore, at least one of the local regions 17 is positioned away from the element region 10A and on the outer periphery of the resurf region 16, relative to the center position 16a. That is, each of the local regions 17 is positioned at a sufficient distance from the deep region 15. As a result, the current flowing within the peripheral region 10B in the negative resistance region after breakdown is dispersed, effectively suppressing the occurrence of element failure. Moreover, by providing such multiple local regions 17, the electric field concentration in the deep region 15 can be mitigated, thereby improving the static breakdown voltage of the semiconductor device 1.
[0027] Furthermore, in the semiconductor device 1, the spacing W2 between adjacent local regions 17 is less than or equal to the thickness T1 of the semiconductor substrate 10. That is, the multiple local regions 17 are arranged so as not to be too far apart from each other. As a result, when the semiconductor device 1 is turned off, the equipotential lines formed in the peripheral region 10B become smooth, and excessive concentration of the electric field at locations corresponding to each of the multiple local regions 17 is suppressed. Therefore, deterioration of the static breakdown voltage of the semiconductor device 1 is suppressed.
[0028] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.
[0029] (Feature 1) A semiconductor substrate (10) having an element region (10A) on which a device structure is formed, and a peripheral region (10B) provided around the element region, The upper electrode (22) provided on the upper surface of the semiconductor substrate, The semiconductor substrate is provided with a lower electrode (24) located on its lower surface, The aforementioned semiconductor substrate is The element region and the first conductivity type drift region (12) provided in the peripheral region, A second conductivity type deep region (15) is provided at the boundary between the element region and the peripheral region and is positioned to be exposed on the upper surface of the semiconductor substrate, A second conductivity type resurf region (16) is provided in the peripheral region and positioned to be exposed on the upper surface of the semiconductor substrate, and extends from the deep region and is shallower than the deep region, A semiconductor device having a second conductivity type local region (17) which is provided projecting downward from the bottom surface of the resurf region, and which is located away from the deep region and whose bottom surface is located deeper than that of the deep region.
[0030] (Feature 2) The semiconductor device according to feature 1, wherein the distance between the deep region and the local region is greater than or equal to the thickness of the semiconductor substrate.
[0031] (Feature 3) The semiconductor device according to feature 1 or 2, wherein the local region is located outside the center position of the resurf region when observed in a direction away from the element region.
[0032] (Feature 4) A semiconductor device according to any one of features 1 to 3, wherein multiple local regions are provided.
[0033] (Feature 5) The semiconductor device according to feature 4, wherein the distance between adjacent local regions is less than or equal to the thickness of the semiconductor substrate.
[0034] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]
[0035] 1: Semiconductor device, 10: Semiconductor substrate, 10A: Element region, 10B: Peripheral region, 11: Collector region, 12: Drift region, 13: Body region, 14: Emitter region, 15: Deep region, 16: Resurf region, 17: Local region, 18: Equipotential ring region, 22: Upper electrode, 24: Lower electrode, 30: Trench gate, 32: Gate insulating film, 34: Gate electrode
Claims
1. A semiconductor substrate (10) having an element region (10A) on which a device structure is formed, and a peripheral region (10B) provided around the element region, The upper electrode (22) provided on the upper surface of the semiconductor substrate, The semiconductor substrate is provided with a lower electrode (24) located on its lower surface, The aforementioned semiconductor substrate is The element region and the first conductivity type drift region (12) provided in the peripheral region, A second conductive body region (13) is provided in the element region and is located in the upper layer of the semiconductor substrate, A deep region (15) of a second conductivity type is provided at the boundary between the element region and the peripheral region and is positioned to be exposed on the upper surface of the semiconductor substrate, and is deeper than the body region. A second conductivity type resurf region (16) is provided in the peripheral region and positioned to be exposed on the upper surface of the semiconductor substrate, and extends from the deep region and is shallower than the deep region, A semiconductor device having a second conductivity type local region (17) which is provided projecting downward from the bottom surface of the resurf region, and which is located away from the deep region and whose bottom surface is located deeper than that of the deep region.
2. The semiconductor device according to claim 1, wherein the distance between the deep region and the local region is greater than or equal to the thickness of the semiconductor substrate.
3. The semiconductor device according to claim 1, wherein the local region is located outside the center position of the resurf region when observed in a direction away from the element region.
4. The semiconductor device according to claim 1, wherein a plurality of the aforementioned local regions are provided.
5. The semiconductor device according to claim 4, wherein the distance between adjacent local regions is less than or equal to the thickness of the semiconductor substrate.
6. A semiconductor substrate (10) having an element region (10A) on which a device structure is formed, and a peripheral region (10B) provided around the element region, The upper electrode (22) provided on the upper surface of the semiconductor substrate, The semiconductor substrate is provided with a lower electrode (24) located on its lower surface, The aforementioned semiconductor substrate is The element region and the first conductivity type drift region (12) provided in the peripheral region, A second conductivity type deep region (15) is provided at the boundary between the element region and the peripheral region and is positioned to be exposed on the upper surface of the semiconductor substrate, A second conductivity type resurf region (16) is provided in the peripheral region and positioned to be exposed on the upper surface of the semiconductor substrate, and extends from the deep region and is shallower than the deep region, A second conductive local region (17) is provided projecting downward from the bottom surface of the Resurf region, and is located away from the Deep region, with its bottom surface being at a deeper position than the Deep region. A semiconductor device wherein the local region is located outside the center position of the resurf region when observed in a direction away from the element region.
7. A semiconductor substrate (10) having an element region (10A) on which a device structure is formed, and a peripheral region (10B) provided around the element region, The upper electrode (22) provided on the upper surface of the semiconductor substrate, The semiconductor substrate is provided with a lower electrode (24) located on its lower surface, The aforementioned semiconductor substrate is The element region and the first conductivity type drift region (12) provided in the peripheral region, A second conductivity type deep region (15) is provided at the boundary between the element region and the peripheral region and is positioned to be exposed on the upper surface of the semiconductor substrate, A second conductivity type resurf region (16) is provided in the peripheral region and positioned to be exposed on the upper surface of the semiconductor substrate, and extends from the deep region and is shallower than the deep region, A semiconductor device comprising: a plurality of local regions (17) of a second conductivity type, which are provided projecting downward from the bottom surface of the resurf region, and which are located away from the deep region, with their bottom surfaces being at a deeper position than the deep region.