Phase adjustment circuit

Abstract

This phase adjustment circuit comprises: a clock generation unit (1) that generates a sinusoidal differential clock signal; a variable amplifier (2) to which the differential clock signal outputted from the clock generation unit (1) is inputted and which outputs a differential clock signal adjusted in amplitude simultaneously with an in-phase signal adjusted in amplitude; an addition unit (3) that adds the in-phase signal to both the positive phase side and the reverse phase side of the differential clock signal outputted from the variable amplifier (2); a differential transmission line (4) through which a differential signal outputted from the addition unit (3) is transmitted; and a termination circuit (5) that terminates the differential transmission line (4).

Description

[Technical Field]

[0001] This invention relates to a sinusoidal phase adjustment circuit. [Background technology]

[0002] In modern times, sine waves play a crucial role. In communications, sine waves are sometimes used to generate carrier waves, and sometimes they are used as clocks. In communications, clocks are used not only as carrier waves, but also as timing standards for determining data.

[0003] When using a clock as the timing reference for data determination, it is necessary to adjust the clock phase and perform data determination at the appropriate timing. One method for performing data determination at the appropriate timing is clock-data recovery. A known configuration for implementing clock-data recovery uses a phase comparator and a phase adjustment circuit. In this configuration, the phases are compared by some means, and the desired phase is generated based on the comparison result.

[0004] Conventionally, the configuration disclosed in Non-Patent Document 1 was known as a phase adjustment circuit. The configuration of the conventional phase adjustment circuit is shown in Figure 9. In the configuration of Figure 9, a waveform with an arbitrary intermediate phase is generated by adding a reference sine wave sinωt and a sine wave cosωt that has a fixed phase difference of π / 2 with respect to the sine wave sinωt. The sine waves sinωt and cosωt are multiplied by constants A and B, respectively, by multipliers 101 and 102. From the trigonometric function synthesis formula, the following equation holds.

[0005]

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[0006] In equation (1), α is given by the following:

[0007]

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[0008] In the configuration shown in Figure 9, a Quadrature-VCO (Voltage Controlled Oscillator) 100 is used to generate sine waves sinωt and cosωt. However, due to its structure, the Quadrature-VCO 100 has a low oscillation frequency, making it difficult to use in the device's limit region. Furthermore, while a method using a 90-degree hybrid is known for creating a sine wave with a fixed phase difference of π / 2 from a sine wave, this method has the drawback of only operating at specific frequencies. [Prior art documents] [Non-patent literature]

[0009] [Non-Patent Document 1] Arun Goyal,et al.,“A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector”,2019 IEEE International Symposium on Circuits and Systems (ISCAS),May 2019 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] This invention was made to solve the above problems and aims to provide a phase adjustment circuit that can be used over a wide range of frequencies. [Means for solving the problem]

[0011] The phase adjustment circuit of the present invention includes a clock generation unit configured to generate a sinusoidal clock signal, a variable amplifier configured to receive the clock signal output from the clock generation unit as an input, output an amplitude-adjusted sinusoidal differential clock signal, and at the same time output an amplitude-adjusted in-phase signal, an addition unit configured to output a differential signal obtained by adding the in-phase signal to each of the positive-phase side and the negative-phase side of the differential clock signal output from the variable amplifier, a differential transmission line configured to transmit the differential signal output from the addition unit, and a termination circuit configured to terminate the differential transmission line, and the in-phase signal is common to each of the positive-phase side and the negative-phase side of the differential clock signal The single phases that are added and is a signal, the differential transmission line is formed by electromagnetic coupling between a positive-phase transmission line and a negative-phase transmission line, and is characterized in that a signal is output from either one of the positive-phase transmission line and the negative-phase transmission line constituting the differential transmission line at a termination end thereof. Also, in one configuration example of the phase adjustment circuit of the present invention, the termination circuit includes a first resistor having one end connected to the termination of the Positive phase side transmission line, a second resistor having one end connected to the termination of the Reverse phase side transmission line, and a third resistor having one end connected to the connection point of the first and second resistors and the other end connected to a fixed potential or ground.

[0013] Also, in one configuration example of the phase adjustment circuit of the present invention, the variable amplifier includes The output from the clock generation unit a Gilbert cell type first variable amplifier that amplitude-adjusts a clock signal and The differential clock signal outputs it, and Output from the clock generation unit a Gilbert cell type second variable amplifier that amplitude-adjusts the clock signal and The aforementioned in-phase signal outputs it.

[0014] Also, in one configuration example of the phase adjustment circuit of the present invention, the The positive-sequence transmission line and the negative-sequence side transmission line and constituting the differential transmission line , each other is arranged adjacent to each other. Also, in one configuration example of the phase adjustment circuit of the present invention, the differential transmission line is composed of The positive-sequence transmission line and the negative-sequence side transmission lines and The length L of each of which is the propagation speed v with respect to the differential mode of the differential transmission line [Figure 1] ,

[0016] , [Figure 4] , , [Figure 3] , , [Figure 2] , , , , , , , the propagation speed with respect to the common mode is v c , when the highest angular frequency of the sinusoidal clock signal to be phase - adjusted is ω, it is set to satisfy L < π / {ω|(1 / v d )-(1 / v c )|}. Also, one configuration example of the phase adjustment circuit of the present invention further includes a level adjustment unit configured to perform amplitude adjustment on a signal output from one of the transmission lines constituting the differential transmission line. The positive-sequence transmission line and the negative-sequence side transmission lines and It is characterized by this.

Advantages of the Invention

[0015] According to the present invention, by providing a clock generation unit, a variable amplifier, an addition unit, a differential transmission line, and a termination circuit, and outputting a signal from one of the two transmission lines constituting the differential transmission line, it is not necessary to use a conventional Quadrature - VCO as the clock generation unit, and an LC - VCO composed of a general LC oscillator can be used as the clock generation unit. Further, in the present invention, different from the configuration using a 90 - degree hybrid as the clock generation unit, it can be used at a wide range of frequencies.

Brief Description of the Drawings

[0016] [Figure 1] FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to the first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the simulation result of the phase adjustment circuit according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of a termination circuit according to the second embodiment of the present invention. [Figure 4]Figure 4 is a circuit diagram showing the configuration of an adder according to a third embodiment of the present invention. [Figure 5] Figure 5 is a circuit diagram showing the configuration of a variable amplifier according to a third embodiment of the present invention. [Figure 6] Figure 6 is a circuit diagram showing the configuration of a variable amplifier according to a third embodiment of the present invention. [Figure 7A-7C] Figures 7A-7C are cross-sectional views showing the configuration of a differential transmission line according to a fourth embodiment of the present invention. [Figure 8] Figure 8 is a block diagram showing the configuration of a phase adjustment circuit according to the fifth embodiment of the present invention. [Figure 9] Figure 9 is a block diagram showing the configuration of a conventional phase adjustment circuit. [Modes for carrying out the invention]

[0017] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. The phase adjustment circuit comprises a clock generation unit 1 that generates a sinusoidal differential clock signal, a variable amplifier 2 that takes the differential clock signal output from the clock generation unit 1 as input and outputs an amplitude-adjusted differential clock signal, and at the same time outputs an amplitude-adjusted common-mode signal, an adder 3 that outputs a differential signal obtained by adding a common-mode signal to the positive-phase side and the negative-phase side of the differential clock signal output from the variable amplifier 2, a differential transmission line 4 that transmits the differential signal output from the adder 3, and a termination circuit 5 that terminates the differential transmission line 4.

[0018] The amplitudes of the differential clock signal and the common-mode signal are adjusted by variable amplifiers 20-1 and 20-2, respectively. Although details are omitted in Figure 1, the input format of variable amplifiers 20-1 and 20-2 can be either common-mode or differential. In other words, the output of the clock generation unit 1 may be a single-phase clock signal.

[0019] The adder 3 is composed of an adder 30-1 that adds and outputs the positive-phase side of the differential clock signal and the in-phase signal, and an adder 30-2 that adds and outputs the negative-phase side of the differential clock signal and the in-phase signal. For the adders 30-1 and 30-2, a design according to the characteristic impedance of the differential transmission line 4 may be made.

[0020] The differential transmission line 4 refers to a transmission line in which the positive-phase side transmission line 40-1 and the negative-phase side transmission line 40-2 are electromagnetically coupled. Also, in the differential transmission line 4 of this embodiment, the propagation speeds of the in-phase signal and the differential signal are different. A termination circuit 5 is connected to the end of the differential transmission line 4. In this embodiment, a sine wave with an intermediate phase can be extracted from the end of the positive-phase side transmission line 40-1. As will be described later, a sine wave may also be extracted from the end of the negative-phase side transmission line 40-2.

[0021] In the differential transmission line 4, it is known that a propagation speed difference occurs between the differential signal and the in-phase signal. Let the propagation speed for the differential mode be v d , and the propagation speed for the in-phase mode be v c . When the lengths of the transmission lines 40-1 and 40-2 are L and the angular frequency of the sine wave is ω, when the propagation delay is converted into a phase, the phase of the sine wave in the differential mode is (L / v d )ω, and the phase of the sine wave in the in-phase mode is (L / v c )ω.

[0022] Assuming that the differential signal at the output end of the adder 3 is αsinωT and the in-phase signal is βsin(ωT + δ), the differential signal at the end of the differential transmission line 4 is αsin(ωT+(ωL / v d )), and the in-phase signal at the end of the differential transmission line 4 is βsin(ωT+(ωL / v c )+δ). Here, δ indicates the phase delay or advance assuming a case where a delay is imparted to the in-phase signal and the differential signal due to manufacturing errors or some influence.

[0023] In this embodiment, the output signal OUT is taken from either of the transmission lines 40-1 and 40-2 that constitute the differential transmission line 4, so the output signal OUT is given by the following equation.

[0024]

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[0025] When the output signal OUT is taken from the end of transmission line 40-1, the first term on the right-hand side of equation (3) is +(α / 2)sin(ωT+(ωL / v d )) and when taking the output signal OUT from transmission line 40-2, -(α / 2)sin(ωT+(ωL / v d )) Here, A=±α / 2, B=β, ωt=ωT+(ωL / v d ),φ=(ωL / v c If we newly define )+δ, the output signal OUT will be given by the following equation.

[0026]

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[0027] Since ωT is merely a translation of ωt, explaining the generation of an intermediate phase in this embodiment using equation (4) is equivalent to explaining it using equation (3). Rearranging equation (4) yields equation (5).

[0028]

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[0029] e in equation (5) jωt This represents the reference sine wave. From equation (5), it can be seen that by adding a sine wave of the reference frequency to a sine wave that differs by an arbitrary phase φ, a sine wave with a phase difference of ρ from the reference phase can be generated. Details are explained below. The amount of change in output phase is re jρSince we only need to calculate this, rearranging equation (5) gives us the following equation.

[0030]

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[0031] From equation (6), the phase angle ρ is given by equation (7).

[0032]

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[0033] Let's consider the range of values ​​when controlling the phase angle ρ using amplitudes A and B. The range of output amplitudes A and B on the circuit is finite, centered around 0, but since A and B are independent, x = A / B ∈ [-∞, +∞], and any real numbers can be selected for amplitudes A and B. The sign of x can be determined by the combination of signs of amplitudes A and B, and increasing the value of x can be achieved by minimizing the denominator B as much as possible.

[0034] Furthermore, when y = x + cos(φ), it is clear that y = (A / B) + cos(φ) ∈ [-∞, +∞]. Therefore, ρ = arg(x + cos(φ) + jsin(φ)) = arg(y + jsin(φ)) can take values ​​from 0 to π [rad] under the condition that sin(φ) ≠ 0. Also, if we consider the case where the polarity of B is reversed, it is clear that ρ = arg(x + cos(φ) + jsin(φ)) = arg(y + jsin(φ)) can take values ​​from -π to 0 [rad]. In other words, according to this embodiment, it is possible to output a signal in which the input sine wave has been adjusted to an arbitrary phase.

[0035] Figure 2 shows the results of circuit simulation confirming that the phase of the sine wave changes due to the phase adjustment circuit of this embodiment. Here, the frequency of the sine wave 20 input from the clock generation unit 1 is set to 50 GHz (period 20 ps), and the values ​​of amplitudes A and B in equations (4) to (7) are changed by varying the control voltage (gain) of variable amplifiers 20-1 and 20-2, resulting in sine waves 21 and 22 with a phase change of approximately 4 ps. Note that in the example in Figure 2, adjustment to equalize the amplitudes of sine waves 20 to 22 was not performed in order to make the phase change easier to understand.

[0036] In this embodiment, although it is necessary to create a difference in propagation speed between the common-mode signal and the differential signal, the type and structure of the transmission lines 40-1 and 40-2 are not limited. That is, coplanar lines or microstrip lines may be used as transmission lines 40-1 and 40-2.

[0037] Furthermore, the length L of transmission lines 40-1 and 40-2 is (L / v d )ω-(L / v c When ω = πn (where n is any integer), there is no phase difference between sinωt and sin(ωt + φ), so phase adjustment cannot be achieved. In other words, when φ = π, it simply becomes -sin, and only the sign of B changes without any phase difference. Therefore, the phase adjustment circuit of this embodiment is designed so that equation (8) holds true at the highest expected frequency of the sinusoidal signal to be phase-adjusted.

[0038]

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[0039] By designing the circuit so that equation (8) holds true, it is possible to design it so that a phase difference always occurs between sinωt and sin(ωt+φ) within the frequency range used. In the range where equation (8) holds true, the transmission line length can be minimized, thereby reducing circuit area and cost.

[0040] [Second Example] Next, a second embodiment of the present invention will be described. This embodiment shows a specific example of the termination circuit 5 of the first embodiment. As shown in Figure 3, the termination circuit 5 consists of a resistor R1 with one end connected to the termination of transmission line 40-1, a resistor R2 with one end connected to the termination of transmission line 40-2, and a resistor R3 with one end connected to the connection point of resistors R1 and R2 and the other end connected to a fixed potential VTT.

[0041] In the first embodiment, since both common-mode and differential signals are transmitted using the differential transmission line 4, it is necessary to set the impedance for each signal. The T-type termination circuit 5 shown in Figure 3 allows the impedance to be set for each signal mode. While the resistor R3 of the termination circuit 5 may be connected to ground, it may also be connected to a fixed potential VTT other than ground, as shown in the example in Figure 3, depending on the bias point of the summing unit 3.

[0042] [Third embodiment] Next, a third embodiment of the present invention will be described. This embodiment shows a specific example of the adder 3 and variable amplifier 2 of the first embodiment. As shown in Figure 4, the adder 3 includes an NPN bipolar transistor Q1 to which the inverse-phase signal IN3n of the differential clock signal output from the variable amplifier 2 is input to the base and the positive-phase signal OUT3p of the differential signal is output from the collector; an NPN bipolar transistor Q2 to which the positive-phase signal IN3p of the differential clock signal output from the variable amplifier 2 is input to the base and the inverse-phase signal OUT3n of the differential signal is output from the collector; an NPN bipolar transistor Q3 to which the common-mode signal IN4 of the variable amplifier 2 is input to the base; a resistor R4 with one end connected to the power supply voltage VCC; and a resistor with one end connected to the other end of resistor R4 and the other end connected to the collector of transistor Q1. It consists of resistor R5 connected to the other end, resistor R6 whose one end is connected to the other end of resistor R4 and whose other end is connected to the collector of transistor Q2, resistor R7 whose one end is connected to the emitter of transistor Q1 and whose other end is connected to the collector of transistor Q3, resistor R8 whose one end is connected to the emitter of transistor Q2 and whose other end is connected to the collector of transistor Q3, resistor R9 whose one end is connected to the power supply voltage VCC and whose other end is connected to the base of transistor Q3, resistor R10 whose one end is connected to the base of transistor Q3 and whose other end is connected to ground, and resistor R11 whose one end is connected to the emitter of transistor Q3 and whose other end is connected to ground.

[0043] Transistor Q3 is a tail current source that supplies current to transistors Q1 and Q2, and requires an appropriate bias voltage. In the example in Figure 4, the bias voltage for the tail current source is generated by a resistive voltage divider circuit consisting of resistors R9 and R10.

[0044] Gilbert cells can be used as variable amplifiers 20-1 and 20-2. As shown in Figure 5, variable amplifier 20-1 includes an NPN bipolar transistor Q4 to which a gain control signal IN1n is input to the base and which outputs the positive-phase signal OUT2p of the differential clock signal from the collector; an NPN bipolar transistor Q5 to which a gain control signal IN1p is input to the base and which outputs the negative-phase signal OUT2n of the differential clock signal from the collector; an NPN bipolar transistor Q6 to which a gain control signal IN1n is input to the base and which outputs the negative-phase signal OUT2n of the differential clock signal from the collector; an NPN bipolar transistor Q7 to which a gain control signal IN1p is input to the base and which outputs the positive-phase signal OUT2p of the differential clock signal from the collector; and an NPN bipolar transistor to which the positive-phase signal IN2p of the differential clock signal output from the clock generation unit 1 is input to the base and whose collector is connected to the emitters of transistors Q4 and Q5. It consists of Q8, an NPN bipolar transistor Q9 to which the inverse phase signal IN2n of the differential clock signal output from the clock generation unit 1 is input to the base and whose collector is connected to the emitters of transistors Q6 and Q7, an NPN bipolar transistor Q10 to which a bias voltage VB is applied to the base, a resistor R12 with one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q4 and Q7, a resistor R13 with one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q5 and Q6, a resistor R14 with one end connected to the emitter of transistor Q8 and the other end connected to the collector of transistor Q10, a resistor R15 with one end connected to the emitter of transistor Q9 and the other end connected to the collector of transistor Q10, and a resistor R16 with one end connected to the emitter of transistor Q10 and the other end connected to ground. The gain of the variable amplifier 20-1 can be controlled by the voltage difference between the gain control signals IN1p and IN1n.

[0045] As shown in Figure 6, the variable amplifier 20-2 includes an NPN bipolar transistor Q11 to which a gain control signal IN5n is input to the base and which outputs a common-mode signal OUT4 from the collector; an NPN bipolar transistor Q12 to which a gain control signal IN5p is input to the base; an NPN bipolar transistor Q13 to which a gain control signal IN5n is input to the base; an NPN bipolar transistor Q14 to which a gain control signal IN5p is input to the base and which outputs a common-mode signal OUT4 from the collector; an NPN bipolar transistor Q15 to which the positive-phase signal IN2p of the differential clock signal output from the clock generation unit 1 is input to the base and whose collector is connected to the emitters of transistors Q11 and Q12; and an NPN bipolar transistor Q15 to which the negative-phase signal IN2n of the differential clock signal output from the clock generation unit 1 is input to the base. The circuit is powered by an NPN bipolar transistor Q16 whose collector is connected to the emitters of transistors Q13 and Q14, an NPN bipolar transistor Q17 with a bias voltage VB applied to its base, a resistor R17 with one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q11 and Q14, a resistor R18 with one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q12 and Q13, a resistor R19 with one end connected to the emitter of transistor Q15 and the other end connected to the collector of transistor Q17, a resistor R20 with one end connected to the emitter of transistor Q16 and the other end connected to the collector of transistor Q17, and a resistor R21 with one end connected to the emitter of transistor Q17 and the other end connected to ground.

[0046] The gain of the variable amplifier 20-1 can be controlled by the voltage difference between the gain control signals IN5p and IN5n. As shown in Figure 6, in the case of a single-phase output variable amplifier 20-2, the common-mode signal OUT4 can be output instead of the positive-phase signal OUT2p of the differential clock signal in Figure 5, and the output terminal of the negative-phase signal OUT2n can be left open or connected to a dummy load.

[0047] Note that Figures 4 to 6 show examples using bipolar transistors as transistors Q1 to Q17, but MOS transistors may also be used. When using MOS transistors, simply replace the base with the gate, the collector with the drain, and the emitter with the source in the above explanation.

[0048] Furthermore, a resistor or capacitance may be inserted between the emitter or source of the transistor for gain adjustment or frequency response adjustment, or both a resistor and a capacitance may be inserted. Additionally, any amplification circuit, such as an emitter follower, can be provided as needed for level adjustment or other purposes.

[0049] [Fourth embodiment] Next, a fourth embodiment of the present invention will be described. This embodiment shows a specific example of the differential transmission line 4 of the first embodiment. As described above, the differential transmission line 4 must have a structure in which a difference in propagation speed occurs between the differential mode and the in-phase mode. To generate a difference in propagation speed between the differential mode and the in-phase mode, it is more efficient to have electromagnetic field coupling between the differential ports.

[0050] Therefore, the differential transmission line 4 used in the present invention is preferably configured such that the transmission lines 40-1 and 40-2 are adjacent to each other so as to be electromagnetically coupled, without a ground plane being placed between them.

[0051] Cross-sectional views of differential transmission lines 4 are shown in Figures 7A to 7C. The example in Figure 7A shows an example of a microstrip line. Transmission line 40-1 consists of a dielectric 400, a signal line 401 consisting of a conductor formed on the surface of the dielectric 400, and a ground plane 403 consisting of a conductor formed on the back surface of the dielectric 400. Transmission line 40-2 consists of a dielectric 400, a signal line 402 consisting of a conductor formed on the surface of the dielectric 400, and a ground plane 403.

[0052] Figure 7B shows an example of a coplanar transmission line. Transmission line 40-1 consists of a dielectric 400, a signal line 401, and a ground plane 404 consisting of a conductor formed on the surface of the dielectric 400 opposite the signal line 402, with the signal line 401 in between. Transmission line 40-2 consists of a dielectric 400, a signal line 402, and a ground plane 405 consisting of a conductor formed on the surface of the dielectric 400 opposite the signal line 401, with the signal line 402 in between.

[0053] The example in Figure 7C shows an example of a coplanar transmission line with back-surface grounding that combines the structures of Figure 7A and Figure 7B. Transmission line 40-1 consists of a dielectric 400, a signal line 401, and ground planes 403 and 404. Transmission line 40-2 consists of a dielectric 400, a signal line 402, and ground planes 403 and 405.

[0054] In the examples shown in Figures 7A to 7C, signal lines 401 and 402 are laid out side by side, but they can also be stacked vertically to create a structure that strengthens the connection between signal lines 401 and 402. Furthermore, it is not necessary to provide the ground planes 403 to 405 shown in Figures 7A to 7C. However, since the present invention requires the transmission of common-mode signals as well, providing at least one ground plane to the side or above and below the signal lines 401 and 402 simplifies the impedance design.

[0055] [Fifth Example] Next, a fifth embodiment of the present invention will be described. Figure 8 is a block diagram showing the configuration of a phase adjustment circuit according to the fifth embodiment of the present invention. The phase adjustment circuit of this embodiment is obtained by adding a level adjustment unit 6 to the output terminal of the phase adjustment circuit of the first embodiment.

[0056] The output amplitude of the phase adjustment circuit of the present invention changes in principle according to the adjusted phase. For this reason, a level adjustment unit 6 may be provided to correspond to the changing output amplitude. The level adjustment unit 6 may be a VGA (Variable Gain Amplifier) ​​capable of adjusting the output amplitude, or an AGC (Automatic Gain Control) circuit that automatically adjusts the output amplitude. The configuration of the VGA or AGC circuit is not limited. When using an AGC circuit, a peak detector or power detector is connected to the output terminal of the phase adjustment circuit (the end of the transmission line 40-1 or 40-2), and the detection result is fed back to the amplifier to adjust the gain. [Industrial applicability]

[0057] This invention can be applied to techniques for adjusting the phase of a sine wave. [Explanation of Symbols]

[0058] 1...Clock generation unit, 2, 20-1, 20-2...Variable amplifier, 3...Adder, 4...Differential transmission line, 5...Termination circuit, 6...Level adjustment unit, 30-1, 30-2...Adder, 40-1, 40-2...Transmission line, 400...Dielectric, 401, 402...Signal line, 403~405...Ground plane, Q1~Q17...Transistor, R1~R21...Resistor.

Claims

1. A clock generation unit configured to generate a sinusoidal clock signal, A variable amplifier is configured to take the clock signal output from the clock generation unit as input, output an amplitude-adjusted sinusoidal differential clock signal, and simultaneously output an amplitude-adjusted common-mode signal. An adder is configured to output a differential signal obtained by adding the in-phase signal to both the positive-phase and negative-phase sides of the differential clock signal output from the variable amplifier, respectively. A differential transmission line configured to transmit the differential signal output from the summing unit, The differential transmission line is terminated by a termination circuit configured to terminate the differential transmission line, The aforementioned in-phase signal is a single-phase signal that is added in common to both the positive-sequence and negative-sequence sides of the differential clock signal. The differential transmission line is one in which the positive-phase transmission line and the negative-phase transmission line are electromagnetically coupled. A phase adjustment circuit characterized by outputting a signal from the termination of either the positive-phase transmission line or the negative-phase transmission line that constitutes the differential transmission line.

2. In the phase adjustment circuit according to claim 1, The termination circuit is, A first resistor, one end of which is connected to the end of the positive-sequence transmission line, A second resistor, one end of which is connected to the termination of the transmission line on the opposite phase side, A phase adjustment circuit characterized by comprising a third resistor, one end of which is connected to the connection point of the first and second resistors, and the other end of which is connected to a fixed potential or ground.

3. In the phase adjustment circuit according to claim 1 or 2, The aforementioned variable amplifier is A first variable amplifier of the Gilbert cell type adjusts the amplitude of the clock signal output from the clock generation unit to output the differential clock signal, A phase adjustment circuit characterized by comprising a second variable amplifier of the Gilbert cell type that adjusts the amplitude of the clock signal output from the clock generation unit to output the common-mode signal.

4. In the phase adjustment circuit according to any one of claims 1 to 3, A phase adjustment circuit characterized in that the positive-phase transmission line and the negative-phase transmission line constituting the differential transmission line are arranged adjacent to each other.

5. In the phase adjustment circuit according to any one of claims 1 to 4, The lengths L of the positive-phase transmission line and the negative-phase transmission line constituting the differential transmission line are such that the propagation speed of the differential transmission line for the differential mode is v ｄ The propagation speed for the in-phase mode is v ｃ When ω is the highest angular frequency of the sinusoidal clock signal to be phase-adjusted, [Math 1] A phase adjustment circuit characterized by being set to satisfy the following conditions.

6. In the phase adjustment circuit according to any one of claims 1 to 5, A phase adjustment circuit further comprising a level adjustment unit configured to adjust the amplitude of a signal output from either the positive-phase transmission line or the negative-phase transmission line that constitutes the differential transmission line.

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