Semiconductor equipment

Abstract

The present invention provides a semiconductor device that is provided with a transistor part and a diode part, which are arranged to be side by side in a first direction. This semiconductor device comprises a first mesa part and a second mesa part that is disposed to be more distant from the diode part than the first mesa part. The first mesa part has a first region which has a first conductivity type and is at least partially provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench part. The second mesa part has a second region which has the first conductivity type and a higher dose than the first region, and is at least partially provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench part.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] In semiconductor devices having transistor and diode sections, a structure is known in which defect regions are partially formed in the diode and transistor sections to adjust the carrier lifetime (see, for example, Patent Document 1). Also, in semiconductor devices, a structure is known in which electrodes and semiconductor substrates are connected by trench-shaped contacts (see, for example, Patent Document 2). Patent Document 1 WO2021 / 145079 Patent Document 2: Problems to be solved by Patent No. 7085975

[0003] In a semiconductor device comprising a transistor section and a diode section, it is preferable to improve characteristics such as the reverse recovery loss of the diode section or the threshold voltage of the transistor section. General Disclosure

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, a transistor portion provided on the semiconductor substrate, and a diode portion provided on the semiconductor substrate and arranged alongside the transistor portion in a first direction. In the above semiconductor device, each of the transistor portion and the diode portion may have a plurality of trench portions provided from the upper surface to the interior of the semiconductor substrate and arranged side by side in the first direction, and a plurality of mesa portions of the semiconductor substrate that are sandwiched between two of the trench portions in the first direction. In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type and a base region of a second conductivity type arranged between the drift region and the upper surface. In any of the above semiconductor devices, the plurality of mesa portions may include a first mesa portion and a second mesa portion arranged further away from the diode portion than the first mesa portion. In any of the above semiconductor devices, the first mesa portion may have a first region of a first conductivity type, provided in at least a portion between the depth position of the lower end of the base region and the depth position of the lower end of the trench portion. In any of the above semiconductor devices, the second mesa portion may have a second region of a first conductivity type having a larger dose than the first region, provided in at least a portion between the depth position of the lower end of the base region and the depth position of the lower end of the trench portion.

[0005] In any of the above semiconductor devices, the first region may be the drift region.

[0006] In any of the above-described semiconductor devices, the first region may be a region with a higher doping concentration than the drift region.

[0007] In any of the semiconductor devices described above, the diode portion may be located on the upper surface side of the semiconductor substrate and may have a lifetime adjustment region that includes a lifetime killer for adjusting the lifetime of carriers.

[0008] In any of the above semiconductor devices, the lifetime adjustment region may extend below the first mesa portion.

[0009] In any of the above semiconductor devices, the plurality of mesa portions may include one or more of the second mesa portions. In any of the above semiconductor devices, the lifetime adjustment region may extend below at least one of the second mesa portions.

[0010] In any of the above semiconductor devices, the lifetime adjustment region may be located away from the second mesa portion in the first direction.

[0011] In any of the above semiconductor devices, the doping concentration in the second region may be higher than that in the first region.

[0012] In any of the above semiconductor devices, the number of doping concentration peaks in the depth direction of the second region may be greater than the number of doping concentration peaks in the depth direction of the first region.

[0013] In any of the above semiconductor devices, the width in the depth direction of the second region may be greater than the width in the depth direction of the first region.

[0014] In any of the above semiconductor devices, the dose per unit area of ​​the second region may be greater than the dose per unit area of ​​the first region.

[0015] In any of the semiconductor devices described above, the plurality of mesa portions may include a third mesa portion disposed in the diode portion.

[0016] In any of the semiconductor devices described above, the third mesa portion may have a second-conductivity-type anode region disposed between the drift region and the upper surface. In any of the semiconductor devices described above, the third mesa portion may have a first-conductivity-type third region provided in at least a part between the depth position of the lower end of the anode region and the depth position of the lower end of the trench portion. In any of the semiconductor devices described above, the second region may have a larger doping amount than the third region.

[0017] In any of the semiconductor devices described above, each of the transistor portion and the diode portion may have a metal electrode provided above the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the first mesa portion may have a first contact portion with which the metal electrode contacts. In any of the semiconductor devices described above, the second mesa portion may have a second contact portion with which the metal electrode contacts. In any of the semiconductor devices described above, the lower end of the second contact portion may be disposed above the lower end of the first contact portion.

[0018] In any of the semiconductor devices described above, each of the transistor portion and the diode portion may have a metal electrode provided above the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the first mesa portion may have a first contact portion with which the metal electrode contacts. In any of the semiconductor devices described above, the second mesa portion may have a second contact portion with which the metal electrode contacts. In any of the semiconductor devices described above, the lower end of the first contact portion may be disposed above the lower end of the second contact portion.

[0019] The summary of the invention above does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0020] [Figure 1] It is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2]This is a magnified view of region D in Figure 1. [Figure 3A] Figure 2 shows an example of an ee cross-section. [Figure 3B] This figure shows another example of the ee section in Figure 2. [Figure 3C] This figure shows another example of the ee section in Figure 2. [Figure 3D] This figure shows another example of the ee section in Figure 2. [Figure 3E] This figure shows another example of the ee section in Figure 2. [Figure 3F] This figure shows another example of the ee section in Figure 2. [Figure 4A] Figure 2 shows an example of an ff cross-section. [Figure 4B] Figure 2 shows an example of an ff cross-section. [Figure 4C] This figure shows an example of an ff cross-section. [Figure 4D] This figure shows an example of an ff cross-section. [Figure 4E] This figure shows an example of an ff cross-section. [Figure 4F] This figure shows an example of an ff cross-section. [Figure 5] Figure 3A shows an example of the doping concentration distribution along the r-r' and s-s' lines. [Figure 6] This figure shows other examples of doping concentration distributions along the r-r' and s-s' lines. [Figure 7] This figure shows another example of an ee section. [Figure 8A] This is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 8B] This is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 9] Figure 2 shows an example of an ff cross-section. [Figure 10A] Figure 9 shows an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 10B] Figure 9 shows an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 11A] This figure shows an example of the doping concentration distribution along the a-a' and b-b' lines in Figure 10. [Figure 11B] This figure shows an example of the doping concentration distribution along the a-a' and b-b' lines in Figure 10. [Figure 12A] Figure 9 is an enlarged view of the area around the first contact portion 211. [Figure 12B] Figure 9 is an enlarged view of the area around the second contact portion 212. [Figure 13] This figure shows another example of an ee section. [Figure 14] This figure shows an example of the arrangement of the adjustment area 201 and the non-adjustment area 202 in a top view. [Figure 15] This figure shows another example of an ee section. [Figure 16] This is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 17] Figure 2 shows an example of an ff cross-section. [Figure 18] Figure 17 is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63 shown. [Figure 19A] Figure 18 shows an example of the doping concentration distribution along the a-a' and b-b' lines. [Figure 19B] Figure 18 shows an example of the doping concentration distribution along the a-a' and b-b' lines. [Figure 20A] This is an enlarged view of the area around the first contact portion 211 shown in Figure 16. [Figure 20B] This is an enlarged view of the area around the second contact portion 212 shown in Figure 16. [Figure 21A] This figure shows another example of an ee section. [Figure 21B] This figure shows another example of an ee section. [Figure 21C] This figure shows another example of an ee section. [Figure 22] This figure shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 23] Figure 22 shows an example of the doping concentration distribution along the gg and hh lines. [Figure 24] This figure shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 25] Figure 24 shows an example of the doping concentration distribution along the gg and hh lines. [Figure 26] This figure shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 27] Figure 26 shows an example of the doping concentration distribution along the gg and hh lines. [Figure 28] This figure shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 29] Figure 28 shows an example of the doping concentration distribution along the gg and hh lines. [Figure 30] This figure shows another example of an ee section. [Figure 31] This figure shows another example of an ee section. [Figure 32] This figure shows another example of an ee section. [Figure 33] This figure shows another example of an ee section. [Figure 34] This figure shows another example of an ee section. [Figure 35] This figure shows another example of an ee section. [Figure 36] This figure shows another example of an ee section. [Figure 37] This figure shows another example of an ee section. [Figure 38] This figure shows another example of an ee section. [Figure 39] This figure shows another example of an ee section. [Figure 40] This figure shows another example of an ee section. [Figure 41] This figure shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 42] This figure shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Figure 43] This figure shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. [Modes for carrying out the invention]

[0021] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0022] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0023] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0024] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0025] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0026] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0027] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0028] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0029] The donor has the function of supplying electrons to the semiconductor. The acceptor has the function of receiving electrons from the semiconductor. The donor and acceptor are not limited to the impurities themselves. For example, the VOH defect formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) present in the semiconductor functions as a donor that supplies electrons. The hydrogen donor may be at least a donor in which vacancies (V) and hydrogen (H) are combined. Alternatively, the interstitial Si-H formed by the combination of interstitial silicon (Si-i) and hydrogen in the silicon semiconductor also functions as a donor that supplies electrons. In this specification, the VOH defect or interstitial Si-H may be referred to as a hydrogen donor.

[0030] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors by dopants that were contained substantially uniformly in the ingot during the production of the ingot from which the semiconductor substrate originated. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also included in the P-type regions. The semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3The oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of that chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doped substrate may be, for example, 1 × 10⁻⁶. 10 / cm 3 The above 5 x 10 12 / cm 3 The following applies: The bulk donor concentration (D0) of the non-doped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 That concludes the explanation. The bulk donor concentration (D0) of the non-doped substrate is preferably 5 × 10⁻⁶. 12 / cm 3 The following applies. Note that the concentrations in this invention may be values ​​at room temperature. For example, the values ​​at room temperature may be those at 300 K (Kelvin) (approximately 26.9°C).

[0031] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0032] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0033] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0034] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0035] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which also acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0036] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0037] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "top view," it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0038] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160.

[0039] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor), and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined first direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). A boundary region is located between the transistor section 70 and the diode section 80 in the X-axis direction, but it is omitted in Figure 1.

[0040] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, a direction different from the first direction in a top view may be referred to as the second direction (Y-axis direction in Figure 1). The second direction may be perpendicular to the first direction. The transistor section 70 and the diode section 80 may each have their longitudinal length in the second direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The second direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section and the longitudinal direction of the mesa section, which will be described later.

[0041] The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0042] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0043] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0044] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is shown with diagonal hatching.

[0045] The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0046] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like, or a wiring formed from a semiconductor such as polysilicon doped with impurities.

[0047] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0048] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be metal wiring containing aluminum or the like, or wiring formed from a semiconductor such as polysilicon doped with impurities.

[0049] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0050] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0051] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0052] Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. Although omitted in Figure 1, a boundary region 200 is located between the transistor section 70 and the diode section 80 in the X-axis direction. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a metal electrode. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0053] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines.

[0054] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive part in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive part of the dummy trench 30 at its tip in the Y-axis direction. The dummy conductive part of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive part, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive part.

[0055] The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0056] The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug portion formed by embedding tungsten or the like in contact with the barrier metal and the aluminum or the like within the contact hole.

[0057] The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+-type.

[0058] Each of the transistor section 70, the diode section 80, and the boundary region 200 has multiple trench sections arranged in a first direction. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the first direction. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the first direction. In this example, the diode section 80 does not have gate trench sections 40. In this example, the boundary region 200 has multiple dummy trench sections 30 provided along the first direction. In this example, the boundary region 200 does not have gate trench sections 40.

[0059] The gate trench section 40 in this example may have two straight sections 39 (the trench section which is linear along the second direction) extending along a second direction perpendicular to the first direction, and a tip section 41 connecting the two straight sections 39. In Figure 2, the second direction is the Y-axis direction.

[0060] Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated.

[0061] In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in a second direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0062] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0063] In the first direction, mesa portions 60 are provided between each trench portion. The mesa portion 60 refers to the region sandwiched between the trench portions within the semiconductor substrate 10. For example, the upper end of the mesa portion 60 is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion 60 is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the second direction (Y-axis direction). The mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200 may have different structures. In this specification, when simply referred to as the mesa portion 60, it refers to the mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200, respectively.

[0064] Each mesa portion 60 is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the second direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0065] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0066] Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the second direction (Y-axis direction) of the trench portion.

[0067] In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region adjacent to the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0068] The diode section 80 and the mesa section 60 of the boundary region 200 do not have an emitter region 12. Base regions 14 and contact regions 15 may be provided on the upper surfaces of the diode section 80 and the mesa section 60 of the boundary region 200. Contact regions 15 may be provided in contact with each base region 14-e in the region sandwiched between the base regions 14-e on the upper surface of the mesa section 60. Base regions 14 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa section 60 of the diode section 80. The base regions 14 may be arranged throughout the entire region sandwiched between the contact regions 15. The mesa section 60 of the boundary region 200 may have the same structure as the mesa section 60 of the diode section 80, or it may have a different structure. In this example, the mesa section 60 of the boundary region 200 has contact regions 15 provided throughout the entire region sandwiched between the base regions 14-e. In other words, the area of ​​the contact region 15 of the mesa portion 60 of the boundary region 200 can be larger than the area of ​​the contact region 15 of the mesa portion 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 can be more easily drawn to the emitter electrode 52 via the mesa portion 60 of the boundary region 200.

[0069] In other examples, the mesa region 60 of the boundary region 200 may be a P-type impurity region with a doping concentration similar to or lower than that of the base region 14 of the transistor region 70. The P-type impurity region may occupy the entire mesa region 60 of the boundary region 200, and other regions may be provided in the mesa region 60 of the boundary region 200. By providing a P-type impurity region with a doping concentration lower than that of the base region 14 in the mesa region 60 of the boundary region 200, hole injection from the mesa region 60 of the boundary region 200 can be suppressed, and the reverse recovery loss can be reduced.

[0070] Furthermore, an N-type impurity region with a doping concentration similar to or lower than that of the emitter region 12 may be provided in the mesa portion 60 of the boundary region 200. However, in this case, the gate trench portion 40 is not provided in the boundary region 200. Also, the trench portion at the boundary between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. Since the N-type impurity region of the mesa portion 60 of the boundary region 200 is not in contact with the gate trench portion 40, the boundary region 200 does not have a greater current flowing through it than the transistor portion 70. As a result, the injection of holes from the mesa portion 60 of the boundary region 200 is suppressed, and the reverse recovery loss can be reduced.

[0071] A contact hole 54 is provided above each mesa portion 60. The contact hole 54 is located in the region sandwiched between the base region 14-e. In this example, the contact hole 54 is provided above the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be located in the center of the mesa portion 60 in the first direction (X-axis direction).

[0072] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0073] The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 11 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 11 and the contact hole 54.

[0074] Figure 3A shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0075] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0076] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction. The emitter electrode 52 may have a titanium-containing barrier metal in the portion that contacts the upper surface 21 of the semiconductor substrate 10. The barrier metal may have a titanium nitride layer, or it may have a laminated structure of a titanium nitride layer and a titanium layer. The emitter electrode 52 may have a plug portion made of tungsten or the like that is filled inside the contact hole 54. The plug portion may also be provided in the trench contact portion described later.

[0077] The semiconductor substrate 10 has N-type or N-type drift regions 18. The drift regions 18 are provided in the transistor section 70, the diode section 80, and the boundary region 200, respectively.

[0078] In this example, the multiple mesa sections 60 include one or more first mesa sections 61, one or more second mesa sections 62, one or more third mesa sections 63, and one or more fourth mesa sections 64. The first mesa sections 61 and 2 mesa sections 62 are provided in the transistor section 70, the third mesa section 63 is provided in the diode section 80, and the fourth mesa section 64 is provided in the boundary region 200. The second mesa section 62 is located further away from the diode section 80 than the first mesa section 61.

[0079] In the first mesa portion 61 and the second mesa portion 62 of the transistor portion 70, an N+ type emitter region 12 and a P type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14.

[0080] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0081] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the first mesa portion 61 and the second mesa portion 62.

[0082] A P-type base region 14 is provided in the third mesa portion 63 of the diode portion 80, in contact with the upper surface 21 of the semiconductor substrate 10. In this specification, the base region 14 of the third mesa portion 63 may be referred to as the anode region. The doping concentration of the base region 14 of the third mesa portion 63 may be the same as, or lower than, the doping concentration of the base regions 14 of the first mesa portion 61 and the second mesa portion 62. A drift region 18 is provided below the base region 14.

[0083] In this example, a P+ type contact region 15 is provided in the fourth mesa portion 64 of the boundary region 200, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the contact region 15. A base region 14 may be provided between the contact region 15 and the drift region 18.

[0084] In each of the transistor section 70, the diode section 80, and the boundary region 200, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. In addition, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is almost flat.

[0085] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0086] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0087] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration in the cathode region 82 is higher than that of the drift region 18. The donor in the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that act as donors and acceptors in each region are not limited to the examples described above.

[0088] In the boundary region 200, a P+ type collector region 22 is provided below the buffer region 20. The collector region 22 of the boundary region 200 is the transistor section 70 Collector area 22It may have the same doping concentration. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 may be the boundary position in the X-axis direction between the diode section 80 and the boundary region 200. In other examples, in the boundary region 200, part or all of the collector region 22 may be replaced with the cathode region 82. If the cathode region 82 is provided on the lower surface of the boundary region 200, the region sandwiched between the base regions 14-e in which the contact region 15 and the base region 14 are alternately arranged may be considered as the diode section 80, and the region sandwiched between the base regions 14-e in which the contact region 15 is arranged throughout may be considered as the boundary region 200. If the cathode region 82 is provided on the lower surface of the boundary region 200, the boundary region 200 may be considered as part of the diode section 80.

[0089] Of the gate trenches 40 that are in contact with the emitter region 12, the gate trench 40 that is closest to the diode region 80 in the X-axis direction is set as the boundary position in the X-axis direction between the transistor region 70 and the boundary region 200 (or diode region 80). The central position of this gate trench 40 in the X-axis direction may be set as the boundary position in the X-axis direction between the transistor region 70 and the boundary region 200 (or diode region 80). Of the two trenches in contact with the emitter region 12 that are closest to the diode region 80 in the X-axis direction, the trench on the diode region 80 side may be a dummy trench 30. In this case, the dummy trench 30 may be set as the boundary position in the X-axis direction between the transistor region 70 and the boundary region 200 (or diode region 80).

[0090] An emitter region 12 may be provided in the boundary region 200. However, in that case, the gate trench 40 is not provided in the boundary region 200. Also, the trench at the boundary position between the transistor 70 and the boundary region 200 is a dummy trench 30. That is, no transistor operation occurs in the boundary region 200. A gate trench 40 may be provided in the boundary region 200. However, in that case, the emitter region 12 is not provided in the boundary region 200. That is, no transistor operation occurs in the boundary region 200.

[0091] The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a metallic material such as aluminum.

[0092] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12 and the contact region 15 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0093] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. In this example, the diode section 80 and the boundary region 200 are provided with a dummy trench section 30, but the gate trench section 40 is not provided. However, the boundary between the boundary region 200 and the transistor section 70 may have a gate trench section 40, or a dummy trench section 30.

[0094] The boundary region 200 is a buffer structure for arranging the different structures of the transistor section 70 and the diode section 80 in parallel. Therefore, the width of the boundary region 200 in the X-axis direction may be short. For example, one or more fourth mesa sections 64 may be provided in the boundary region 200, and the boundary region 200 may not be provided at all.

[0095] Furthermore, the boundary region 200 may include multiple fourth mesa sections 64 in the X-axis direction. This makes it possible to suppress the influence of the transistor section 70 on the characteristics of the diode section 80, for example, the operation of the gate trench section 40 and the discharge or injection of holes in the contact region 15 on the forward voltage and reverse recovery characteristics. Here, the number of mesa sections refers to the number of mesa sections arranged in a line in the X-axis direction.

[0096] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0097] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0098] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0099] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0100] The semiconductor device 100 in this example includes a lifetime adjustment region 206 that includes a lifetime killer to adjust the lifetime of carriers. The lifetime adjustment region 206 in this example is a region where the lifetime of charge carriers is locally short. Charge carriers are electrons or holes. Charge carriers are sometimes simply referred to as carriers. The lifetime adjustment region 206 in this example is formed by injecting charged particles such as helium ions from the upper surface 21 of the semiconductor substrate 10. In this example, the concentration distribution of helium, etc., in the depth direction of the semiconductor substrate 10 may have a shape that extends from the lifetime adjustment region 206 to the upper surface 21 of the semiconductor substrate 10. That is, from the lifetime adjustment region 206 to the upper surface 21, the concentration of helium, etc. ( / cm³) 3The concentration of helium, etc., on the upper surface 21 may decrease monotonically. The concentration of helium, etc., on the upper surface 21 may be greater than 0. On the other hand, in the direction from the lifetime adjustment region 206 toward the lower surface 23, the concentration of helium, etc., may have a shape that trails downwards. However, the concentration of helium, etc., decreases more steeply toward the lower surface 23 than toward the upper surface 21. The concentration of helium, etc., on the lower surface 23 is lower than the concentration of helium, etc., on the upper surface 21. The concentration of helium, etc., on the upper surface 21 may be below the detection limit, or may be 0. The lifetime adjustment region 206 may be formed by injecting charged particles such as helium ions from the lower surface 23 side of the semiconductor substrate 10.

[0101] By implanting charged particles such as helium ions into a semiconductor substrate 10, lattice defects 204, such as vacancies, are formed near the implantation site. These lattice defects 204 generate recombination centers. The lattice defects 204 may be mainly vacancies, such as single-atom vacancies (V) or double-atom vacancies (VV), but may also be dislocations, interstitial atoms, or transition metals. For example, atoms adjacent to a vacancy have dangling bonds. In a broad sense, lattice defects 204 may also include donors and acceptors, but in this specification, lattice defects 204 mainly consisting of vacancies may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, lattice defects 204 may be referred to simply as recombination centers or lifetime killers, as they contribute to carrier recombination. Lifetime killers may be formed by implanting helium ions into the semiconductor substrate 10. The helium chemical concentration may be used as the density of lattice defects 204. Furthermore, since the lifetime killer formed by the helium ion implantation may be terminated by hydrogen present in the buffer region 20, the depth position of the lifetime killer density peak may not coincide with the depth position of the helium chemical concentration peak. In addition, when hydrogen ions are implanted into the semiconductor substrate 10, the lifetime killer may be formed in the hydrogen ion passage region on the implantation surface side of the range.

[0102] Lattice defects 204 are an example of lifetime killers. In Figure 3A, lattice defects 204 at the injection site of charged particles are schematically shown with an "x". In regions where many lattice defects 204 remain, carriers are trapped by the lattice defects 204, thus shortening the carrier lifetime. By adjusting the carrier lifetime, characteristics such as the reverse recovery time and reverse recovery loss of the diode section 80 can be adjusted. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime shows a minimum value may be set as the depth position of the lifetime adjustment region 206.

[0103] The lifetime adjustment region 206 is located on the upper surface 21 side of the semiconductor substrate 10. The upper surface 21 side is the region from the central position in the depth direction of the semiconductor substrate 10 to the upper surface 21 of the semiconductor substrate 10. In this example, the lifetime adjustment region 206 is located below the lower end of the trench.

[0104] Furthermore, when the lifetime adjustment region 206 is formed by irradiation with a highly penetrating particle beam such as an electron beam, lattice defects are formed almost uniformly from the upper surface 21 to the lower surface 23 of the semiconductor substrate 10. In this case as well, the depth position of the lifetime adjustment region 206 can be considered to be located on the upper surface 21 side of the semiconductor substrate 10.

[0105] The lifetime adjustment region 206 is provided in the diode section 80. If the semiconductor device 100 has a boundary region 200, the lifetime adjustment region 206 is also provided in the boundary region 200. The lifetime adjustment region 206 may be provided over the entire diode section 80 in the X-axis direction. The lifetime adjustment region 206 may also be provided over the entire boundary region 200.

[0106] The lifetime adjustment region 206 of the diode section 80 extends in the X-axis direction to a portion of the transistor section 70. The lifetime adjustment region 206 of the diode section 80 and the lifetime adjustment region 206 of the transistor section 70 are located at the same depth. In the transistor section 70, the region where the lifetime adjustment region 206 is provided is designated as the adjustment region 201, and the region where the lifetime adjustment region 206 is not provided is designated as the non-adjustment region 202. The adjustment region 201 is the region that overlaps with the lifetime adjustment region 206 when viewed from above. The non-adjustment region 202 is the region that does not overlap with the lifetime adjustment region 206 when viewed from above. The non-adjustment region 202 is the region where the carrier lifetime at the same depth as the lifetime adjustment region 206 is longer than the carrier lifetime of the lifetime adjustment region 206 of the diode section 80. The non-adjustment region 202 may also be a region where charged particles such as helium ions for forming lifetime killers such as lattice defects 204 have not been implanted. Chemical concentrations of helium, etc. in the unadjusted region 202 ( / cm³) 3 ) may be the same as the chemical concentration of the charged particle at the center of the drift region 18 in the Z-axis direction.

[0107] The adjustment region 201 has one or more first mesa portions 61. The lifetime adjustment region 206 extends from below the diode portion 80 to below the first mesa portions 61. All mesa portions 60 in the adjustment region 201 may be first mesa portions 61. The non-adjustment region 202 has one or more second mesa portions 62. All mesa portions 60 in the non-adjustment region 202 may be second mesa portions 62. The diode portion 80 has one or more third mesa portions 63. All mesa portions 60 in the diode portion 80 may be third mesa portions 63. The boundary region 200 has one or more fourth mesa portions 64. All mesa portions 60 in the boundary region 200 may be fourth mesa portions 64.

[0108] The first mesa portion 61 has an N-shaped first region 301 provided in at least a portion between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion such as the gate trench portion 40. In this specification, the depth position of the lower end of the base region 14 may be referred to as Z14, and the depth position of the lower end of the trench portion may be referred to as Zt. The first region 301 may be provided over the entire area between depth position Z14 and depth position Zt.

[0109] The second mesa section 62 is located at a depth position Z It has an N+ type second region 302 provided between 14 and depth position Zt. The second region 302 may be provided over the entire area between depth position Z14 and depth position Zt. The second region 302 is a region with a higher doping concentration than the first region 301. The first region 301 and the second region 302 may be provided over the entire X-axis direction of each mesa. The first region 301 and the second region 302 may be provided so as to cover the entire lower surface of the base region 14 of each mesa.

[0110] Dosage of N-type dopant in region 2, 302 ( / cm²) 2 ) is greater than the dose amount of N-type dopant in the first region 301. The dose amount in each region may be the value obtained by integrating the doping concentration of each region over a predetermined region in the depth direction. The predetermined region may be an N-type region between the base region 14 and the drift region 18 where the doping concentration is higher than that of the drift region 18. The predetermined region may also be the range of the full width at half maximum of the peak of the N-type doping concentration between the base region 14 and the drift region 18. In this example, the second region 302 is a region with a higher doping concentration than that of the drift region 18. By providing a high-concentration second region 302 between the drift region 18 and the base region 14, the carrier injection promoting effect (IE effect) can be enhanced and the on-voltage can be reduced. The doping concentration in the second region 302 may be 10 times or more, 50 times or more, or 100 times or more than the doping concentration in the drift region 18.

[0111] In this example, the doping concentration in the first region 301 is greater than or equal to the doping concentration in the drift region 18 and less than the doping concentration in the second region 302. The peak values ​​may be used for the doping concentrations in each region. The doping concentration in the first region 301 may be the same as the doping concentration in the drift region 18. In other words, the drift region 18 provided in the first mesa section 61 may be treated as the first region 301. The doping concentration in the first region 301 may be higher than the doping concentration in the drift region 18. The doping concentration in the first region 301 may be half or less of the doping concentration in the second region 302, or it may be 1 / 10 or less, or it may be 1 / 100 or less.

[0112] In the adjustment region 201, charged particles are irradiated from the upper surface 21, forming a lifetime adjustment region 206 (see Figure 3A). On the other hand, irradiation with charged particles can form energy levels in the gate insulating film 42 of the adjustment region 201, causing the threshold voltage (on voltage, off voltage) in the adjustment region 201 to drop below the threshold voltage in the non-adjusted region 202. A decrease in the threshold voltage delays the turn-off timing, so the turn-off of the adjustment region 201 may be delayed compared to the non-adjusted region 202, potentially leading to a current concentration in the adjustment region 201 and a decrease in its withstand capability.

[0113] In this example, the doping concentration in the first region 301 of the adjustment region 201 is lower than that in the second region 302. Therefore, the carrier concentration in the drift region 18 and other areas of the adjustment region 201 is reduced, thereby suppressing the current flowing through the adjustment region 201. Consequently, even if the turn-off of the adjustment region 201 is delayed, the current flowing through the adjustment region 201 is suppressed, thereby preventing a decrease in withstand capability.

[0114] In the example shown in Figure 3A, all mesa portions 60 in the adjustment region 201 are first mesa portions 61, which are provided with a low-concentration first region 301. In other examples, some of the mesa portions 60 in the adjustment region 201 may be second mesa portions 62, which are provided with a high-concentration second region 302. For example, one or more mesa portions 60 in the adjustment region 201 that are closest to the non-adjusted region 202 may be second mesa portions 62. One or more mesa portions 60 in the adjustment region 201 that are closest to the diode portion 80 may be first mesa portions 61.

[0115] The doping concentration in the first region 301 may be the same or different in each first mesa portion 61. For example, the doping concentration in the first region 301 may be higher in the first mesa portion 61 that is closer to the unadjusted region 202.

[0116] The doping concentration in the first region 301 may be adjusted according to the density of lattice defects 204 in the lifetime adjustment region 206 located below it. For example, the higher the density of lattice defects 204 below, the lower the doping concentration in the first region 301 can be. This allows the doping concentration in the first region 301 to be lower in regions with a higher dose of charged particles. Therefore, the lower the threshold voltage of the first mesa section 61, the lower the doping concentration in the first region 301 can be, thereby lowering the carrier concentration. This allows the lower carrier concentration to be lower in the first mesa section 61 where the turn-off is delayed, thereby suppressing current concentration. As an example, the density of lattice defects 204 in the lifetime adjustment region 206 within the adjustment region 201 may decrease as it moves away from the diode section 80. In this case, the further the first mesa section 61 is from the diode section 80, the higher the doping concentration in the first region 301 can be.

[0117] The third mesa section 63 and the fourth mesa section 64 have an N-shaped third region 303 provided between depth position Z14 and depth position Zt. The third region 303 may be provided over the entire area between depth position Z14 and depth position Zt. In this example, the second region 302 may have a larger dose than the third region 303. In this example, the third region 303 is a region with a lower doping concentration than the second region 302. The third region 303 may have a higher doping concentration than the first region 301, the same doping concentration as the first region 301, or a lower doping concentration than the first region 301. In other examples, the third region 303 may have the same doping concentration as the second region 302. The third region 303 may be provided over the entire X-axis direction of each mesa section. The third region 303 may be provided so as to cover the entire lower surface of the base region 14 of each mesa section.

[0118] Figure 3B shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0119] Figure 3B differs from Figure 3A in that it includes a third plug region 223 that covers the bottom of the third contact region 213, which is provided in the third mesa region 63 of the diode region 80 and the fourth mesa region 64 of the boundary region 200. The other structures are the same as those shown in Figure 3A. In this specification, the portion of each mesa region that contacts the emitter electrode 52 may be referred to as the contact region. The contact region of the first mesa region 61 is referred to as the first contact region 211, the contact region of the second mesa region 62 as the second contact region 212, and the contact regions of the third mesa region 63 and the fourth mesa region 64 as the third contact region 213. The third plug region 223 is a P++ type region with a higher doping concentration than the contact region 15.

[0120] Even when the third plug region 223 is provided so as to cover the bottom of the third contact region 213 located in the third mesa region 63 of the diode region 80 and the fourth mesa region 64 of the boundary region 200, as in this example, the same effect as in Figure 3A can be obtained.

[0121] Figure 3C shows another example of the ee section. This example differs from the example shown in Figure 3A in that the lifetime adjustment region 206 extends below at least one second mesa 62. The other structures are the same as those shown in Figure 3A.

[0122] In this example, of the mesa portions 60 in the adjustment region 201, one or more mesa portions 60 closest to the non-adjustment region 202 are second mesa portions 62, and the other mesa portions 60 are first mesa portions 61. In this example, the second region 302 and the lifetime adjustment region 206 partially overlap in a top view. By having first mesa portions 61 in the adjustment region 201, the carrier density in the vicinity of the first mesa portions 61 can be reduced, thereby suppressing a decrease in tolerance. The number of first mesa portions 61 in the adjustment region 201 may be equal to or greater than the number of second mesa portions 62 in the adjustment region 201, and may be greater. Also, one first mesa portion 61 may be placed between two second mesa portions 62 in the adjustment region 201. Furthermore, a second mesa portion 62 may be located on the boundary between the adjustment region 201 and the non-adjustment region 202.

[0123] Figure 3D shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0124] Figure 3D differs from Figure 3C in that it includes a third plug region 223 that covers the bottom of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200. The other structures are the same as those shown in Figure 3C. Even when the third plug region 223 is provided that covers the bottom of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200, as in this example, the same effects as in Figure 3C can be obtained.

[0125] Figure 3E shows another example of the ee section. This example differs from the example shown in Figure 3A in that the second mesa 62 and the second region 302 are located separately from the lifetime adjustment region 206 in the X-axis direction. The other structures are the same as those shown in Figure 3A.

[0126] One or more first mesa portions 61 may be provided between the X-axis end of the lifetime adjustment region 206 and the X-axis end of the second region 302. In this example, one or more mesa portions 60 in the non-adjusted region 202 that are closest to the adjustment region 201 are the first mesa portions 61, and the other mesa portions 60 are the second mesa portions 62. Having one or more first mesa portions 61 in the non-adjusted region 202 ensures a sufficient distance between the lifetime adjustment region 206 and the second region 302, further suppressing the decrease in tolerance. The doping concentration of the first region 301 in the first mesa portion 61 of the non-adjusted region 202 may be the same as, or higher than, the doping concentration of the first region 301 in the first mesa portion 61 of the adjustment region 201. However, the doping concentration in the first mesa portion 61 of the unmodified region 202 is lower than the doping concentration in the second region 302. Furthermore, the first mesa portion 61 may be located on the boundary between the modified region 201 and the unmodified region 202.

[0127] Figure 3F shows another example of the ee cross-section. This example differs from the example shown in Figure 3E in that it includes a third plug region 223 that covers the bottom of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200. The other structures are the same as those shown in Figure 3E. Even when the third plug region 223 is provided that covers the bottom of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200, as in this example, the same effect as in Figure 3E can be obtained.

[0128] Figure 4A shows an example of the ff cross-section in Figure 2. The ff cross-section is the XZ plane passing through the contact region 15 and the cathode region 82. The cross-section in this example has a structure in which the emitter region 12 in the example shown in Figure 3A is replaced with the contact region 15. The structure other than the contact region 15 is the same as in Figure 3A.

[0129] Figure 4B shows an example of the ff cross-section in Figure 2. The ff cross-section is the XZ plane passing through the contact region 15 and the cathode region 82. The cross-section in this example has a structure in which the emitter region 12 in the example shown in Figure 3B is replaced with the contact region 15. The structure other than the contact region 15 is the same as in Figure 3B. Also, as shown in Figure 4B, the first mesa portion 61 may be provided with a first plug region 221 that covers the first contact portion 211. The second mesa portion 62 may be provided with a second plug region 222 that covers the second contact portion 212. The first plug region 221 and the second plug region 222 are P++ type regions with a higher doping concentration than the contact region 15.

[0130] Figure 4C shows an example of an ff cross-section. The cross-section in this example has a structure in which the emitter region 12 in the example shown in Figure 3C is replaced with a contact region 15. The structure other than the contact region 15 is the same as in Figure 3C.

[0131] Figure 4D shows an example of an ff cross-section. The cross-section in this example has a structure in which the emitter region 12 in the example shown in Figure 3D is replaced with a contact region 15. The structure other than the contact region 15 is the same as in Figure 3D. Also, as shown in Figure 4D, the first mesa portion 61 may be provided with a first plug region 221 that covers the first contact portion 211. The second mesa portion 62 may be provided with a second plug region 222 that covers the second contact portion 212.

[0132] Figure 4E shows an example of an ff cross-section. The cross-section in this example has a structure in which the emitter region 12 in the example shown in Figure 3E is replaced with a contact region 15. The structure other than the contact region 15 is the same as in Figure 3E.

[0133] Figure 4F shows an example of an ff cross-section. The cross-section in this example has a structure in which the emitter region 12 in the example shown in Figure 3F is replaced with a contact region 15. The structure other than the contact region 15 is the same as in Figure 3F. Also, as shown in Figure 4F, the first mesa portion 61 may be provided with a first plug region 221 that covers the first contact portion 211. The second mesa portion 62 may be provided with a second plug region 222 that covers the second contact portion 212.

[0134] Figure 5 shows an example of the doping concentration distribution along the r-r' and s-s' lines in Figure 3A. The r-r' line is a line parallel to the Z-axis passing through the first region 301, and the s-s' line is a line parallel to the Z-axis passing through the second region 302.

[0135] A PN junction is provided at the boundary between the second region 302 and the base region 14 in this example. The depth position of this boundary is denoted as Z14. The doping concentration distribution in the second region 302 has a peak. The doping concentration at the peak is denoted as P302. The doping concentration in the drift region 18 is denoted as D18. The peak concentration P302 is higher than the doping concentration D18. Below the peak, on the lower surface 23 side, the position where the doping concentration first becomes D18 is denoted as the depth position Z302 at the lower end of the second region 302.

[0136] A PN junction is provided at the boundary between the first region 301 and the base region 14 in this example. The depth position of this boundary is denoted as Z14. The doping concentration distribution in the first region 301 in this example has a peak. The doping concentration at the peak is denoted as P301. The peak concentration P301 is higher than the doping concentration D18. The position where the doping concentration first becomes D18 on the lower surface 23 side of the peak is denoted as the depth position Z301 at the lower end of the first region 301. Depth position Z301 may be the same as or different from depth position Z302.

[0137] The peak concentration P301 is smaller than the peak concentration P302. As mentioned above, the peak concentration P301 may be less than half, less than 1 / 10, or less than 1 / 100 of the peak concentration P302.

[0138] Dosage of dopant ions per unit area (ions / cm²) for the first region 301 2 Let Do301 be the dose amount Do301 in the first region 301. The dose amount Do301 in the first region 301 may be the value obtained by integrating the doping concentration in the first region 301 from depth position Z14 to Z301. The dose amount per unit area of ​​dopant ions (ions / cm²) for the second region 302. 2 Let ) be Do302. The dose amount Do302 in the second region 302 may be the value obtained by integrating the doping concentration in the second region 302 from depth position Z14 to Z302. In Figure 5, the area of ​​the hatched portion corresponds to each dose amount.

[0139] The dose Do302 may be greater than the dose Do301. The dose Do302 may be more than twice, more than 10 times, or even more than 100 times the dose Do301.

[0140] Figure 6 shows another example of the doping concentration distribution along the r-r' and s-s' lines. In this example, the doping concentration in the first region 301 is the same as the doping concentration in the drift region 18. In this case, the depth position Z302 at the lower end of the second region 302 may be used as the depth position at the lower end of the first region 301.

[0141] The doping concentration D18 in the first region 301 is lower than the peak concentration P302. Also, the dose Do301 in the first region 301 is lower than the dose Do302 in the second region 302.

[0142] Figure 7 shows another example of the ee section. This example differs from the example described in Figures 1 to 6 in that the first mesa section 61 has a first contact section 211, the second mesa section 62 has a second contact section 212, and the third mesa section 63 and the fourth mesa section 64 have a third contact section 213. The other structures are the same as in any of the examples described in Figures 1 to 6.

[0143] A first contact portion 211 may be provided for some of the first mesa portions 61, or all of the first mesa portions 61 may be provided with a first contact portion 211. A second contact portion 212 may be provided for some of the second mesa portions 62, or all of the second mesa portions 62 may be provided with a second contact portion 212. A third contact portion 213 may be provided for some of the third mesa portions 63, or all of the third mesa portions 63 may be provided with a third contact portion 213. A third contact portion 213 may be provided for some of the fourth mesa portions 64, or all of the fourth mesa portions 64 may be provided with a third contact portion 213.

[0144] In this example, each contact portion refers to the interface where the emitter electrode 52 and the semiconductor substrate 10 are in contact. The contact portion may include the surface of the emitter electrode 52 and the surface of the semiconductor substrate 10. If a metal silicide layer is formed at the interface between the emitter electrode 52 and the semiconductor substrate 10, the metal silicide layer may be included in the emitter electrode 52 (metal electrode). In other words, the interface between the metal silicide layer and the semiconductor substrate 10 may be considered the contact portion.

[0145] A trench contact portion 17 may be provided in at least some of the mesa portions 60. The trench contact portion 17 is a portion in which a metal electrode, such as an emitter electrode 52, is provided inside the semiconductor substrate 10. The trench contact portion 17 can be formed by forming a groove in the upper surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the inside of the groove with a metal electrode. In a mesa portion 60 in which a trench contact portion 17 is provided, the region in the trench contact portion 17 in which the mesa portion 60 and the metal electrode, such as the emitter electrode 52, come into contact corresponds to the contact portion. In the example in Figure 7, a trench contact portion 17 is provided in the first mesa portion 61.

[0146] At least a portion of the mesa portion 60 may have a plug region in the area that contacts the lower end of the contact portion. The plug region is a P++ type region with a higher doping concentration than the contact region 15. In the example in Figure 7, a third plug region 223 is provided in contact with the third contact portion 213.

[0147] The first contact portion 211 of the first mesa portion 61 shown in Figure 7 may be provided at a depth shallower than the lower end of the emitter region 12. Note that the first plug region 221 is not provided at the lower end of the first contact portion 211. In other examples, the lower end of the first contact portion 211 may be provided at a depth that reaches the base region 14, or the first plug region 221 may be provided so as to be in contact with the lower end of the first contact portion 211.

[0148] Figure 8A is an enlarged view of the vicinity of the first mesa 61, the second mesa 62, and the third mesa 63. In Figure 8A, the first mesa 61, the second mesa 62, and the third mesa 63 are shown individually, and the areas between each mesa are omitted.

[0149] Let Z1 be the depth position of the lower end of the first contact portion 211, Z2 be the depth position of the lower end of the second contact portion 212, and Z3 be the depth position of the lower end of the third contact portion 213. The lower end of each contact portion refers to the lowest part of the interface where the metal electrode and the semiconductor substrate 10 are in contact. Depth position Z2 is located above depth position Z1. In other words, depth position Z1 is further from the upper surface 21 of the semiconductor substrate 10 than depth position Z2. In the example of Figure 8A, depth position Z1 is below the upper surface 21 of the semiconductor substrate 10, and depth position Z2 is at the same depth as the upper surface 21 of the semiconductor substrate 10. In other examples, depth position Z2 may be located between depth position Z1 and the upper surface 21 of the semiconductor substrate 10. In this case, with respect to the upper surface 21 of the semiconductor substrate 10, depth position Z2 may be less than half the depth of depth position Z1, or less than one-quarter the depth.

[0150] In the adjustment region 201, charged particles are irradiated from the upper surface 21, forming a lifetime adjustment region 206 (see Figure 7). On the other hand, irradiation with charged particles can form energy levels in the gate insulating film 42 of the adjustment region 201, causing the threshold voltage (on voltage, off voltage) in the adjustment region 201 to drop below the threshold voltage in the non-adjusted region 202. A decrease in the threshold voltage delays the turn-off timing, so the turn-off of the adjustment region 201 may be delayed compared to the non-adjusted region 202, potentially leading to a current concentration in the adjustment region 201 and a decrease in its withstand capability.

[0151] In the semiconductor device 100 of this example, the depth position Z1 of the first contact portion 211 is deeper than the depth position Z2 of the second contact portion 212. This makes it easier to extract holes from the semiconductor substrate 10 to the emitter electrode 52 in the first mesa portion 61. Therefore, even if current concentrates in the first mesa portion 61, a decrease in withstand power can be suppressed. The depth position Z1 of the first contact portion 211 may be shallower or deeper than the emitter region 12.

[0152] In this example, the lower end of the third contact portion 213 is positioned above the first contact portion 211. The depth position Z3 of the third contact portion 213 may be the same as the depth position Z2 of the second contact portion 212, or it may be positioned between depth position Z2 and depth position Z1. Alternatively, the depth position Z3 of the third contact portion 213 may be the same as the depth position Z1 of the first contact portion 211.

[0153] The third mesa portion 63 is provided in contact with the lower end of the third contact portion 213 and may have a P++ type third plug region 223 with a higher doping concentration than the base region 14 (anode region). The third plug region 223 may have a higher doping concentration than the contact region 15. The base region 14 (anode region) of the third mesa portion 63 may have a lower doping concentration than the base region 14 of the transistor portion 70. In this case, the injection of holes from the third mesa portion 63 into the drift region 18 can be suppressed.

[0154] As shown in Figure 7, at least one first mesa portion 61 is provided with both a trench contact portion 17 and a first region 301. All first mesa portions 61 may have both a trench contact portion 17 and a first region 301. In other examples, some first mesa portions 61 may not have a trench contact portion 17 but may have a first region 301.

[0155] Figure 8B is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63. In Figure 8B, the first mesa section 61, the second mesa section 62, and the third mesa section 63 are shown individually, and the areas between each mesa section are omitted.

[0156] The emitter electrode 52 (metal electrode) in this example includes a barrier metal portion 252 and an upper portion 251. The barrier metal portion 252 is provided above the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54 or the trench contact portion 17. The barrier metal portion 252 may be provided at the lower end of each contact portion. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side surfaces of the contact hole 54 and the trench contact portion 17. The barrier metal portion 252 may or may not be provided on the upper surface of the interlayer insulating film 38.

[0157] The barrier metal portion 252 is formed of a material with higher hydrogen storage capacity than the upper portion 251. This suppresses the penetration of hydrogen into the semiconductor substrate 10. In this example, the barrier metal portion 252 contains titanium. The barrier metal portion 252 may contain a titanium nitride layer. The barrier metal portion 252 may also be a laminated film of a titanium layer and a titanium nitride layer.

[0158] The upper portion 251 is provided above the barrier metal portion 252. The upper portion 251 is also provided above the interlayer insulating film 38. The upper portion 251 is made of a different material than the barrier metal portion 252. In this example, the upper portion 251 does not contain titanium. As an example, the upper portion 251 contains aluminum. The upper portion 251 may be an alloy of aluminum and silicon. The upper portion 251 inside the contact hole 54 or trench contact portion 17 may include a plug portion made of tungsten or the like, and the plug portion may extend above the interlayer insulating film 38. Even when the barrier metal portion 252 is provided in the first contact portion 211, the second contact portion 212, and the third contact portion 213 as in this example, the same effect as in Figure 8A can be obtained.

[0159] Figure 9 shows an example of the ff cross-section in Figure 2. The ff cross-section is the XZ plane passing through the contact region 15 and the cathode region 82. In the ff cross-section, the contact region 15 is positioned in place of the emitter region 12 in the ee cross-section shown in Figure 7. The other structures are the same as in the ee cross-section. In the ff cross-section, the structures of the first contact portion 211, the second contact portion 212, and the third contact portion 213 are the same as in the ee cross-section.

[0160] In this example, the first mesa portion 61 is provided in contact with the lower end of the first contact portion 211 and has a P++ type first plug region 221 with a higher doping concentration than the contact region 15. At least a portion of the first plug region 221 is provided so as to overlap with the contact region 15 in a top view. In other words, the first plug region 221 is provided in any XZ cross section that passes through the contact region 15. Y A first plug region 221 may be provided in the XZ cross section passing through the axial center. A portion of the first plug region 221 may overlap with the emitter region 12 in a top view. A first plug region 221 may be provided in the end region of the emitter region 12 that is in contact with the contact region 15. A first plug region 221 does not have to be provided in any XZ cross section passing through the emitter region 12. For example, in the emitter region 12 Y The first plug region 221 is not provided in the XZ cross-section passing through the center in the axial direction. The entire first plug region 221 may be provided so as to overlap with the contact region 15. In this case, the first plug region 221 does not overlap with the emitter region 12 when viewed from above.

[0161] In this example, the second mesa portion 62 is provided in contact with the lower end of the second contact portion 212 and has a P++ type second plug region 222 with a higher doping concentration than the contact region 15. At least a portion of the second plug region 222 is provided so as to overlap with the contact region 15 in a top view. In other words, the second plug region 222 is provided in any XZ cross section that passes through the contact region 15. YA second plug region 222 may be provided in the XZ cross section passing through the axial center. A portion of the second plug region 222 may overlap with the emitter region 12 in a top view. A second plug region 222 may be provided in the end region of the emitter region 12 that is in contact with the contact region 15. A second plug region 222 does not have to be provided in any XZ cross section passing through the emitter region 12. For example, in the emitter region 12 Y The second plug region 222 is not provided in the XZ cross section passing through the axial center. The entire second plug region 222 may be provided so as to overlap with the contact region 15. In this case, the second plug region 222 does not overlap with the emitter region 12 when viewed from above. By providing each plug region, it becomes easier to extract holes in each mesa. This suppresses a decrease in withstand capability.

[0162] Figure 10A is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63 shown in Figure 9. In Figure 10A, one of each of the first mesa section 61, the second mesa section 62, and the third mesa section 63 is shown, and the regions between each mesa section are omitted. The structure of the third mesa section 63 is the same as that of the third mesa section 63 shown in Figure 8A.

[0163] The first mesa portion 61 has a contact region 15 instead of the emitter region 12 compared to the structure shown in Figure 8A, and a first plug region 221 adjacent to the lower end of the first contact portion 211. The other structures are the same as in the example in Figure 8A. The second mesa portion 62 has a contact region 15 instead of the emitter region 12 compared to the structure shown in Figure 8A, and a second plug region 222 adjacent to the lower end of the second contact portion 212. The other structures are the same as in the example in Figure 8A.

[0164] The first plug region 221 may extend below the second plug region 222. Each plug region is a high-concentration P++ type region. Therefore, if each plug region is located near the channel region (the contact area between the base region 14 and the gate trench portion 40), the acceptor injected into the plug region will easily diffuse into the channel region, increasing the doping concentration in the channel region. When the doping concentration in the channel region increases, the threshold voltage rises.

[0165] In this example, the first plug region 221 is formed to a greater depth than the second plug region 222. This allows the threshold voltage of the first mesa region 61 to be relatively increased. This compensates for the decrease in the threshold voltage of the first mesa region 61 caused by the formation of the lifetime adjustment region 206.

[0166] The first plug region 221 and the second plug region 222 are defined by different dose amounts ( / cm²) of impurities. 2 They may be formed by injection. This allows for more precise adjustment of the threshold voltage of each mesa region. For example, the difference in dose between the first plug region 221 and the second plug region 222 may be set according to the amount of fluctuation in the threshold voltage of the first mesa region 61 due to the formation of the lifetime adjustment region 206. This allows for precise cancellation of the threshold voltage fluctuation. The first plug region 221 and the second plug region 222 may also be formed by injecting impurities in the same dose. In this case, the semiconductor device can be manufactured by a simple process.

[0167] Figure 10B is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63 shown in Figure 9. In Figure 10B, one of each of the first mesa section 61, the second mesa section 62, and the third mesa section 63 is shown, and the regions between each mesa section are omitted. The structure of the third mesa section 63 is the same as that of the third mesa section 63 shown in Figure 8B.

[0168] The first mesa portion 61 has a contact region 15 instead of an emitter region 12 compared to the structure shown in Figure 8B, and has a first plug region 221 in contact with the lower end of the first contact portion 211. The other structures are the same as in the example in Figure 8B. The second mesa portion 62 has a contact region 15 instead of an emitter region 12 compared to the structure shown in Figure 8B, and has a second plug region 222 in contact with the lower end of the second contact portion 212. The other structures are the same as in the example in Figure 8B. Even when barrier metal portions 252 are provided in the first contact portion 211, the second contact portion 212, and the third contact portion 213 as in this example, the same effects as in Figure 10A can be obtained.

[0169] Figure 11A shows an example of the doping concentration distribution along the a-a' and b-b' lines in Figure 10A. The a-a' line is parallel to the Z-axis and passes through the second plug region 222. The b-b' line is parallel to the Z-axis and passes through the first plug region 221. The first plug region 221 and the second plug region 222 have a first peak 231 and a second peak 232 of doping concentration. The second plug region 222 has a junction 242 of doping concentration at its boundary with the contact region 15. In this example, the first plug region 221 does not have a dip in doping concentration at its boundary with the contact region 15, but it may have a junction 242 that forms a dip.

[0170] Let D2 be the dose amount for the second plug region 222, and D1 be the dose amount for the first plug region 221. The dose amount D2 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z2 of the second contact portion 212 to the doping concentration junction 242. Similarly, the dose amount D1 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z1 of the first contact portion 211 to the doping concentration junction 241. If there is no dip in the doping concentration at the boundary between the first plug region 221 and the contact region 15, the dose amount D1 may be the value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z1. The distance L2 is, for example, the distance in the depth direction from the depth position Z2 in the second plug region 222 to the junction 242. In other words, the value obtained by integrating the doping concentration over the same distance L2 in both the first plug region 221 and the second plug region 222 may be used as the respective dose amounts. In other examples, the doping concentration may be integrated from the lower end position of each contact area (Z1 or Z2) to the peak of the doping concentration (first peak 231 or second peak 232) and used as an indicator of each dose. Alternatively, the doping concentration at the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of each dose.

[0171] As mentioned above, doses D1 and D2 may be the same. The same dose means that an error of ±20%, ±10%, or ±5% may be allowed.

[0172] Figure 11B shows an example of the doping concentration distribution along the a-a' and b-b' lines in Figure 10B. The a-a' line is parallel to the Z-axis and passes through the second plug region 222. The b-b' line is parallel to the Z-axis and passes through the first plug region 221. The first plug region 221 and the second plug region 222 have the first peak 231 and second peak 232 of the doping concentration.

[0173] Let D2 be the dose amount for the second plug region 222, and D1 be the dose amount for the first plug region 221. The dose amount D2 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z2 of the second contact portion 212 to the doping concentration junction 242. Similarly, the dose amount D1 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z1 of the first contact portion 211 to the doping concentration junction 241. The dose amount D1 may also be the value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z1. The distance L2 is, for example, the distance in the depth direction from the depth position Z2 in the second plug region 222 to the junction 242. In other words, the value obtained by integrating the doping concentration over the same distance L2 in the first plug region 221 and the second plug region 222 may be used as the respective dose amounts. In other examples, the doping concentration may be integrated from the lower end position of each contact area (Z1 or Z2) to the peak of the doping concentration (first peak 231 or second peak 232) and used as an indicator of each dose. Alternatively, the doping concentration at the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of each dose.

[0174] The lower end of the first contact portion 211, which is the bottom of the trench contact portion 17, is in contact with a region of the contact area 15 where the doping concentration is lower than that of the lower end of the second contact portion 212. As a result, compared to the case where the lower end position Z1 of the first contact portion 211 is at the same depth as the lower end position Z2 of the second contact portion 212, the injection of holes from the first mesa portion 61 is suppressed, and the reverse recovery loss is reduced. Therefore, by providing the trench contact portion 17 in the first mesa portion 61 of the transistor portion 70, the reverse recovery loss can be reduced.

[0175] As mentioned above, doses D1 and D2 may be the same. The same dose means that an error of ±20%, ±10%, or ±5% may be allowed.

[0176] The first plug region 221 and the second plug region 222 are formed by exposing the bottoms of the first contact portion 211 and the second contact portion 212 and performing ion implantation on the exposed portions. The difference in doping concentration between the contact region 15 of the first contact portion 211 and the second contact portion 212 is sufficiently smaller than the doping concentrations of the first peak 231 and the second peak 232.

[0177] Figure 12A is an enlarged view of the area around the first contact portion 211. The barrier metal portion 252 in this example has a first layer 253 and a second layer 254. The first layer 253 is a titanium layer or titanium nitride layer provided between the upper portion 251 and the semiconductor substrate 10. The second layer 254 is a titanium nitride layer provided between the first layer 253 and the semiconductor substrate 10.

[0178] The barrier metal portion 252 of the first mesa portion 61 has a contact hole 54 to It is provided. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may further have a silicide layer 255. The silicide layer 255 is formed at a position in contact with the semiconductor substrate 10. The silicide layer 255 is a layer in which a part of the second layer 254 has been silicided. At the position of the barrier metal portion 252 in contact with the semiconductor substrate 10, the second layer 254 does not have to be entirely transformed into the silicide layer 255.

[0179] Figure 12B is an enlarged view of the area around the second contact portion 212. 12 Similar to example A, the barrier metal portion 252 has a first layer 253 and a second layer 254. The barrier metal portion 252 may also have a silicide layer 255.

[0180] The barrier metal portion 252 of the second mesa portion 62 is located inside the contact hole 54 and the trench contact portion 17. Therefore, its volume is larger than that of the barrier metal portion 252 of the first mesa portion 61. The thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the first mesa portion 61 and the thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the second mesa portion 62 may be the same. The barrier metal portion 252 of the first mesa portion 61 and the barrier metal portion 252 of the second mesa portion 62 may be formed in the same process.

[0181] Figure 13 shows another example of the ee section. In this example, the adjustment region 201 includes two or more first mesa portions 61 aligned in the X-axis direction. The semiconductor device 100 in this example differs from the other examples described herein in the structure of the trench contact portions 17 of the first mesa portions 61. The structure of the first mesa portions 61 other than the trench contact portions 17 is the same as in any of the embodiments described herein.

[0182] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 extends deeper than the trench contact portion 17-1 of a first mesa portion 61 that is located closer to the diode portion 80 than the first mesa portion 61. The trench contact portion 17 of each first mesa portion 61 may be formed deeper as it moves further away from the diode portion 80. However, the adjustment region 201 may include two or more trench contact portions 17 that are adjacent to each other in the X-axis direction and of the same depth. This structure allows for a gradual change in the ease with which holes can be extracted in the adjustment region 201.

[0183] In other examples, the depth of each trench contact portion 17 may be adjusted according to the density of lattice defects 204 in the lower lifetime adjustment region 206. For example, the lower the density of lattice defects 204 located, the shallower the trench contact portion 17 may be formed. This makes it easier to cancel out fluctuations in the threshold voltage. For example, if the density of lattice defects 204 decreases as you move away from the diode portion 80, the trench contact portion 17 may be formed shallower as you move away from the diode portion 80.

[0184] Figure 14 shows an example of the arrangement of the adjustment region 201 and the non-adjustment region 202 in a top view. The arrangement in this example may be applied to any embodiment of the semiconductor device 100 described herein. Figure 14 shows two diode sections 80 and one transistor section 70, with other regions omitted. Also in Figure 14, the region where the lifetime adjustment region 206 is provided is hatched with diagonal lines.

[0185] The adjustment region 201 may be provided over the entire diode section 80 in the X-axis direction. The adjustment region 201 is also provided in the region of the transistor section 70 that is in contact with the diode section 80 (or boundary region 200). The area of ​​the non-adjustment region 202 in the transistor section 70 may be larger than the area of ​​the adjustment region 201. In the non-adjustment region 202, the second contact section 212 is positioned above the first contact section 211. Therefore, the threshold voltage of the non-adjustment region 202 may be lower than the threshold voltage of the adjustment region 201. Even in this case, by increasing the area of ​​the non-adjustment region 202, local current concentration can be suppressed even if the turn-off of the non-adjustment region 202 is later than that of the adjustment region 201.

[0186] In the transistor section 70, the number of second mesa sections 62 (see Figure 7, etc.) may be greater than the number of first mesa sections 61 (see Figure 7, etc.). This suppresses local current concentration even if the turn-off of the non-adjustable region 202 is delayed compared to the adjustable region 201. In the transistor section 70, the threshold voltage of the second mesa section 62 may be lower than the threshold voltage of the first mesa section 61. The threshold voltage of each mesa section can be adjusted by adjusting the depth of the trench contact section 17 in the first mesa section 61 and the dose amount of each plug region. The threshold voltage of a mesa section is the voltage at which at least one channel region in that mesa section transitions from off to on.

[0187] Figure 15 shows another example of the ee section. This example differs from the example described in Figures 1 to 6 in that the first mesa section 61 has a first contact section 211, the second mesa section 62 has a second contact section 212, and the third mesa section 63 and the fourth mesa section 64 have a third contact section 213. The other structures are the same as those described in Figures 1 to 6.

[0188] A first contact portion 211 may be provided for some of the first mesa portions 61, or all of the first mesa portions 61 may be provided with a first contact portion 211. A second contact portion 212 may be provided for some of the second mesa portions 62, or all of the second mesa portions 62 may be provided with a second contact portion 212. A third contact portion 213 may be provided for some of the third mesa portions 63, or all of the third mesa portions 63 may be provided with a third contact portion 213. A third contact portion 213 may be provided for some of the fourth mesa portions 64, or all of the fourth mesa portions 64 may be provided with a third contact portion 213.

[0189] In this example, each contact portion refers to the interface where the emitter electrode 52 and the semiconductor substrate 10 are in contact. The contact portion may include the surface of the emitter electrode 52 and the surface of the semiconductor substrate 10. If a metal silicide layer is formed at the interface between the emitter electrode 52 and the semiconductor substrate 10, the metal silicide layer may be included in the emitter electrode 52 (metal electrode). In other words, the interface between the metal silicide layer and the semiconductor substrate 10 may be considered the contact portion.

[0190] Trench contact portions 17 may be provided in at least some of the mesa portions 60. The trench contact portion 17 is a portion in which a metal electrode, such as an emitter electrode 52, is provided inside the semiconductor substrate 10. A trench contact portion 17 can be formed by forming a groove in the upper surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the inside of the groove with a metal electrode. In the mesa portion 60 in which a trench contact portion 17 is provided, the region in the trench contact portion 17 in which the mesa portion 60 and the metal electrode, such as the emitter electrode 52, come into contact corresponds to the contact portion. In the example in Figure 15, trench contact portions 17 are provided in the second mesa portion 62, the third mesa portion 63, and the fourth mesa portion 64.

[0191] At least some of the mesa portion 60 may have a plug region in the area that contacts the lower end of the contact portion. The plug region is a P++ type region with a higher doping concentration than the contact region 15. In the example in Figure 15, a third plug region 223 is provided in contact with the third contact portion 213.

[0192] Figure 16 is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63. In Figure 16, the first mesa section 61, the second mesa section 62, and the third mesa section 63 are shown individually, and the areas between each mesa section are omitted.

[0193] The emitter electrode 52 (metal electrode) in this example includes a barrier metal portion 252 and an upper portion 251. The barrier metal portion 252 is provided above the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54 or the trench contact portion 17. The barrier metal portion 252 may be provided at the lower end of each contact portion. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side surfaces of the contact hole 54 and the trench contact portion 17. The barrier metal portion 252 may or may not be provided on the upper surface of the interlayer insulating film 38.

[0194] The barrier metal portion 252 is formed of a material with higher hydrogen storage capacity than the upper portion 251. This suppresses the penetration of hydrogen ions into the semiconductor substrate 10. In this example, the barrier metal portion 252 contains titanium. The barrier metal portion 252 may contain a titanium nitride layer. The barrier metal portion 252 may also be a laminated film of a titanium layer and a titanium nitride layer.

[0195] The upper portion 251 is provided above the barrier metal portion 252. The upper portion 251 is also provided above the interlayer insulating film 38. The upper portion 251 is made of a different material than the barrier metal portion 252. In this example, the upper portion 251 does not contain titanium. As an example, the upper portion 251 contains aluminum. The upper portion 251 may be an alloy of aluminum and silicon. The upper portion 251 inside the contact hole 54 or trench contact portion 17 may include a plug portion made of tungsten or the like, and the plug portion may extend above the interlayer insulating film 38.

[0196] Let Z1 be the depth position of the lower end of the first contact portion 211, Z2 be the depth position of the lower end of the second contact portion 212, and Z3 be the depth position of the lower end of the third contact portion 213. The lower end of each contact portion refers to the lowest part of the interface where the metal electrode and the semiconductor substrate 10 are in contact. Depth position Z1 is located above depth position Z2. That is, depth position Z2 is further from the upper surface 21 of the semiconductor substrate 10 than depth position Z1. In the example of Figure 16, depth position Z2 is below the upper surface 21 of the semiconductor substrate 10, and depth position Z1 is at the same depth as the upper surface 21 of the semiconductor substrate 10. In other examples, depth position Z1 may be located between depth position Z2 and the upper surface 21 of the semiconductor substrate 10. In this case, with respect to the upper surface 21 of the semiconductor substrate 10, depth position Z1 may be less than half the depth of depth position Z2, or less than one-quarter the depth.

[0197] In the adjustment region 201, charged particles are irradiated from the upper surface 21, forming a lifetime adjustment region 206 (see Figure 15). On the other hand, irradiation with charged particles can form energy levels in the gate insulating film 42 of the adjustment region 201, causing the threshold voltage (on voltage, off voltage) in the adjustment region 201 to drop below the threshold voltage in the non-adjusted region 202. A decrease in the threshold voltage delays the turn-off timing, so the turn-off of the adjustment region 201 may be delayed compared to the non-adjusted region 202, potentially leading to a current concentration in the adjustment region 201 and a decrease in its withstand capability.

[0198] In the semiconductor device 100 of this example, the depth position Z2 of the second contact portion 212 is made deeper than the depth position Z1 of the first contact portion 211. This makes it easier to make the volume of the barrier metal portion 252 in one second mesa portion 62 larger than the volume of the barrier metal portion 252 in one first mesa portion 61. The volume of the barrier metal portion 252 in one mesa portion refers to the volume of the barrier metal portion 252 provided inside the trench contact portion 17 and contact hole 54 above that mesa portion.

[0199] The manufacturing process for the semiconductor device 100 includes, for example, a process of annealing the semiconductor substrate 10 in a hydrogen atmosphere. This process allows oxygen to penetrate into the semiconductor substrate 10 and the insulating film, terminating defects. This suppresses a decrease in the threshold voltage.

[0200] Since the barrier metal portion 252 absorbs hydrogen, the number of barrier metal portions 252 formed in the first 2 Mesa section 6 2 In the first 1 Mesa section 6 1 Compared to this, hydrogen intrusion is suppressed. Therefore, 2 Mesa section 6 2 is the 1 Mesa section 6 1 Compared to this, the threshold voltage is lowered, and the threshold voltage of the first mesa portion 61 can be relatively increased. This can offset the decrease in the threshold voltage of the first mesa portion 61 caused by the formation of the lifetime adjustment region 206. The volume of the barrier metal portion 252 in one second mesa portion 62 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more, than the volume of the barrier metal portion 252 in one first mesa portion 61.

[0201] In this example, the lower end of the first contact portion 211 is positioned above the third contact portion 213. The depth position Z3 of the third contact portion 213 may be the same as the depth position Z2 of the second contact portion 212, or it may be positioned between depth position Z2 and depth position Z1. Alternatively, the depth position Z3 of the third contact portion 213 may be the same as the depth position Z1 of the first contact portion 211.

[0202] The third mesa portion 63 is provided in contact with the lower end of the third contact portion 213 and may have a P++ type third plug region 223 with a higher doping concentration than the base region 14 (anode region). The third plug region 223 may have a higher doping concentration than the contact region 15. The base region 14 (anode region) of the third mesa portion 63 may have a lower doping concentration than the base region 14 of the transistor portion 70. In this case, the injection of holes from the third mesa portion 63 into the drift region 18 can be suppressed.

[0203] As shown in Figure 15, at least one second mesa portion 62 is provided with both a trench contact portion 17 and a second region 302. All second mesa portions 62 may have both a trench contact portion 17 and a second region 302. In other examples, some second mesa portions 62 may not have a trench contact portion 17 but have a second region 302. Also, some second mesa portions 62 may have a trench contact portion 17 but not a second region 302.

[0204] Figure 17 shows an example of the ff cross-section in Figure 2. The ff cross-section is the XZ plane passing through the contact region 15 and the cathode region 82. In the ff cross-section, the contact region 15 is positioned in place of the emitter region 12 in the ee cross-section shown in Figure 15. The other structures are the same as in the ee cross-section. In the ff cross-section, the structures of the first contact portion 211, the second contact portion 212, and the third contact portion 213 are the same as in the ee cross-section.

[0205] In this example, the first mesa portion 61 is provided in contact with the lower end of the first contact portion 211 and has a P++ type first plug region 221 with a higher doping concentration than the contact region 15. At least a portion of the first plug region 221 is provided so as to overlap with the contact region 15 in a top view. In other words, the first plug region 221 is provided in any XZ cross section that passes through the contact region 15. Y A first plug region 221 may be provided in the XZ cross section passing through the axial center. A portion of the first plug region 221 may overlap with the emitter region 12 in a top view. A first plug region 221 may be provided in the end region of the emitter region 12 that is in contact with the contact region 15. A first plug region 221 does not have to be provided in any XZ cross section passing through the emitter region 12. For example, in the emitter region 12 YThe first plug region 221 is not provided in the XZ cross-section passing through the center in the axial direction. The entire first plug region 221 may be provided so as to overlap with the contact region 15. In this case, the first plug region 221 does not overlap with the emitter region 12 when viewed from above.

[0206] In this example, the second mesa portion 62 is provided in contact with the lower end of the second contact portion 212 and has a P++ type second plug region 222 with a higher doping concentration than the contact region 15. At least a portion of the second plug region 222 is provided so as to overlap with the contact region 15 in a top view. In other words, the second plug region 222 is provided in any XZ cross section that passes through the contact region 15. Y A second plug region 222 may be provided in the XZ cross section passing through the axial center. A portion of the second plug region 222 may overlap with the emitter region 12 in a top view. A second plug region 222 may be provided in the end region of the emitter region 12 that is in contact with the contact region 15. A second plug region 222 does not have to be provided in any XZ cross section passing through the emitter region 12. For example, in the emitter region 12 Y The second plug region 222 is not provided in the XZ cross section passing through the axial center. The entire second plug region 222 may be provided so as to overlap with the contact region 15. In this case, the second plug region 222 does not overlap with the emitter region 12 when viewed from above. By providing each plug region, it becomes easier to extract holes in each mesa. This suppresses a decrease in withstand capability.

[0207] Figure 18 is an enlarged view of the vicinity of the first mesa section 61, the second mesa section 62, and the third mesa section 63 shown in Figure 17. In Figure 18, the first mesa section 61, the second mesa section 62, and the third mesa section 63 are shown individually, and the regions between each mesa section are omitted. The structure of the third mesa section 63 is the same as that of the third mesa section 63 shown in Figure 16.

[0208] The first mesa portion 61 has a contact region 15 instead of an emitter region 12 compared to the structure shown in Figure 16, and a first plug region 221 adjacent to the lower end of the first contact portion 211. The other structures are the same as in the example in Figure 16. The second mesa portion 62 has a contact region 15 instead of an emitter region 12 compared to the structure shown in Figure 16, and a second plug region 222 adjacent to the lower end of the second contact portion 212. The other structures are the same as in the example in Figure 16.

[0209] The second plug region 222 may extend below the first plug region 221. Each plug region is a high-concentration P++ type region. The first plug region 221 and the second plug region 222 are separated by different doses ( / cm²) of impurities. 2 The first plug region 221 and the second plug region 222 may be formed by injecting impurities in the same dose. In this case, the semiconductor device can be manufactured by a simple process.

[0210] Figure 19A shows an example of the doping concentration distribution along the a-a' and b-b' lines in Figure 18. The a-a' line is parallel to the Z-axis and passes through the second plug region 222. The b-b' line is parallel to the Z-axis and passes through the first plug region 221. The first plug region 221 and the second plug region 222 have a first peak 231 and a second peak 232 of doping concentration. The first plug region 221 has a junction 241 of doping concentration at its boundary with the contact region 15. In this example, the second plug region 222 does not have a dip in doping concentration at its boundary with the contact region 15, but it may have a junction 241 that forms a dip.

[0211] Let D2 be the dose amount for the second plug region 222, and D1 be the dose amount for the first plug region 221. The dose amount D1 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z1 of the first contact portion 211 to the doping concentration junction 241. Similarly, the dose amount D2 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z2 of the second contact portion 212 to the doping concentration junction 242. If there is no dip in the doping concentration at the boundary between the second plug region 222 and the contact region 15, the dose amount D2 may be the value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z2. The distance L2 is, for example, the distance in the depth direction from the depth position Z1 in the first plug region 221 to the junction 241. In other words, the value obtained by integrating the doping concentration over the same distance L2 in both the first plug region 221 and the second plug region 222 may be used as the respective dose amounts. In other examples, the integrated doping concentration from the lower end of each contact area (Z1 or Z2) to the peak of doping concentration (peak 231 or peak 232) may be used as an indicator of each dose. Alternatively, the doping concentration at the peak of doping concentration (peak 231 or peak 232) may be used as an indicator of each dose.

[0212] As described above, dose amounts D1 and D2 may be the same. The same dose amounts mean that an error of ±20%, ±10%, or ±5% may be allowed. The first plug region 221 and the second plug region 222 are formed by exposing the first contact portion 211 and the second contact portion 212 and performing ion implantation. The difference in doping concentrations in the contact region 15 of the first contact portion 211 and the second contact portion 212 is sufficiently smaller than the doping concentrations of the formed first peak 231 and second peak 232.

[0213] Figure 19B shows an example of the doping concentration distribution along the a-a' and b-b' lines in Figure 18. The a-a' line is parallel to the Z-axis and passes through the second plug region 222. The b-b' line is parallel to the Z-axis and passes through the first plug region 221. The first plug region 221 and the second plug region 222 have the first peak 231 and second peak 232 of the doping concentration.

[0214] Let D2 be the dose amount for the second plug region 222, and D1 be the dose amount for the first plug region 221. The dose amount D1 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z1 of the first contact portion 211 to the doping concentration junction 241. Similarly, the dose amount D2 may be the value obtained by integrating the doping concentration in the depth direction from the lower end position Z2 of the second contact portion 212 to the doping concentration junction 242. The dose amount D2 may also be the value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z2. The distance L2 is, for example, the distance in the depth direction from the depth position Z1 in the first plug region 221 to the junction 241. In other words, the value obtained by integrating the doping concentration over the same distance L2 in both the first plug region 221 and the second plug region 222 may be used as the respective dose amounts. In other examples, the doping concentration may be integrated from the lower end position of each contact area (Z1 or Z2) to the peak of the doping concentration (first peak 231 or second peak 232) and used as an indicator of each dose. Alternatively, the doping concentration at the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of each dose.

[0215] The lower end of the first contact portion 211 is in contact with a region of the contact area 15 where the doping concentration is higher than that of the second contact portion 212, which is the bottom of the trench contact portion 17. Therefore, compared to the case where the lower end position Z1 of the first contact portion 211 is at the same depth as the lower end position Z2 of the second contact portion 212, more holes are injected from the first mesa portion 61, and the forward voltage is lower. Thus, by providing the trench contact portion 17 in the first mesa portion 61 of the transistor portion 70, the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0216] As described above, dose amounts D1 and D2 may be the same. The same dose amounts mean that an error of ±20%, ±10%, or ±5% may be allowed. The first plug region 221 and the second plug region 222 are formed by exposing the first contact portion 211 and the second contact portion 212 and performing ion implantation. The difference in doping concentrations in the contact region 15 of the first contact portion 211 and the second contact portion 212 is sufficiently smaller than the doping concentrations of the formed first peak 231 and second peak 232.

[0217] Figure 20A is an enlarged view of the area around the first contact portion 211 shown in Figure 16. The first contact portion 211 may have a structure similar to that of the example in Figure 12A. The barrier metal portion 252 in this example has a first layer 253 and a second layer 254. The first layer 253 is a titanium layer or titanium nitride layer provided between the upper portion 251 and the semiconductor substrate 10. The second layer 254 is a titanium nitride layer provided between the first layer 253 and the semiconductor substrate 10.

[0218] The barrier metal portion 252 of the first mesa portion 61 is provided inside the contact hole 54. The barrier metal portion 252 may be in contact with the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 may further have a silicide layer 255. The silicide layer 255 is formed at a position in contact with the semiconductor substrate 10. The silicide layer 255 is a layer in which a part of the second layer 254 has been silicided. At the position of the barrier metal portion 252 in contact with the upper surface 21 of the semiconductor substrate 10, the second layer 254 does not have to be entirely transformed into the silicide layer 255.

[0219] Figure 20B is an enlarged view of the area around the second contact portion 212 shown in Figure 16. The second contact portion 212 may have a structure similar to that of the example in Figure 12B. Similar to the example in Figure 20A, the barrier metal portion 252 has a first layer 253 and a second layer 254. The barrier metal portion 252 may also have a silicide layer 255.

[0220] The barrier metal portion 252 of the second mesa portion 62 is located inside the contact hole 54 and the trench contact portion 17. Therefore, its volume is larger than that of the barrier metal portion 252 of the first mesa portion 61. The thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the first mesa portion 61 and the thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the second mesa portion 62 may be the same. The barrier metal portion 252 of the first mesa portion 61 and the barrier metal portion 252 of the second mesa portion 62 may be formed in the same process.

[0221] Figure 21A shows another example of the ee section. In this example, the adjustment region 201 includes two or more first mesa portions 61 aligned in the X-axis direction. The semiconductor device 100 in this example differs from the other examples described herein in the structure of the trench contact portions 17 of the first mesa portions 61. The structure of the first mesa portions 61 other than the trench contact portions 17 is the same as in any of the embodiments described herein.

[0222] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 extends deeper than the trench contact portion 17-1 of the first mesa portion 61 that is located closer to the diode portion 80 than the first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed to be deeper as they move away from the diode portion 80. However, the adjustment region 201 may include two or more trench contact portions 17 that are adjacent to each other in the X-axis direction and of the same depth. With such a structure, the volume of the barrier metal portion 252 in the first mesa portion 61 can be gradually changed.

[0223] In other examples, the depth of each trench contact portion 17 may be adjusted according to the density of lattice defects 204 in the lower lifetime adjustment region 206. For example, the lower the density of lattice defects 204 located, the deeper the trench contact portion 17 may be formed. The deeper the trench contact portion 17 is formed, the larger the volume of the barrier metal portion 252 becomes. This makes it easier to cancel out fluctuations in the threshold voltage. For example, if the density of lattice defects 204 decreases as you move away from the diode portion 80, the trench contact portion 17 may be formed deeper as you move away from the diode portion 80.

[0224] Figure 21B shows another example of the ee section. In this example, the unadjusted region 202 includes two or more second mesa portions 62 aligned in the X-axis direction. The semiconductor device 100 in this example differs from the other examples described herein in the structure of the trench contact portions 17 of the second mesa portions 62. The structure of the second mesa portions 62 other than the trench contact portions 17 is the same as in any of the embodiments described herein.

[0225] In this example, the trench contact portion 17-2 of at least one second mesa portion 62 extends deeper than the trench contact portion 17-1 of a second mesa portion 62 that is located closer to the diode portion 80 than that second mesa portion 62. The trench contact portion 17 of each second mesa portion 62 may be formed deeper as it moves away from the diode portion 80. However, the non-adjustable region 202 may include two or more trench contact portions 17 that are adjacent to each other in the X-axis direction and of the same depth. With such a structure, the volume of the barrier metal portion 252 in the second mesa portion 62 can be gradually changed.

[0226] Figure 21C shows another example of the ee section. In this example, the adjustment region 201 includes two or more first mesa portions 61 aligned in the X-axis direction. The semiconductor device 100 in this example differs from the other examples described herein in the structure of the trench contact portions 17 of the first mesa portions 61. The structure of the first mesa portions 61 other than the trench contact portions 17 is the same as in any of the embodiments described herein.

[0227] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 extends deeper than the trench contact portion 17-1 of the first mesa portion 61 that is located closer to the diode portion 80 than the first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed to be deeper as they move away from the diode portion 80. However, the adjustment region 201 may include two or more trench contact portions 17 that are adjacent to each other in the X-axis direction and of the same depth. With such a structure, the volume of the barrier metal portion 252 in the first mesa portion 61 can be gradually changed.

[0228] In other examples, the depth of each trench contact portion 17 may be adjusted according to the density of lattice defects 204 in the lower lifetime adjustment region 206. For example, the lower the density of lattice defects 204 located, the deeper the trench contact portion 17 may be formed. The deeper the trench contact portion 17 is formed, the larger the volume of the barrier metal portion 252 becomes. This makes it easier to cancel out fluctuations in the threshold voltage. For example, if the density of lattice defects 204 decreases as you move away from the diode portion 80, the trench contact portion 17 may be formed deeper as you move away from the diode portion 80.

[0229] Figure 22 shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. In this example, the second mesa section 62 has a plurality of second regions 302 in the depth direction. Each second region 302 has a doping concentration peak in the depth direction. In this example, the second mesa section 62 has second region 302-1 and second region 302-2.

[0230] In this example, the first mesa section 61 has fewer first regions 301 than the number of second regions 302 in the second mesa section 62. In Figure 22, the first mesa section 61 has one first region 301. The doping concentration of the first region 301 in this example is the same as that of the drift region 18. The doping concentration in the depth direction of the first region 301 in this example may be constant.

[0231] In this example, the third mesa region 63 has fewer third regions 303 than the number of second regions 302 in the second mesa region 62. The doping concentration of the third region 303 in this example is the same as that of the first region 301.

[0232] Structures other than the first region 301, the second region 302, and the third region 303 are the same as in any of the embodiments described herein. For example, in the example of Figure 22, each mesa does not have a trench contact portion 17, but each mesa may have a trench contact portion 17 similar to in any of the embodiments described herein.

[0233] Figure 23 shows an example of the doping concentration distribution in the gg and hh lines of Figure 22. The gg line is a line parallel to the Z axis, reaching from the base region 14 to the drift region 18 in the second mesa section 62. The hh line is a line parallel to the Z axis, reaching from the base region 14 to the drift region 18 in the first mesa section 61. In this specification, the doping concentration in the drift region 18 is denoted as D18. In this example, the number of doping concentration peaks in the depth direction of the second region 302 of the second mesa section 62 is greater than the number of doping concentration peaks in the depth direction of the first region 301 of the first mesa section 61. The number of peaks in the first region 301 may be 0.

[0234] In this example, the second mesa portion 62 has a second region 302-1 and a second region 302-2 in order from the upper surface 21 side. The second region 302-1 and the second region 302-2 each have doping concentration peaks. In other words, the number of doping concentration peaks in the second region 302 in this example is two. The doping concentration P302-1 in the second region 302-1 and the doping concentration P302-2 in the second region 302-2 may be the same or different.

[0235] Between the second region 302-1 and the second region 302-2, there is a valley where the doping concentration is at its minimum. The doping concentration in this valley may be the same as that in the drift region 18. In other examples, the doping concentration in this valley may be higher than that in the drift region 18.

[0236] In this example, the first mesa portion 61 has a first region 301 with the same doping concentration as the drift region 18. In this example, the number of doping concentration peaks in the first region 301 is 0. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted to suppress the decrease in withstand voltage and adjust the trade-off between reverse recovery loss and forward voltage.

[0237] FIG. 24 is a diagram showing another configuration example of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. The second mesa portion 62 in this example is the same as the example in FIG. 22. The first mesa portion 61 in this example has a plurality of first regions 301 in the depth direction. Each first region 301 has a peak of doping concentration in the depth direction. The first mesa portion 61 in this example has a first region 301-1 and a first region 301-2.

[0238] The third mesa portion 63 in this example has the same number of first regions 301 (or third regions 303) as the first mesa portion 61. The structure other than the first region 301, the second region 302, and the third region  303 is the same as any form described in this specification.

[0239] FIG. 25 is a diagram showing an example of the doping concentration distribution at the g-g line and the h-h line in FIG. 24. The doping concentration distribution in the second mesa portion 62 in this example is the same as the example in FIG. 23.

[0240] The first mesa portion 61 in this example has a first region 301-1 and a first region 301-2 in order from the upper surface 21 side. The number of the first regions 301 in the first mesa portion 61 may be the same as or different from the number of the second regions 302 in the second mesa portion 62.

[0241] The first regions 301-1 and 301-2 each have a peak in doping concentration. The doping concentration P301-1 in the first region 301-1 and the doping concentration P301-2 in the first region 301-2 may be the same or different. The doping concentration P301-1 in the first region 301-1 may be lower than either the doping concentration P302-1 in the second region 302-1 or the doping concentration P302-2 in the second region 302-2. The doping concentration P301-2 in the first region 301-2 is lower than either the doping concentration P302-1 in the second region 302-1 or the doping concentration P302-2 in the second region 302-2. The doping concentration P301-1 may be less than or equal to half of the doping concentration P302-1, or may be less than or equal to 1 / 10 thereof. The doping concentration P301-2 may be less than or equal to half of the doping concentration P302-2, or may be less than or equal to 1 / 10 thereof.

[0242] Between the first regions 301-1 and 301-2, there is a valley portion where the doping concentration shows a minimum value. The doping concentration of the valley portion may be the same as that of the drift region 18. In other examples, the doping concentration of the valley portion may be higher than that of the drift region 18. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, reduction in withstand voltage can be suppressed, and the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0243] FIG. 26 is a diagram showing another configuration example of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. The second mesa portion 62 in this example is the same as that in the example of FIG. 22. The first mesa portion 61 in this example has one or more first regions 301 in the depth direction. Each of the first regions 301 has a peak in doping concentration in the depth direction. The number of first regions 3�1 in the first mesa portion 61 is less than the number of second regions 302 in the second mesa portion 62. The second mesa portion 62 in this example has two second regions 302, and the first mesa portion 61 has one first region 301.

[0244] The third mesa portion 63 in this example has the same number of first regions 301 (or third region 303) as the first mesa portion 61. The structure other than the first region 301, second region 302, and third region 303 is the same as in any of the embodiments described herein.

[0245] Figure 27 shows an example of the doping concentration distribution along the gg and hh lines in Figure 26. The doping concentration distribution in the second mesa 62 in this example is the same as in the example in Figure 23.

[0246] In this example, the first mesa section 61 has one first region 301. The doping concentration P301 of the first region 301 may be smaller than that of either the second region 302-1 or the second region 302-2. In other examples, the doping concentration P301 of the first region 301 may be the same as that of either the second region 302-1 or the second region 302-2. Since the number of first regions 301 is less than the number of second regions 302, even if the doping concentrations of each peak are the same, the total dose of the first region 301 can be less than the total dose of the second region 302. According to this example, hole injection in the transistor section 70 near the diode section 80 can be adjusted to suppress the decrease in withstand capability and adjust the trade-off between reverse recovery loss and forward voltage.

[0247] Figure 28 shows other configuration examples of the first mesa section 61, the second mesa section 62, and the third mesa section 63. In this example, the number of first regions 301 in the first mesa section 61 is the same as the number of second regions 302 in the second mesa section 62. The number of first regions 301 (or third regions 303) in the third mesa section 63 may also be the same as the number of first regions 301 in the first mesa section 61. In the example in Figure 28, the first mesa section 61 has one first region 301, the second mesa section 62 has one second region 302, and the third mesa section 63 has one third region 303.

[0248] In this example, the width of the second region 302 in the depth direction is greater than the width of the first region 301 in the depth direction. Each region has a peak in doping concentration in the depth direction. The structure other than the first region 301, the second region 302, and the third region 303 is the same as in any of the embodiments described herein.

[0249] Figure 29 shows an example of the doping concentration distribution in the gg and hh lines of Figure 28. The second region 302 has one or more doping concentration peaks. The second region 302 in this example may be formed by injecting dopants at different depth positions. In this case, doping concentration peaks are provided at each depth position, but if the depth positions are close to each other, the doping concentration peaks may merge and be observed as a single peak.

[0250] In this example, the first region 301 has one peak in doping concentration. The first region 301 in this example may be formed by injecting a dopant at a single depth position. In this example, the depth-direction width W2 of the second region 302 is greater than the depth-direction width W1 of the first region 301. The width W2 may be 1.5 times or more the width W1, or it may be 2 times or more. The widths of the first region 301 and the second region 302 are the widths of the region in the N-type region between the base region 14 and the drift region 18 where the doping concentration is higher than that of the drift region 18.

[0251] The doping concentration P301 in the first region 301 may be smaller than the doping concentration P302 in the second region 302. In other examples, the doping concentration P301 in the first region 301 may be the same as the doping concentration P302 in the second region 302. In this example as well, the total dose in the first region 301 can be made less than the total dose in the second region 302. According to this example, hole injection in the transistor section 70 near the diode section 80 can be adjusted to suppress the decrease in withstand capability and adjust the trade-off between reverse recovery loss and forward voltage.

[0252] Figure 30 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the semiconductor device 100 described herein in that it does not have a lifetime adjustment region 206, an adjustment region 201, and a non-adjustment region 202. The other structures are the same as those of any embodiment of the semiconductor device 100 described herein. Figure 30 shows an example in which the lifetime adjustment region 206, an adjustment region 201, and a non-adjustment region 202 have been removed from the structure shown in Figure 3A, but the lifetime adjustment region 206, an adjustment region 201, and a non-adjustment region 202 may also be removed from the structures shown in other figures.

[0253] Figure 31 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the semiconductor device 100 described herein in that the lifetime adjustment region 206 is provided over the entire X-axis direction of the transistor section 70. Other structures are the same as those of the semiconductor device 100 in any embodiment described herein. In Figure 31, an example is shown in the structure shown in Figure 3A in which the lifetime adjustment region 206 is arranged over the entire transistor section 70, but in the structures shown in other figures, the lifetime adjustment region 206 may also be arranged over the entire transistor section 70.

[0254] Figure 32 shows another example of the ee cross section. The semiconductor device 100 in this example differs from the structure described in Figure 13 in the depth of the trench contacts 17-1 and 17-2. The other structures are the same as those of the semiconductor device 100 in any embodiment described herein.

[0255] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is shallower than the trench contact portion 17-1 of a first mesa portion 61 that is located closer to the diode portion 80 than that first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed shallower the further they are from the diode portion 80. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, suppressing a decrease in withstand voltage and adjusting the trade-off between reverse recovery loss and forward voltage.

[0256] Figure 33 shows another example of the ee cross section. The semiconductor device 100 in this example differs from the structure described in Figure 21A in the depth of the trench contacts 17-1 and 17-2. The other structures are the same as those of the semiconductor device 100 in any embodiment described herein.

[0257] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is shallower than the trench contact portion 17-1 of a first mesa portion 61 that is located closer to the diode portion 80 than that first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed shallower the further they are from the diode portion 80. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, suppressing a decrease in withstand voltage and adjusting the trade-off between reverse recovery loss and forward voltage.

[0258] Figure 34 shows another example of the ee cross section. The semiconductor device 100 in this example differs from the structure described in Figure 21B in the depth of the trench contacts 17-1 and 17-2. The other structures are the same as those of the semiconductor device 100 in any embodiment described herein.

[0259] In this example, the trench contact portion 17-2 of at least one second mesa portion 62 is shallower than the trench contact portion 17-1 of a second mesa portion 62 located closer to the diode portion 80 than that second mesa portion 62. The trench contact portions 17 of each second mesa portion 62 may be formed shallower the further they are from the diode portion 80. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, suppressing a decrease in withstand voltage and adjusting the trade-off between reverse recovery loss and forward voltage.

[0260] Figure 35 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the structure described in Figure 7 in that at least one first mesa portion 61 comprises a second contact portion 212. The other structures are the same as those of the semiconductor device 100 in any embodiment described herein. One or more first mesa portions 61 located closest to the second mesa portion 62 may also comprise the second contact portion 212.

[0261] In this example, at least one first mesa portion 61, like the second mesa portion 62, does not have a trench contact portion 17. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted to suppress the decrease in withstand voltage and adjust the trade-off between reverse recovery loss and forward voltage.

[0262] Figure 36 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the structure described in Figure 7 in that at least one second mesa portion 62 comprises a first contact portion 211. The other structures are the same as those of the semiconductor device 100 in any embodiment described herein. One or more second mesa portions 61 located closest to the first mesa portion 61 may comprise the first contact portion 211.

[0263] In this example, at least one second mesa portion 62 is equipped with a trench contact portion 17, similar to the first mesa portion 61. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted to suppress the decrease in withstand voltage and adjust the trade-off between reverse recovery loss and forward voltage.

[0264] FIG. 37 is a diagram showing another example of an e-e cross section. The semiconductor device 100 in this example is different in that at least one first mesa portion 61 includes a second contact portion 212 as compared with the structure described in FIG. 15. Other structures are the same as those of the semiconductor device 100 in any aspect described in this specification. One or more first mesa portions 61 disposed closest to the second mesa portion 62 may include the second contact portion 212.

[0265] In this example, at least one first mesa portion 61 includes a trench contact portion 17 in the same manner as the second mesa portion 62. According to this example, hole injection in the transistor portion 70 in the vicinity of the diode portion 80 can be adjusted, reduction of withstand voltage can be suppressed, and the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0266] FIG. 38 is a diagram showing another example of an e-e cross section. The semiconductor device 100 is different in that at least one second mesa portion 62 includes a first contact portion 211 as compared with the structure described in FIG. 15. Other structures are the same as those of the semiconductor device 100 in any aspect described in this specification. One or more second mesa portions 61 disposed closest to the first mesa portion 61 may include the first contact portion 211.

[0267] In this example, at least one second mesa portion 62 does not include a trench contact portion 17 in the same manner as the first mesa portion 61. According to this example, hole injection in the transistor portion 70 in the vicinity of the diode portion 80 can be adjusted, reduction of withstand voltage can be suppressed, and the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0268] Figure 39 shows another example of the ee cross-section. In this example, the semiconductor device 100 has a trench contact portion 17 in at least one third mesa portion 63 of the diode portion 80. All third mesa portions 63 of the diode portion 80 may have a trench contact portion 17. Also, at least one fourth mesa portion 64 of the boundary region 200 may have a trench contact portion 17. All fourth mesa portions 64 of the boundary region 200 may have a trench contact portion 17. Other structures are the same as those of the semiconductor device 100 in any embodiment described herein. Figure 39 shows an example in the structure shown in Figure 3A in which the third mesa portion 63 and the fourth mesa portion 64 have a trench contact portion 17, but in structures shown in other figures, the third mesa portion 63 and the fourth mesa portion 64 may also have a trench contact portion 17.

[0269] The trench contact portion 17 of the third mesa portion 63 may be formed shallower than the trench contact portion 17 of the transistor portion 70, may be formed deeper than the trench contact portion 17 of the transistor portion 70, or may be formed to the same depth. The trench contact portion 17 of the fourth mesa portion 64 may be formed shallower than the trench contact portion 17 of the transistor portion 70, may be formed deeper than the trench contact portion 17 of the transistor portion 70, or may be formed to the same depth.

[0270] As shown in Figure 39, the lower end of the third contact portion 213 may be positioned lower than the lower end of the second contact portion 212. The lower end of the third contact portion 213 may also be positioned at the same depth as the lower end of the second contact portion 212.

[0271] Figure 40 shows another example of the ee cross-section. In this example, the semiconductor device 100 has a third contact portion 213 of at least one third mesa portion 63 of the diode portion 80 positioned above the lower end of the second contact portion 212. The lower ends of the third contact portions 213 of all third mesa portions 63 of the diode portion 80 may be positioned above the lower ends of the second contact portions 212. The lower ends of the third contact portions 213 may be positioned at the same height as the upper surface 21 of the semiconductor substrate 10. The fourth mesa portion 64 of the boundary region 200 may have a third contact portion 213 similar to that of the third mesa portion 63. Other structures are the same as those of the semiconductor device 100 in any embodiment described herein.

[0272] The lower end of the third contact portion 213 may be positioned at the same depth as the lower end of the first contact portion 211. The lower end of the third contact portion 213 may be positioned above or below the lower end of the first contact portion 211. The lower end of the third contact portion 213 provided in the fourth mesa portion 64 and the third mesa portion 63 of the boundary region 200 may have a third plug region 223.

[0273] In this example, since the third contact portion 213 is formed shallowly, a large portion of the base region 14 of the third mesa portion 63 can be retained. Therefore, the amount of hole injected in the diode portion 80 can be increased, and the forward voltage can be reduced to adjust the trade-off with reverse recovery loss. Furthermore, even when a barrier metal is provided in the semiconductor device 100, the amount of barrier metal in the third contact portion 213 can be reduced. This suppresses hydrogen absorption in the third contact portion 213 and maintains the amount of hydrogen injected into the transistor portion 70 via the third contact portion 213. This suppresses a decrease in the threshold voltage of the transistor portion 70.

[0274] Figure 41 shows another example configuration of the first mesa section 61, the second mesa section 62, and the third mesa section 63. In this example, the first mesa section 61 is provided with a first contact section 211, the second mesa section 62 is provided with a second contact section 212, and the third mesa section 63 is provided with a third contact section 213.

[0275] The emitter electrode 52 in this example does not have a barrier metal portion 252 in the portion that contacts the semiconductor substrate 10. Furthermore, it does not have a first plug region 221, a second plug region 222, and a third plug region 223. Other structural features are the same as those of any of the semiconductor devices 100 described herein.

[0276] In this example as well, the dose amount in the first region 301 of the first mesa section 61 is made smaller than the dose amount in the second region 302 of the second mesa section 62. According to this example, hole injection in the transistor section 70 near the diode section 80 can be adjusted to suppress the decrease in withstand voltage and adjust the trade-off between reverse recovery loss and forward voltage.

[0277] Figure 42 shows another example configuration of the first mesa section 61, the second mesa section 62, and the third mesa section 63. This example differs from Figure 41 in that trench contact sections 17 are provided in the second mesa section 62 and the third mesa section 63.

[0278] In this example, the first mesa section 61 is provided with a first contact section 211. The second mesa section 62 is provided with a trench contact section 17 having a second contact section 212, and the third mesa section 6 3 It is equipped with a trench contact portion 17 having a third contact portion 213.

[0279] The emitter electrode 52 in this example does not have a barrier metal portion 252 in the portion that contacts the semiconductor substrate 10. Furthermore, it does not have a first plug region 221, a second plug region 222, and a third plug region 223. Other structural features are the same as those of any of the semiconductor devices 100 described herein. This allows for a reduction in the forward voltage by not providing a trench contact portion 17 in the first mesa portion 61 of the transistor portion 70. As described above, this example allows for adjustment of hole injection in the transistor portion 70 near the diode portion 80, suppression of reduced withstand capability, and adjustment of the trade-off between reverse recovery loss and forward voltage.

[0280] Figure 43 shows another example of the configuration of the first mesa section 61, the second mesa section 62, and the third mesa section 63. This example differs from Figure 41 in that a trench contact section 17 is provided in the first mesa section 61.

[0281] In this example, the second mesa section 62 is equipped with a second contact section 212, and the third mesa section 6 3 It is equipped with a third contact portion 213. Furthermore, the first mesa portion is equipped with a trench contact portion 17 having a first contact portion 211.

[0282] The emitter electrode 52 in this example does not have a barrier metal portion 252 in the portion that contacts the semiconductor substrate 10. Furthermore, it does not have a first plug region 221, a second plug region 222, and a third plug region 223. Other structural features are the same as those of any of the semiconductor devices 100 described herein. As a result, by providing a trench contact portion 17 in the first mesa portion 61 of the transistor portion 70, the reverse recovery loss can be reduced. Thus, according to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, suppressing a decrease in withstand voltage and adjusting the trade-off between reverse recovery loss and forward voltage.

[0283] In Figures 41, 42, and 43, the presence or absence of the trench contact portion 17 corresponds to the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. For example, all first mesa portions 61 may have the trench contact portion 17, or all first mesa portions 61 may not have the trench contact portion 17. Similarly, all second mesa portions 62 may have the trench contact portion 17, or all second mesa portions 62 may not have the trench contact portion 17. Similarly, all third mesa portions 63 may have the trench contact portion 17, or all third mesa portions 63 may not have the trench contact portion 17.

[0284] In other examples, the presence or absence of trench contact portions 17 is not required for all first mesa portions 61, second mesa portions 62, and third mesa portions 63. For example, some first mesa portions 61 may have trench contact portions 17, while the remaining first mesa portions 61 do not. Similarly, some second mesa portions 62 may have trench contact portions 17, while the remaining second mesa portions 62 do not. Similarly, some third mesa portions 63 may have trench contact portions 17, while the remaining third mesa portions 63 do not. Furthermore, there may be a fourth mesa portion 64 (not shown) that does not have a third plug region 223. This fourth mesa portion 64 that does not have a third plug region 223 may or may not have trench contact portions 17.

[0285] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0286] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order. [Explanation of Symbols]

[0287] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 17...Trench contact region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 29...Straight section, 30...Dummy trench section, 31...Tip section, 32...Dummy insulating film, 34... 38...Dummy conductive part, 39...Interlayer insulating film, 40...Straight section, 41...Tip section, 42...Gate insulating film, 44...Gate conductive part, 52...Emitter electrode, 54...Contact hole, 60...Mesa section, 61...First mesa section, 62...Second mesa section, 63...Third mesa section, 64...Fourth mesa section, 70...Transistor section, 80...Diode section, 81...Extended section Long region, 82... Cathode region, 90... Edge termination structure, 100... Semiconductor device, 130... Outer periphery gate wiring, 131... Active side gate wiring, 160... Active region, 162... Edge, 164... Gate pad, 200... Boundary region, 201... Adjustment region, 202... Non-adjustment region, 204... Lattice defect, 206... Lifetime adjustment region, 211... First contact region, 212... Second contact area, 213...Third contact area, 221...First plug area, 222...Second plug area, 223...Third plug area, 231...Peak, 232...Peak, 241, 242...Joint area, 251...Upper part, 252...Barrier metal part, 253...First layer, 254...Second layer, 255...Silicide layer, 301...First region, 302...Second region, 303...Third region

Claims

1. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, a transistor portion provided on the semiconductor substrate, and a diode portion provided on the semiconductor substrate and arranged alongside the transistor portion in a first direction, Each of the transistor section and the diode section is, A plurality of trench portions are provided from the upper surface to the interior of the semiconductor substrate and are arranged in the first direction, The semiconductor substrate comprises a plurality of mesa portions which are sandwiched between the two trench portions in the first direction. It has, The semiconductor substrate has a drift region of a first conductivity type and a base region of a second conductivity type disposed between the drift region and the upper surface. The plurality of mesa portions include a first mesa portion and a second mesa portion that is positioned further away from the diode portion than the first mesa portion. The first mesa portion has a first region of a first conductivity type, which is provided in at least a portion of the depth position between the lower end of the base region and the lower end of the trench portion. The second mesa portion is provided in at least a part of the depth position between the lower end of the base region and the lower end of the trench portion, and has a second region of a first conductivity type with a larger dose than the first region. The diode portion is located on the upper surface side of the semiconductor substrate and has a lifetime adjustment region including a lifetime killer that adjusts the lifetime of the carriers. The lifetime adjustment region is also provided in a part of the transistor section, The transistor section includes an adjustment region in which the lifetime adjustment region is provided and a non-adjustment region in which the lifetime adjustment region is not provided. At least one mesa portion in the adjustment region is the first mesa portion, At least one mesa portion in the non-adjusted region is the second mesa portion, The first region is a region with a higher doping concentration than the drift region. Semiconductor equipment.

2. All of the mesa portions in the adjustment region are the first mesa portions, All of the mesa portions in the non-adjusted region are the second mesa portions. The semiconductor device according to claim 1.

3. The first mesa portion is provided between the upper surface of the semiconductor substrate and the base region and has an emitter region with a doping concentration higher than that of the drift region. The semiconductor device according to claim 1 or 2.

4. The plurality of mesa portions include one or more of the second mesa portions, The lifetime adjustment region extends below at least one of the second mesa portions, but does not extend below any other second mesa portions. The semiconductor device according to claim 1.

5. The lifetime adjustment region is positioned away from the second mesa portion in the first direction. The semiconductor device according to claim 1 or 2.

6. The second region has a higher doping concentration than the first region. The semiconductor device according to claim 1 or 2.

7. The number of doping concentration peaks in the depth direction of the second region is greater than the number of doping concentration peaks in the depth direction of the first region. The semiconductor device according to claim 1 or 2.

8. The width in the depth direction of the second region is greater than the width in the depth direction of the first region. The semiconductor device according to claim 1 or 2.

9. The dose per unit area of ​​the second region is greater than the dose per unit area of ​​the first region. The semiconductor device according to claim 1 or 2.

10. The plurality of mesa portions include a third mesa portion arranged in the diode portion. The third mesa section is, A second conductivity type anode region is disposed between the drift region and the upper surface, It has a third region of the first conductivity type, which is provided in at least a portion between the depth position of the lower end of the anode region and the depth position of the lower end of the trench portion, The second region has a larger dose than the third region. The semiconductor device according to claim 1 or 2.

11. Each of the transistor section and the diode section has a metal electrode provided above the upper surface of the semiconductor substrate. The first mesa portion has a first contact portion into which the metal electrode makes contact, The second mesa portion has a second contact portion into which the metal electrode makes contact, The lower end of the second contact portion is positioned above the lower end of the first contact portion. The semiconductor device according to claim 1 or 2.

12. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, a transistor portion provided on the semiconductor substrate, and a diode portion provided on the semiconductor substrate and arranged alongside the transistor portion in a first direction, Each of the transistor section and the diode section is, A plurality of trench portions are provided from the upper surface to the interior of the semiconductor substrate and are arranged in the first direction, The semiconductor substrate comprises a plurality of mesa portions which are sandwiched between the two trench portions in the first direction. It has, The semiconductor substrate has a drift region of a first conductivity type and a base region of a second conductivity type disposed between the drift region and the upper surface. The plurality of mesa portions include a first mesa portion and a second mesa portion that is positioned further away from the diode portion than the first mesa portion. The first mesa portion has a first region of a first conductivity type, which is provided in at least a portion of the depth position between the lower end of the base region and the lower end of the trench portion. The second mesa portion is provided in at least a part of the depth position between the lower end of the base region and the lower end of the trench portion, and has a second region of a first conductivity type with a larger dose than the first region. The diode portion is located on the upper surface side of the semiconductor substrate and has a lifetime adjustment region including a lifetime killer that adjusts the lifetime of the carriers. Each of the transistor section and the diode section has a metal electrode provided above the upper surface of the semiconductor substrate. The first mesa portion has a first contact portion into which the metal electrode makes contact, The second mesa portion has a second contact portion into which the metal electrode makes contact, The lower end of the first contact portion is positioned above the lower end of the second contact portion. Semiconductor equipment.

13. The adjustment region includes the first mesa portion and the second mesa portion, The number of the first mesa portion in the adjustment region is equal to or greater than the number of the second mesa portion in the adjustment region. The semiconductor device according to claim 1.

14. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, a transistor portion provided on the semiconductor substrate, and a diode portion provided on the semiconductor substrate and arranged alongside the transistor portion in a first direction, Each of the transistor section and the diode section is, A plurality of trench portions are provided from the upper surface to the interior of the semiconductor substrate and are arranged in the first direction, The semiconductor substrate comprises a plurality of mesa portions which are sandwiched between the two trench portions in the first direction. It has, The semiconductor substrate has a drift region of a first conductivity type and a base region of a second conductivity type disposed between the drift region and the upper surface. The plurality of mesa portions include a first mesa portion and a second mesa portion that is positioned further away from the diode portion than the first mesa portion. The first mesa portion has a first region of a first conductivity type, which is provided in at least a portion of the depth position between the lower end of the base region and the lower end of the trench portion. The second mesa portion is provided in at least a part of the depth position between the lower end of the base region and the lower end of the trench portion, and has a second region of a first conductivity type with a larger dose than the first region. The diode portion is located on the upper surface side of the semiconductor substrate and has a lifetime adjustment region including a lifetime killer that adjusts the lifetime of the carriers. The lifetime adjustment region is also provided in a part of the transistor section, The transistor section includes an adjustment region in which the lifetime adjustment region is provided and a non-adjustment region in which the lifetime adjustment region is not provided. At least a portion of the adjustment region is the first mesa portion, The density of lattice defects in the lifetime adjustment region within the adjustment region decreases as it moves away from the diode portion. In the adjustment region, the doping concentration in the first region is higher the further the first mesa portion is from the diode portion. Semiconductor equipment.

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