Field-effect transistor
The field-effect transistor design addresses dielectric breakdown risks by using a trench with a specific curvature and low-concentration n-layer to manage electric fields, maintaining low on-resistance and preventing dielectric breakdown.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2025-09-18
- Publication Date
- 2026-07-29
AI Technical Summary
The provision of a current diffusion n-layer in field-effect transistors leads to easy diffusion of current and reduced on-resistance, but it also causes a high electric field in the gate insulating film, increasing the risk of dielectric breakdown.
The field-effect transistor design includes a trench with a specific curvature on its side surface and a low-concentration n-layer at the bottom connection surface, preventing excessive electric fields from applying to the gate insulating film by ensuring the current-diffusing n-layer contacts the gate insulating film on the side surface with a radius of curvature of 0.7 μm or more.
This design effectively suppresses dielectric breakdown of the gate insulating film while maintaining low on-resistance by distributing the n-type impurity concentration and using a low-concentration n-layer to manage electric fields.
Smart Images
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Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to a field-effect transistor.
[0002] The field-effect transistor disclosed in Patent Document 1 has a trench-type gate electrode. Further, this field-effect transistor has an n-type source layer, a p-type body layer, and a lower n-layer disposed below the body layer in a range contacting the gate insulating film. When a predetermined potential is applied to the gate electrode, a channel is formed in the body layer, and the source layer and the lower n-layer are connected in the channel. Thereby, the field-effect transistor is turned on.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In a range adjacent to the body layer in the lower n-layer, a current diffusion n-layer having a high n-type impurity concentration may be provided. According to this configuration, electrons flowing from the channel into the lower n-layer diffuse horizontally in the current diffusion n-layer. Therefore, the current diffuses and flows easily in a region below the current diffusion n-layer in the lower n-layer (so-called drift layer), and the on-resistance of the field-effect transistor is reduced. However, when the current diffusion n-layer is provided, a high electric field is likely to occur in the gate insulating film in a range adjacent to the current diffusion n-layer. In this specification, a technique for suppressing dielectric breakdown of the gate insulating film when the current diffusion n-layer is provided is proposed.
Means for Solving the Problems
[0005] The field-effect transistor disclosed herein comprises a semiconductor substrate having a trench on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed within the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has an n-type source layer in contact with the gate insulating film, a p-type body layer in contact with the gate insulating film below the source layer, and a lower n-layer disposed below the body layer. The lower n-layer has a current-diffusing n-layer in contact with the body layer from below, and a low-concentration n-layer in contact with the current-diffusing n-layer from below and having a lower n-type impurity concentration than the current-diffusing n-layer. The n-type impurity concentration distribution in the current-diffusing n-layer in the depth direction of the semiconductor substrate is distributed to have a peak value. The inner surface of the trench has a side surface composed of a surface with a radius of curvature of 0.7 μm or more, and a bottom connection surface that connects the side surface to the lower end of the trench and is composed of a concave curved surface with a radius of curvature of less than 0.7 μm. The portion of the current-diffusing n layer having the peak value is in contact with the gate insulating film on its side surface.
[0006] A high electric field is easily applied to the gate insulating film in the area covering the bottom connection surface. Therefore, if a high-density n-layer is in contact with the gate insulating film in the area covering the bottom connection surface, an excessively high electric field is easily applied to the gate insulating film in that area, making the gate insulating film prone to dielectric breakdown. In contrast, in the field-effect transistor disclosed herein, the portion having the peak value of the current-diffusing n-layer is in contact with the gate insulating film on the side surface of the trench. The side surface of the trench is composed of a relatively flat surface with a radius of curvature of 0.7 μm or more. Therefore, even if the portion having the peak value of the current-diffusing n-layer is in contact with the gate insulating film on the side surface of the trench, it is possible to prevent the electric field applied to the gate insulating film from becoming excessively high. Consequently, in this field-effect transistor, the gate insulating film is less prone to dielectric breakdown. [Brief explanation of the drawing]
[0007] [Figure 1] Cross-sectional perspective view of the MOSFET of Example 1. [Figure 2] Enlarged cross-sectional view of the top of the MOSFET in Example 1. [Figure 3] Enlarged cross-sectional view of the top of the MOSFET in Example 2. [Figure 4] Enlarged cross-sectional view of the top of the MOSFET in Example 3. [Figure 5] Enlarged cross-sectional view of the top of the MOSFET in Example 4. [Figure 6] Enlarged cross-sectional view of the top of the MOSFET in Example 5. [Modes for carrying out the invention]
[0008] In the field-effect transistor described above, the current-diffusing n-layer does not need to be in contact with the gate insulating film at the bottom connection surface.
[0009] This configuration allows for more effective suppression of dielectric breakdown in the gate insulating film.
[0010] The field-effect transistor described above may further have a bottom p-layer that contacts the gate insulating film at the lower end of the trench.
[0011] This configuration makes it possible to suppress the electric field applied to the gate insulating film around the lower end of the trench.
[0012] In the field-effect transistor described above, the bottom p layer may be in contact with the current-diffusing n layer to the extent that it is in contact with the gate insulating film. The thickness of the current-diffusing n layer between the body layer and the bottom p layer may be 0.1 μm or more.
[0013] This configuration allows for reliable separation of the body layer and the bottom p-layer by the current-diffusing n-layer. [Examples]
[0014] The MOSFET (metal-oxide-semiconductor field effect transistor) 10 shown in FIGS. 1 and 2 has a semiconductor substrate 12. In FIGS. 1 and 2, the x-direction is a direction parallel to the upper surface 12a of the semiconductor substrate 12, and the y-direction is a direction parallel to the upper surface 12a and perpendicular to the x-direction. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si or GaN. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends in the y-direction on the upper surface 12a. The trenches 14 are arranged at intervals in the x-direction. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is arranged in each trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is arranged above the semiconductor substrate 12. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. The gate electrode 18 is insulated from the source electrode 22 by the interlayer insulating film 20. The lower surface 12b of the semiconductor substrate 12 is covered with a drain electrode 24.
[0015] As shown in FIG. 2, the trench 14 has a side surface 14a, a bottom connection surface 14b, and a bottom surface 14c. The side surface 14a is a flat surface (more specifically, a surface with a radius of curvature in the cross section of 0.7 μm or more) extending along the depth direction (i.e., the thickness direction) of the semiconductor substrate 12. The bottom surface 14c is a surface extending substantially parallel to the upper surface 12a of the semiconductor substrate 12 and constitutes the lower end of the trench 14. The bottom connection surface 14b is a concave curved surface connecting the lower end of the side surface 14a and the bottom surface 14c. In the cross section, the radius of curvature of the bottom connection surface 14b is less than 0.7 μm.
[0016] The semiconductor substrate 12 has a source layer 30, a body contact layer 32, a body layer 34, a bottom p-layer 36, a connection p-layer 38, and a lower n-layer 40.
[0017] The source layer 30 is an n-type layer and is in contact with the gate insulating film 16 at the upper end of the side surface 14a of the trench 14. The source layer 30 is in ohmic contact with the source electrode 22.
[0018] The body contact layer 32 is a p-type layer and is in ohmic contact with the source electrode 22 at a position adjacent to the source layer 30.
[0019] The body layer 34 is a p-type layer with a lower p-type impurity concentration than the body contact layer 32. The body layer 34 contacts the source layer 30 and the body contact layer 32 from below. The body layer 34 contacts the gate insulating film 16 below the source layer 30. The body layer 34 contacts the gate insulating film 16 on the side surface 14a of the trench 14.
[0020] The bottom p-layer 36 is a p-type layer and is in contact with the gate insulating film 16 on the bottom surface 14c of the trench 14. The bottom p-layer 36 extends along the y direction along the bottom surface 14c of the trench 14.
[0021] The connecting p-layer 38 is a p-type layer and protrudes downward from the body layer 34. The connecting p-layer 38 extends linearly along the x direction when viewed from above the semiconductor substrate 12. The connecting p-layer 38 extends to the depth of the bottom p-layer 36 in the depth direction. The connecting p-layer 38 connects the body layer 34 and the bottom p-layer 36.
[0022] The lower n-layer 40 is disposed below the body layer 34. The lower n-layer 40 is separated from the source layer 30 by the body layer 34. The lower n-layer 40 extends from the position of the lower end of the body layer 34 to the lower surface 12b of the semiconductor substrate 12. The lower n-layer 40 has a current diffusion n-layer 40a, an electric field relaxation n-layer 40b, a drift layer 40c, a buffer layer 40d, and a drain layer 40e.
[0023] The current-diffusing n-layer 40a is an n-type layer having a relatively high concentration of n-type impurities. The current-diffusing n-layer 40a is in contact with the body layer 34 from below. The current-diffusing n-layer 40a is in contact with the gate insulating film 16 on the underside of the body layer 34.
[0024] The electric field relaxation n layer 40b is an n-type layer having a lower n-type impurity concentration than the current diffusion n layer 40a. The electric field relaxation n layer 40b is in contact with the current diffusion n layer 40a from below. The electric field relaxation n layer 40b is distributed from the lower end of the current diffusion n layer 40a to a position below the bottom p layer 36. The electric field relaxation n layer 40b is in contact with the gate insulating film 16 below the current diffusion n layer 40a. The electric field relaxation n layer 40b is in contact with the side and bottom surfaces of the bottom p layer 36.
[0025] The drift layer 40c is an n-type layer having a lower n-type impurity concentration than the field-relaxed n-layer 40b. The drift layer 40c is in contact with the field-relaxed n-layer 40b from below.
[0026] The buffer layer 40d is an n-type layer having a higher n-type impurity concentration than the drift layer 40c. The buffer layer 40d is in contact with the drift layer 40c from below.
[0027] The drain layer 40e is an n-type layer having a higher n-type impurity concentration than the buffer layer 40d. The drain layer 40e is in contact with the buffer layer 40d from below. The drain layer 40e is in ohmic contact with the drain electrode 24.
[0028] As shown in Figure 2, within the current-diffusing n layer 40a, the n-type impurity concentration is distributed in a normal distribution in the depth direction of the semiconductor substrate 12. Within the current-diffusing n layer 40a, the n-type impurity concentration is distributed in a normal distribution in the depth direction of the semiconductor substrate 12 such that it has a peak value nmax. In other words, the region where the n-type impurity concentration is distributed in a normal distribution such that it has a peak value nmax is the current-diffusing n layer 40a. Within the electric field relaxation n layer 40b, the n-type impurity concentration is distributed at a nearly constant value that is lower than that within the current-diffusing n layer 40a. Within the drift layer 40c, the n-type impurity concentration is distributed at a nearly constant value that is lower than that within the electric field relaxation n layer 40b.
[0029] The portion of the current-diffusing n-layer 40a having a peak value nmax is in contact with the gate insulating film 16 on the side surface 14a of the trench 14 (i.e., the surface with a radius of curvature of 0.7 μm or more). In Example 1, the entire current-diffusing n-layer 40a is in contact with the gate insulating film 16 on the side surface 14a of the trench 14. That is, the current-diffusing n-layer 40a is not in contact with the gate insulating film 16 at the bottom connection surface 14b of the trench 14. The electric field relaxation n-layer 40b is in contact with the gate insulating film 16 in the range between the current-diffusing n-layer 40a and the bottom p-layer 36. The electric field relaxation n-layer 40b is in contact with the gate insulating film 16 at the bottom connection surface 14b.
[0030] When the MOSFET 10 is in use, a higher potential is applied to the drain electrode 24 than to the source electrode 22. The potential of the gate electrode 18 is controlled independently of the potentials of the drain electrode 24 and the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the area adjacent to the gate insulating film 16 within the body layer 34, and the source layer 30 and the current-diffusing n layer 40a are connected by this channel. Then, electrons flow from the source layer 30 to the drain layer 40e via the channel, current-diffusing n layer 40a, field-relaxing n layer 40b, drift layer 40c, and buffer layer 40d. This turns on the MOSFET 10. The current-diffusing n layer 40a has a relatively high n-type impurity concentration and therefore has low resistance. Consequently, electrons flowing from the channel into the current-diffusing n layer 40a tend to flow along the x-direction within the current-diffusing n layer 40a. Therefore, within the drift layer 40c, which is located below the current-diffusing n layer 40a, electrons flow toward the drain layer 40e while dispersed in the x direction. Because electrons flow dispersedly within the drift layer 40c in this way, the on-resistance of the MOSFET 10 is low.
[0031] When the potential of the gate electrode 18 is reduced to a potential below the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET 10 turns off. Then, a depletion layer extends from the body layer 34 into the current diffusion n layer 40a, the field relaxation n layer 40b, and the drift layer 40c. The depletion layer extending into the current diffusion n layer 40a, the field relaxation n layer 40b, and the drift layer 40c maintains the voltage between the drain electrode 24 and the source electrode 22. Also, when the MOSFET 10 turns off, a depletion layer extends from the bottom p layer 36 into the surrounding field relaxation n layer 40b. The depletion layer extending from the bottom p layer 36 suppresses electric field concentration near the lower end of the trench 14.
[0032] When the current-diffusing n layer 40a and the electric field-relaxing n layer 40b become depleted, an electric field is applied to the gate insulating film 16. The electric field tends to concentrate in the curved portion of the gate insulating film 16. That is, the electric field tends to concentrate more in the gate insulating film 16 covering the bottom connection surface 14b than in the gate insulating film 16 covering the side surface 14a. On the other hand, if the density of fixed charges present in the depletion layer in contact with the gate insulating film 16 is high, the electric field applied to the gate insulating film 16 will be high. That is, the higher the n-type impurity concentration in the n-type layer in contact with the gate insulating film 16, the higher the electric field applied to the gate insulating film 16. In this embodiment, at the bottom connection surface 14b where electric field concentration is likely to occur, the electric field-relaxing n layer 40b with a low n-type impurity concentration is in contact with the gate insulating film 16. This prevents an excessively high electric field from being applied to the gate insulating film 16 covering the bottom connection surface 14b, and thus suppresses dielectric breakdown of the gate insulating film 16 in this portion. Furthermore, the current-diffusing n layer 40a, which has a high concentration of n-type impurities, is connected to the gate insulating film 16 on the side surface 14a where electric field concentration is less likely to occur. Therefore, an excessively high electric field is prevented from being applied to the gate insulating film 16 in the area where the current-diffusing n layer 40a is in contact, and dielectric breakdown of the gate insulating film 16 is suppressed in this area.
[0033] As described above, the MOSFET 10 of this embodiment can reduce the on-resistance of the MOSFET 10 by the current-diffusing n layer 40a while suppressing dielectric breakdown of the gate insulating film 16. [Examples]
[0034] In the MOSFET of Example 2 shown in Figure 3, the thickness of the current-diffusing n layer 40a is greater than that of the MOSFET 10 in Example 1. The other configurations of the MOSFET of Example 2 are the same as those of the MOSFET 10 in Example 1.
[0035] In Example 2, the lower end of the current-diffusing n layer 40a is in contact with the gate insulating film 16 at the bottom connection surface 14b. However, the portion of the current-diffusing n layer 40a having a peak value nmax is in contact with the gate insulating film 16 at the side surface 14a. That is, the portion having a peak value nmax is not in contact with the gate insulating film 16 at the bottom connection surface 14b, while the portion of the current-diffusing n layer 40a with a low n-type impurity concentration is in contact with the gate insulating film 16 at the bottom connection surface 14b. Therefore, even with this configuration, the electric field applied to the portion of the gate insulating film 16 covering the bottom connection surface 14b can be suppressed. [Examples]
[0036] The bottom p-layer 36 can be formed by ion implanting p-type impurities into the bottom of the trench 14 before the formation of the gate electrode 18. In this case, as shown in Figure 4, the bottom p-layer 36 may be formed such that it contacts the current-diffusing n-layer 40a from below in the area that contacts the gate insulating film 16. In this configuration, the bottom p-layer 36 is in contact with the gate insulating film 16 over the entire bottom connection surface 14b. Even in this configuration, the electric field applied to the gate insulating film 16 covering the bottom connection surface 14b can be reduced.
[0037] In Figure 4, if the thickness T of the current-diffusing n layer 40a is too thin, the separation of the body layer 34 and the bottom p layer 36 will be insufficient, and the characteristics of the MOSFET will deteriorate. To ensure the separation of the body layer 34 and the bottom p layer 36, the thickness T of the current-diffusing n layer 40a between the body layer 34 and the bottom p layer 36 can be made thicker than the width W of the depletion layer that forms in the current-diffusing n layer 40a when no voltage is applied to the MOSFET. The width W of the depletion layer can be calculated using the following formula. W=(2εVbi / qNd) -1 / 2 In the above equation, ε is the dielectric constant of the semiconductor substrate 12, Vbi is the built-in potential, q is the elementary charge, and Nd is the n-type impurity concentration of the current-diffusing n layer 40a. The built-in potential Vbi can be calculated using the following formula. Vbi = (kT / q) × ln(NaNd / ni) 2 ) In the above equation, k is Boltzmann's constant, T is temperature, Na is the p-type impurity concentration in body layer 34, and ni is the intrinsic carrier density. More specifically, Na = 4 × 10 17 cm -3 Nd = 3 × 10 17 cm -3 ni = 1 × 10 -8 cm -3 In this case, the thickness T can be 0.1 μm or more. [Examples]
[0038] In the MOSFET of Example 4 shown in Figure 5, the electric field relaxation n layer 40b is absent, and the drift layer 40c is in contact with the current diffusion n layer 40a from below. The other configurations of the MOSFET of Example 4 are the same as those of the MOSFET 10 of Example 1. In Example 4, the drift layer 40c, which has an even lower n-type impurity concentration than the electric field relaxation n layer 40b, is in contact with the gate insulating film 16 at the bottom connection surface 14b. Therefore, the electric field applied to the gate insulating film 16 covering the bottom connection surface 14b can be suppressed more effectively. [Examples]
[0039] In the MOSFET of Example 5 shown in Figure 6, the bottom p-layer 36 is absent. In this case, the connecting p-layer 38 may not be provided. The other configurations of the MOSFET of Example 5 are the same as those of the MOSFET of Example 4. Even with this configuration, the electric field applied to the gate insulating film 16 covering the bottom connection surface 14b can be suppressed. In Examples 1 and 2, the bottom p-layer 36 may not be provided.
[0040] The electric field relaxation n-layer 40b in Examples 1-3 and the drift layer 40c in Examples 4 and 5 are examples of low-concentration n-layers.
[0041] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]
[0042] 10: MOSFET, 12: Semiconductor substrate, 14: Trench, 14a: Side, 14b: Bottom connection surface, 16: Gate insulating film, 18: Gate electrode, 34: Body layer, 40a: Current diffusion n layer, 40b: Field relaxation n layer, 40c: Drift layer
Claims
1. It is a field-effect transistor, A semiconductor substrate having multiple trenches on its upper surface, A gate insulating film covering the inner surface of each trench, A gate electrode, which is disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film, It has, The aforementioned semiconductor substrate An n-type source layer in contact with each of the aforementioned gate insulating films, A p-type body layer in contact with each gate insulating film on the lower side of the source layer, A lower n layer located below the body layer, At the lower end of each trench, a bottom p layer in contact with the gate insulating film, A plurality of connecting p layers are provided, which protrude downward from the body layer, extend linearly along the direction intersecting each trench, and connect the body layer and each bottom p layer. It has, The aforementioned lower n layer is A current-diffusing n-layer is in contact with the body layer from below, A low-concentration n-layer is in contact with the current-diffusing n-layer from below and has a lower n-type impurity concentration than the current-diffusing n-layer. It has, The n-type impurity concentration distribution in the current-diffusing n-layer of the semiconductor substrate in the depth direction is distributed such that it has a peak value. The inner surface of each trench is A side surface composed of a surface with a radius of curvature of 0.7 μm or more, A bottom connecting surface is formed by a concave curved surface with a radius of curvature of less than 0.7 μm, connecting the aforementioned side surface and the aforementioned lower end of the trench. It has, The portion of the current diffusion n layer having the peak value is in contact with each of the gate insulating films on the side surface. In the range between the current-diffusing n layer and the bottom p layer, the low-concentration n layer is in contact with each of the gate insulating films at the bottom connection surface. Field-effect transistor.
2. The field-effect transistor according to claim 1, wherein the current-diffusing n layer is not in contact with the gate insulating film at the bottom connection surface.
3. The field-effect transistor according to claim 1 or 2, further comprising a bottom p layer in contact with the gate insulating film at the lower end of the trench.
4. The bottom p layer is in contact with the current diffusion n layer in the area in contact with the gate insulating film, The thickness of the current diffusion n layer between the body layer and the bottom p layer is 0.1 μm or more. The field-effect transistor according to claim 3.