Image sensor

Abstract

This imaging element comprises: a storage unit that stores a signal read from a pixel; a shift register that transfers the signal stored in the storage unit by a clock signal that has been supplied; a clock signal propagation circuit that propagates the clock signal through a plurality of inverters that are mutually connected in series; and a load circuit that matches the load of a first inverter, from among the plurality of inverters, that supplies the clock signal to the shift register, with a load of a second inverter, from among the plurality of inverters, that supplies the clock signal to the first inverter.

Description

Technical Field

[0001] The present invention relates to an imaging device. This application claims priority based on Japanese Patent Application No. 2023-033771 filed on March 6, 2023, the content of which is incorporated herein by reference.

Background Art

[0002] An imaging device capable of processing signals output from a plurality of pixels in parallel is known (for example, Patent Document 1). Conventionally, an increase in current consumption caused by processing signals output from pixels in parallel has been a problem.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] One aspect of the present invention is an imaging device including a storage unit that stores a signal read from a pixel, a shift register that transfers the signal stored in the storage unit by a supplied clock signal, a clock signal propagation circuit that propagates the clock signal through a plurality of inverters connected in series to each other, a load of a first inverter that supplies the clock signal to the shift register among the plurality of inverters, and a load circuit that matches a load of a second inverter that supplies the clock signal to the first inverter among the plurality of inverters.

Brief Description of the Drawings

[0005] [Figure 1] It is a diagram showing an outline of the configuration of the imaging device of this embodiment. [Figure 2] In this embodiment, it is a diagram showing a configuration example of a data bus circuit included in a pixel unit circuit and a peripheral circuit included in a pixel array. [Figure 3] This is a timing chart illustrating an example of the operation in which the pixel unit circuit measures the exposure charge amount in this embodiment. [Figure 4] This diagram shows the flow of operations in which the data bus circuit reads AD conversion result data from the pixel unit circuit in this embodiment. [Figure 5] This is a schematic diagram showing an example of the data bus circuit configuration in this embodiment. [Figure 6] This figure shows the detailed configuration of the clock repeater circuit in the image sensor of this embodiment. [Figure 7] This figure shows an example of a conventional clock repeater circuit configuration. [Figure 8] This figure shows an example of how the duty cycle of a clock signal changes when a conventional clock repeater circuit is configured with a smaller inverter. [Modes for carrying out the invention]

[0006] The embodiments will be described in detail below with reference to the drawings.

[0007] Figure 1 is a schematic diagram of the configuration of an image sensor according to an embodiment. The image sensor 1 is a circuit that captures an image of a subject, and takes light emitted by the subject as input and outputs digital image data (hereinafter referred to as "image data") that represents the subject. The image sensor 1 includes, for example, a pixel array 11 and peripheral circuits 12. The pixel array 11 is a collection of individual pixel circuits (hereinafter referred to as "pixel unit circuits") that constitute the digital image. The pixel unit circuit generates a digital signal that represents the subject in the area corresponding to its own pixel within the imaging range. The pixel unit circuit 20 shown in Figure 1 schematically represents the fact that a pixel unit circuit is provided corresponding to each pixel of the image data.

[0008] The peripheral circuit 12 reads pixel signals from each pixel unit circuit of the pixel array 11 and outputs each read pixel signal to other circuits. Specifically, the peripheral circuit 12 comprises a shift register and a data bus circuit including a clock repeater circuit. The peripheral circuit 12 drives the shift register with a clock signal supplied by the clock repeater circuit, thereby sequentially reading pixel signals from each pixel unit circuit into the shift register. The peripheral circuit 12 can acquire pixel signals from all pixel unit circuits included in the pixel array 11 by sequentially saving the pixel signals read into the shift register to memory or the like.

[0009] The peripheral circuit 12 may be configured to perform predetermined processing on each pixel signal read from the pixel array 11 before outputting it. For example, the peripheral circuit 12 may be configured to output a result of filtering or correction processing on each read pixel signal. For example, the peripheral circuit 12 may be configured to generate image data based on each read pixel signal and output the generated image data.

[0010] Figure 2 shows an example of the configuration of a data bus circuit provided by the pixel unit circuit and peripheral circuit 12 included in the pixel array 11. The pixel unit circuit 20 includes a photodiode PD, a transfer transistor TX, a floating diffusion FD, a reset transistor RST, a power supply VDD, an ADC (Analog-to-Digital Converter) 21, a control circuit 22, and a memory 23. The photodiode PD is a light-receiving element that converts light into electric charge. The photodiode PD stores an amount of charge corresponding to the intensity of the incident light. The ADC 21 includes a comparator CMP. The ADC 21 and the control circuit 22 convert the amount of charge generated by exposure of the photodiode PD into a digital signal and store it in the memory 23. The memory 23 is an example of a "storage unit".

[0011] Specifically, the transfer transistor TX transfers charge from the photodiode PD to the floating diffusion transistor FD. The floating diffusion transistor FD receives the charge from the photodiode PD via the transfer transistor TX and converts the charge into a voltage. The reset transistor RST resets the potential of the floating diffusion transistor FD. VDD is the power supply potential. The comparator CMP outputs "1" when the inverting input potential is lower than the reference potential RAMP, which is the non-inverting input. The comparator CMP outputs "0" when the inverting input potential is higher than the reference potential RAMP. The reference potential RAMP is controlled by the control circuit 22.

[0012] With this configuration, the control circuit 22 measures the amount of charge generated by exposure of the photodiode PD (hereinafter referred to as "exposure charge") and stores the measured value as a pixel value in the memory 23. Each pixel unit circuit 20 performs this operation, thereby acquiring data for the entire image. Methods for measuring exposure charge include the SS (Single Slope) method, which measures a small amount of light; the so-called LOFIC (Lateral Over Flow Integration Capacitor) method, which stores the excess charge in the floating diffusion FD for measurement; and the PFM (Pulse Frequency Modulation) method, which measures the amount of charge based on the number of resets while resetting the charge in the floating diffusion FD. However, the method for measuring exposure charge is not limited to a specific one. The method for measuring exposure charge may also be a hybrid method combining these methods.

[0013] For example, when there is a large amount of incident light, the saturation of the charge generated in the photodiode PD overflows into the FD, causing the FD potential to decrease over time. When the control circuit 22 detects that the FD potential has fallen below the reference potential RAMP(Qth), that is, that the output of CMP has changed from "0" to "1", it resets the charge of the floating diffusion FD. By counting the number of these resets, the control circuit 22 measures the amount of charge generated by exposure to the photodiode PD (hereinafter referred to as "exposure charge") and stores this measured value as a pixel value in the memory 23. By having each pixel unit circuit 20 perform this operation, data for the entire image is acquired. (PFM method)

[0014] On the other hand, if the incident light is not as abundant as described above (i.e., less than the RAMP voltage (Qth) in PFM mode), the reference potential RAMP is changed from a low potential to a high potential in response to the signal overflowing to the FD. When the output of the comparator CMP changes from "0" to "1", the charge of the floating diffusion FD is reset, and the reference potential RAMP is reset to its initial value. By measuring the time when the output of CMP changes, the amount of charge generated by the exposure of the photodiode PD is measured, and this measured value is stored as a pixel value in memory 23. (SS method)

[0015] Figure 3 is a timing chart illustrating an example of the operation of the pixel unit circuit 20 in which exposure charge is measured in a hybrid manner. In the operation example in Figure 3, exposure of the photodiode PD during the period when the transfer transistor TX is ON causes the reset counter cnt to count up from 1 to a final value of 4, and the final charge amount of the floating diffusion FD is Qend. In this case, the control circuit 22 can calculate the exposure charge amount Qtx as Qtx = Qpd + 4 × Qth + Qend, based on the final value of the reset counter cnt (4), the final charge amount of the floating diffusion FD (Qend), a threshold Qth for determining the reset timing of the charge amount of the floating diffusion FD, and the charge amount Qpd based on the capacitance of the photodiode PD. In other words, the example in Figure 3 measures up to the final value of the reset counter cnt (4) using the PFM method, and then measures up to the final charge amount Qend using the SS method. In the PFM method, the charge of the floating diffusion FD is reset according to the result of a comparison with a fixed reference potential RAMP. In the SS method, the charge quantity Qend is measured by sweeping the reference potential RAMP.

[0016] Returning to Figure 2, the data bus circuit 30 will now be described. The data bus circuit 30 includes, for example, a shift register 31 and a clock repeater circuit 32. The shift register 31 sequentially reads data indicating the result of AD conversion (hereinafter referred to as "AD conversion result data") from the memory 23 of each pixel unit circuit 20, while switching the source memory 23 in synchronization with the clock signal supplied from the clock repeater circuit 32. The clock repeater circuit 32 is connected to the shift register 31 for each pixel in the clock signal propagation direction and transmits the clock signal in the clock signal propagation direction while repeatedly supplying and amplifying the signal. The AD conversion result data read into the shift register 31 is recorded as the pixel value of the image data after the necessary processing has been performed.

[0017] FIG. 4 is a diagram showing the flow of an operation in which the data bus circuit 30 reads AD conversion result data from the pixel unit circuit 20. The horizontal axis represents the time axis. FIG. 4 shows the flow of an operation in the case of measuring the exposure charge amount by the PFM method at high light amounts. In FIG. 4, steps S1 to S9 are repeated for each reset of the floating diffusion FD, and an operation of reducing noise by CDS (Correlated double sampling) processing is shown. Noise reduction by CDS processing is realized by two operations, DARK conversion and SIG conversion. DARK conversion is an AD conversion process for measuring the potential immediately after the reset of the floating diffusion FD. SIG conversion is an AD conversion process for measuring the amount of charge accumulated in the floating diffusion FD after the reset. In CDS processing, by subtracting the potential measured by DARK conversion from the potential measured by SIG conversion, a measurement result with reduced influence of noise due to dark current can be obtained.

[0018] In CDS processing, the operation of the pixel unit circuit 20 and the operation of the data bus circuit 30 are performed in parallel. An example of a specific operation of CDS processing will be described. First, the pixel unit circuit 20 turns on the reset transistor RST, whereby the floating diffusion FD is reset (step S1). When the floating diffusion FD is reset, subsequently, DARK conversion is performed by the ADC21 (step S2: DARK conversion).

[0019] The data bus circuit 30 supplies a clock signal for data writing to the pixel unit circuit 20 in parallel with the DARK conversion in step S2. When the clock signal for data writing is supplied to the pixel unit circuit 20, the AD conversion result data of the DARK conversion is written into the memory 23 of the pixel unit circuit 20 (step S3: data write (1)). When the AD conversion result data of the DARK conversion is written into the memory 23, the data bus circuit 30 supplies a clock signal for data reading to the pixel unit circuit 20. When the clock signal for data reading is supplied to the pixel unit circuit 20, the AD conversion result data of the DARK conversion written into the memory 23 of the pixel unit circuit 20 is read out to the peripheral circuit 12 (step S4: data read (1)).

[0020] When the DARK conversion in step S2 is completed, the pixel unit circuit 20 waits for a predetermined time until charge is accumulated in the photodiode PD (step S5: IDLE), and then turns on the transfer transistor TX. When the transfer transistor TX is turned on, the charge transfer from the photodiode PD to the floating diffusion FD is performed in parallel with the data reading in step S4 (step S6: PD charge transfer). When the charge is transferred from the photodiode PD to the floating diffusion FD, subsequently, in the pixel unit circuit 20, the SIG conversion is performed by the ADC21 (step S7: SIG conversion).

[0021] The data bus circuit 30 supplies a clock signal for data writing to the pixel unit circuit 20 in parallel with the SIG conversion in step S7. When the clock signal for data writing is supplied to the pixel unit circuit 20, the AD conversion result data of the SIG conversion is written to the memory 23 of the pixel unit circuit 20 (step S8: data writing (2)). Once the AD conversion result data of the SIG conversion is written to the memory 23, the data bus circuit 30 supplies a clock signal for data reading to the pixel unit circuit 20. When the clock signal for data reading is supplied to the pixel unit circuit 20, the AD conversion result data of the SIG conversion written to the memory 23 of the pixel unit circuit 20 is read out to the peripheral circuit 12 (step S9: data reading (2)).

[0022] As described above, in the image sensor 1 of this embodiment, the memory 23 for storing AD conversion result data is shared between DARK conversion and SIG conversion, so the writing and reading of AD conversion result data for DARK conversion and SIG conversion are repeatedly performed in series. In such a configuration, if the data reading time becomes long, the time interval (CDS interval) between DARK conversion and SIG conversion becomes long, and the reading noise increases. If the memory 23 is not shared, the writing and reading of AD conversion result data for DARK conversion and SIG conversion can be performed in parallel, but in a configuration such as the image sensor 1 of this embodiment, where an ADC 21 is provided for each pixel unit circuit 20, the difficulty of constructing the circuit increases. Therefore, when an ADC 21 is provided for each pixel unit circuit 20 and the memory 23 is shared between DARK conversion and SIG conversion, it is required to keep the CDS interval as short as possible.

[0023] Figure 5 is a schematic diagram showing an example configuration of the data bus circuit 30. Figure 5 shows how the AD conversion result data stored in each pixel of the pixel array 11 is read out to the shift register 31 in groups of M clusters of a predetermined size. A cluster is a set of a predetermined number of consecutive pixels. Figure 5 shows the case where one cluster is a set of N pixels.

[0024] For example, the shift register 31 has D flip-flop circuits 33 for each cluster, corresponding to the resolution of the ADC 21 (in this case, k bits). By inputting a clock signal to the D flip-flop circuits 33 of each cluster, the AD conversion result data is sequentially read from the N pixel memories 23-1 to N in synchronization with the clock signal and read into the k D flip-flop circuits 33. This operation is performed in parallel for each of the M clusters.

[0025] On the other hand, the clock repeater circuit 32 has a configuration in which a first inverter 41A and a second inverter 41B are connected in series for each cluster. The first inverter 41A and second inverter 41B of each cluster amplify the clock signal supplied from the first inverter 41A and second inverter 41B of the preceding cluster and supply it to the shift register 31.

[0026] Generally, electronic circuits contain capacitive components that are not intended by the designer, due to wiring, electronic components, or their physical structure. These capacitive components, called parasitic capacitance, can cause malfunctions because they repeatedly charge and discharge during circuit operation. For example, in the data bus circuit 30 shown in Figure 5, the shift register 31 and clock repeater circuit 32 also have parasitic capacitance. As the circuit operates at high frequency and high speed, the frequency of charge and discharge per unit time increases, and therefore the current generated by parasitic capacitance (hereinafter referred to as "parasitic current") also increases. This increase in parasitic current causes a voltage drop due to the resistive component (so-called IR drop), which lowers the operating voltage and increases the likelihood of malfunction.

[0027] The image sensor 1 of this embodiment suppresses malfunctions due to parasitic capacitance by having a clock repeater circuit 32 with the configuration described below. First, before describing the details of the clock repeater circuit 32, the configuration of a conventional clock repeater circuit will be described.

[0028] Figure 7 shows an example of a conventional clock repeater circuit configuration. As shown in Figure 7, the conventional clock repeater circuit 90 has a configuration in which two inverters 91 are connected in series adjacent to each other, and a D flip-flop circuit (D-FF) 92 corresponding to one cluster is connected between each pair of adjacent inverters 91 connected in series. Hereafter, the repeating unit of circuit in such a repeater configuration will be called a "stage". In other words, in Figure 7, the first stage includes the first inverter 91A, the second inverter 91B, the D flip-flop circuit 92, and the parasitic capacitance 93. In Figure 7, the parasitic capacitance 93 is represented by the circuit symbol for a capacitive element (capacitor). However, the parasitic capacitance 93 represents the capacitive component described above and does not necessarily have to be a capacitive element.

[0029] In conventional clock repeater circuits, the transistor size (e.g., number of fingers, hereinafter simply referred to as "size") is large (for example, several tens of fingers), and two inverters 91 of different sizes are connected in series. Figure 7 shows an example where, of the first inverter 91A and the second inverter 91B connected adjacently in series, the second inverter 91B, which is closer to the subsequent D flip-flop circuit 92, is larger in size than the first inverter 91A, which is further from the D flip-flop circuit 92. In Figure 7, the capacitive elements 93 include the parasitic capacitance that the clock repeater circuit 90 has for each stage. Since the clock repeater circuit 90 is a repeater configuration that repeats the configuration for each stage, the capacitive elements 93 for each stage are basically of similar capacitance.

[0030] In the clock repeater circuit 90, the second inverter 91B supplies the clock signal to the D flip-flop circuit 92. In this case, the first inverter 91A receives a non-inverting phase clock signal and outputs an inverting phase clock signal, while the second inverter 91B receives an inverting phase clock signal and outputs a non-inverting phase clock signal. That is, the first inverter 91A is driven by a pMOS transistor, and the second inverter 91B is driven by an nMOS transistor.

[0031] Thus, in the conventional clock repeater circuit 90, two large inverters 91 were connected in series adjacent to each other in one stage, resulting in a large gate parasitic capacitance. This generated a large parasitic current, which could cause the data bus circuit to malfunction. In contrast, it is conceivable to connect an inverter of a smaller size (for example, a few fingers to a dozen or so fingers), but in this case, the reduction in gate size decreases the driving force of the nMOS (negative-channel metal oxide semiconductor) and pMOS (positive-channel metal oxide semiconductor) that make up the inverter. This can cause a change in the duty cycle of the clock signal, potentially leading to malfunctions in the data bus circuit.

[0032] Figure 8 shows an example of the change in the duty cycle of a clock signal when a conventional clock repeater circuit is configured with a smaller inverter. As an example, Figure 8 shows the change in the duty cycle of a non-inverting phase clock signal. In this case, the rising edge of the input signal is affected by the operating speed of the nMOS of the second inverter 91B, and the falling edge is affected by the operating speed of the pMOS of the first inverter 91A.

[0033] Generally, because the operating speed of pMOS is faster than that of nMOS, the difference between the rising edge and the falling edge tends to widen in the first inverter 91A, while the difference tends to narrow in the second inverter 91B. In a conventional clock repeater circuit, the second inverter 91B is larger and has a stronger driving force than the first inverter 91A, so the overall tendency for the difference between the rising edge and the falling edge to narrow is greater. Therefore, in a clock repeater circuit, as the clock signal propagates in the propagation direction, the difference between the rising edge and the falling edge narrows, and the time during which the clock signal can be recognized as high level gradually decreases. In other words, the duty cycle gradually decreases.

[0034] For example, Figure 8 illustrates a case where the duty cycle, which was 50% at position y0 in the propagation direction (the position where the initial clock signal is input), decreases as the clock signal propagates, becoming zero at position y3. In other words, this can be described as a situation where the fast-acting falling edge catches up with the slow-acting rising edge. In such a situation, the clock signal cannot be correctly recognized as high level after position y0 (i.e., a portion of the clock signal is lost), which can lead to malfunctions. Furthermore, the likelihood of such malfunctions increases as the operating speed increases, that is, as the frequency of the clock signal increases.

[0035] If the size of both the first inverter 91A and the second inverter 91B is increased, they can be operated with sufficient driving force, thus reducing the likelihood of the falling edge catching up to the rising edge, but the circuit size will increase. On the other hand, if the size of both the first inverter 91A and the second inverter 91B is simply reduced, the circuit size will decrease, but the likelihood of the falling edge catching up to the rising edge will increase, making it easier for the clock to disappear.

[0036] In this embodiment, the image sensor 1 is configured to have an ADC 21 for each pixel unit circuit 20. Therefore, it is desirable to reduce the circuit size of components other than the ADC 21 as much as possible. However, simply reducing the size of the inverter in a conventional configuration increases the likelihood of malfunction, as described above. In this embodiment, the image sensor 1 can solve this problem by having a clock repeater circuit 32 with the configuration shown in Figure 6.

[0037] Figure 6 shows a detailed configuration of the clock repeater circuit 32 in the image sensor 1 of this embodiment. The clock repeater circuit 32 in this embodiment includes a clock signal propagation circuit 40 that propagates a clock signal, and a load circuit 50 that applies the same load to each inverter 41 included in the clock signal propagation circuit 40.

[0038] Specifically, in a conventional clock repeater circuit configuration, the load on the first inverter 91A and the load on the second inverter 91B were different in each stage. In contrast, in the clock signal propagation circuit 40 of this embodiment, the load circuit 50 is connected to both the first inverter 41A and the second inverter 41B within one stage and between adjacent stages.

[0039] Figure 6 shows an example in which a shift register 31 and a first capacitance element 52A are connected sequentially between the output side of the first inverter 41A and the input side of the second inverter 41B, and a dummy circuit D and a second capacitance element 52B are connected sequentially between the output side of the second inverter 41B and the input side of the first inverter 41A. In this case, the non-inverting phase circuit and the inverting phase circuit are configured such that the first load on the first inverter 41A and the second load on the second inverter 41B are of the same magnitude. The first load and the second load may be adjusted by the configuration of the clock signal propagation circuit 40 or by the configuration of the load circuit 50.

[0040] For example, the first load may be adjusted by the first capacitive element 52A, by the size of the first amplifying element 51A connected to the shift register 31, or by the wiring configuration (thickness, length, etc.) between the output side of the first inverter 41A and the input side of the second inverter 41B. Similarly, the second load may be adjusted by the second capacitive element 52B, by the size of the second amplifying element 51B connected to the dummy circuit D, or by the wiring configuration between the output side of the second inverter 41B and the input side of the first inverter 41A.

[0041] Thus, in the clock repeater circuit 32 of this embodiment, the clock signal propagation circuit 40 and the load circuit 50 should be configured such that the load of the first inverter 41A and the load of the second inverter 41B are the same magnitude. However, in order to simplify the configuration, the circuit configurations of the non-inverting phase and the inverting phase can preferably be made symmetrical. That is, the clock repeater circuit 32 can preferably be configured such that each component satisfies at least the following conditions.

[0042] (1) The size of the first inverter 41A and the size of the second inverter 41B are the same. (2) The wiring spacing from the first inverter 41A to the second inverter 41B is the same as the wiring spacing from the second inverter 41B to the first inverter 41A. (3) The first capacitance element 52A and the second capacitance element 52B have the same capacitance. (4) The size of the first amplification element 51A connected to the shift register 31 and the size of the second amplification element 51B connected to the dummy circuit D are the same.

[0043] The embodiments of the present invention have been described above, but here we will provide a supplementary explanation regarding the correspondence between the present invention and the above embodiments.

[0044] (1) In the above embodiment, the image sensor 1 includes a memory 23 for storing signals read from pixels, a shift register 31 for transferring the signals stored in the memory 23 by a supplied clock signal, a clock signal propagation circuit 40 for propagating the clock signal through a plurality of inverters 41 connected in series with each other, and a load circuit 50 for matching the load of a first inverter 41A that supplies the clock signal to the shift register 31 with the load of a second inverter 41B that supplies the clock signal to the first inverter 41A.

[0045] With the image sensor 1 configured in this way, it is possible to average out the tendency for the difference between the rising edge and falling edge of the clock signal, thereby suppressing malfunctions of the data bus circuit 30.

[0046] (2) In addition, in the above embodiment, the load circuit 50 can be configured to include a capacitive element with a capacity that matches the output load of the first inverter 41A and the output load of the second inverter 41B.

[0047] (3) In addition, in the above embodiment, the load circuit 50 can be configured such that the output side of the first inverter 41A is provided with a first amplification element 51A that amplifies the input to the shift register 31, and the output side of the second inverter 41B is provided with a second amplification element 51B that matches the load of the first amplification element 51A.

[0048] (4) In addition, in the above embodiment, each of the plurality of inverters 41 can be configured to connect to other adjacent inverters 41 at equal intervals, thereby configuring the clock signal propagation circuit 40.

[0049] With this configuration, the output load of the first inverter 41A and the output load of the second inverter 41B can be matched, and the driving force of the rising edge and the falling edge of the clock signal can be made equal.

[0050] (5) In addition, in the above embodiment, the clock signal propagation circuit 40 can be configured such that a plurality of inverters 41 are composed of inverters having the same driving force.

[0051] This configuration allows the driving force for the rising edge and falling edge of the clock signal to be made equal, and also allows the non-inverting phase subsystem and the inverting phase subsystem to have the same configuration.

[0052] (6) In addition, in the above embodiment, the clock signal propagation circuit 40 can be configured such that the plurality of inverters 41 are inverters having a number of fingers ranging from a few fingers to more than ten fingers.

[0053] This configuration allows for a reduction in circuit size while suppressing malfunctions of the data bus circuit 30.

[0054] (7) In addition, in the above embodiment, the clock signal propagation circuit 40 and the load circuit 50 can be configured such that the non-inverting phase subcircuit having the first inverter 41A and the inverting phase subcircuit having the second inverter 41B have the same configuration.

[0055] With this configuration, the clock signal propagation circuit 40 can be constructed by repeating the same subcircuit configuration, thereby suppressing malfunctions of the data bus circuit 30 and making it easier to construct the image sensor 1.

[0056] In the above embodiment, an example of a hybrid method was shown for AD conversion. However, the above circuit configurations do not necessarily require that the AD conversion method of the pixel unit circuit 20 be a hybrid method. For example, the above circuit configurations are applicable when reading AD conversion result data from a pixel unit circuit 20 that performs AD conversion using an SS method that does not store the number of resets, and also when reading AD conversion result data from a pixel unit circuit 20 that performs AD conversion using a PFM method that stores the number of resets.

[0057] Although one embodiment of this invention has been described in detail above with reference to the drawings, the specific configuration is not limited to that described above, and various design changes can be made without departing from the spirit of this invention. [Explanation of Symbols]

[0058] 1…Image sensor, 11…Pixel array, 12…Peripheral circuitry, 20…Pixel unit circuitry, 21…ADC, 22…Control circuitry, 23…Memory, 30…Data bus circuitry, 31…Shift register, 32…Clock repeater circuitry, 33…D flip-flop circuitry, 40…Clock signal propagation circuitry, 41…Inverter, 41A…First inverter, 41B…Second inverter, 50…Load circuitry, 51A…First amplifier element, 51B…Second amplifier element, 52A…First capacitor element, 52B…Second capacitor element, 90…Clock repeater circuitry, 91…Inverter, 91A…First inverter, 91B…Second inverter, 92…D flip-flop circuitry, 93…Capacitor element

Claims

1. A memory unit that stores the signals read from the pixels, A shift register that transfers the signal stored in the memory unit based on the supplied clock signal, A clock signal propagation circuit that propagates the clock signal through a plurality of inverters connected in series with each other, A load circuit that matches the load of the first inverter that supplies the clock signal to the shift register among the plurality of inverters with the load of the second inverter that supplies the clock signal to the first inverter among the plurality of inverters, An image sensor equipped with the following features.

2. The load circuit includes a capacitive element with a capacitance that matches the output load of the first inverter with the output load of the second inverter. The image sensor according to claim 1.

3. The aforementioned load circuit is The output side of the first inverter is provided with a first amplification element that amplifies the input to the shift register, The output side of the second inverter is provided with a second amplification element that matches the load of the first amplification element. The image sensor according to claim 1.

4. In the clock signal propagation circuit, each of the plurality of inverters is connected to other adjacent inverters at equal intervals. The image sensor according to claim 1.

5. In the clock signal propagation circuit, the plurality of inverters are composed of inverters having the same driving force. The image sensor according to claim 1.

6. In the clock signal propagation circuit, the plurality of inverters are composed of inverters having a number of fingers ranging from a few fingers to a dozen or so fingers. The image sensor according to claim 5.

7. The clock signal propagation circuit and the load circuit are configured such that the non-inverting phase subcircuit having a first inverter and the inverting phase subcircuit having a second inverter have the same configuration. The image sensor according to claim 1.

Images