Drive circuits and semiconductor devices
The drive circuit for SiC and GaN power semiconductor devices prevents false firing and reduces switching losses by managing gate potential with controlled voltage signals, addressing the challenges of lower threshold voltages and substrate films.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SANKEN ELECTRIC CO LTD
- Filing Date
- 2023-03-16
- Publication Date
- 2026-07-29
AI Technical Summary
SiC and GaN power semiconductor devices experience false firing due to lower substrate films and lower gate drive threshold voltages, leading to increased switching losses and noise during transitions.
A drive circuit configuration with a first and second switching circuit and a control circuit that applies drive and potential control signals with specific cycles to manage the gate potential, ensuring a negative voltage margin and controlling the slope of voltage changes to prevent false firing and reduce switching losses.
The drive circuit effectively prevents false firing and reduces switching losses and noise by maintaining a negative gate-source voltage margin and optimizing voltage transition slopes.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a drive circuit for driving a power semiconductor device and a semiconductor device.
Background Art
[0002] Currently, in many electrical devices, power semiconductor devices are used for conversion of electrical energy, motor drive, etc. Examples of power semiconductor devices include insulated gate bipolar transistors on a silicon substrate, metal oxide semiconductor field effect transistors on a silicon substrate (hereinafter referred to as Si devices), metal oxide semiconductor field effect transistors on a silicon carbide substrate (hereinafter referred to as SiC devices), and field effect transistors using gallium nitride (GaN) crystals (hereinafter referred to as GaN devices).
[0003] A power semiconductor device is driven by a drive circuit. The drive circuit includes a switching circuit that applies a gate drive signal to the gate terminal of the power semiconductor device, and a control circuit that controls the switching circuit. The power semiconductor device changes its turn-on time, turn-off time, associated switching loss, and noise during transition according to the gate drive signal applied from the switching circuit. Therefore, the drive circuit needs to apply a gate drive signal with an appropriate profile to the power semiconductor device.
[0004] Regarding gate drive signals with appropriate profiles, various methods have been devised. For example, in order to simply switch the switching speed of a power semiconductor device (Si device) between a high-speed mode and a low-speed mode, a technique of connecting a capacitor and a switch in series between the gate and emitter of this power semiconductor device has been proposed (see, for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0005] [[ID=XX]] [[ID=XX]]
Patent Document 1
[0006] When using SiC or GaN elements as power semiconductor devices, they have the advantage of reducing switching losses because their on-resistance is lower compared to Si elements. However, SiC and GaN elements have thinner substrate films and lower gate drive threshold voltages (Vth) compared to Si elements, which leads to the problem of false firing when the element is off.
[0007] This invention was made in view of the aforementioned problems, and its objective is to provide a drive circuit and semiconductor device that can prevent false firing while achieving both a reduction in switching loss and a reduction in noise during transitions. [Means for solving the problem]
[0008] To achieve the above objective, the drive circuit according to the present invention is configured as follows. The drive circuit according to the present invention is a drive circuit for driving a power semiconductor element and comprises: a first switching circuit connected between the positive and negative terminals of a power supply for the drive circuit, with its output node connected to the negative terminal of the power semiconductor element; a second switching circuit connected between the positive and negative terminals of the power supply for the drive circuit, with its output node connected to the control terminal of the power semiconductor element; and a control circuit that drives the first switching circuit with a drive control signal that switches between a high level and a low level in a first cycle that turns the power semiconductor element on and off, and drives the second switching circuit with a potential control signal that switches between a high level and a low level in a second cycle that is shorter than the first cycle. Furthermore, the drive circuit according to the present invention is a drive circuit for driving a power semiconductor element, comprising: a power supply for a first drive circuit; a power supply for a second drive circuit connected in series with the power supply for the first drive circuit, the positive terminal connected to the negative terminal of the power supply for the first drive circuit being connected to the negative terminal side terminal of the power semiconductor element; a first switching circuit connected between the positive terminal of the power supply for the first drive circuit and the negative terminal of the power supply for the second drive circuit, the output node being connected to the control terminal of the power semiconductor element; and a control circuit that drives the first switching circuit with a drive control signal that switches between a high level and a low level in a first cycle for turning the power semiconductor element on and off, and switches between a high level and a low level in a second cycle shorter than the first cycle during the turn-on period when the power semiconductor element transitions from off to on and the turn-off period when the power semiconductor element transitions from on to off. [Effects of the Invention]
[0009] The drive circuit of the present invention controls the potential of the control terminal to a negative potential lower than the potential of the negative terminal when the power semiconductor element is off, thereby making the voltage between the control terminal and the negative terminal negative. This ensures a margin up to the threshold voltage of the power semiconductor element, and thus prevents mis-pointing of the power semiconductor element even at low threshold voltages. [Brief explanation of the drawing]
[0010] [Figure 1] This figure shows the configuration of a first embodiment of the drive circuit according to the present invention. [Figure 2] Figure 1 shows a waveform diagram illustrating the output signal of the control circuit. [Figure 3] This figure shows the down converter configured by the second switching circuit shown in Figure 1. [Figure 4] Figure 1 is a waveform diagram showing the operation of the drive circuit when it is turned on. [Figure 5] Figure 1 shows a waveform diagram illustrating the operation of the drive circuit during turn-off. [Figure 6]This figure shows the configuration of a second embodiment of the drive circuit according to the present invention. [Figure 7] Figure 6 shows the waveform of the output signal of the control circuit. [Figure 8] Figure 6 is a waveform diagram showing the operation of the drive circuit when it is turned on. [Figure 9] Figure 3 is a waveform diagram showing the operation of the drive circuit when it is turned off. [Modes for carrying out the invention]
[0011] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
[0012] (First Embodiment) The drive circuit 1 of the first embodiment, as shown in Figure 1, is a circuit that drives a power semiconductor element P1 utilizing a silicon carbide (SiC) substrate or gallium nitride (GaN) crystal. The power semiconductor element P1 is, for example, a MOSFET (metal oxide semiconductor field-effect transistor) equipped with a gate terminal G which is a control terminal, a drain terminal D which is a positive terminal, and a source terminal S which is a negative terminal. The power semiconductor element P1 is used as a switching element in a power conversion device such as an inverter circuit.
[0013] The drive circuit 1 is a semiconductor device integrated on a semiconductor substrate, and comprises a first switching circuit 10, a second switching circuit 20, and a control circuit 30 that controls the first switching circuit 10 and the second switching circuit 20.
[0014] The first switching circuit 10 is a push-pull circuit (also called a totem-pole circuit) connected between the positive terminal Vp and the negative terminal Vn of the power supply V for the drive circuit. The first switching circuit 10 is, for example, a series circuit consisting of a first upper arm switch element PM1 and a first lower arm switch element NM1.
[0015] The first upper arm switch element PM1 is composed of a P-type MOSFET, and the first lower arm switch element NM1 is composed of an N-type MOSFET. The source of the first upper arm switch element PM1 is connected to the positive electrode Vp of the power supply V for the drive circuit, the drain of the first upper arm switch element PM1 is connected to the drain of the first lower arm switch element NM1, and the source of the first lower arm switch element NM1 is connected to the negative electrode Vn of the power supply V for the drive circuit, respectively. [[ID=
[0021] The drive control signal S10 shown in Figure 2(a) is a pulse signal such as a PWM signal that switches between a high level (Hi) and a low level (Low) during the first on / off cycle T1 of the power semiconductor element P1. The drive control signal S10 is input to the gates of the first upper arm switch element PM1 and the first lower arm switch element NM1 in the first switching circuit 10.
[0022] The potential control signal S20 shown in Figure 2(b) is a signal that controls the potential Vg of the gate terminal G of the power semiconductor element P1. It is a pulse signal such as a PWM signal that switches between high and low levels in a second period T2 which is sufficiently shorter than the first period T1. The potential control signal S20 is set to a frequency (1 / T2) that is sufficiently higher than the frequency (1 / T1) of the drive control signal S10.
[0023] Referring to Figure 1, a parasitic inductance Lp1 exists in the wiring connecting the output node N2 and the gate terminal G of the power semiconductor element P1, and a parasitic inductance Lp2 exists in the wiring connecting the output node N1 and the source terminal S of the power semiconductor element P1. In addition, a gate capacitance Cgs exists between the gate terminal G and the source terminal S of the power semiconductor element P1. Therefore, as shown in Figure 3, the second switching circuit 20 constitutes a pseudo-down converter with the parasitic inductances Lp1 and Lp2 and the gate capacitance Cgs. When considered as a pseudo-down converter, the input voltage is V, the output voltage is Vgs, and the load is Cgs.
[0024] In Figure 3, parasitic inductances Lp1 and Lp2 are equivalently combined into one. Figure 3(a) shows the state where the first lower arm switch element NM1 is ON (the first upper arm switch element PM1 is OFF) and the source terminal S of the power semiconductor element P1 is connected to the negative terminal Vn of the drive circuit power supply V. Figure 3(b) shows the state where the first upper arm switch element PM1 is ON (the first lower arm switch element NM1 is OFF) and the source terminal S of the power semiconductor element P1 is connected to the positive terminal Vp of the drive circuit power supply V.
[0025] When considered as a pseudo-downconverter, the potential Vg of the gate terminal G of the power semiconductor element P1 is controlled to a predetermined value less than or equal to the potential Vp of the positive terminal of the power supply V for the drive circuit, depending on the duty cycle of the potential control signal S20. The potential Vg of the gate terminal G is controlled to be higher as the duty cycle of the potential control signal S20 decreases and the high-level period becomes shorter, and lower as the duty cycle of the potential control signal S20 increases and the high-level period becomes longer.
[0026] The operation during turn-on will be explained in detail with reference to Figure 4. When the drive control signal S10 shown in Figure 4(a) is at a low level, the first upper arm switch element PM1 is in the ON state, and the first lower arm switch element NM1 is in the OFF state. Therefore, the potential Vs of the source terminal S of the power semiconductor element P1 is the potential Vp of the positive terminal of the power supply V for the drive circuit.
[0027] As shown in Figure 4(b), the potential Vg of the gate terminal G of the power semiconductor element P1 is controlled to a predetermined value less than or equal to the potential Vp of the positive terminal of the power supply V for the drive circuit, according to the duty cycle of the potential control signal S20. From the perspective of the power semiconductor element P1, the potential Vg of the gate terminal G is a negative potential lower than the potential Vs of the source terminal S, and the voltage Vgs between the gate and source becomes negative. This ensures a margin up to the threshold voltage Vth of the power semiconductor element P1, so that even if the threshold voltage Vth is low, mis-firing of the power semiconductor element P1 is prevented.
[0028] When the drive control signal S10 shown in Figure 4(a) transitions to a high level at time t1, the first upper arm switch element PM1 turns off, and the first lower arm switch element NM1 turns on. Consequently, the potential Vs of the source terminal S of the power semiconductor element P1 drops to the potential of the negative terminal Vn of the power supply V for the drive circuit. The slope at which the potential Vs drops is determined by the parasitic inductance Lp1 and wiring resistance of the wiring connecting the output node N2 and the gate terminal G of the power semiconductor element P1, the gate capacitance Cgs of the power semiconductor element P1, and so on.
[0029] The potential Vg of the gate terminal G of the power semiconductor element P1 is controlled to a predetermined value according to the duty cycle of the potential control signal S20 shown in Figure 4(b). As the potential Vs of the source terminal S decreases, the voltage Vgs between the gate and source increases, as shown in Figure 4(c). When the voltage Vgs between the gate and source exceeds the threshold voltage Vth of the power semiconductor element P1, drain current begins to flow, and the power semiconductor element P1 transitions to the ON state.
[0030] During the period when the voltage Vgs between the gate and source rises (the turn-on period when the power semiconductor element P1 transitions from off to on), the control circuit 30 controls the duty cycle of the potential control signal S20 to change the potential Vg of the gate terminal G, thereby adjusting the slope of the rise in voltage Vgs to an appropriate profile. In the early part of the turn-on period (for example, the period until the voltage Vgs reaches the threshold voltage Vth), the control circuit 30 sets the potential Vg of the gate terminal G to a low value. This reduces the rate of change of the drain current over time and suppresses the occurrence of surges. In the later part of the turn-on period (for example, the period after the voltage Vgs reaches the threshold voltage Vth), the control circuit 30 sets the potential Vg of the gate terminal G to a high value. This shortens the turn-on period and suppresses switching losses.
[0031] The operation during turn-off will be explained in detail with reference to Figure 5. When the drive control signal S10 shown in Figure 5(a) transitions to a low level at time t2, the first upper arm switch element PM1 turns ON, and the first lower arm switch element NM1 turns OFF. Consequently, the potential Vs of the source terminal S of the power semiconductor element P1 rises to the potential Vp of the positive terminal of the power supply V for the drive circuit. The slope at which the potential Vs rises is determined by the parasitic inductance Lp1 and wiring resistance of the wiring connecting the output node N2 and the gate terminal G of the power semiconductor element P1, the gate capacitance Cgs of the power semiconductor element P1, and so on.
[0032] The potential Vg of the gate terminal G of the power semiconductor element P1 is controlled to a predetermined value according to the duty cycle of the potential control signal S20 shown in Figure 5(b). As the potential Vs of the source terminal S rises, the voltage Vgs between the gate and source decreases, as shown in Figure 5(c). When the voltage Vgs between the gate and source falls below the threshold voltage Vth of the power semiconductor element P1, the power semiconductor element P1 transitions to the off state.
[0033] During the period when the voltage Vgs between the gate and source decreases (the turn-off period when the power semiconductor element P1 transitions from on to off), the control circuit 30 controls the duty cycle of the potential control signal S20 to change the potential Vg of the gate terminal G, thereby adjusting the slope of the decrease in voltage Vgs to an appropriate profile. In the initial part of the turn-off period (for example, the period until the voltage Vgs reaches the threshold voltage Vth), the control circuit 30 sets the potential Vg of the gate terminal G to a low value. This shortens the turn-off period and suppresses switching losses. In the later part of the turn-off period (for example, the period after the voltage Vgs reaches the threshold voltage Vth), the control circuit 30 sets the potential Vg of the gate terminal G to a high value. This reduces the rate of change of the drain current over time and suppresses the occurrence of surges.
[0034] (Second Embodiment) Referring to Figure 6, the drive circuit 1a of the second embodiment is a circuit that drives a power semiconductor element P1 using a silicon carbide (SiC) substrate or gallium nitride (GaN) crystal, similar to the drive circuit 1 of the first embodiment.
[0035] The drive circuit 1a is a semiconductor device integrated on a semiconductor substrate and comprises a first switching circuit 10 and a control circuit 30a that controls the first switching circuit 10.
[0036] A power supply V1 for the first drive circuit and a power supply V2 for the second drive circuit are connected in series, and the connection point Vc between the negative terminal of the power supply V1 for the first drive circuit and the positive terminal of the power supply V2 for the second drive circuit is connected to the source terminal S of the power semiconductor element P1. The first switching circuit 10 is a push-pull circuit (also called a totem-pole circuit) connected between the positive terminal Vp of the power supply V1 for the first drive circuit and the negative terminal Vn of the power supply V2 for the second drive circuit. The first switching circuit 10 is, for example, a series circuit consisting of a first upper arm switch element PM1 and a first lower arm switch element NM1.
[0037] The first upper arm switch element PM1 is a P-type MOSFET, and the first lower arm switch element NM1 is an N-type MOSFET. The source of the first upper arm switch element PM1 is connected to the positive terminal Vp of the power supply V for the first drive circuit, the drain of the first upper arm switch element PM1 is connected to the drain of the first lower arm switch element NM1, and the source of the first lower arm switch element NM1 is connected to the negative terminal Vn of the power supply V for the second drive circuit.
[0038] In the first switching circuit 10, the output node N1, that is, the connection point between the drain of the first upper arm switch element PM1 and the drain of the first lower arm switch element NM1, is connected to the gate terminal G of the power semiconductor element P1.
[0039] The control circuit 30a outputs a drive control signal S11 to the first switching circuit 10. The drive control signal S11 is a signal that controls the on / off state of the power semiconductor element P1. The drive control signal S11 is input to the gates of the first upper arm switch element PM1 and the first lower arm switch element NM1 in the first switching circuit 10.
[0040] As shown in Figure 7, the drive control signal S11 is a pulse signal such as a PWM signal that switches between a high level and a low level during the first on / off cycle T1 of the power semiconductor element P1. The drive control signal S11 is a pulse signal (for example, a pulse-modulated signal such as PWM) that switches between a high level and a low level during a second cycle that is sufficiently shorter than the first cycle T1, during the turn-on period when the power semiconductor element P1 transitions from off to on, and during the turn-off period when the power semiconductor element P1 transitions from on to off.
[0041] Referring to Figure 6, a parasitic inductance Lp1 exists in the wiring connecting the output node N1 and the gate terminal G of the power semiconductor element P1, and a parasitic inductance Lp2 exists in the wiring connecting the connection point Vc and the source terminal S of the power semiconductor element P1. In addition, a gate capacitance Cgs exists between the gate terminal G and the source terminal S of the power semiconductor element P1. Therefore, the first switching circuit 10 constitutes a pseudo-downconverter with the parasitic inductances Lp1 and Lp2 and the gate capacitance Cgs. When considered as a pseudo-downconverter, the input voltage during the on period is V1, the input voltage during the off period is V2, the input voltage is V1+V2, the output voltage is Vgs, and the load is Cgs.
[0042] The operation during turn-on will be explained in detail with reference to Figure 8. When the drive control signal S11 shown in Figure 8(a) is at a high level (before time t3), the first upper arm switch element PM1 is in the off state and the first lower arm switch element NM1 is in the on state. The output node N1 is at the potential of the negative terminal Vn of the power supply V for the drive circuit, as shown in Figure 8(b). The source terminal S of the power semiconductor element P1 is at potential Vs. Therefore, as viewed from the power semiconductor element P1, the potential Vg of the gate terminal G is a negative potential lower than the potential Vs of the source terminal S, and as shown in Figure 8(c), the gate-source voltage Vgs is negative. This ensures a margin up to the threshold voltage Vth of the power semiconductor element P1, so that even if the threshold voltage Vth is low, mis-pointing of the power semiconductor element P1 is prevented.
[0043] When the drive control signal S11 shown in Figure 8(a) enters its turn-on period at time t3, the first switching circuit 10 forms a downconverter with the parasitic inductance Lp1 and the gate capacitance Cgs, causing the potential Vg at the gate terminal G of the power semiconductor element P1 to rise. The slope at which the potential Vg at the gate terminal G of the power semiconductor element P1 rises is controlled by the duty cycle of the drive control signal S11.
[0044] As the potential Vg increases, the gate-source voltage Vgs increases, as shown in Figure 8(c). When the gate-source voltage Vgs exceeds the threshold voltage Vth of the power semiconductor element P1, drain current begins to flow, and the power semiconductor element P1 transitions to the ON state.
[0045] In the initial part of the turn-on period (for example, the period until the voltage Vgs reaches the threshold voltage Vth), the control circuit 30a controls the duty cycle of the drive control signal S11 to reduce the slope of the potential Vg rising. This reduces the rate of change of the drain current over time and suppresses the occurrence of surges. In the later part of the turn-on period (for example, the period after the voltage Vgs reaches the threshold voltage Vth), the control circuit 30a controls the duty cycle of the drive control signal S11 to increase the slope of the potential Vg rising. This shortens the turn-on period and suppresses switching losses.
[0046] The operation during turn-off will be explained in detail with reference to Figure 9. When the drive control signal S11 shown in Figure 9(a) enters its turn-off period at time t4, the first switching circuit 10 forms a downconverter with the parasitic inductance Lp1 and the gate capacitance Cgs, causing the potential Vg at the gate terminal G of the power semiconductor element P1 to decrease. The slope at which the potential Vg at the gate terminal G of the power semiconductor element P1 decreases is controlled by the duty cycle of the drive control signal S11.
[0047] As the potential Vg decreases, the gate-source voltage Vgs decreases, as shown in Figure 9(c). When the gate-source voltage Vgs falls below the threshold voltage Vth of the power semiconductor element P1, the power semiconductor element P1 transitions to the off state.
[0048] In the initial part of the turn-off period (for example, the period until the voltage Vgs reaches the threshold voltage Vth), the control circuit 30a controls the duty cycle of the drive control signal S11 to increase the slope of the potential Vg decrease. This shortens the turn-off period and suppresses switching losses. In the later part of the turn-on period (for example, the period after the voltage Vgs reaches the threshold voltage Vth), the control circuit 30a controls the duty cycle of the drive control signal S11 to decrease the slope of the potential Vg decrease. This reduces the rate of change of the drain voltage over time and suppresses the occurrence of surges.
[0049] The drive control signal S11 may be a pulse signal (for example, a pulse-modulated signal such as PWM) that switches between a high level and a low level in a second period that is sufficiently shorter than the first period T1, not only during the turn-on and turn-off periods, but also during the off and on periods.
[0050] In this embodiment, the first switching circuit 10 and the second switching circuit 20 are configured as CMOS, but similar effects can be obtained by using NMOS components or other switching elements, provided that an input signal suitable for the constituent elements is applied. Furthermore, in this embodiment, parasitic inductance Lp1 and gate capacitance Cgs are used to simulate the operation of the first switching circuit 10 and the second switching circuit 20 as downconverters. Inductors or capacitors may be added to the circuit to achieve more appropriate characteristics as a downconverter.
[0051] As described above, the first embodiment is a drive circuit 1 for driving a power semiconductor element P1, comprising: a first switching circuit 10 connected between the positive electrode Vp and the negative electrode Vn of a power supply V for the drive circuit, with its output node N1 connected to the source terminal S (negative terminal) of the power semiconductor element P1; a second switching circuit 20 connected between the positive electrode Vp and the negative electrode Vn of a power supply V for the drive circuit, with its output node N2 connected to the gate terminal G (control terminal) of the power semiconductor element P1; and a control circuit 30 that drives the first switching circuit 10 with a drive control signal S10 that switches between a high level and a low level in a first cycle that turns the power semiconductor element P1 on and off, and drives the second switching circuit 20 with a potential control signal S20 that switches between a high level and a low level in a second cycle T2 which is shorter than the first cycle T1. In this configuration, the drive circuit 1 causes the second switching circuit 20 to operate as a downconverter, and when the power semiconductor element P1 is off, it controls the potential Vg of the gate terminal G to a negative potential lower than the potential Vs of the source terminal S, thereby making the gate-source voltage Vgs negative. This ensures a margin up to the threshold voltage Vth of the power semiconductor element P1, so that even if the threshold voltage Vth is low, mis-pointing of the power semiconductor element P1 is prevented.
[0052] Furthermore, in this embodiment, the control circuit 30 controls the duty cycle of the potential control signal S20 to lower the potential Vg of the gate terminal G during the initial turn-on period when the power semiconductor element P1 transitions from off to on, and controls the duty cycle of the potential control signal S20 to raise the potential Vg of the gate terminal G during the later part of the turn-on period. This configuration allows the drive circuit 1 to reduce the time rate of change of the drain current, suppress the generation of surges, shorten the turn-on period, and reduce switching losses.
[0053] Furthermore, in this embodiment, the control circuit 30 controls the duty cycle of the potential control signal S20 to raise the potential Vg of the gate terminal G to a high value during the initial turn-off period when the power semiconductor element P1 transitions from on to off, and controls the duty cycle of the potential control signal S20 to lower the potential Vg of the gate terminal G to a low value during the later part of the turn-off period. This configuration allows the drive circuit 1 to shorten the turn-off period, suppress switching losses, reduce the rate of change of the drain current over time, and suppress surge generation.
[0054] As described above, the second embodiment is a drive circuit 1a for driving a power semiconductor element P1, comprising: a power supply V1 for a first drive circuit; a power supply V2 for a second drive circuit connected in series with the power supply V1, the positive terminal of which is connected to the negative terminal of the power supply V1 is connected to the source terminal S (negative terminal) of the power semiconductor element P1; and an output node N1 connected between the positive terminal Vp of the power supply V1 and the negative terminal Vn of the power supply V2, the gate terminal G (control terminal) of the power semiconductor element P1. The system includes a first switching circuit 10 connected to the power semiconductor element P1, and a control circuit 30a that drives the first switching circuit 10 with a drive control signal S11 which is a pulse signal (for example, a pulse-modulated signal such as PWM) that switches between a high level and a low level in a second period shorter than the first period T1, during the turn-on period when the power semiconductor element P1 transitions from off to on and the turn-off period when the power semiconductor element P1 transitions from on to off. With this configuration, the drive circuit 1a can make the gate-source voltage Vgs negative when the power semiconductor element P1 is off. This ensures a margin up to the threshold voltage Vth of the power semiconductor element P1, so that even if the threshold voltage Vth is low, mis-pointing of the power semiconductor element P1 is prevented.
[0055] Furthermore, in this embodiment, the control circuit 30a simulates the operation of the first switching circuit 10 as a downconverter during the initial turn-on period when the power semiconductor element P1 transitions from off to on, controlling the duty cycle of the drive control signal S11 to reduce the slope of the voltage Vgs between the gate terminal G and the source terminal S, and during the later part of the turn-on period, controlling the duty cycle of the drive control signal S11 to increase the slope of the voltage Vgs between the gate terminal G and the source terminal S. This configuration allows the drive circuit 1a to shorten the turn-off period, suppress switching losses, reduce the rate of change of the drain current over time, and suppress surge generation.
[0056] Furthermore, in this embodiment, the control circuit 30a simulates the operation of the first switching circuit 10 as a downconverter during the initial turn-off period when the power semiconductor element P1 transitions from on to off, controlling the duty cycle of the drive control signal S11 to increase the slope of the voltage Vgs between the gate terminal G and the source terminal S, and during the later part of the turn-off period, controlling the duty cycle of the drive control signal S11 to decrease the slope of the voltage Vgs between the gate terminal G and the source terminal S. This configuration allows the drive circuit 1a to shorten the turn-off period, suppress switching losses, reduce the rate of change of the drain voltage over time, and suppress surge generation.
[0057] It is clear that the present invention is not limited to the above embodiments, and that each embodiment can be modified as appropriate within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-mentioned components are not limited to the above embodiments, and can be set to a number, position, shape, etc. that is suitable for carrying out the present invention. In each figure, the same reference numeral is used for the same component. [Explanation of Symbols]
[0058] 1, 1a Drive Circuit 10. First switching circuit 20 Second switching circuit 30, 30a control circuit N1 Output Node N2 Output Node NM1 First lower arm switch element NM2 Second lower arm switch element P1 Power Semiconductor Device PM1 First Upper Arm Switch Element PM2 Second Upper Arm Switch Element Power supply for V drive circuit V1 Power supply for the first drive circuit V2 Power supply for the second drive circuit
Claims
1. A drive circuit for driving power semiconductor elements, A first switching circuit is connected between the positive and negative terminals of the power supply for the drive circuit, and its output node is connected to the negative terminal of the power semiconductor element. A second switching circuit is connected between the positive and negative terminals of the power supply for the drive circuit, and its output node is connected to the control terminal of the power semiconductor element. A drive circuit comprising: a drive control that drives the first switching circuit with a drive control signal that switches between a high level and a low level in a first cycle for turning the power semiconductor element on and off, and a control circuit that drives the second switching circuit with a potential control signal that switches between a high level and a low level in a second cycle shorter than the first cycle.
2. The drive circuit according to claim 1, wherein the control circuit controls the duty cycle of the potential control signal to lower the potential of the control terminal to a low value during the initial turn-on period when the power semiconductor element transitions from off to on, and controls the duty cycle of the potential control signal to raise the potential of the control terminal to a high value during the later part of the turn-on period.
3. The drive circuit according to claim 1 or 2, wherein the control circuit controls the duty cycle of the potential control signal to raise the potential of the control terminal to a high value during the initial turn-off period when the power semiconductor element transitions from on to off, and controls the duty cycle of the potential control signal to lower the potential of the control terminal to a low value during the later part of the turn-off period.
4. A drive circuit for driving power semiconductor elements, Power supply for the first drive circuit, A second drive circuit power supply is connected in series with the first drive circuit power supply, and the positive terminal connected to the negative terminal of the first drive circuit power supply is connected to the negative terminal side terminal of the power semiconductor element, A first switching circuit is connected between the positive terminal of the power supply for the first drive circuit and the negative terminal of the power supply for the second drive circuit, and its output node is connected to the control terminal of the power semiconductor element. A drive circuit comprising: a control circuit that drives the first switching circuit by a drive control signal that switches between a high level and a low level in a first cycle for switching the power semiconductor element on and off, and switches between a high level and a low level in a second cycle shorter than the first cycle during the turn-on period when the power semiconductor element transitions from off to on and the turn-off period when the power semiconductor element transitions from on to off.
5. The drive circuit according to claim 4, wherein the control circuit controls the duty cycle of the drive control signal to reduce the slope of the voltage between the control terminal and the negative terminal during the initial turn-on period when the power semiconductor element transitions from off to on, and controls the duty cycle of the drive control signal to increase the slope of the voltage between the control terminal and the negative terminal during the later part of the turn-on period.
6. The drive circuit according to claim 4 or 5, wherein the control circuit controls the duty cycle of the drive control signal to increase the slope of the voltage drop between the control terminal and the negative terminal during the initial turn-off period when the power semiconductor element transitions from on to off, and controls the duty cycle of the drive control signal to decrease the slope of the voltage drop between the control terminal and the negative terminal during the later part of the turn-off period.
7. A semiconductor device characterized in that the drive circuit described in claim 1 or 4 is integrated on a substrate.