Gate drive circuit and power converter

Abstract

Provided are a gate drive circuit and a power conversion device in which both the reduction of switching loss of a switching element and the reduction of switching surge can be achieved. In a gate drive circuit (4) of a power conversion device (1), an adjustment unit (6) is connected to the gate of a switching element (3). The adjustment unit (6) adjusts the resistance value of the gate resistance in accordance with a resistance pattern indicating a temporal change in the resistance value. A switching measurement unit (5) measures switching time and switching surge voltage when switching between the ON state and the OFF state of the switching element (3). On the basis of the switching time and the switching surge voltage measured by the switching measurement unit (5), a processing unit (7) determines the resistance pattern of the adjustment unit (6) so that the voltage of the main circuit terminal of the switching element (3) becomes equal to or less than a preset reference value.

Description

Technical Field

[0001] The present disclosure relates to a gate drive circuit and a power conversion device.

Background Art

[0002] Patent Document 1 discloses an example of a gate drive circuit. The gate drive circuit includes a drive unit that drives the gate of a switching element, a peak voltage detection unit, and a drive ability calculation unit. The peak voltage detection unit detects the peak voltage of the main terminal of the switching element when the switching element turns off. The drive ability calculation unit obtains the difference between the detected value of the peak voltage by the peak voltage detection unit and the allowable value of the voltage of the main terminal determined according to the specifications of the switching element, and changes the drive ability of the drive unit so that the difference gradually decreases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The gate drive circuit according to this disclosure is a gate drive circuit for driving the gate of a switching element mounted on a power converter, and comprises: an adjustment unit connected to the gate of the switching element and adjusting the resistance value of the gate resistor according to a resistance pattern representing the time change of the resistance value; a switching measurement unit that measures the switching time and switching surge voltage when the switching element switches to the ON state and the OFF state; and a processing unit that determines the resistance pattern of the adjustment unit based on the switching time and the switching surge voltage measured by the switching measurement unit so that the voltage at the main circuit terminal of the switching element is less than or equal to a preset reference value. The switching time is the rise time or fall time of the voltage at the main circuit terminal, and in the resistance pattern, the resistance value at the beginning of the switching time is smaller than the resistance value at the end of the switching time. . The gate drive circuit according to this disclosure is a gate drive circuit for driving the gate of a switching element mounted on a power converter, and comprises: an adjustment unit connected to the gate of the switching element and adjusting the resistance value of the gate resistor according to a resistance pattern representing the time change of the resistance value; and a storage unit that stores the resistance pattern of the adjustment unit, which has been predetermined so that the voltage at the main circuit terminal of the switching element is less than or equal to a preset reference value, based on the switching time and switching surge voltage measured when the switching element is switched to the ON state and when it is switched to the OFF state, so that the adjustment unit can read it. The switching time is the rise time or fall time of the voltage at the main circuit terminal, and in the resistance pattern, the resistance value at the beginning of the switching time is smaller than the resistance value at the end of the switching time. .

[0007] The power conversion device according to this disclosure comprises the above-described gate drive circuit and a switching element whose gate is driven by the gate drive circuit. [Effects of the Invention]

[0008] The gate drive circuit or power converter according to this disclosure makes it possible to achieve both a reduction in switching loss of switching elements and a reduction in switching surges. [Brief explanation of the drawing]

[0009] [Figure 1] This is a configuration diagram of the power conversion device according to Embodiment 1. [Figure 2] This is a block diagram illustrating an example of the configuration of a gate drive circuit according to Embodiment 1. [Figure 3] This figure shows an example of a signal waveform in a switching element corresponding to the gate drive circuit according to Embodiment 1. [Figure 4] This is a block diagram illustrating an example of the configuration of the first switching time measurement unit according to Embodiment 1. [Figure 5] This is a block diagram illustrating an example of the configuration of the second switching time measurement unit according to Embodiment 1. [Figure 6] This is a block diagram illustrating an example of the configuration of the delay time measurement unit according to Embodiment 1. [Figure 7] This is a block diagram illustrating an example of the configuration of the voltage measurement unit according to Embodiment 1. [Figure 8] This is a block diagram illustrating an example of the configuration of the processing unit according to Embodiment 1. [Figure 9] This is a block diagram illustrating an example of the configuration of the adjustment unit according to Embodiment 1. [Figure 10] As a comparative example, the figure shows an example where the gate resistance is constant. [Figure 11] This figure shows an example of a resistance pattern in a gate drive circuit according to Embodiment 1. [Figure 12] This figure shows another example of a resistance pattern in the gate drive circuit according to Embodiment 1. [Figure 13] This is a hardware configuration diagram of the main part of the gate drive circuit according to Embodiment 1. [Figure 14] This is a block diagram illustrating an example of the configuration of a gate drive circuit according to Embodiment 2. [Modes for carrying out the invention]

[0010] Embodiments for implementing the subject matter of the present disclosure will be described with reference to the accompanying drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals, and duplicate descriptions will be appropriately simplified or omitted. Note that the subject matter of the present disclosure is not limited to the following embodiments, and within the scope not departing from the gist of the present disclosure, deformation of any component of the embodiment or omission of any component of the embodiment is possible.

[0011] Embodiment 1. FIG. 1 is a configuration diagram of a power conversion device 1 according to Embodiment 1.

[0012] The power conversion device 1 is a device that converts and outputs input power. The power conversion device 1 is, for example, an inverter that drives an electric motor. In this example, the power conversion device 1 is an inverter that drives the hoist 2 of an elevator. The power conversion device 1 includes one or more switching elements 3 and one or more gate drive circuits 4. The switching element 3 is an element whose state such as an on state and an off state is switched according to an input gate signal. In this example, the switching element 3 is an IGBT (Insulated Gate Bipolar Transistor). Each switching element 3 is connected to the hoist 2. Each gate drive circuit 4 corresponds to one of the switching elements 3. Each gate drive circuit 4 is connected to the corresponding switching element 3. The gate drive circuit 4 is a circuit that drives the corresponding switching element 3 by inputting a gate signal to the corresponding switching element 3. When the power conversion device 1 includes a plurality of switching elements 3 and gate drive circuits 4, each switching element 3 and gate drive circuit 4 may have the same configuration as each other or different configurations. In this example, each gate drive circuit 4 includes a switching measurement unit 5, an adjustment unit 6, and a processing unit 7.

[0013] The switching measurement unit 5 is a part that has a function of measuring the switching characteristics of the switching element 3 corresponding to the gate drive circuit 4. The switching characteristics include, for example, the voltages of the input terminal and the main circuit terminal of the switching element 3 when the switching element 3 switches to the on state and to the off state. The voltages of the input terminal and the main circuit terminal of the switching element 3 include switching surge voltages such as the peak value of the voltage during the state transition. The switching characteristics include, for example, the switching time of the switching element 3. The switching time of the switching element 3 includes the rise time and the fall time of the voltages of the input terminal and the main circuit terminal of the switching element 3. The switching time of the switching element 3 includes the delay time of the voltage of the main circuit terminal with respect to the voltage of the input terminal of the switching element 3. In this example, the input terminal of the switching element 3 is the gate terminal. Also, the main circuit terminal of the switching element 3 is the collector terminal. The switching measurement unit 5 outputs the measured switching characteristics to the processing unit 7.

[0014] The adjustment unit 6 is connected to input terminals such as the gate terminal of the switching element 3. The adjustment unit 6 is a part that has a function of adjusting the resistance value of the gate resistance of the gate drive circuit 4. The adjustment unit 6 adjusts the resistance value of the gate resistance according to a preset resistance pattern. The resistance pattern is a pattern representing the time change of the resistance value during the state transition of the switching element 3.

[0015] The processing unit 7 is the part that performs information processing on the resistance pattern used by the adjustment unit 6 to adjust the resistance value of the gate resistor. The processing unit 7 stores the information on the resistance pattern so that the adjustment unit 6 can read it. For example, the processing unit 7 determines the resistance pattern to be used by the adjustment unit 6 based on the switching characteristics of the switching element 3 measured by the switching measurement unit 5. The processing unit 7 determines the resistance pattern so that the voltage at the main circuit terminals of the switching element 3, such as the collector terminal, during the switching of the state of the switching element 3 is below a preset reference value. This voltage is the switching surge voltage of the switching element 3, for example. The processing unit 7 may also determine the resistance pattern so that the switching loss of the switching element 3 is below a preset reference value. Alternatively, the processing unit 7 may determine the resistance pattern so that the weighted sum of the switching surge voltage and switching loss is below a preset reference value, or is a local minimum value. Switching loss includes, for example, the turn-on loss and turn-off loss of the switching element 3.

[0016] In the gate drive circuit 4, the processing unit 7 determines the resistance pattern, for example, before the normal operation of the power converter 1. The processing unit 7 may also determine the resistance pattern after a periodic inspection of the power converter 1. The switching measurement unit 5 measures the switching characteristics of the switching element 3, for example, when the state of the switching element 3 is switched while the adjustment unit 6 adjusts the resistance value of the gate resistor according to the resistance pattern. The processing unit 7 updates the resistance pattern based on the switching characteristics measured in this way. The processing unit 7 determines the resistance pattern used during normal operation by repeating this measurement of switching characteristics and updating of the resistance pattern, for example, before the normal operation of the power converter 1. The processing unit 7 stores the resistance pattern used during normal operation, for example, determined in this way. The adjustment unit 6 adjusts the resistance value of the gate resistor according to the resistance pattern read from the processing unit 7.

[0017] Next, the configuration of the gate drive circuit 4 will be explained using Figure 2. Figure 2 is a block diagram illustrating an example of the configuration of the gate drive circuit 4 according to Embodiment 1.

[0018] In this example, when determining the resistance pattern, the switching element 3 is disconnected from the elevator-side circuit, such as the hoisting machine 2, by the circuit switching device 8 and connected to the switching measurement unit 5. At this time, during normal operation of the power converter 1 after the resistance pattern has been determined, the switching element 3 is disconnected from the switching measurement unit 5 by the circuit switching device 8 and connected to the elevator-side circuit, such as the hoisting machine 2.

[0019] The gate terminal of the switching element 3 is connected to the input pulse generation unit 9 via the adjustment unit 6. The input pulse generation unit 9 is the part that generates a pulse signal to be input to the gate terminal. The collector terminal of the switching element 3 is directly connected to the coil 14 and the power supply 15 via the circuit switching device 8. The coil 14 is provided to generate a switching surge for determining the resistance pattern. The power supply 15 is provided to apply a voltage to the collector terminal of the switching element 3. The emitter terminal of the switching element 3 is connected to a reference potential point via the circuit switching device 8.

[0020] The switching measurement unit 5 comprises a first switching time measurement unit 10, a second switching time measurement unit 11, a delay time measurement unit 12, and a voltage measurement unit 13. The first switching time measurement unit 10 measures the rise time and fall time of the gate terminal voltage input when the state of the switching element 3 is switched. The first switching time measurement unit 10 is connected to the gate terminal of the switching element 3 via a circuit switching device 8. The second switching time measurement unit 11 measures the rise time and fall time of the collector terminal voltage when the state of the switching element 3 is switched. The second switching time measurement unit 11 is connected to the collector terminal of the switching element 3 via a circuit switching device 8. The delay time measurement unit 12 measures the delay time from the input of the gate terminal voltage to the response of the collector terminal voltage when the state of the switching element 3 is switched. The delay time measurement unit 12 is connected to the gate terminal and collector terminal of the switching element 3 via a circuit switching device 8. The voltage measurement unit 13 is the part that measures the switching surge voltage in the switching element 3. The voltage measurement unit 13 is connected to the collector terminal of the switching element 3 via the circuit switching device 8. Each part of the switching measurement unit 5 that performs measurements, such as the first switching time measurement unit 10, the second switching time measurement unit 11, the delay time measurement unit 12, and the voltage measurement unit 13, is connected to the processing unit 7.

[0021] Next, we will explain an example of a signal waveform in the switching element 3 using Figure 3. Figure 3 shows an example of a signal waveform in the switching element 3 corresponding to the gate drive circuit 4 according to Embodiment 1.

[0022] Figure 3 shows graphs representing the signal waveforms of the gate terminal voltage and collector terminal voltage at the switching element 3. The upper graph in Figure 3 represents the signal waveform of the gate terminal voltage at the switching element 3. The lower graph in Figure 3 represents the signal waveform of the collector terminal voltage at the switching element 3. In each graph, the horizontal axis represents the passage of time.

[0023] In this example, the input pulse generation unit 9 generates a rectangular pulse signal. The adjustment unit 6 adjusts, for example, the resistance value of the gate resistor to a preset value. At this time, the signal waveform of the gate terminal voltage in the switching element 3 rises from 0V to voltage V1, holds voltage V1 for a certain period of time, and then falls from voltage V1 to 0V. The state of the switching element 3 is switched to the ON state in response to the rising gate terminal voltage, and at this time the signal waveform of the collector terminal voltage falls from voltage V2 to 0V. The state of the switching element 3 is switched to the OFF state in response to the falling gate terminal voltage, and at this time the signal waveform of the collector terminal voltage rises from 0V to voltage V2. A switching surge voltage Vs with a peak occurs at the collector terminal voltage.

[0024] In this example, the rise time and fall time of the signal at each terminal of the switching element 3 are expressed as the time difference between the time when the terminal voltage becomes the first reference voltage and the time when the terminal voltage becomes the second reference voltage. The first and second reference voltages are, for example, preset voltage values ​​for each terminal. In this example, the first reference voltage of the gate terminal is set to 0.1 times voltage V1. The second reference voltage of the gate terminal is set to 0.9 times voltage V1. The first reference voltage of the collector terminal is set to 0.1 times voltage V2. The second reference voltage of the collector terminal is set to 0.9 times voltage V2. In this case, the time when the terminal voltage becomes the first reference voltage corresponds to the start time of the signal's rising edge or the end time of its falling edge. Also, the time when the terminal voltage becomes the second reference voltage corresponds to the end time of the signal's rising edge or the start time of its falling edge. Furthermore, the delay time in the switching element 3 is expressed as the time from the end of the rising or falling edge of the gate terminal voltage to the end of the collector terminal voltage response.

[0025] The rise time A of the gate terminal voltage is the time from when the gate terminal voltage reaches the first reference voltage of 0.1 × V1 until it reaches the second reference voltage of 0.9 × V1 during the rising edge of the signal. The fall time B of the gate terminal voltage is the time from when the gate terminal voltage reaches the second reference voltage of 0.9 × V1 until it reaches the first reference voltage of 0.1 × V1 during the falling edge of the signal. The fall time C of the collector terminal voltage is the time from when the collector terminal voltage reaches the second reference voltage of 0.9 × V2 until it reaches the first reference voltage of 0.1 × V2 during the falling edge of the signal. The rise time D of the collector terminal voltage is the time from when the collector terminal voltage reaches the first reference voltage of 0.1 × V2 until it reaches the second reference voltage of 0.9 × V2 during the rising edge of the signal. The delay time E is the time from when the gate terminal voltage reaches the second reference voltage of 0.9 × V1 until it reaches the first reference voltage of 0.1 × V2 when the collector terminal voltage falls in response to the rise of the gate terminal voltage. The delay time F is the time it takes for the collector terminal voltage to rise in response to the falling of the gate terminal voltage, from when the gate terminal voltage reaches the first reference voltage of 0.9 × V1 until the collector terminal voltage reaches the second reference voltage of 0.9 × V2.

[0026] Next, the configuration of the first switching time measurement unit 10 will be explained using Figure 4. Figure 4 is a block diagram illustrating an example of the configuration of the first switching time measurement unit 10 according to Embodiment 1.

[0027] The first switching time measurement unit 10 includes a first comparator 16a, a second comparator 17a, a first voltage input unit 18a, a second voltage input unit 19a, a reference pulse generation unit 20a, and a timing circuit 21a.

[0028] The positive terminal of the first comparator 16a, i.e., the non-inverting input terminal, is connected to the gate terminal of the switching element 3 via the circuit switching device 8. The negative terminal of the first comparator 16a, i.e., the inverting input terminal, is connected to the first voltage input section 18a. The first voltage input section 18a is the part that inputs a preset voltage to the first comparator 16a. For example, the first voltage input section 18a inputs the first reference voltage of the gate terminal to the inverting input terminal of the first comparator 16a. The output terminal of the first comparator 16a is connected to the timing circuit 21a.

[0029] The positive terminal of the second comparator 17a, i.e., the non-inverting input terminal, is connected to the gate terminal of the switching element 3 via the circuit switching device 8. The negative terminal of the second comparator 17a, i.e., the inverting input terminal, is connected to the second voltage input section 19a. The second voltage input section 19a is the part that inputs a preset voltage to the second comparator 17a. For example, the second voltage input section 19a inputs the second reference voltage of the gate terminal to the inverting input terminal of the second comparator 17a. The output terminal of the second comparator 17a is connected to the timing circuit 21a.

[0030] The reference pulse generation unit 20a is the part that generates a reference pulse that serves as the reference for time measurement. The reference pulse generation unit 20a includes an oscillating element such as a clock oscillator. In this example, the reference pulse generation unit 20a generates a reference pulse with a period of 10 MHz. That is, each reference pulse is generated at an interval of 0.1 μs. The reference pulse generation unit 20a outputs the generated reference pulse to the timing circuit 21a.

[0031] The timing circuit 21a is, for example, a counter circuit. The timing circuit 21a uses the output from one of the first comparator 16a and the second comparator 17a as the start signal. The timing circuit 21a also uses the output from the other of the first comparator 16a and the second comparator 17a as the stop signal. The timing circuit 21a measures the time from when the start signal is input to when the stop signal is input by counting the reference pulses input from the reference pulse generation unit 20a during the period from when the start signal is input to when the stop signal is input.

[0032] The measurement by the first switching time measurement unit 10 will be explained using the case of measuring the rise time A of the gate terminal voltage shown in Figure 3 as an example. When the gate terminal voltage of the switching element 3 rises, the first comparator 16a outputs a signal to the timing circuit 21a when the gate terminal voltage reaches the first reference voltage of 0.1 × V1 input by the first voltage input unit 18a to the first comparator 16a. At this time, the timing circuit 21a receives this signal as a start signal and starts counting the reference pulse from the reference pulse generation unit 20a. Subsequently, when the gate terminal voltage reaches the second reference voltage of 0.9 × V1 input by the second voltage input unit 19a to the second comparator 17a, the second comparator 17a outputs a signal to the timing circuit 21a. At this time, the timing circuit 21a receives this signal as a stop signal and ends counting the reference pulse from the reference pulse generation unit 20a. The timing circuit 21a outputs the measured rise time A by multiplying the number of reference pulses from the start to the end of counting by the interval between reference pulses. For example, when the timing circuit 21a counts 10 reference pulses, it multiplies the number of reference pulses by the interval between reference pulses, which is 0.1 μs, to obtain a measured rise time A of 1 μs. The first switching time measurement unit 10 similarly measures the fall time B of the gate terminal voltage.

[0033] Next, the configuration of the second switching time measurement unit 11 will be explained using Figure 5. Figure 5 is a block diagram illustrating an example of the configuration of the second switching time measurement unit 11 according to Embodiment 1.

[0034] The second switching time measurement unit 11 includes a first comparator 16b, a second comparator 17b, a first voltage input unit 18b, a second voltage input unit 19b, a reference pulse generation unit 20b, and a timing circuit 21b.

[0035] The positive terminal of the first comparator 16b, i.e., the non-inverting input terminal, is connected to the collector terminal of the switching element 3 via the circuit switching device 8. The negative terminal of the first comparator 16b, i.e., the inverting input terminal, is connected to the first voltage input section 18b. The first voltage input section 18b is the part that inputs a preset voltage to the first comparator 16b. For example, the first voltage input section 18b inputs the first reference voltage from the collector terminal to the inverting input terminal of the first comparator 16b. The output terminal of the first comparator 16b is connected to the timing circuit 21b.

[0036] The positive terminal of the second comparator 17b, i.e., the non-inverting input terminal, is connected to the collector terminal of the switching element 3 via the circuit switching device 8. The negative terminal of the second comparator 17b, i.e., the inverting input terminal, is connected to the second voltage input section 19b. The second voltage input section 19b is the part that inputs a preset voltage to the second comparator 17b. For example, the second voltage input section 19b inputs the second reference voltage from the collector terminal to the inverting input terminal of the second comparator 17b. The output terminal of the second comparator 17b is connected to the timing circuit 21b.

[0037] The reference pulse generation unit 20b is the part that generates a reference pulse that serves as the reference for time measurement. The reference pulse generation unit 20b includes an oscillating element such as a clock oscillator. In this example, the reference pulse generation unit 20b generates a reference pulse with a period of 10 MHz. That is, each reference pulse is generated at an interval of 0.1 μs. The reference pulse generation unit 20b outputs the generated reference pulse to the timing circuit 21b.

[0038] The timing circuit 21b is, for example, a counter circuit. The timing circuit 21b uses the output from one of the first comparator 16b and the second comparator 17b as the start signal. The timing circuit 21b also uses the output from the other of the first comparator 16b and the second comparator 17b as the stop signal. The timing circuit 21b measures the time from when the start signal is input to when the stop signal is input by counting the reference pulses input from the reference pulse generation unit 20b between the time the start signal is input and the time from when the stop signal is input.

[0039] The measurement by the second switching time measurement unit 11 will be explained using the case of measuring the fall time C of the collector terminal voltage shown in Figure 3 as an example. When the gate terminal voltage reaches the second reference voltage of 0.9 × V2 input by the second voltage input unit 19b to the second comparator 17b during the fall of the collector terminal voltage of the switching element 3, the second comparator 17b outputs a signal to the timing circuit 21b. At this time, the timing circuit 21b receives this signal as a start signal and starts counting the reference pulse from the reference pulse generation unit 20b. Subsequently, when the collector terminal voltage reaches the first reference voltage of 0.1 × V2 input by the first voltage input unit 18b to the first comparator 16b, the first comparator 16b outputs a signal to the timing circuit 21b. At this time, the timing circuit 21b receives this signal as a stop signal and ends counting the reference pulse from the reference pulse generation unit 20b. The timing circuit 21b multiplies the number of reference pulses from the start to the end of counting by the interval between reference pulses and outputs it as a measured value of the fall time C. For example, when the timing circuit 21b counts 10 reference pulses, it multiplies the number of reference pulses by the interval between reference pulses of 0.1 μs to obtain a measured value of 1 μs for the fall time C. The second switching time measurement unit 11 similarly measures the rise time D of the collector terminal voltage.

[0040] Next, the configuration of the delay time measurement unit 12 will be explained using Figure 6. Figure 6 is a block diagram illustrating an example of the configuration of the delay time measurement unit 12 according to Embodiment 1.

[0041] The delay time measurement unit 12 includes a first comparator 16c, a second comparator 17c, a first voltage input unit 18c, a second voltage input unit 19c, a reference pulse generation unit 20c, and a timing circuit 21c.

[0042] The positive terminal of the first comparator 16c, i.e., the non-inverting input terminal, is connected to the gate terminal of the switching element 3 via the circuit switching device 8. The negative terminal of the first comparator 16c, i.e., the inverting input terminal, is connected to the first voltage input section 18c. The first voltage input section 18c is the part that inputs a preset voltage to the first comparator 16c. For example, the first voltage input section 18c inputs the second reference voltage of the gate terminal to the inverting input terminal of the first comparator 16c. The output terminal of the first comparator 16c is connected to the timing circuit 21c.

[0043] The positive terminal of the second comparator 17c, i.e., the non-inverting input terminal, is connected to the collector terminal of the switching element 3 via the circuit switching device 8. The negative terminal of the second comparator 17c, i.e., the inverting input terminal, is connected to the second voltage input section 19c. The second voltage input section 19c is the part that inputs a preset voltage to the second comparator 17c. For example, the second voltage input section 19c inputs the first reference voltage from the collector terminal to the inverting input terminal of the second comparator 17c. The output terminal of the second comparator 17c is connected to the timing circuit 21c.

[0044] The reference pulse generation unit 20c is the part that generates a reference pulse that serves as the reference for time measurement. The reference pulse generation unit 20c includes an oscillating element such as a clock oscillator. In this example, the reference pulse generation unit 20c generates a reference pulse with a period of 10 MHz. That is, each reference pulse is generated at an interval of 0.1 μs. The reference pulse generation unit 20c outputs the generated reference pulse to the timing circuit 21c.

[0045] The timing circuit 21c is, for example, a counter circuit. The timing circuit 21c uses the output from one of the first comparator 16c and the second comparator 17c as the start signal. The timing circuit 21c uses the output from the other of the first comparator 16c and the second comparator 17c as the stop signal. The timing circuit 21c measures the time from when the start signal is input to when the stop signal is input by counting the reference pulses input from the reference pulse generation unit 20c during the period from when the start signal is input to when the stop signal is input.

[0046] The measurement by the delay time measurement unit 12 will be explained using the case of measuring the delay time E shown in Figure 3 as an example. When the gate terminal voltage of the switching element 3 rises, the second comparator 17c outputs a signal to the timing circuit 21c when the gate terminal voltage reaches the second reference voltage of 0.9 × V1 input by the first voltage input unit 18c to the first comparator 16c. At this time, the timing circuit 21c accepts this signal as a start signal and starts counting the reference pulse from the reference pulse generation unit 20c. Subsequently, when the collector terminal voltage reaches the first reference voltage of 0.1 × V2 input by the second voltage input unit 19c to the second comparator 17c, the second comparator 17c outputs a signal to the timing circuit 21c. At this time, the timing circuit 21c accepts this signal as a stop signal and ends counting the reference pulse from the reference pulse generation unit 20c. The timing circuit 21c outputs a measured value of the delay time E by multiplying the number of reference pulses from the start to the end of counting by the interval between reference pulses. For example, when the timing circuit 21c counts 10 reference pulses, it multiplies the number of reference pulses by the interval between reference pulses, which is 0.1 μs, to obtain a measured value of 1 μs for the delay time E.

[0047] The delay time measurement unit 12 also measures the delay time F in the same manner. Here, the first voltage input unit 18c may switch the voltage input to the first comparator 16c based on, for example, a steady voltage value of the gate terminal voltage or the collector terminal voltage. For example, when the voltage value of the gate terminal voltage is constant at 0V, the first voltage input unit 18c inputs the second reference voltage of the gate terminal to the inverting input terminal of the first comparator 16c. On the other hand, when the voltage value of the gate terminal voltage is constant at V1, the first voltage input unit 18c inputs the first reference voltage of the gate terminal to the inverting input terminal of the first comparator 16c. Similarly, the second voltage input unit 19c may switch the voltage input to the second comparator 17c based on, for example, a steady voltage value of the gate terminal voltage or the collector terminal voltage, or the voltage value that the first voltage input unit 18c inputs to the first comparator 16c. For example, when the first voltage input unit 18c inputs the second reference voltage from its gate terminal to the inverting input terminal of the first comparator 16c, the second voltage input unit 19c inputs the first reference voltage from its collector terminal to the inverting input terminal of the second comparator 17c. On the other hand, when the first voltage input unit 18c inputs the first reference voltage from its gate terminal to the inverting input terminal of the first comparator 16c, the second voltage input unit 19c inputs the second reference voltage from its collector terminal to the inverting input terminal of the second comparator 17c.

[0048] Next, the configuration of the voltage measurement unit 13 will be explained using Figure 7. Figure 7 is a block diagram illustrating an example of the configuration of the voltage measuring unit 13 according to Embodiment 1.

[0049] The voltage measurement unit 13 includes a peak hold circuit 22. The peak hold circuit 22 is connected to the collector terminal of the switching element 3 via a circuit switching device 8. The peak hold circuit 22 holds the peak value of the collector terminal voltage as the switching surge voltage Vs.

[0050] Next, the configuration of the processing unit 7 will be explained using Figure 8. Figure 8 is a block diagram illustrating an example of the configuration of the processing unit 7 according to Embodiment 1.

[0051] The processing unit 7 comprises a resistance value calculation unit 23, a resistance pattern calculation unit 24, and a storage unit 25.

[0052] The resistance calculation unit 23 is connected to the voltage measurement unit 13 of the switching measurement unit 5. The resistance calculation unit 23 is the part that calculates the resistance value of the gate resistor in the resistance pattern according to the switching surge voltage measured by the voltage measurement unit 13. Generally, increasing the gate resistance lowers the switching surge voltage, so the resistance calculation unit 23 calculates a larger resistance value, for example, when the measurement value from the voltage measurement unit 13 is larger. For example, the resistance calculation unit 23 calculates the resistance value of the gate resistor in the resistance pattern so that the collector terminal voltage of the switching element 3 is below a preset reference value.

[0053] The resistance pattern calculation unit 24 is connected to the first switching time measurement unit 10, the second switching time measurement unit 11, and the delay time measurement unit 12 of the switching measurement unit 5. The resistance pattern calculation unit 24 calculates the timing of the change in resistance value in the resistance pattern according to the switching time measured by the first switching time measurement unit 10, the second switching time measurement unit 11, and the delay time measurement unit 12. The resistance pattern calculation unit 24 defines the resistance pattern using, for example, a piecewise linear function with respect to time so that the resistance value changes continuously with respect to time. The timing of the change in resistance value is, for example, the timing of the boundary of each section in the piecewise linear function. The resistance pattern calculation unit 24 calculates a resistance pattern such that the resistance value calculated by the resistance value calculation unit 23 is the peak value. In general, reducing the gate resistance shortens the rise time and fall time of the signal at each terminal of the switching element 3, and shorter rise and fall times result in lower switching losses. Also, the switching surge voltage occurs at the end of the collector terminal voltage response. Therefore, the resistance pattern calculation unit 24 calculates the timing of the resistance change so that the gate resistance is small at the beginning of the collector terminal voltage response and large at the end of the collector terminal voltage response. For example, the resistance pattern calculation unit 24 calculates the timing of the resistance change in the resistance pattern so that the switching loss in the switching element 3 is less than or equal to a preset reference value.

[0054] The resistance pattern determined by the resistance value calculation unit 23 and the resistance pattern calculation unit 24 is stored in the storage unit 25. The storage unit 25 stores the resistance pattern in a format that can be read by the adjustment unit 6.

[0055] Next, the configuration of the adjustment unit 6 will be explained using Figure 9. Figure 9 is a block diagram illustrating an example of the configuration of the adjustment unit 6 according to Embodiment 1.

[0056] The adjustment unit 6 comprises a transistor 26 and a base resistor 27. The base terminal of the transistor 26 is connected to the processing unit 7 via the base resistor 27. The collector terminal of the transistor 26 is connected to the input pulse generation unit 9. The emitter terminal of the transistor 26 is connected to the gate terminal of the switching element 3.

[0057] The adjustment unit 6 applies a voltage signal V3 to the base resistor 27 according to the resistance pattern read from the memory unit 25 of the processing unit 7. If the resistance value of the base resistor 27 is Rb, the base current Ib flowing through the base resistor 27 is Ib = V3 / Rb. At this time, the collector current Ic of the transistor 26 is expressed as the product of the base current Ib and the DC current amplification factor hfe. Also, a voltage Vce is generated between the collector terminal and the emitter terminal of the transistor 26. According to Ohm's law, the voltage Vce between the collector terminal and the emitter terminal divided by the collector current Ic is the resistance value Rg, and this resistance value Rg becomes the resistance value of the gate resistor of the gate drive circuit 4 that drives the switching element 3. The adjustment unit 6 changes the base current Ib and the resistance value Rg of the gate resistor by changing the voltage signal V3. In this example, the resistance pattern corresponds to the energization pattern of the transistor 26, which is represented by the time change of the voltage signal V3.

[0058] Next, we will explain examples of resistance patterns using Figures 10 to 12. Figure 10 shows an example where the gate resistance is constant, as a comparative example. Figure 11 shows an example of a resistance pattern in the gate drive circuit 4 according to Embodiment 1. Figure 12 shows another example of the resistance pattern in the gate drive circuit 4 according to Embodiment 1.

[0059] Figure 10 shows graphs representing the signal waveforms of the gate terminal voltage and collector terminal voltage in the switching element of the comparative example. In the upper graph of Figure 10, the solid line represents the signal waveform of the gate terminal voltage in the switching element, and the dashed line represents the resistance value of the gate resistor. In the lower graph of Figure 10, the solid line represents the signal waveform of the collector terminal voltage in the switching element, and the dashed line represents the signal waveform of the collector terminal current. In each graph, the horizontal axis represents the passage of time. In this comparative example, the resistance value of the gate resistor is set to a constant value that is large enough to suppress the switching surge voltage.

[0060] When the gate terminal voltage waveform rises, the switching element switches to the ON state. At this time, the collector terminal voltage waveform falls, and the collector terminal current waveform rises. Conversely, when the gate terminal voltage waveform falls, the switching element switches to the OFF state. At this time, the collector terminal voltage waveform rises, and the collector terminal current waveform falls. Since the gate resistor value is set to a sufficiently large value, the switching surge voltage is suppressed compared to when the gate resistor value is small. On the other hand, setting the gate resistor value to a large value increases the rise time of the signal waveform, so the switching loss increases.

[0061] Figures 11 and 12 show graphs representing the signal waveforms of the gate terminal voltage and collector terminal voltage at the switching element 3. In the upper graphs of Figures 11 and 12, the solid line represents the signal waveform of the gate terminal voltage at the switching element 3, and the dashed line represents the resistance value of the gate resistor. In the lower graphs of Figures 10 and 12, the solid line represents the signal waveform of the collector terminal voltage at the switching element 3, and the dashed line represents the signal waveform of the collector terminal current. In each graph, the horizontal axis represents the passage of time.

[0062] Figure 11 shows an example of a resistance pattern in which the gate resistor value changes discontinuously. The resistance pattern is, for example, a pattern in which the resistance value changes with time to form a rectangular waveform. In the resistance pattern, the gate resistor value is set to a value small enough to suppress switching losses in the steady state and at the beginning of the collector terminal voltage response. In the middle of the collector terminal voltage response, the gate resistor value changes discontinuously to a value large enough to suppress switching surge voltage. After the collector terminal voltage response ends and the system transitions to the steady state, the gate resistor value changes discontinuously to a value small enough to suppress switching losses.

[0063] When the gate terminal voltage waveform falls, the state of switching element 3 is switched to the off state. At this time, the collector terminal voltage waveform rises, and the collector terminal current waveform falls. At the beginning of the collector terminal voltage response, the gate resistance value is set to a sufficiently small value, so the rise time of the signal waveform is shorter compared to when the gate resistance value is large, and switching losses are suppressed. Also, at the end of the collector terminal voltage response, the gate resistance value is set to a sufficiently large value, so the switching surge voltage is suppressed compared to when the gate resistance value is small. In this way, both the reduction of switching losses and the reduction of switching surges of switching element 3 are achieved. The same applies when switching switching element 3 to the on state.

[0064] On the other hand, because the resistance value of the gate resistor changes rapidly, a surge voltage may be applied to the gate terminal. This can potentially generate noise. Such noise can be mitigated by, for example, implementing a snubber circuit.

[0065] Figure 12 shows an example of a resistance pattern in which the gate resistance value changes continuously. The resistance pattern is one in which the resistance value changes piecewise linearly with respect to time, for example, to form a triangular pulse waveform. In the resistance pattern, the gate resistance value is set to a value small enough to suppress switching losses in the steady state and at the beginning of the collector terminal voltage response. In the middle of the collector terminal voltage response, the gate resistance value increases linearly to a peak value large enough to suppress switching surge voltage. In this example, the resistance pattern is set so that the gate resistance value reaches its peak value at a timing when switching surge voltage may occur. After the gate resistance value reaches its peak value, the gate resistance value decreases linearly. After the collector terminal voltage response ends and the system transitions to the steady state, the gate resistance value changes to a value small enough to suppress switching losses.

[0066] When the gate terminal voltage waveform falls, the state of switching element 3 is switched to the off state. At this time, the collector terminal voltage waveform rises, and the collector terminal current waveform falls. At the beginning of the collector terminal voltage response, the resistance value of the gate resistor is set to a sufficiently small value, so the rise time of the signal waveform is shorter compared to when the resistance value of the gate resistor is large, and switching losses are suppressed. Also, at the end of the collector terminal voltage response, the resistance value of the gate resistor is set to a sufficiently large value, so the switching surge voltage is suppressed compared to when the resistance value of the gate resistor is small. In this way, both the reduction of switching losses and the reduction of switching surges of switching element 3 are achieved. The same applies when switching switching element 3 to the on state. Furthermore, since the resistance value of the gate resistor changes continuously, the surge voltage applied to the gate terminal is suppressed. As a result, the generation of noise in the gate drive circuit 4 is suppressed.

[0067] Note that the switching element 3 to which the gate drive circuit 4 is applied is not limited to IGBTs. The switching element 3 may be, for example, a FET (Field-Effect Transistor). In this case, the gate drive circuit 4 operates, for example, with the gate terminal of the switching element 3 as the input terminal and the drain terminal as the main circuit terminal.

[0068] Furthermore, the gate drive circuit 4 applied to the power converter 1, for example, may read a resistance pattern pre-set by an external device and adjust the resistance value of the gate resistor. The resistance pattern is pre-set for, for example, a switching element 3 of the same type or a power converter 1 of the same type. In this case, the external device may include functions such as a switching measurement unit 5 and a resistance value calculation unit 23 and a resistance pattern calculation unit 24 of the processing unit 7. In this case, the processing unit 7 of the gate drive circuit 4 only needs to have the function of a storage unit 25.

[0069] Furthermore, the gate drive circuit 4 does not have to be applied to an inverter that drives the electric motor of an elevator. The gate drive circuit 4 may be applied to, for example, a performance evaluation device for a switching element 3.

[0070] As described above, the power conversion device 1 according to Embodiment 1 comprises a gate drive circuit 4 and a switching element 3. The gate drive circuit 4 drives the gate of the switching element 3. The gate drive circuit 4 comprises an adjustment unit 6, a switching measurement unit 5, and a processing unit 7. The adjustment unit 6 is connected to the gate of the switching element 3. The adjustment unit 6 adjusts the resistance value of the gate resistor according to a resistance pattern. The resistance pattern represents the change in resistance value over time. The switching measurement unit 5 measures the switching time and switching surge voltage when the switching element 3 switches to the ON state and when it switches to the OFF state. Based on the switching time and switching surge voltage measured by the switching measurement unit 5, the processing unit 7 determines the resistance pattern of the adjustment unit 6 so that the voltage at the main circuit terminal of the switching element 3 is less than or equal to a preset reference value.

[0071] Generally, in a switching element 3, there is a trade-off: increasing the gate resistance suppresses the switching surge voltage, but increases the switching time and thus the switching loss. On the other hand, since the timing at which the switching surge voltage can occur and the timing at which the switching loss can occur are different, the trade-off regarding the switching loss can be resolved by using a resistance pattern that represents the time change of the resistance value. The processing unit 7 determines the resistance pattern of the adjustment unit 6 so that the voltage at the main circuit terminal of the switching element 3 is below a preset reference value. The adjustment unit 6 adjusts the resistance value of the gate resistance according to the determined resistance pattern, thereby achieving both a reduction in the switching loss and a reduction in the switching surge of the switching element 3. Furthermore, by reducing the switching surge, the snubber circuit provided in the power converter 1 and the like can be made more compact, and power consumption can be further reduced.

[0072] Furthermore, the resistance pattern is determined so that the resistance value changes continuously with respect to time. Alternatively, the resistance pattern can be determined so that the resistance value changes linearly and piecewise with respect to time. This suppresses the generation of noise, thereby reducing erroneous switching between the on and off states of the switching element 3. In addition, the suppression of noise and erroneous switching reduces the possibility of malfunctions in the power converter 1 and damage to individual elements. Furthermore, the suppression of erroneous switching and the reduction of switching surges allow for the absorption of characteristic variations when using low-voltage components for the switching element 3 of the power converter 1, making component selection in the power converter 1 easier.

[0073] Next, we will explain an example of the hardware configuration of the gate drive circuit 4 using Figure 13. Figure 13 is a hardware configuration diagram of the main part of the gate drive circuit 4 according to Embodiment 1.

[0074] Each function of the gate drive circuit 4 can be realized by a processing circuit. The processing circuit comprises at least one processor 100a and at least one memory 100b. The processing circuit may also include at least one dedicated hardware 200 together with the processor 100a and memory 100b, or as a substitute for them.

[0075] When the processing circuit includes a processor 100a and a memory 100b, each function of the gate drive circuit 4 is realized by software, firmware, or a combination of software and firmware. At least one of the software and firmware is written as a program. This program is stored in the memory 100b. The processor 100a realizes each function of the gate drive circuit 4 by reading and executing the program stored in the memory 100b.

[0076] The processor 100a is also called a CPU (Central Processing Unit), processing unit, arithmetic unit, microprocessor, microcomputer, or DSP. The memory 100b is composed of non-volatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, or EEPROM.

[0077] If the processing circuit includes dedicated hardware 200, the processing circuit may be implemented as, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0078] Each function of the gate drive circuit 4 can be implemented by a separate processing circuit. Alternatively, each function of the gate drive circuit 4 can be implemented collectively by a processing circuit. Some functions of the gate drive circuit 4 may be implemented by dedicated hardware 200, while others are implemented by software or firmware. Thus, the processing circuit implements each function of the gate drive circuit 4 using dedicated hardware 200, software, firmware, or a combination thereof.

[0079] Embodiment 2. In Embodiment 2, the differences from the example disclosed in Embodiment 1 will be explained in particular detail. For features not described in Embodiment 2, any of the features from the example disclosed in Embodiment 1 may be adopted.

[0080] Figure 14 is a block diagram illustrating an example of the configuration of the gate drive circuit 4 according to Embodiment 2.

[0081] The gate drive circuit 4 includes a temperature measuring unit 28. The temperature measuring unit 28 measures the temperature of the switching element 3. The temperature measuring unit 28 outputs the measurement results to the processing unit 7 and the adjustment unit 6. The processing unit 7 determines the resistance pattern to be used by the adjustment unit 6 based on, for example, the switching characteristics of the switching element 3 measured by the switching measurement unit 5 and the temperature of the switching element 3 measured by the temperature measuring unit 28. The processing unit 7 determines the resistance pattern for, for example, each of the temperature categories of the switching element 3 that have been set in advance. The adjustment unit 6 also adjusts the resistance value of the gate resistor according to the resistance pattern determined by the processing unit 7, in accordance with the temperature of the switching element 3 measured by the temperature measuring unit 28.

[0082] With this configuration, the gate drive circuit 4 can achieve both a reduction in switching loss and a reduction in switching surge, even when the temperature of the switching element 3 changes. [Industrial applicability]

[0083] The gate drive circuit described herein can be applied to a power conversion device. The power conversion device described herein can be applied, for example, as an inverter to an elevator hoisting machine. [Explanation of Symbols]

[0084] 1 Power converter, 2 Hoisting machine, 3 Switching element, 4 Gate drive circuit, 5 Switching measurement unit, 6 Adjustment unit, 7 Processing unit, 8 Circuit switching device, 9 Input pulse generation unit, 10 First switching time measurement unit, 11 Second switching time measurement unit, 12 Delay time measurement unit, 13 Voltage measurement unit, 14 Coil, 15 Power supply, 16a, 16b, 16c First comparator, 17a, 17b, 17c Second comparator, 18a, 18b, 18c First voltage input unit, 19a, 19b, 19c Second voltage input unit, 20a, 20b, 20c Reference pulse generation unit, 21a, 21b, 21c Timing circuit, 22 Peak hold circuit, 23 Resistance value calculation unit, 24 Resistance pattern calculation unit, 25 Memory unit, 26 transistors, 27 base resistors, 28 temperature measurement unit, 100a processor, 100b memory, 200 dedicated hardware

Claims

1. This is a gate drive circuit that drives the gate of a switching element mounted on a power converter. An adjustment unit connected to the gate of the switching element adjusts the resistance value of the gate resistor according to a resistance pattern that represents the time change of the resistance value, A switching measurement unit that measures the switching time and switching surge voltage when the switching element is switched to the ON state and when it is switched to the OFF state, A processing unit that determines the resistance pattern of the adjustment unit based on the switching time and switching surge voltage measured by the switching measurement unit so that the voltage at the main circuit terminal of the switching element is less than or equal to a preset reference value, Equipped with, The switching time is the rise time or fall time of the voltage at the main circuit terminal. In the aforementioned resistance pattern, the resistance value at the beginning of the switching time is smaller than the resistance value at the end of the switching time. Gate drive circuit.

2. This is a gate drive circuit that drives the gate of a switching element mounted on a power converter. An adjustment unit connected to the gate of the switching element adjusts the resistance value of the gate resistor according to a resistance pattern that represents the time change of the resistance value, A storage unit stores, in a manner that allows the adjustment unit to read the resistance pattern of the adjustment unit, which is predetermined so that the voltage at the main circuit terminal of the switching element is less than or equal to a predetermined reference value, based on the switching time and switching surge voltage measured when the switching element is switched to the ON state and when it is switched to the OFF state. Equipped with, The switching time is the rise time or fall time of the voltage at the main circuit terminal. In the aforementioned resistance pattern, the resistance value at the beginning of the switching time is smaller than the resistance value at the end of the switching time. Gate drive circuit.

3. The aforementioned resistance pattern is determined such that the resistance value changes continuously with respect to time. The gate drive circuit according to claim 1 or claim 2.

4. The aforementioned resistance pattern is determined such that the resistance value changes linearly and piecewise with respect to time. The gate drive circuit according to claim 3.

5. The resistance pattern is determined such that the switching loss of the switching element is less than or equal to a preset reference value. The gate drive circuit according to claim 1 or claim 2.

6. The resistance pattern is determined based on the measured temperature of the switching element. The gate drive circuit according to claim 1 or claim 2.

7. The switching element is an IGBT. The gate drive circuit according to claim 1 or claim 2.

8. The switching element is an FET. The gate drive circuit according to claim 1 or claim 2.

9. A gate drive circuit according to claim 1 or claim 2, A switching element whose gate is driven by the gate drive circuit, A power conversion device equipped with the following features.

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