converter

Abstract

This invention provides a converter that can increase the input current even under conditions of low output voltage. [Solution] The converter's control circuit performs an alternative control using a specific formula (2) if the control using a specific formula (1) causes period T3 to be longer than period T2. T1 is the period during which the switching element of the second leg of one switching circuit is turned on, Tt is the switching period in one switching circuit, T3 is the period during which the switching element of the first leg of the other switching circuit is turned on, Vin is the voltage input from between the two terminals of one switching circuit, Vo is the voltage output from between the two terminals of the other switching circuit, n1 and n2 are the number of turns of the primary and secondary windings of the transformer, respectively, and L is the inductance of the inductance means.

Description

Technical Field

[0001] The present disclosure relates to a converter.

Background Art

[0002] Converters and bidirectional converters that can handle a wide range of input and output voltage currents and reduce switching losses are known (see, for example, Patent Documents 1 and 2). Further, in the converters and bidirectional converters of Patent Documents 1 and 2, a control method is disclosed that can increase the maximum input current without increasing the power loss even when the input voltage is low (see, for example, Patent Document 3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] When applying the control (FIG. 14) described in Patent Document 3 to the converters (FIG. 1) of Patent Documents 1 and 2, according to the following formula (1), the value of period T2 decreases as periods T3 to T3' increase. Here, as shown in FIG. 20, when the output voltage Vo is not sufficiently high, the value of T2 may be less than the value of T3, and the period during which the secondary-side output voltage is applied to transformer 11 is limited to T2, the input current decreases, and the object of Patent Document 3 (increasing the maximum input current without increasing the power loss and increasing the output power) may not be achieved.

[0005] As described above, the converters disclosed in Patent Documents 1 and 2, which apply the control described in Patent Document 3, have the problem that when the output voltage is not sufficiently high, it is difficult to increase the input current and thus the output power without increasing power loss. Therefore, the present invention aims to provide a converter that can increase the input current and obtain the desired output power even under conditions of low output voltage, in order to solve the above problems. [Means for solving the problem]

[0006] To achieve the above objective, the converter according to the present invention performs specific switching control when it is desired to increase the input current.

[0007] Specifically, the converter according to the present invention is A transformer having a primary winding and a secondary winding, A switching element having a switching element in which an antiparallel diode and a parallel capacitor are connected in parallel, is connected in parallel to two terminals, forming an upper and lower arm, a first leg and a second leg, a first capacitor connected in parallel to one of the switching elements on the upper or lower arm of the first or second leg, or to one of the switching elements on the upper or lower arm of the first and second legs, and a second capacitor connected in parallel to the other switching element on the upper or lower arm of the first and second legs, or to the other switching element on the upper or lower arm of the first and second legs, and two switching circuits connected to the primary winding side and the secondary winding side of the transformer, respectively. An inductance means is connected via the primary winding or the secondary winding on the primary winding side or the secondary winding of the transformer between the connection point side of the upper and lower arms of the first leg and the connection point side of the upper and lower arms of the second leg, A control circuit that performs switching control of the switching circuit and Equipped with, The switching control of the control circuit includes: This includes zero-volt switching control, energy transition switching control, and low-input switching control performed in conjunction with the energy transition switching control. The aforementioned zero-volt switching control is For one of the switching circuits, the switching element on the upper arm of the first or second leg and the switching element on the lower arm of the second or first leg are paired and alternately turned on and off to convert the DC input from the two terminals into AC and output from the switching circuit, and in controlling the alternate on and off of the pair of switching elements, the switching element of the pair of switching elements of the upper arm of the first or second leg and the switching element of the lower arm of the second or first leg that is in the ON state is turned off first, the switching element to which the first capacitor or the second capacitor is connected in parallel, The aforementioned energy transition switching control is To cause the detected voltage, current, or power output from the two terminals of the other switching circuit or the detected voltage, current, or power input from the two terminals of one of the switching circuits to approach the target value, the switching elements of the second leg of the other switching circuit are forward-conducted so that the energy input from the two terminals of one of the switching circuits is stored in the inductance means during the period when the pair of switching elements in one of the switching circuits is ON, and the switching elements of the second leg of the other switching circuit that were forward-conducted are turned OFF before the switching elements of the one of the switching circuits that are turned OFF first are turned OFF, and The low-input switching control described above is When the detected voltage, current, or power input from the two terminals of one of the switching circuits falls below a certain standard, the switching element of the first leg of one of the switching circuits is turned on, and at the same time, the switching element of the upper arm or lower arm of the second leg and the switching element of the lower arm or upper arm of the first leg of the other switching circuit are turned on, and the switching element of the first leg is turned off before the switching element of the second leg of the other switching circuit is turned off. It is characterized by, The aforementioned control circuit is In the low-input switching control, the period T2 for turning on the switching element of the second leg of the other switching circuit is set by formula (1), and When performing the low-input switching control described above, if the calculation result of equation (1) shows that period T3 is longer than period T2, then the alternative control shown in equation (2) should be performed. It is characterized by the following.

number

number

[0008] When the calculation result of T2 by the formula (1) is T2 < T3, this converter stops the calculation of the formula (1) and sets T2 = T3. Just setting T2 = T3 can increase the input current, but cannot increase the output current. Therefore, by optimizing T1, an increase in the output current is achieved (see FIG. 21). Note that under the condition of T2 ≥ T3, the operation described in Patent Document 3 is performed, so the advantages described in Patent Document 3 are not impaired.

[0009] Therefore, the present invention can provide a converter that can increase the input current even under the condition of a low output voltage and obtain a desired output power.

Effect of the Invention

[0010] The present invention can provide a converter that can increase the input current even under the condition of a low output voltage and obtain a desired output power.

Brief Description of the Drawings

[0011] [Figure 1] It is a configuration diagram of a converter (bidirectional converter) according to the present invention. [Figure 2] It is a waveform diagram showing an example of drive signals of switching elements S1 to S4 of switching circuit 1 and switching elements S5 and S6 of switching circuit 2 when switching elements S5 and S6 of switching circuit 2 are turned on and off in the converter according to the present invention. [Figure 3] It is a waveform diagram showing an example of the voltage, current of switching elements S1 to S4 of switching circuit 1 and the exciting current of transformer 11 when switching elements S5 and S6 of switching circuit 2 are turned on and off in the converter according to the present invention. [Figure 4] It is a waveform diagram showing an example of the voltage, current of switching elements S5 and S6 of switching circuit 2 and the voltage, current of antiparallel diodes D7 and D8 when switching elements S5 and S6 of switching circuit 2 are turned on and off in the converter according to the present invention. [Figure 5] This is a magnified view of a portion of the waveform shown in Figure 3. [Figure 6] This is a circuit diagram formed at each timing when switching elements S5 and S6 of the switching circuit 2 are turned on and off in the converter according to the present invention. [Figure 7] This is an example of a waveform diagram showing the drive signals for the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5 and S6 of the switching circuit 2 in a converter according to the present invention, where the voltage output between the third terminal Ter3 and the fourth terminal Ter4 is made lower than the output voltage obtained by turning the switching elements S5 and S6 of the switching circuit 2 on and off. [Figure 8] This waveform diagram shows an example of the voltages and currents of the switching elements S1 to S4 of the switching circuit 1 and the excitation current of the transformer 11 in a converter according to the present invention, where the voltage output between the third terminal Ter3 and the fourth terminal Ter4 is lower than the output voltage obtained by turning the switching elements S5 and S6 of the switching circuit 2 on and off. [Figure 9] This waveform diagram shows an example of the voltage and current across the antiparallel diodes D5 to D8 of the switching circuit 2 in the converter according to the present invention, when the voltage output between the third terminal Ter3 and the fourth terminal Ter4 is made lower than the output voltage obtained by switching the switching elements S5 and S6 of the switching circuit 2 on and off. [Figure 10] This is a circuit diagram formed at each timing for the operation in the converter according to the present invention, which makes the voltage output between the third terminal Ter3 and the fourth terminal Ter4 lower than the output voltage obtained by turning the switching elements S5 and S6 of the switching circuit 2 on and off. [Figure 11] This diagram illustrates the switching control performed by the control circuit of the converter according to the present invention. [Figure 12] This diagram illustrates the switching control performed by the control circuit of the converter according to the present invention. [Figure 13] This diagram illustrates the switching control performed by the control circuit of the converter according to the present invention. [Figure 14] This diagram illustrates the switching control performed by the control circuit of the converter according to the present invention. [Figure 15] This diagram illustrates the current waveform on the primary side of a transformer. [Figure 16] This figure illustrates the current waveform on the primary side of the transformer of the converter according to the present invention. [Figure 17] This diagram illustrates the current waveform flowing through the switch element that is turned off later, among the pair of switching elements (S1 and S4, and S3 and S2) in the converter according to the present invention. [Figure 18] This diagram illustrates the current waveform flowing through the switch element that is turned off later, among the pair of switching elements (S1 and S4, and S3 and S2) in the converter according to the present invention. [Figure 19] This diagram illustrates the current waveform flowing through the switch element that is turned off later, among the pair of switching elements (S1 and S4, and S3 and S2) in the converter according to the present invention. [Figure 20] This figure illustrates the problem of the present invention. [Figure 21] This figure illustrates the effects of the present invention. [Figure 22] This is a circuit diagram formed in the converter according to the present invention at the timing when switching elements S5 and S6 of the switching circuit 2 are turned on and off, as well as switching elements S8 and S7. [Figure 23] This diagram illustrates the current flow when T2 > T3 and when T2 > T3. [Figure 24] This diagram illustrates the waveforms of the current flowing through the transformer and switch during period τ3. [Figure 25] This diagram illustrates alternative control for the converter according to the present invention. [Figure 26] This diagram illustrates alternative control for the converter according to the present invention. [Figure 27] This diagram illustrates the current flow when T2 = T3. [Figure 28]This figure illustrates the waveform of the current flowing through the transformer and switch in the alternative control of the converter according to the present invention. [Modes for carrying out the invention]

[0012] Embodiments of the present invention will be described with reference to the attached drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to these embodiments. In this specification and in the drawings, components with the same reference numerals refer to the same components. Furthermore, the inventions (examples) described below can be combined as much as possible.

[0013] Figure 1 is a diagram illustrating the converter 301 of this embodiment. The converter 301 is A transformer (11) having a primary winding and a secondary winding, A switching element (S1-S4) having switching elements (Q1-Q4) each having antiparallel diodes (D1-D4) and parallel capacitors (C1-C4) connected in parallel, is connected in parallel to two terminals (Ter1 & Ter2) as an upper and lower arm, forming a first leg (12) and a second leg (13), respectively, and a switching element (S1 / S2 / S3 / S4) on one of the upper or lower arms of the first leg or second leg (12 / 13) or a switching element (S) on one of the upper or lower arms of the first leg and second leg (12 & 13) Two switching circuits (1&2) are provided, each having a first capacitor (Ca) connected in parallel to (1 / S2 / S3 / S4), and a second capacitor (Cb) connected in parallel to the other switching element (S1 / S2 / S3 / S4) on the upper or lower arm of the first or second leg (12 / 13), or to the other switching element (S1 / S2 / S3 / S4) on the upper or lower arm of the first and second legs (12&13), respectively, and connected to the primary winding (11a) side and the secondary winding (11b) side of the transformer, On the primary winding (11a) side or the secondary winding (11b) side of the transformer, an inductance means (L) is connected via the primary winding (11a) or the secondary winding (11b) between the connection point side of the upper and lower arms of the first leg (12) and the connection point side of the upper and lower arms of the second leg (13), A control circuit (3) that controls the switching of the switching circuits (1 and 2) and It is equipped with. The switching control of the control circuit (3) includes: This includes zero-volt switching control, energy transition switching control, and low-input switching control performed in conjunction with the energy transition switching control. The aforementioned zero-volt switching control is For one of the switching circuits (1 / 2), the switching elements (S1 / S3) on the upper arm of the first or second leg (12 / 13) and the switching elements (S4 / S2) on the lower arm of the second or first leg (13 / 12) are alternately turned on and off as a pair to convert the DC input from the two terminals (Ter1 & Ter2) to AC and output it from the switching circuit (1 / 2), and in controlling the alternate on / off state of the pair of switching elements (S1 & S4 / S3 & S2), the switching element (S3 / S4) on the upper arm of the first or second leg (12 / 13) and the switching element (S4 / S2) on the lower arm of the second or first leg (13 / 12) are turned off first, with the first capacitor or the second capacitor (Ca / Cb) connected in parallel. The aforementioned energy transition switching control is In order for the voltage, current, or power detected value output from the side between the two terminals (Ter3 & Ter4) of the other switching circuit (2 / 1) or the voltage, current, or power detected value input from the side between the two terminals (Ter1 & Ter2) of one of the switching circuits (1 / 2) to approach the target value, the two terminals (Ter1 & Ter2) of the one switching circuit (1 / 2) are turned on during the period when the pair of switching elements (S1 & S4 / S3 & S2) are turned on in one of the switching circuits (1 / 2). The switching elements (S5 / S6) of the second leg (13) of the other switching circuit (2 / 1) are made to conduct in the forward direction so that the energy input from the side is stored in the inductance means (L), and the switching elements (S5 / S6) of the second leg (13) of the other switching circuit (2 / 1), which were conducted in the forward direction, are turned off before the switching elements (S3 / S4) of the one switching circuit (1 / 2) that are to be turned off first are turned off, and The low-input switching control described above is When the detected voltage, current, or power input from between the two terminals (Ter1 & Ter2) of one of the switching circuits (1 / 2) falls below a certain standard, the switching elements (S1 / S2) of the first leg (12) in one of the switching circuits (1 / 2) are turned on, and at the same time, the switching elements (S5 / S6) of the upper or lower arm of the second leg (24) and the switching elements (S7 / S8) of the lower or upper arm of the first leg (25) in the other switching circuit (2 / 1) are turned on, and the switching elements (S7 / S8) of the first leg (25) are turned off before the switching elements (S5 / S6) of the second leg (24) in the other switching circuit (2 / 1) are turned off.

[0014] And the control circuit is, In the low-input switching control, the period T2 for turning on the switching element of the second leg of the other switching circuit is set by Equation 1, and When performing the low-input switching control described above, if the calculation result in Equation 1 shows that time T3 is longer than time T2, then perform the alternative control in Equation 2. A converter characterized by the following.

number

number

[0015] The present invention is characterized by using the operations of the converter and bidirectional converter disclosed in Patent Documents 1 and 2 as basic operations (basic operations 1 and 2), and by additional operations (basic operation 3) that are added to increase the maximum input current, etc.

[0016] (Basic movement 1) A converter according to the first embodiment of the present invention will be described with reference to Figures 1 to 6. Figure 1 shows a configuration diagram of a converter 301 according to the first embodiment of the present invention. The converter 301 shown in Figure 1 comprises a transformer 11, a switching circuit 1 connected to the primary winding 11a side of the transformer 11, a second circuit 2 connected to the secondary winding 11b side of the transformer 11, an inductance means L, and a control circuit 3. This converter converts the DC input from the first terminal Ter1 and the second terminal Ter2 side into AC and outputs it from the switching circuit 1, and the AC is converted back into DC by the switching circuit 2 via the transformer 11 and supplied to the output side third terminal Ter3 and fourth terminal Ter4. In this description, the two terminals (Ter1 and Ter2) are described as the input side and the two terminals (Ter3 and Ter4) as the output side, but since the circuit configuration is symmetrical with respect to the transformer 11, it will operate similarly even if the input and output are reversed.

[0017] Switching circuit 1 has switching elements (S1-S4) with switch elements (Q1-Q4) each having antiparallel diodes (D1-D4) and parallel capacitors (C1-C4) connected in parallel, respectively, and a first leg (12) and a second leg (13) connected in parallel between two terminals (Ter1 & Ter2) with upper and lower arms. Switching elements (S1 / S2 / S3 / S4) on one of the upper and lower arms of the first leg or the second leg (12 / 13) or the first leg and The device comprises a first capacitor (Ca) connected in parallel to one of the switching elements (S1 / S2 / S3 / S4) on the upper or lower arm of the second leg (12 & 13), and a second capacitor (Cb) connected in parallel to the other switching element (S1 / S2 / S3 / S4) on the upper or lower arm of the first or second leg (12 / 13), or to the other switching element (S1 / S2 / S3 / S4) on the upper or lower arm of the first and second legs (12 & 13).

[0018] Switching circuit 2 has a first leg (25) and a second leg (24) connected in parallel between two terminals (Ter3 & Ter4) with switching elements (S5-S8) having switching elements (Q5-Q8) each having antiparallel diodes (D5-D8) and parallel capacitors (C5-C8) connected in parallel, respectively, and one of the upper and lower arms of the first leg or the second leg (25 / 24) has a switching element (S7 / S8 / S5 / S6) or the first leg and The device comprises a first capacitor (Cc) connected in parallel to one of the switching elements (S7 / S8 / S5 / S6) on the upper or lower arm of the second leg (25 & 24), and a second capacitor (Cd) connected in parallel to the other switching element (S7 / S8 / S5 / S6) on the upper or lower arm of the first or second leg (25 / 24), or to the other switching element (S7 / S8 / S5 / S6) on the upper or lower arm of the first and second legs (25 & 24).

[0019] Power from an external power supply is input to the first terminal Ter1 and the second terminal Ter2. A capacitor 16 is connected between the first terminal Ter1 and the second terminal Ter2, resulting in a DC voltage. Furthermore, a switching circuit 1 is connected between the first terminal Ter1 and the second terminal Ter2, and the switching circuit 1 is a full-bridge circuit in which the upper and lower arms of the first leg 12 and the second leg 13 are composed of switching elements S1 to S4. The detection means 19 detects the voltage between the first terminal Ter1 and the second terminal Ter2, or the current or power input to and output from the switching circuit 1 via the first terminal Ter1 and the second terminal Ter2. In the following description, the detection target is described as voltage, but the present invention is not limited to voltage; it operates similarly and achieves similar effects when detecting current or power.

[0020] The first leg 12 and the second leg 13 are connected in parallel between the first and second terminals, respectively. The first leg 12 has switching elements S1 and S2 as its upper and lower arms, and the second leg 13 has switching elements S3 and S4 as its upper and lower arms. In Figure 1, switching elements S1 to S4 are used, in which antiparallel diodes D1 to D4 and parallel capacitors C1 to C4 are connected in parallel to the switching elements Q1 to Q4, respectively. In other words, the antiparallel diodes D1 to D4 are the internal diodes of the switching elements S1 to S4, and the parallel capacitors C1 to C4 are the parasitic capacitances of the switching elements S1 to S4.

[0021] In this invention, the antiparallel diodes D1 to D4 connected in parallel to the switching elements Q1 to Q4 may be the built-in diodes of the switching elements S1 to S4 as shown in Figure 1, or external diodes separate from the switching elements S1 to S4, or a combination thereof. Similarly, the parallel capacitors C1 to C4 connected in parallel to the switching elements Q1 to Q4 may be the parasitic capacitances of the switching elements S1 to S4 as shown in Figure 1, or external capacitors separate from the switching elements S1 to S4, or a combination thereof.

[0022] The first capacitor Ca and the second capacitor Cb are connected in parallel to the switching elements S1 and S4 or S2 and S3 of the paired switching circuit 1 that are to be turned off first. In Figure 1, the first capacitor Ca and the second capacitor Cb are connected in parallel to the switching elements S3 and S4 of the upper and lower arms of the second leg 13 that are to be turned off first.

[0023] Switching circuit 2 has a circuit configuration that mirrors switching circuit 1 with transformer 11 in between. However, for ease of explanation, it is given different reference numerals than switching circuit 1. Specifically, capacitor 17 is connected between the third terminal Ter3 and the fourth terminal Ter4, resulting in a DC voltage. Furthermore, switching circuit 2 is connected between the third terminal Ter3 and the fourth terminal Ter4, and switching circuit 2 is a full-bridge circuit in which the upper and lower arms of the first leg 25 and the second leg 24 are composed of switching elements S5 to S8. The detection means 18 detects the voltage between the third terminal Ter3 and the fourth terminal Ter4, or the current or power input and output to switching circuit 2 via the third terminal Ter3 and the fourth terminal Ter4.

[0024] Furthermore, the first capacitor Cc and the second capacitor Cd of switching circuit 2 correspond to the first capacitor Ca and the second capacitor Cb of switching circuit 1. For ease of explanation, in this specification, the first capacitor Cc and the second capacitor Cd of switching circuit 2 may be referred to as the "third capacitor Cc" and the "fourth capacitor Cd," respectively.

[0025] In the bridge connection circuit of switching circuit 2, the secondary winding 11b of transformer 11 is connected to the connection point where parallel diodes D5 and D6 are connected in series with the same polarity, and to the other connection point where antiparallel diodes D7 and D8 are connected in series with the same polarity. In addition, capacitor 17 is connected between the third terminal Ter3 and the fourth terminal Ter4, and a DC voltage is output between the third terminal Ter3 and the fourth terminal Ter4.

[0026] The inductance means L is connected to the connection point side of the upper and lower arms of the first leg 12 and the connection point side of the upper and lower arms of the second leg 13 via the primary winding 11a of the transformer 11. This inductance means L may also be connected to the connection point side of the bridge connection circuit of the switching circuit 2 via the secondary winding 11b of the transformer 11 to the other connection point side of the bridge connection circuit where antiparallel diodes D5 and D6 are connected in series with the same polarity and antiparallel diodes D7 and D8 are connected in series with the same polarity. In Figure 1, one end of the inductance means L is connected to the connection point side of the upper and lower arms of the first leg 12 and the other end is connected to the primary winding 11a of the transformer 11, but one end of the inductance means L may also be connected to the connection point side of the upper and lower arms of the second leg 13 and the other end is connected to the primary winding 11a of the transformer 11. The same applies when the inductance means L is connected via the secondary winding 11b.

[0027] Control circuit 3 provides drive signals to the switching elements S1-S4 of switching circuit 1 and the switching elements S5 and S6 of switching circuit 2, respectively, to control the on / off state of each switching element. First, zero-volt switching (ZVS) control will be explained. In the converter 301 of Figure 1, the switching elements S1 or S3 on the upper arm of the first leg 12 or second leg 13 and the switching elements S4 or S2 on the lower arm of the second leg 13 or first leg 12 each form a pair and alternately turn on and off. Of the switching elements S1 and S4 of the paired switching elements of switching circuit 1, switching element S4 or S1 is turned off first, and then switching element S1 or S4 is turned off later. Similarly, of the switching elements S2 and S3 of the other paired switching elements of switching circuit 1, switching element S3 or S2 is turned off first, and then switching element S2 or S3 is turned off later.

[0028] Next, energy transition switching control will be explained. The detection means 18 of the switching circuit 2 shown in Figure 1 detects the output voltage of the switching circuit 2 output between the third terminal Ter3 and the fourth terminal Ter4. This detected output voltage value is input to the control circuit 3. Based on the detected output voltage value, the control circuit 3 controls the output voltage of the switching circuit 2 by turning on and off the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5 and S6 of the switching circuit 2. For example, the control circuit 3 performs pulse control to modulate the pulse width, frequency, etc., of the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5 and S6 of the switching circuit 2 so that the detected output voltage value approaches a target voltage value according to the load conditions. The detection means 18 of the switching circuit 2, for example, connects a resistor to the output side and detects the voltage applied to this resistor.

[0029] The control circuit 3 controls the amount of energy stored in the inductance means L from the first terminal Ter1 and second terminal Ter2 by controlling the pulse of the drive signal supplied to the switching element S5 or S6 of the switching circuit 2. In this case, the switching element S5 or S6 of the switching circuit 2 is turned on during the period when the switching elements S1 and S4 or S2 and S3 of the paired switching circuit 1 are both turned on, thereby short-circuiting the secondary winding 11b side of the transformer 11. This causes the energy input from the first terminal Ter1 and second terminal Ter2 side to be stored in the inductance means L. Next, the switching element S5 or S6 of the switching circuit 2 is turned off during the period when the switching elements S1 and S4 or S2 and S3 of the paired switching circuit 1 remain turned on. This causes the energy stored in the inductance means L to be supplied to the third terminal Ter3 and fourth terminal Ter4 side.

[0030] Furthermore, when the control circuit 3 is operating to lower the voltage output between the third terminal Ter3 and the fourth terminal Ter4 to a level lower than the output voltage obtained by switching the switching elements S5 and S6 of the switching circuit 2 on and off, the control circuit 3 pulse-controls the switching elements of the switching circuit 1 and operates so that the switching elements S5 and S6 of the switching circuit 2 do not conduct in the forward direction. Specifically, during the period when the pair of switching elements S1 and S4 of the switching circuit 1 or the switching elements S2 and S3 of the switching circuit 1 are in the ON state, the control circuit 3 pulse-controls the switching elements of the switching circuit 1 to supply the energy input from the first terminal Ter1 and the second terminal Ter2 to the third terminal Ter3 and the fourth terminal Ter4 via the inductance means L, and operates so that the switching elements S5 and S6 of the switching circuit 2 do not conduct in the forward direction. In this operation, the control circuit 3 prevents the switching elements S5 and S6 of the switching circuit 2 from conducting in the forward direction. Therefore, the bridge connection circuit of the switching circuit 2 functions as a full-bridge rectifier circuit in which the antiparallel diodes D5 to D8 conduct.

[0031] Regarding the drive signals, the drive signals used to turn on the switching elements of switching circuit 1 and switching circuit 2 are referred to as "on signals," and the drive signals used to turn them off are referred to as "off signals." The drive signals can be voltage, current, etc. Furthermore, the on signals, off signals, etc., may be signals that are applied throughout the entire on / off period, or signals that are applied for a short period as a trigger; they are not particularly limited.

[0032] Next, an example of the operation (ZVS control and energy transition control) of the converter 301 according to the first embodiment of the present invention will be described. First, the operation of turning the switching elements S5 and S6 of the switching circuit 2 of the converter 301 on and off will be described using Figures 2 to 6. In Embodiment 1, the switching elements S7 and S8 of the switching circuit 2 are always off. Figure 2 is a waveform diagram showing an example of the drive signals for the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5 and S6 of the switching circuit 2. Figure 3 is a waveform diagram showing an example of the voltage, current of the switching elements S1 to S4 of the switching circuit 1 and the excitation current of the transformer 11. Figure 4 is a waveform diagram showing an example of the voltage, current of the switching elements S5 and S6 of the switching circuit 2 and the voltage, current of the antiparallel diodes D7 and D8. Figure 5 is an enlarged view of a portion of the time period Tx of the waveform diagram in Figure 3. Figure 6 is a circuit diagram formed at each timing. In the current waveforms shown in Figures 3 to 5, the current flowing in the forward direction through switching elements S1 to S4 of switching circuit 1 and switching elements S5 and S6 of switching circuit 2 is considered positive, while the current flowing in the reverse direction through switching elements S1 to S4 of switching circuit 1 and switching elements S5 and S6 of switching circuit 2, as well as the current flowing in the forward direction through antiparallel diodes D7 and D8, is considered negative.

[0033] Assume that at time t1, ON signals are applied to the switching elements S1 and S4 of the paired switching circuit 1. Assume that the ON signal for the switching element S6 of switching circuit 2 has already been applied before time t1. In this case, the switching elements Q1, Q4 and Q6 conduct in the forward direction. In this state, as shown in Figure 6(a), current flows from the first terminal Ter1 side through the switching element Q1, the inductance means L, the primary winding 11a, the switching element Q4, and the second terminal Ter2 side due to the input power supplied from the first terminal Ter1 and the second terminal Ter2 side. On the secondary winding 11b side of the transformer 11, current flows through the secondary winding 11b, the switching element Q6, and the antiparallel diode D8, resulting in a short circuit on the secondary winding 11b side. Therefore, energy is stored in the inductance means L due to the input power supplied from the first terminal Ter1 and the second terminal Ter2 side. Furthermore, power is supplied from capacitor 17 to the third terminal Ter3 and the fourth terminal Ter4.

[0034] At time t2, for example, if an off signal is applied to the switching element S6 of the switching circuit 2 at a timing determined by the control circuit 3 so that the voltage detected between the third terminal Ter3 and the fourth terminal Ter4 detected by the detection means 18 of the switching circuit 2 approaches the target value, then the supply to the output side of the switching circuit 2 by the energy stored in the inductance means L begins. As shown in Figure 6(b), current flows through the same path on the primary winding 11a side of the transformer 11 from time t1, but the switching element Q6 is in the off state on the secondary winding 11b side. As shown in Figure 4, at this time t2, the switching element Q6 of the switching circuit 2 is turned off while a large current is flowing through it, so switching loss becomes a problem. As a means of reducing this switching loss, it is possible to lower the voltage across the switching element S6 when it is off.

[0035] In this invention, the capacitance of the capacitor is increased by connecting a parallel capacitor C6 and a fourth capacitor Cd in parallel with the switch element Q6. Similarly, the capacitance of the capacitor is increased by connecting a parallel capacitor C5 and a third capacitor Cc in parallel with the switch element Q5. When the switch element Q6 is turned off at time t2, as shown in Figure 6(b), on the secondary winding 11b side, current flows from the secondary winding 11b to the parallel capacitor C6 and the fourth capacitor Cd, and the antiparallel diode D8, in the direction of charging the parallel capacitor C6 and the fourth capacitor Cd connected in parallel with the turned-off switch element Q6. On the other hand, discharge current flows from the parallel capacitor C5 and the fourth capacitor Cc through the third terminal Ter3, the fourth terminal Ter4, the antiparallel diode D8, and the secondary winding 11b. By increasing the capacitance of the capacitors, the rise in voltage across the switching element S6 of the switching circuit 2 due to the charging and discharging operation of the parallel capacitor C6 and the fourth capacitor Cd, and the parallel capacitor C5 and the third capacitor Cc can be made more gradual. Therefore, the switching loss when the switching element S6 of the switching circuit 2 is turned off can be reduced.

[0036] At time t3, when the charging and discharging of the parallel capacitors C6 and the fourth capacitor Cd of the switching circuit 2, and the parallel capacitors C5 and the third capacitor Cc are complete, the antiparallel diode D5 becomes conductive, as shown in Figure 6(c). The current on the secondary winding 11b side flows from the secondary winding 11b through the antiparallel diode D5, the third terminal Ter3, the fourth terminal Ter4, and the antiparallel diode D8. The energy stored in the inductance means L between time t1 and time t2 is supplied to the output side of the switching circuit 2. In addition to supplying power to the load connected to the third terminal Ter3 and the fourth terminal Ter4, the energy stored in the inductance means L is also used to charge the capacitor 17 that was discharged between time t1 and time t2. Furthermore, the current on the primary winding 11a side continues to flow through the same current path from time t1 until time t4 when the switch element Q4 is turned off.

[0037] At time t4, the control circuit 3 sends an off signal to switching element S4 of switching circuit 1, which is the first of the pair of switching elements S1 and S4 in switching circuit 1 to be turned off. As a result, as shown in Figure 3, switching element Q4 is turned off while the current value is relatively large, and switching loss occurs when switching element S4 of switching circuit 1 is turned off. One way to reduce this switching loss is to lower the voltage across switching element S4 of switching circuit 1 when it is turned off.

[0038] In this invention, in addition to the parallel capacitor C4, a second capacitor Cb is also connected in parallel to the switch element Q4 to increase its capacitance. Similarly, in addition to the parallel capacitor C3, a first capacitor Ca is also connected in parallel to the switch element Q3 to increase its capacitance. Therefore, when the switch element Q4 is turned off at time t4, as shown in Figure 6(d), current flows from the inductance means L, primary winding 11a, parallel capacitor C4 and second capacitor Cb, second terminal Ter2, and first terminal Ter1 through the switch element Q1 on the primary winding 11a side in the direction of charging the parallel capacitor C4 and second capacitor Cb connected in parallel to the turned-off switch element Q4. On the other hand, discharge current flows from the parallel capacitor C3 and first capacitor Ca through the switch element Q1, inductance means L, and primary winding 11a. By increasing the capacitance of the capacitors, the voltage rise across the switching element S4 due to the charging and discharging operation of the parallel capacitor C4 and second capacitor Cb, and the parallel capacitor C3 and first capacitor Ca can be made more gradual. Therefore, the switching loss when the switching element S4 of the switching circuit 1 is turned off can be reduced.

[0039] At time t5, when the discharge of parallel capacitor C3 and the first capacitor Ca, and the charging of parallel capacitor C4 and the second capacitor Cb are complete, the antiparallel diode D3 connected in parallel to the switch element Q3 becomes conductive, as shown in Figure 6(e). On the primary winding 11a side, due to the energy stored in the inductance means L and the excitation current of the transformer 11, current flows from the inductance means L and primary winding 11a through the antiparallel diode D3 and switch element Q1 in the same direction as the current that flowed through the primary winding 11a and inductance means L immediately before time t5. On the secondary winding 11b side, current continues to flow from time t3 through the secondary winding 11b, antiparallel diode D5, the third terminal Ter3 side, the fourth terminal Ter4 side, and antiparallel diode D8. The period during which current flows through this current path on the secondary winding 11b side continues from the time the antiparallel diode D5 becomes conductive until the current flowing through the antiparallel diode D5 becomes almost zero.

[0040] At time t6, the drive signal of switching element S1, which is to be turned off later, is turned off. As switching element Q1 is turned off, the excitation current of the transformer that was flowing just before time t6 causes current to flow from the primary winding 11a through the antiparallel diode D3, parallel capacitor C1, and inductance means L, charging the parallel capacitor C1. Meanwhile, a discharge current flows from the parallel capacitor C2 through the inductance means L, primary winding 11a, antiparallel diode D3, the first terminal Ter1 side, and the second terminal Ter2 side. At this time, switching element Q1 is turned off while current is still flowing, but this current can be used as the excitation current of the transformer 11, which has a very small value. Therefore, by turning off switching element S1 later, the current value at the time of turning off can be reduced, and thus the switching loss can be reduced compared to when switching element Q4 is turned off earlier.

[0041] At time t7, when the charging and discharging of parallel capacitors C1 and C2 is complete, the antiparallel diode D2 becomes conductive, as shown in Figure 6(g). On the primary winding 11a side, current flows from the primary winding 11a through the antiparallel diode D3, the first terminal Ter1 side, the second terminal Ter2 side, the antiparallel diode D2, and the inductance means L in the same direction as the current that flowed through the primary winding 11a immediately before time t7, due to the excitation current of the transformer 11. Meanwhile, the current on the secondary winding 11b side continues to flow from time t3 through the secondary winding 11b, the antiparallel diode D5, the third terminal Ter3 side, the fourth terminal Ter4 side, and the antiparallel diode D8. The period during which current flows through this current path on the secondary winding 11b side continues from the time the antiparallel diode D5 becomes conductive until the current flowing through the antiparallel diode D5 becomes almost zero.

[0042] At time t8, the drive signals for switching elements S2 and S3 of the other pair of switching circuits 1 are turned ON. As shown in Figure 6(h), on the primary winding 11a side, switching elements Q2 and Q3 conduct in the forward direction, and current flows through the first terminal Ter1, switching element Q3, primary winding 11a, inductance means L, switching element Q2, and second terminal Ter2. On the secondary winding 11b side, an ON signal is given to the drive signal for switching element S5 of switching circuit 2 before time t8, so at time t8, switching element Q5 is in a state where it can conduct in the forward direction. Therefore, when switching element Q5 conducts in the forward direction, current flows from the secondary winding 11b through the antiparallel diode D7 and switching element Q5, and the secondary winding 11b side becomes short-circuited. Thus, energy is stored in the inductance means L by the power input between the first terminal Ter1 and the second terminal Ter2.

[0043] In this invention, immediately before time t8, the antiparallel diodes D2 and D3, which are connected in parallel to the switch elements Q2 and Q3 respectively, are conducting. As shown in Figure 5, the switching elements S2 and S3 of the switching circuit 1 can achieve zero-voltage switching (ZVS) when they are turned on.

[0044] Furthermore, since the antiparallel diode D5, which is in parallel with the switch element Q5, is conducting just before time t8, the switch element Q5 can be turned on at zero voltage. In order to achieve zero-voltage switching (ZVS) of the switch element Q5, the ON signal, which is the drive signal for the switching element S5 of the switching circuit 2, should be applied during the period from time t3 to time 8, which is the period when the antiparallel diode D5 is conducting.

[0045] The operation of the other pair of switching elements S2 and S3 of switching circuit 1 after time t8 is performed in the same way as the pair of switching elements S1 and S4 described above from time t1 to time t8. That is, during the period when switch elements Q2 and Q3 are conducting, an off signal is applied to the switching element S5 of switching circuit 2 at a timing determined by the control circuit 3 so that, for example, the voltage detection value between the third terminal Ter3 and the fourth terminal Ter4, which are the output side of switching circuit 2, reaches a predetermined value. This supplies the energy stored in the inductance means L to the third terminal Ter3 and the fourth terminal Ter4. Subsequently, of the pair of switching elements S2 and S3, the switch element Q3, which has the first capacitor Ca connected in parallel, is turned off first, followed by the switch element Q2.

[0046] In this invention, as shown in Figure 1, the switching elements S1 and S2 of the switching circuit 1, which will be turned off later, are connected in series. In order to achieve zero-voltage switching for these switching elements S1 and S2, for example, when turning off switching element S1, the voltage across the other switching element S2 on the lower arm of the same first leg is lowered to zero before an ON signal is applied to switching element Q2. Here, the period from when an OFF signal is applied to switching element Q1 until an ON signal is applied to switching element Q2, that is, the period during which both switching elements S1 and S2 are turned off, is denoted as Td.

[0047] The discharge operation that reduces the voltage across the switching element S2 to zero, that is, discharges it until the voltage across the capacitor C2 becomes zero, is caused by the flow of the excitation current described above. Therefore, in order to achieve zero-voltage switching of the switching element S2, which will be turned off later, it is first necessary to set the excitation current to a size that can reduce the voltage across the switching element S2 to zero. Furthermore, it is necessary to provide a period Td during which both switching elements S1 and S2 are turned off, such that the excitation current can reduce the voltage across the switching element S2 to zero. The same applies when achieving zero-voltage switching (ZVS) for the switching element S1 of the switching circuit 1, which will be turned off later. It is necessary to provide an excitation current of a size that can reduce the voltage across the switching element S1 to zero, and a period Td during which both switching elements S1 and S2 are turned off.

[0048] Furthermore, if the period Td for turning off both switching elements S1 and S2 of switching circuit 1 is set to a large value, the voltage across switching element S1 or S2 may drop to zero and then rise again, meaning that capacitor C1 or C2 may be discharged to zero and then charged. For this reason, it is preferable that the period Td for turning off both switching elements S1 and S2 be approximately the period for which the voltage across switching element S1 or S2 drops to zero. In addition, the parallel capacitors C1 and C2, which are connected in parallel to the switching elements Q1 and Q2 that are turned off later, will have small capacitance values, such as the parasitic capacitance built into switching elements S1 and S2, and may vary depending on the component. For this reason, an additional capacitor may be connected in parallel to the parasitic capacitance built into switching elements S1 and S2, and the combined capacitance of these may be used as the parallel capacitors C1 and C2.

[0049] Next, using the circuit diagram of converter 301 in Figure 1 and Figures 7 to 10, we will explain the operation in which the switching circuit 2 functions as a full-bridge rectifier circuit when the voltage output between the third terminal Ter3 and the fourth terminal Ter4 is made lower than the output voltage obtained by the operation of switching elements S5 and S6 of the switching circuit 2 described above on and off. Figure 7 is a waveform diagram showing an example of the drive signals for switching elements S1 to S4 of switching circuit 1 and switching elements S5 and S6 of switching circuit 2 in this operation. Figure 8 is a waveform diagram showing an example of the voltage, current of switching elements S1 to S4 of switching circuit 1 and the excitation current of transformer 11 in this operation. Figure 9 is a waveform diagram showing an example of the voltage and current of antiparallel diodes D5 to D8 of switching circuit 2 in this operation. Figure 10 is a circuit diagram formed at each timing for this operation of converter 301 according to the first embodiment of the present invention. In the current waveforms shown in Figures 8 and 9, the current flowing in the forward direction through switching elements S1 to S4 of switching circuit 1 is considered positive, while the current flowing in the reverse direction through switching elements S1 to S4 of switching circuit 1 and the current flowing in the forward direction through antiparallel diodes D5 to D8 are considered negative.

[0050] In this operation, the converter circuit in Figure 1 functions as a full-bridge rectifier circuit in which the bridge connection circuit of switching circuit 2 conducts through the antiparallel diodes D5 to D8. Therefore, in the converter 301 of Embodiment 1, at least the switching circuit 2 only needs to have antiparallel diodes D5 to D8, and as shown in Figure 7, no ON signal is applied to the drive signals of switching elements S5 and S6 of switching circuit 2.

[0051] Time t21 is the point at which an ON signal is applied to the switching elements S1 and S4 of the paired switching circuit 1. At this time, no ON signal is applied to the switching elements S5 and S6 of the switching circuit 2. As shown in Figure 10(a), on the primary winding 11a side of the transformer 11, current flows from the first terminal Ter1 side through the switching element Q1, inductance means L, primary winding 11a, switching element Q4, and second terminal Ter2 side. On the secondary winding 11b side of the transformer 11, current flows from the secondary winding 11b through the antiparallel diode D5, and from the third terminal Ter3 and fourth terminal Ter4 sides through the antiparallel diode D8. The input power supplied from the first terminal Ter1 and second terminal Ter2 side is supplied to the third terminal Ter3 and fourth terminal Ter4 side via the inductance means L.

[0052] At time t22, for example, the control circuit 3 provides an off signal to switching element S4 of the pair of switching elements S1 and S4 of the switching circuit 1 so that the voltage detected between the third terminal Ter3 and the fourth terminal Ter4 detected by the detection means 18 of the switching circuit 2 approaches the target value. As a result, as shown in Figure 8, the switching element Q4 is turned off when the current value is relatively large, so switching loss occurs when the switching element S4 is turned off. In this invention, as explained in the operation of turning the switching elements S5 and S6 of the switching circuit 2 on and off, a second capacitor Cb is connected in parallel with the switching element Q4 in addition to the parallel capacitor C4 to increase the capacitance of the capacitor. Similarly, a first capacitor Ca is connected in parallel with the switching element Q3 in addition to the parallel capacitor C3 to increase the capacitance of the capacitor.

[0053] Therefore, when the switching element Q4 is turned off at time t22, as shown in Figure 10(b), on the primary winding 11a side, current flows through the switching element Q1 from the inductance means L, primary winding 11a, parallel capacitor C4 and second capacitor Cb, second terminal Ter2, and first terminal Ter1 side in the direction of charging the parallel capacitor C4 and second capacitor Cb connected in parallel to the turned-off switching element Q4. On the other hand, discharge current flows from the parallel capacitor C3 and first capacitor Ca through the switching element Q1, inductance means L, and primary winding 11a. By increasing the capacitance of the capacitors connected in parallel to the switching elements S4 and S3 of the switching circuit 1 that are turned off first, the rise in voltage across the switching element S4 is slowed down, thereby reducing the switching loss when the switching element S4 of the switching circuit 1 is turned off.

[0054] At time t23, when the discharge of parallel capacitor C3 and the first capacitor Ca, and the charging of parallel capacitor C4 and the second capacitor Cb are complete, the antiparallel diode D3 connected in parallel to the switch element Q3 becomes conductive, as shown in Figure 10(c). On the primary winding 11a side, due to the energy stored in the inductance means L and the excitation current of the transformer 11, current flows from the inductance means L and primary winding 11a through the antiparallel diode D3 and switch element Q1 in the same direction as the current that flowed through the primary winding 11a and inductance means L just before time t5. The current on the secondary winding 11b side continues to flow from time t21 through the secondary winding 11b, antiparallel diode D5, the third terminal Ter3 side, the fourth terminal Ter4 side, and antiparallel diode D8.

[0055] At time t24, the drive signal of switching element S1, which is to be turned off later, is turned off. As switching element Q1 is turned off, the excitation current of the transformer that was flowing just before time t23 causes current to flow from the primary winding 11a through the antiparallel diode D3, parallel capacitor C1, and inductance means L, as shown in Figure 10(d), and charges the parallel capacitor C1. Meanwhile, a discharge current flows from the parallel capacitor C2 through the inductance means L, primary winding 11a, antiparallel diode D3, first terminal Ter1, and second terminal Ter2. At this time, switching element Q1 is turned off while current is still flowing through it, but the current can be made smaller than when switching element Q4 is turned off earlier. Therefore, the switching loss of switching element Q1, which is turned off later, can be made smaller compared to when switching element Q4 is turned off earlier.

[0056] At time t25, when the charging and discharging of parallel capacitors C1 and C2 is complete, the antiparallel diode D2 becomes conductive, as shown in Figure 10(e). On the primary winding 11a side, the excitation current of the transformer 11 causes current to flow from the primary winding 11a in the same direction as the current that was flowing in the primary winding 11a immediately before time t25, through the antiparallel diode D3, the first terminal Ter1, the second terminal Ter2, the antiparallel diode D2, and the inductance means L. On the secondary winding 11b side, the current continues to flow from time t21 through the secondary winding 11b, the antiparallel diode D5, the third terminal Ter3, the fourth terminal Ter4, and the antiparallel diode D8.

[0057] At time t26, an ON signal is applied to the switching elements S2 and S3 of the other pair of switching circuits 1. As shown in Figure 10(f), on the primary winding 11a side, the switching elements Q2 and Q3 conduct in the forward direction, and current flows through the first terminal Ter1, the switching element Q3, the primary winding 11a, the inductance means L, the switching element Q2, and the second terminal Ter2. Since the current flowing through the primary winding 11a is in the opposite direction, on the secondary winding 11b side, the antiparallel diodes D6 and D7 conduct in the forward direction, and current flows from the secondary winding 11b through the antiparallel diode D7, the third terminal Ter3, and the fourth terminal Ter4 through the antiparallel diode D6. Similar to the case in Figure 10(a), the power input between the first terminal Ter1 and the second terminal Ter2 is supplied to the third terminal Ter3 and the fourth terminal Ter4 via the inductance means L.

[0058] Similar to the operation of switching elements S5 and S6 of switching circuit 2 described above, when the bridge connection circuit of switching circuit 2 is operated as a full-bridge rectifier circuit, the antiparallel diodes D2 and D3 connected in parallel to the switch elements Q2 and Q3, respectively, conduct just before time t26. Therefore, as shown in Figure 8, the switching elements S2 and S3 of switching circuit 1 can achieve zero-voltage switching when they are turned on.

[0059] The operation of the switching elements S2 and S3 of the other pair of switching circuits 1 after time t26 is to be the same as that of the pair of switching elements S1 and S4 described above, from time t21 to time t26. That is, for example, in order for the output voltage between the third terminal Ter3 and the fourth terminal Ter4 to become the desired value, the control circuit 3 first turns off the switching element Q3 of the pair of switching elements S2 and S3, which has the first capacitor Ca connected in parallel, and then turns off the switching element Q2.

[0060] In the converter 301 according to the first embodiment described above, when the control circuit 3 is operating to make the bridge connection circuit of the switching circuit 2 function as a full-bridge rectifier circuit, if the detected voltage output from the third terminal Ter3 and the fourth terminal Ter4 does not approach the target value even when the pulse width and frequency of the switching elements of the switching circuit 1 are modulated, the control circuit 3 switches to the operation of turning the switching elements S5 and S6 of the switching circuit 2 on and off. Conversely, when the control circuit 3 is operating to turn the switching elements S5 and S6 of the switching circuit 2 on and off, if the detected voltage output from the third terminal Ter3 and the fourth terminal Ter4 does not approach the target value even when the pulse width and frequency of the switching elements S5 and S6 of the switching circuit 2 are modulated, the control circuit 3 switches to the operation of making the bridge connection circuit of the switching circuit 2 function as a full-bridge rectifier circuit. By switching between these two operations, it is possible to accommodate a wide range of input and output voltages and currents without being constrained by circuit constants such as the turns ratio of the transformer 11 or load conditions.

[0061] Furthermore, similar to the operation of switching elements S5 and S6 of switching circuit 2 described above, when the bridge connection circuit of switching circuit 2 functions as a full-bridge rectifier circuit, the capacitance of the capacitor connected in parallel to the switching element that is turned off first among the set of switching elements of switching circuit 1 is made larger than the capacitance of the capacitor connected in parallel to the switching element that is turned off later. In addition, in order to achieve zero-voltage switching for the switching elements S1 and S2 of switching circuit 1 that are turned off later, it is necessary to first make the excitation current large enough to reduce the voltage across switching element S2 or S1 to zero. Furthermore, it is necessary to provide a period Td in which both switching elements S1 and S2 are turned off so that the voltage across switching element S2 or S1 can be reduced to zero by the excitation current.

[0062] The period Td during which both switching elements S1 and S2 of switching circuit 1 are turned off is preferably approximately the period during which the voltage across either switching element S1 or S2 drops to zero. Furthermore, the parallel capacitors C1 and C2, which are connected in parallel to the switching elements Q1 and Q2 that are turned off later, will have small capacitance values, such as when they are built into the switching elements S1 and S2, and may vary depending on the component. For this reason, separate capacitors may be connected in parallel to the parasitic capacitance built into the switching elements S1 and S2, and the combined capacitance of these capacitors may be used as the parallel capacitors C1 and C2.

[0063] Figures 2 and 7 show an example of operation in which the ON signals, which are the drive signals for the switching elements S2 and S3 of the switching circuit 1, are simultaneously applied at times t8 and t26, and the switching elements Q2 and Q3 begin to conduct in the forward direction. However, the operation is not limited to the example of operation in the above embodiment, and the timing of applying the ON signals to the switching elements S2 and S3 does not have to be simultaneous. Also, the timing of applying the ON signals to the switching elements S2 and S3 may be during the period when the antiparallel diodes D2 and D3 are conducting. In this case, the timing of applying the ON signals to the switching elements S2 and S3 and the timing of the start of forward conduction of the switching elements Q2 and Q3 do not coincide. For example, current begins to flow in the forward direction through the switching elements Q2 and Q3 after the current conducting through the antiparallel diodes D2 and D3 becomes zero. Furthermore, if the voltage drop across switching elements Q2 and Q3 when current flows in the reverse direction is smaller than the forward voltage, which is the voltage drop across antiparallel diodes D2 and D3 when current flows in the forward direction, an ON signal can be applied to switching elements S2 and S3, causing switching elements Q2 and Q3 to conduct in the reverse direction and reducing the conduction loss of switching elements S2 and S3. The same applies to switching elements S1 and S4 of the other pair of switching circuits 1.

[0064] In the first embodiment described above, the switching elements S4 and S3 of the upper and lower arms of the second leg 13 are turned off first among the switching elements S1 and S4, S2 and S3 of the paired switching circuit 1. However, the switching elements S1 and S2 of the upper and lower arms of the first leg 12 may be turned off first. In this case, the first capacitor Ca and the second capacitor Cb are connected to the switching elements S1 and S2 that are turned off first, respectively. Alternatively, the switching elements of the switching circuit 1 that are turned off first may be the switching elements S1 and S3 of the upper arms of the first leg 12 and the second leg 13, or the switching elements S2 and S4 of the lower arms of the first leg 12 and the second leg 13. In this case, the first capacitor Ca and the second capacitor Cb are connected in parallel to the switching elements S1 and S3 or the switching elements S2 and S4 that are turned off first, respectively.

[0065] Furthermore, in the first embodiment described above, the positions of the series circuits of switching elements S5 and S6 connected between the third terminal Ter3 and the fourth terminal Ter4 and the series circuits of antiparallel diodes D7 and D8 within the bridge connection circuit of the switching circuit 2 shown in Figure 1 may be swapped. In this case as well, the third capacitor Cc and the fourth capacitor Cd are connected in parallel to the switching elements S5 and S6 of the switching circuit 2 that are to be turned on and off, respectively. Alternatively, the switching circuit 2 may be configured as a mixed bridge connection in which the series circuits of antiparallel diodes D7 or D8 and the switching elements S5 or S6 of the switching circuit 2 are connected between the third terminal Ter3 and the fourth terminal Ter4, respectively. In this case as well, the third capacitor Cc and the fourth capacitor Cd are connected in parallel to the switching elements S5 and S6 of the switching circuit 2 that are to be turned on and off, respectively.

[0066] In the description of the operation of the bridge connection circuit of the switching circuit 2 described above as functioning as a full-bridge rectifier circuit, during the period when the antiparallel diodes D5 and D6 conduct, an ON signal may be applied to the switching elements S5 and S6 in Figure 1, for example, to cause the switching elements Q5 and Q6 to conduct in the reverse direction, i.e., in the forward direction of the antiparallel diodes D5 and D6. If the voltage drop across the switching elements Q5 and Q6 when current flows in the reverse direction is smaller than the forward voltage, which is the voltage drop across the antiparallel diodes D5 and D6 when forward current flows, the conduction loss of the antiparallel diodes D5 and D6 can be reduced. Similarly, when using switching elements S7 and S8 including antiparallel diodes D7 and D8, or switching elements S7 and S8 connected in parallel with antiparallel diodes D7 and D8, the conduction loss of the switching elements Q7 and Q8 can be reduced to the conduction loss of the antiparallel diodes D7 and D8 by causing them to conduct in the reverse direction. Furthermore, if the converter 301 described above is used solely for the purpose of lowering the voltage output between the third terminal Ter3 and the fourth terminal Ter4 to a level lower than the output voltage obtained by switching the switching elements S5 and S6 of the switching circuit 2 on and off, then the switching circuit 2 only needs to have at least antiparallel diodes D5 to D8 that operate as a full-bridge rectifier circuit, or switching elements that can pass current in the same direction as the forward direction of antiparallel diodes D5 to D8.

[0067] The converter 301 of the present invention uses inductance means connected to the primary or secondary winding side of the transformer to enable switching the switching elements of the switching circuit 2 and to enable the bridge connection circuit of the switching circuit 2 to function as a full-bridge rectifier circuit, thereby enabling it to handle a wide range of input and output voltages and currents. Furthermore, it can reduce switching losses that occur when a switching element is turned off while current is flowing, and it can also reduce switching losses that occur when one of the switching elements of a pair of switching circuits 1 is turned off later. In addition, switching losses can be reduced by achieving zero-voltage switching.

[0068] (Basic movement 2) The converter circuit described in Figure 1 has a circuit configuration in which the switching circuit 2 and the switching circuit 1 are mirror images of each other with the transformer 11 in between, so it also functions as a bidirectional converter. In other words, if the control circuit 3 operates the switching elements S1 to S6 as described in Embodiment 1, power can be moved from the input side (first terminal Ter1, second terminal Ter2) to the output side (third terminal Ter3, fourth terminal Ter4). If the switching elements S3 to S8 are operated as described in Embodiment 1 so that the input side is the third terminal Ter3 and fourth terminal Ter4 and the output side is the first terminal Ter1 and second terminal Ter2, power can be moved from the input side (third terminal Ter3, fourth terminal Ter4) to the output side (first terminal Ter1, second terminal Ter2).

[0069] In the present invention, as described above, the inductance component provided in parallel with the primary or secondary winding of the transformer 11 to make the excitation current an appropriate size is also included in the excitation inductance of the transformer. Furthermore, as described above, the current flowing due to the combined inductance formed by the excitation inductance of the transformer 11 and the inductance component provided in parallel therewith is also included in the excitation current. The excitation inductance of the transformer can be adjusted in the structure of the transformer, for example, by the core gap width, the number of turns in the winding, the material of the core, etc.

[0070] In the first and second embodiments described above, the control circuit 3 adjusts the voltage values ​​detected by the detection means 18 of the switching circuit 2 and the detection means 19 of the switching circuit 1 to approach the target value. However, the detection values ​​used may be the output current value, output power, or a combination thereof. Similarly, the detection values ​​of the input voltage, current, or power may be adjusted to approach the target value. Generally, the power detection value is calculated by multiplying the detected voltage and current. The output voltage, current, or power detection values ​​or input voltage, current, or power detection values ​​described above also include values ​​obtained by multiplying or dividing these values ​​by a coefficient, or by adding or subtracting a certain value.

[0071] This invention enables the handling of a wide range of input and output voltages and currents by using an inductance means connected to the primary or secondary winding side of a transformer to enable and disable the switching elements of the output-side switching circuit 2 or switching circuit 1, and to enable the output-side switching circuit 2 or switching circuit 1 to function as a rectifier circuit. Furthermore, it can reduce switching losses that occur when a switching element is turned off while current is flowing, and it can also reduce switching losses that occur when one of the switching elements of a pair of switching circuits 1 is turned off later. In addition, switching losses can be reduced by achieving zero-voltage switching.

[0072] (Basic movement 3) This section describes additional operation (low-input switching control) in the converter 301 (bidirectional converter) having the circuit shown in Figure 1. This explanation assumes that two terminals (Ter1 and Ter2) are the input side and two terminals (Ter3 and Ter4) are the output side. However, since the circuit configuration is symmetrical with respect to transformer 11, the operation will be the same even if the input and output are reversed.

[0073] When the detected voltage, current, or power input from between the two terminals (Ter1 & Ter2) of one of the switching circuits (1) falls below a certain standard, the control circuit 3 turns on the switching elements (S1 / S2) of the first leg (12) of one of the switching circuits (1), and at the same time turns on the switching elements (S6 / S5) of the upper or lower arm of the second leg (24) and the switching elements (S7 / S8) of the lower or upper arm of the first leg (25) of the other switching circuit (2), and before turning off the switching elements (S6 / S5) of the second leg (24) of the other switching circuit (2), it turns off the switching elements (S7 / S8) of the first leg (25).

[0074] Figures 11 to 14 illustrate the switching control performed by the control circuit 3. Figure 11 is a waveform diagram (same as Figure 2) that drives each switch during steady-state operation when the detected values, such as the input current, input to the two terminals (Ter1 and Ter2) are greater than or equal to a predetermined value. The switching frequency is the reciprocal of one period Tt, which is the time from when the switching element S1 or S2 is turned on until it is turned on again after being turned off. For example, the steady-state switching frequency is 50 kHz.

[0075] In this converter 301, the control circuit 3 drives each switch as shown in Figure 11 during steady-state operation. The control circuit 3 monitors the input voltage to the two terminals (Ter1 and Ter2) detected by the detection means 19 of the switching circuit 1, and performs energy transition switching control to adjust the energy transition period (Tp) during which the pair of switching elements (S1&S4 / S3&S2) of one of the switching circuits (1) and the switching elements (S6 / S5) of the second leg (24) of the other switching circuit (2) are in the ON state.

[0076] For example, the control circuit (3) is If the voltage input from the side between the two terminals (Ter1 & Ter2) of one of the switching circuits (1) decreases, and the current value Itr flowing through the winding (11a) of the transformer (11) to which one of the switching circuits (1) is connected cannot meet a predetermined value, then the energy transition switching control shall be performed as follows: To lengthen the energy transition period (Tp), phase control is performed to shift the phase of the on / off cycle of the switching element (S6 / S5) in the second leg (13) of the other switching circuit (2) (Figures 11 to 12), and time control is performed to adjust the period T2 during which the switching element (S6 / S5) in the second leg (13) of the other switching circuit (2) is ON (from Figure 12 to Figure 13, the period T2 is extended to T2').

[0077] Specifically, when the control circuit 3 detects a decrease in detected values ​​such as the input current, it delays the phase of the switching elements (S5, S6) (shifting them to the right in the diagram) as shown in Figures 11 to 12, and performs phase control to lengthen the period Tp during which the switching elements (S1, S4, and S6) and the switching elements (S2, S3, and S5) are simultaneously turned on. In other words, even if the input current decreases, lengthening the period Tp through phase control prevents a decrease in the energy required for the transition from switching circuit 1 to switching circuit 2, and also prevents a decrease in the current value Itr flowing through the primary side of transformer 11, which is necessary for realizing ZVS for the switching elements (S1, S2) (see Figure 6(a) or (h)). At time t6, the input current from the two terminals (Ter1, Ter2) is used to charge and discharge the parallel capacitors (C1, C2) to realize ZVS.

[0078] Here, the phase control of switching elements S5 and S6 can be delayed until the time (t1 or t8) when the switching elements (S2, S3 or S1, S4) turn on. After delaying the phase of switching elements S5 and S6 to the maximum extent, if the control circuit 3 detects that the input current value is still insufficient to the target value, it controls the switching elements (S5 and S6) to turn on from the period T2 to T2', as shown in Figures 12 to 13, thereby lengthening the period Tp. In other words, even if the input current is further reduced, lengthening the period Tp prevents a decrease in the energy required for the transition from switching circuit 1 to switching circuit 2, and also prevents a decrease in the current value Itr flowing on the primary side of transformer 11, which is necessary for realizing ZVS.

[0079] Thus, in energy transition switching control, the switching elements (S5, S6) are turned on at appropriate timings and durations, and the secondary side of the transformer 11 is short-circuited, thereby applying an input voltage to the inductance means L and increasing the current value Itr.

[0080] Here, by controlling the time of switching elements S5 and S6, it is possible to extend the period Tp to the time when the switching elements (S2, S3) are turned on (the time from time t1 to t4 in Figures 11 to 13). Although it is possible to extend the period T2', the time when the switching elements (S2, S3) are turned on (t1-t4) does not change, so the period Tp cannot be extended any further. Note that, as will be discussed later, there is an optimal value for the period T2 (T2').

[0081] Therefore, if the current value Itr cannot satisfy the predetermined value even after performing the energy transition switching control described above, the control circuit 3 performs the low input switching control (Figure 14).

[0082] Specifically, when the control circuit 3 detects a further decrease in input current, as shown in Figure 14, it turns on the switching elements (S8, S7) that were normally off at the time (t1 or t8) when the switching elements (S2, S3, and S5) turn on simultaneously and the switching elements (S1, S4, and S6) turn on simultaneously. The period T3 during which the switching elements (S8, S7) are turned on will be described later.

[0083] Figure 15 illustrates the current value Itr when low-input switching control is not performed. The horizontal axis represents time, and the vertical axis represents the current value Itr. As mentioned above, the converter 301 uses the primary current of the transformer 11 to reduce the charge of the parallel capacitors (C1 / C2) of the switching elements (S1 / S2) between times t6 and t7, thereby achieving ZVS at time t8. When the input voltage becomes extremely low (for example, 0V), the voltage applied to the inductance means L also becomes low, so even if the phase control and time control of the switching elements (S5, S6) are performed to lengthen the period Tp (dotted line) as shown in Figure 15, it becomes difficult to increase the current value Itr, i.e., ZVS becomes difficult.

[0084] Therefore, as in this embodiment, for example, low-input switching control is performed to turn on the switching element S8 during the period Tp when the primary-side switching elements (S2, S3) and secondary-side switching element S5 of the transformer 11 are simultaneously turned on. Specifically, between Figure 6(g) and Figure 6(h), the switching element S8 is turned on for a time T3 to form the circuit state shown in Figure 22. With this control, the output voltage Vo generated at the two terminals (Ter3, Ter4) is applied to the secondary side of the transformer 11, and the sum of the primary-side equivalent value of the output voltage Vo and the input voltage Vin input from the two terminals (Ter1 & Ter2) (VL = Vin + Vo) is applied to the inductance means L. As a result, the slope (increase rate) of the current value Itr of the transformer 11 can be increased compared to Figure 15. (Figures 16, 22). Compared to Figure 15, which does not perform low-input switching control, Figure 16, which performs low-input switching control, can significantly increase the current value Itr during the period T3. Thus, in this embodiment, the charge of the parallel capacitors (C1, C2) of the switching elements (S1, S2) can be sufficiently reduced, and the value x of the current Itr required for ZVS can be secured.

[0085] On the other hand, when the switching element S5 is turned off at time t2 (period T2), the increase in the current value Itr during period T3 becomes the residual current. This residual current becomes reactive current and increases losses. From the perspective of reducing residual current (reactive current) and minimizing losses, it is desirable to turn off the switching element S5 earlier (shorten period T2) in order to extend the discharge time of the parallel capacitor C5 and capacitor Cc.

[0086] In other words, there is a trade-off relationship between period T2 and period T3, where the input current increases and losses occur, and there is an optimal period T2 for obtaining the desired input current. Here, we will explain the optimal value of period T2 (T2') using Figures 17 to 19. Figures 17 to 19 show the current waveforms flowing through the switching elements (S1, S2) (the antiparallel diodes (D1, D2) and parallel capacitors connected in parallel to each of the switching elements (Q1, Q2) ( This diagram illustrates the current waveforms including C1 and C2. The horizontal axis represents time, and the vertical axis represents the current value Isw flowing through the switch elements (S1 and S2). Figure 17 shows the current waveform when the period T2 (T2') is optimal, Figure 18 shows the current waveform when the period T2 (T2') is short, and Figure 19 shows the current waveform when the period T2 (T2') is too long.

[0087] The optimal period T2(T2') is calculated as follows: First, the current value Itr required to make the switching elements (S1, S2) zero-voltage (ZVS) is set as the current value x. The current value x is determined by the type of switching elements (S1, S2) and the specifications of the converter.

[0088] The control circuit 3 then sets the period T2 for turning on the switching element (S6 / S5) of the second leg 24 of the other switching circuit 2 using formula (1) in the low-input switching control.

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[0089] If period T2 is appropriate, current flows through the switching element (S1 or S2) as follows (we will describe switching element S1 here). At time t6 (t6 on the leftmost side of the horizontal axis), the switching element Q2 turns off and at the same time discharge begins from the parallel capacitor C1 (the parallel capacitor C2 starts charging) (spike portion A01 in the current waveform). Because the capacitance of the parallel capacitor C1 is small, once the discharge of the parallel capacitor C1 is complete, current begins to flow through the antiparallel diode D1 (similarly, spike portion A01 in the current waveform). Note that this time is t7 (the time when current is flowing as shown in Figure 6(g)), but this is omitted in Figure 17. The switching element Q1 is turned on before this current becomes zero (time t1=t8; end of period Td). At time t1, the switching element Q7 also turns on, so period T3 begins. During period T3, the voltages from the two terminals (Ter3 and Ter4) are applied to the secondary side of the transformer 11. The sum of the primary-side equivalent value of the output voltage and the input voltages from the two terminals (Ter1 and Ter2) is applied to the inductance means L, increasing the current value Itr and the current Isw flowing through the switching element S1. After period T3, the switching element Q7 is turned off, and the application of the voltages from the two terminals (Ter3 and Ter4) to the secondary side of the transformer 11 ceases during period T3. As a result, the increase in the current Isw flowing through the switching element S1 becomes small (and in some cases, does not increase at all).

[0090] At time t4, the switch element Q4 is turned off first, and then at time t2, the switch element Q6 is also turned off. After time t2, the inductance means L releases energy, so the current value Itr decreases, and the current Isw flowing through the switching element S1 also decreases. Then, at time t6, as the switch element Q1 is turned off, current begins to flow through the parallel capacitor C1, but because the capacitance of the parallel capacitor C1 is small, charging is completed quickly, and the current Isw flowing through the switching element S1 becomes zero (part A02 of the current waveform). Note that this time is t7, but it is omitted from Figure 17.

[0091] If the period T3 is long and the period T2 calculated as shown in equation (1) is short, the current Isw will flow in the reverse direction just before the switching of the switch elements Q1 / Q2 (part A1), as shown in Figure 18, and ZVS cannot be realized. On the other hand, if the period T3 is short and the period T2 calculated as shown in equation (1) is long, the switch elements Q1 / Q2 will turn off before the current becomes zero (part A2), as shown in Figure 19, and the switching loss will increase. Furthermore, since that current flows in the reverse direction after the other switch element Q2 / Q1 turns on (part A3), the current input from the side between the two terminals (Ter1 & Ter2) will decrease.

[0092] In this way, by calculating the maximum value of period T2 using formula (1), it is possible to set an optimal period T2 that ensures the current value x required for ZVS when the switching elements (S1, S2) are ON, while preventing the current value when they are OFF from becoming too large.

[0093] Specifically, when the input current decreases, the control circuit 3 controls the switching element as follows: To increase the input current, control circuit 3 controls the switching elements (S5, S6) by first advancing the phase of the drive signal while keeping the pulse width of the drive signal fixed (Figures 11 to 12). Then, control circuit 3 fixes the phase and widens the pulse width when the timing of turning on the switching elements (S5, S6) is approximately the same as the timing of turning on the switching elements (S1, S2) (Figure 13). Furthermore, when the pulse width period T2 reaches the calculated value Tca, control circuit 3 applies a drive signal to the switching elements (S7, S8) to create period T3 and start low-input switching control (Figure 14). Here, the value Tca is the period T2 calculated under condition 2 (T3=0) of equation (1). Under condition 2 of equation (1), when period T3 expands, period T2 also expands. Here, when the expanded period T3 satisfies condition 1 of equation (1), period T2 is calculated as T3'=T3. Control circuit 3 continues to calculate equation (1) to maintain the state shown in Figure 17, and periods T2 and T3 are shortened or expanded depending on the situation.

[0094] (Embodiment 1) The control circuit 3 of the converter 301 in this embodiment controls the period of T2 to an appropriate value as in the above-described basic operations 1 to 3. However, depending on the input and output states (for example, the condition that the output voltage is low), the calculation result of the mathematical formula (1) in the basic operation 3 may be such that T2 < T3. The problem that occurs when T2 < T3 will be described using FIG. 23.

[0095] FIG. 23 is a diagram for explaining the case where the calculation result of the mathematical formula (1) is T2 > T3 and the case where T2 < T3 in the basic operation 3. FIG. 23(D) is a timing chart (for a half cycle) of the drive signals for driving each switching element when T2 > T3. FIG. E is a timing chart (for a half cycle) of the drive signals for driving each switching element when T2 < T3.

[0096] Let the period during which both the switching element S6 (switching element Q6) and the switching element S7 (switching element Q7) are on be τ1. FIG. 23(A) is a diagram for explaining the current flow during the period τ1. The current flow in FIG. 23(A) is the same as the current flow described in FIG. 22. However, FIG. 22 shows one half cycle of the switching period Tt, and FIG. 23(A) shows the current flow in the other half cycle of the switching period Tt.

[0097] During the period τ1, as described in FIG. 22, the output voltage Vo is applied to the secondary side of the transformer 11, and the added value (VL = Vin + Vo') of the value Vo' of the output voltage Vo converted to the primary side and the input voltage Vin is applied to the inductance means L. Therefore, the current value Itr of the transformer 11 can be increased, that is, the input current can be increased. [Supplement]<L The "value Vo' of the output voltage Vo converted to the primary side" is determined by the turns ratio (n1 / n2) of the transformer. Vo' = Vo × (n1 / n2) [Supplement End]

[0098] After the period τ1, the period during which the switching element S6 (switching element Q6) is on and the switching element S7 (switching element Q7) is off is defined as τ2. FIG. 23(B) is a diagram for explaining the current flow during the period τ2. During the period τ2, since the switch element Q7 is off, the output voltage Vo is not applied to the secondary side of the transformer 11, and only the input voltage Vin is applied to the inductance means L. According to the formula (1) of the basic operation 3, when increasing the input current, the period T3 during which the switch element Q7 is on is lengthened (the period τ1 is lengthened), so the period τ2 becomes shorter.

[0099] As a result of following the formula (1) of the basic operation 3, the period T3 may become longer than the period T2 during which the switching element Q6 is on. After the period τ1, the period during which the switching element S6 (switching element Q6) is off and the switching element S7 (switching element Q7) is on is defined as τ3. FIG. 23(C) is a diagram for explaining the current flow during the period τ3. FIG. 24 is a diagram for explaining the current waveforms flowing through each part (transformer and switch) of the converter 301. FIG. 24(A) shows the current waveform when the result according to the formula (1) is T2 = T3, and FIG. 24(B) explains the current waveform when the result according to the formula (1) is T2 < T3. Note that “T2’” is the calculated period of T2 obtained by the formula (1). Also, “T1max” is the period of T1 calculated by the formula (1), and is longer than T1 obtained by the formula (2) described later (T1 obtained by the formula (2) is shorter than T1max).

[0100] Even during period τ3, since the switch element Q6 is off, the output voltage Vo is not applied to the secondary side of the transformer 11, and only the input voltage Vin is applied to the inductance means L. For this reason, if period T3 is lengthened from the state in Figure 24(A) according to equation (1) of basic operation 3, the state in Figure 24(B) is reached. In other words, since period τ1 is not lengthened, as shown at point P03 in the figure, the current of the switch element Q6 decreases from T2 onward, so the rate of increase of the currents of the switch elements Q1 and Q4 decreases as shown at point P01 in the figure (although we want to increase the current as shown by the dotted line P02 in the figure, the actual current cannot follow the dotted line P02), and at the time when the switch element Q4 is turned off (the end time of T1, corresponding to time t4 explained in Figures 11 to 14), the currents of the switch elements Q1 and Q4 have not increased from the current values ​​in Figure 24(A) (see dashed line P12). Thus, it is not possible to increase the input current with control according to equation (1) of basic operation 3.

[0101] Therefore, the control circuit 3 makes a decision (step St2) and performs alternative control (step St4) as shown in Figure 25. The control circuit 3 is characterized in that, when performing low-input switching control (step St1), if the calculation result of formula (1) shows that period T3 is longer than period T2 ("No" in step St2), it performs the alternative control of formula (2) (step St4). On the other hand, if the calculation result of formula (1) shows that period T3 is shorter than period T2 ("Yes" in step St2), the control circuit 3 continues low-input switching control (step St3).

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[0102] In other words, the control circuit 3 ensures the current increase by setting T2 = T3 when T3 > T2 under control according to equation (1). Furthermore, the optimal value of T1 is set in the lower part of equation (2) to ensure the current value required for ZVS when the primary side Q1 and Q2 are ON, while not making the current value too large when they are OFF.

[0103] Specifically, a drive signal as shown in Figure 26 is applied to each switch. Figure 26(A) is the drive signal waveform when T3 > T2 occurs under control according to equation (1). Figure 26(B) is the drive signal waveform when control is performed according to equation (2).

[0104] Figure 27 illustrates the case where T2=T3 using alternative control. Figure 27(D) shows the timing chart (for half a cycle) of the drive signals that drive each switching element when T2=T3.

[0105] Let τ1 be the period during which both switching element S6 (switch element Q6) and switching element S7 (switch element Q7) are turned on. The current flow during period τ1 is the same as in Figure 23(A). Note that the change in the primary side current Itr during period τ1 is dItr / dt=(Vi+Vo') / L That is the case.

[0106] After period τ1, switching elements S6 (switch element Q6) and S7 (switch element Q7) turn off simultaneously. At this time, the current flow changes in the order of period τ4-1 and period τ4-2, finally reaching the state of period τ4-3. Periods τ4-1 and τ4-2 are very short periods.

[0107] Figure 27(A) is a diagram illustrating the current flow during period τ4-1. In the secondary circuit, charge is charged to capacitors C6, C7, and Cd, which are in parallel with the conducting switching elements Q6 and Q7, and charge is discharged from capacitors C5, C8, and Cc. The current that was flowing from the secondary side of transformer 11 is divided to the switching elements S5 and S6, so an equal current flows through each capacitor. The current flow in the primary circuit is the same as during period τ1. However, the change in the primary current Itr is dItr / dt≒(Vi+Vo') / L This is the result.

[0108] Figure 27(B) is a diagram illustrating the current flow during period τ4-2. This period is the time when the charging and discharging of capacitors C5, C6, Cc, and Cd continues after the charging and discharging of capacitors C7 and C8 in the secondary circuit is complete. The current path that flowed through capacitors C7 and C8 begins to flow through the antiparallel diode D8. The direction of the current Ia flowing to the output side changes. The current flow in the primary circuit is the same as during period τ1. However, the change in the primary current Itr is dItr / dt=Vi / L This is the result.

[0109] Figure 27(C) is a diagram illustrating the current flow during period τ4-3. This period is the time after the charging and discharging of capacitors C5, C6, Cc, and Cd in the secondary circuit is complete. The current that was flowing through capacitors C5, C6, Cc, and Cd begins to flow through the antiparallel diode D5. The current flow in the primary circuit is the same as during period τ1. However, the change in the primary current Itr is dItr / dt=(Vi-Vo') / L This is the result. The state during this period is the same as shown in Figure 6(C), and the subsequent operations will be the same as the basic operations 1-3 already explained.

[0110] Figure 28 illustrates the waveforms of the current flowing through each part (transformer and switch) of the converter 301. Figure 28(A) shows the current waveform when T2 = T3 according to equation (2), and Figure 28(B) shows the current waveform when T1 is adjusted according to equation (2).

[0111] As shown in Figure 28(A), when T2 = T3, the current flowing through switch elements Q1 and Q4 does not experience the decrease in the rate of increase of the current as explained in P01 in Figure 24(B). However, because T1 is not controlled, the current value at the end of the half-cycle is large (P05 in Figure 28(A)). The current value at P05 is the starting point of the next half-cycle, and a positive current value means that the next half-cycle starts with a negative current. Therefore, a large current value at P05 makes it difficult to increase both the primary and secondary winding currents. Thus, in this alternative control (equation (2)), the period of T1 is optimized to reduce the current value at the end of the half-cycle (P06 in Figure 28(B)). As a result, both the primary and secondary winding currents increase, and the currents of the switch elements Q1 and Q4 in Figure 28(B), i.e., the input current, can be increased from the current values ​​in Figure 24(A) (shown as P04 in Figure 28(B)).

[0112] (Other embodiments) In the electrical circuit of the present invention, a connection point refers to a part that is electrically connected and at the same potential, and not a point that is physically connected. Furthermore, the configuration, structure, number, arrangement, shape, material, etc., of each part of the converter and bidirectional converter of the present invention are not limited to the above specific examples, and those that are appropriately selected and adopted by those skilled in the art are also included in the scope of the present invention as long as they encompass the gist of the present invention.

[0113] More specifically, for example, elements exemplified by symbols as semiconductor elements are not limited to these specific electrical elements, but can be configured as a single electrical element or an electrical circuit including multiple electrical elements having similar functions or operations, and all such variations are included within the scope of the present invention. Similarly, the number and arrangement of each circuit element, including diodes, capacitors, and switching elements, as appropriately designed by those skilled in the art are also included within the scope of the present invention. [Explanation of Symbols]

[0114] Ter1: First terminal TER2: Second terminal Ter3: Third terminal Ter4: Terminal 4 1, 2: Switching circuits 3: Control circuit 11: Trans 12: First leg (First leg of switching circuit 1) 13: Second leg (Second leg of switching circuit 1) 24: Third leg (Second leg of switching circuit 2) 25: Fourth leg (first leg of switching circuit 2) 16, 17: Capacitors 18: Detection means for switching circuit 2 19: Detection means for switching circuit 1 S1~S4: Switching elements of switching circuit 1 Q1~Q4: Switching elements D1~D4: Antiparallel diodes C1~C4: Parallel capacitors D5~D8: Antiparallel diodes S5~S8: Switching elements of switching circuit 2 Q5~Q8: Switching element C5~C8: Parallel capacitors Ca: First capacitor of switching circuit 1 Cb: Second capacitor of switching circuit 1 Cc: The first capacitor in switching circuit 2 (sometimes described as the "third capacitor"). Cd: The second capacitor in switching circuit 2 (sometimes described as the "fourth capacitor"). L: Inductance means

Claims

[Claim 1] A transformer having a primary winding and a secondary winding, A switching element having a switching element in which an antiparallel diode and a parallel capacitor are connected in parallel, is connected in parallel to two terminals, forming an upper and lower arm, with a first leg and a second leg, respectively; a first capacitor connected in parallel to one of the switching elements on the upper or lower arm of the first or second leg, or to one of the switching elements on the upper or lower arm of the first and second legs; and a second capacitor connected in parallel to the other switching element on the upper or lower arm of the first and second legs, or to the other switching element on the upper or lower arm of the first and second legs; and two switching circuits connected to the primary winding side and the secondary winding side of the transformer, respectively. An inductance means is connected via the primary winding or the secondary winding on the primary winding side or the secondary winding between the connection point side of the upper and lower arms of the first leg and the connection point side of the upper and lower arms of the second leg of the transformer, A control circuit that performs switching control of the switching circuit and Equipped with, The switching control of the control circuit includes: This includes zero-volt switching control, energy transition switching control, and low-input switching control performed in conjunction with the energy transition switching control. The aforementioned zero-volt switching control is In the switching circuit described above, the switching element of the upper arm of the first or second leg and the switching element of the lower arm of the second or first leg are paired and alternately turned on and off to convert the DC input from the two terminals into AC and output from the switching circuit, and in controlling the alternate on and off of the paired switching elements, the switching element of the paired switching element of the upper arm of the first or second leg and the switching element of the lower arm of the second or first leg that is in the ON state is turned off first, the switching element to which the first capacitor or the second capacitor is connected in parallel, The aforementioned energy transition switching control is To cause the detected voltage, current, or power output from the two terminals of the other switching circuit or the detected voltage, current, or power input from the two terminals of one of the switching circuits to approach the target value, the switching elements of the second leg of the other switching circuit are forward-conducted so that the energy input from the two terminals of one of the switching circuits is stored in the inductance means during the period when the pair of switching elements in one of the switching circuits is ON, and the switching elements of the second leg of the other switching circuit that were forward-conducted are turned OFF before the switching elements of the one of the switching circuits that are turned OFF first are turned OFF, and The low-input switching control described above is When the detected voltage, current, or power input from the two terminals of one of the switching circuits falls below a certain standard, the switching element of the first leg of one of the switching circuits is turned on, and at the same time, the switching element of the upper arm or lower arm of the second leg and the switching element of the lower arm or upper arm of the first leg of the other switching circuit are turned on, and the switching element of the first leg is turned off before the switching element of the second leg of the other switching circuit is turned off. It is characterized by, The aforementioned control circuit is In the low-input switching control, the period T2 for turning on the switching element of the second leg of the other switching circuit is set by formula (1), and When performing the low-input switching control described above, if the calculation result of formula (1) shows that period T3 is longer than period T2, then perform the alternative control shown in formula (2). A converter characterized by the following. [Math 1] [Math 2] T1 is the period during which the switching element of the second leg of one of the switching circuits is turned on. Tt is the switching period in one of the switching circuits. T3 is the period during which the switching element of the first leg of the other switching circuit is turned on. Vin is the voltage input from the side between the two terminals of one of the switching circuits. Vo is the voltage output from the side between the two terminals of the other switching circuit. n1 and n2 are the number of turns of the primary winding and the secondary winding of the transformer, respectively. L is the inductance of the inductance means. x is any current value, That is the case.

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