Information processing device

Abstract

To provide an information processor capable of flexible accommodation by a mounting shape and a shape change.SOLUTION: An information processor includes a plurality of chips. The plurality of chips are accumulated in a horizontal direction. Each of the plurality of chips is formed with a transmission coil and a reception coil as one pair. Each of the plurality of chips executes radio communication between the chips using inductive coupling in the horizontal direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an information processing apparatus.

Background Art

[0002] A System-on-a-Chip (Soc) that mounts different blocks on a single chip is known. FIG. 2 of Patent Document 1 discloses a processor Soc.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] [Figure 1] Figure 1 is a diagram (part 1) showing an example of a horizontal wireless bus between chips. [Figure 2] Figure 2 is a diagram (part 2) showing an example of a horizontal wireless bus between chips. [Figure 3] Figure 3 is a diagram (part 3) showing an example of a horizontal wireless bus between chips. [Figure 4] Figure 4 shows an example of a case where wireless power transfer technology is used in combination. [Figure 5] Figure 5 is a diagram (part 1) illustrating the horizontal inductive coupling between coils. [Figure 6] Figure 6 is a diagram (part 2) illustrating the horizontal inductive coupling between coils. [Figure 7] Figure 7 shows an example of a transmitting and receiving core circuit. [Figure 8] Figure 8 shows an example of an operating waveform in a transmit / receive core circuit. [Figure 9] Figure 9 shows an example of a transceiver circuit configured on a chip. [Figure 10] Figure 10 shows an example of a transmitting coil and a receiving coil. [Figure 11] Figure 11 shows an example of an electromagnetic field simulation environment. [Figure 12] Figure 12 shows an example of the mutual inductance of a vertically elongated rectangular coil. [Figure 13] Figure 13 shows an example of the mutual inductance of a long, rectangular coil. [Figure 14] Figure 14 shows the simulation results when the relative angle between coils changes. [Figure 15] Figure 15 is a diagram illustrating the coil diameter and communication distance. [Figure 16] Figure 16 shows an example of a simulated waveform of the transmit / receive core circuit. [Figure 17] Figure 17 is a diagram showing the relationship between the coil diameter and the maximum transfer speed. [Figure 18] Figure 18 is a diagram showing a performance comparison between a conventional wired communication technology and a wireless bus technology. [Figure 19] Figure 19 is a diagram showing the influence of a ring-shaped wiring. [Figure 20] Figure 20 is a diagram showing the influence of a power ring. [Figure 21] Figure 21 is a diagram showing the influence of a seal ring. [Figure 22] Figure 22 is a diagram showing an example of a prototype board. [Figure 23] Figure 23 is a diagram showing an example of a measured eye pattern and a bathtub curve. [Figure 24] Figure 24 is a diagram showing an example of an electromagnetic field simulation environment. [Figure 25] Figure 25 is a diagram showing the relationship between the communication distance and the coupling coefficient. [Figure 26] Figure 26 is a diagram showing the relationship between the coil misalignment and the coupling coefficient. [Figure 27] Figure 27 is a diagram showing the coupling coefficient when a plurality of coils are arranged. [Figure 28] Figure 28 is a diagram for explaining the communication distance. [Figure 29] Figure 29 is a diagram showing an example of a simulation waveform of a transmission / reception core circuit. [Figure 30] Figure 30 is a diagram showing an example of a measured eye pattern and a bathtub curve.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Various characteristic matters shown in the embodiments described below can be combined with each other.

[0010] In this specification, "part" may include, for example, hardware resources implemented by circuits in a broad sense, and the information processing of software that can be specifically realized by these hardware resources. Furthermore, various types of information are handled in this embodiment, and these types of information are represented by high and low signal values ​​as a set of binary bits consisting of 0s and 1s, and communication and calculations can be performed on circuits in a broad sense.

[0011] Furthermore, a circuit in a broad sense is a circuit realized by combining at least a suitable combination of circuits (cIRCUIT), circuits (cIRCUITRY), processors (pROCESSOR), and memory (mEMORY). In other words, it includes application-specific integrated circuits (aPPLICATION sPECIFIC INTEGRATED cIRCUIT: ASIC), programmable logic devices (for example, simple programmable logic devices (sIMPLE pROGRAMMABLE lOGIC dEVICE: SPLD), complex programmable logic devices (cOMPLEX pROGRAMMABLE lOGIC dEVICE: CPLD), and field programmable gate arrays (fIELD pROGRAMMABLE gATE aRRAY: FPGA)).

[0012] <Embodiment 1> 1. Horizontal inter-chip wireless bus Figure 1 is a diagram (part 1) showing an example of a horizontal wireless bus between chips. Figure 2 is a diagram (part 2) showing an example of a horizontal wireless bus between chips. The information processing device 100 has multiple chips 110 A ~110 E It has multiple chips 110 A ~110 E These are integrated horizontally. Each of the multiple chips has a pair of transmitting and receiving coils. Multiple chips 110 A ~110 E Each of these uses horizontal inductive coupling to establish wireless connectivity between chips. As shown in Figure 1, an on-chip coil is formed using the chip's internal wiring. Furthermore, as shown in Figures 1 and 2, wireless connections between chips are achieved using horizontal inductive coupling. This configuration eliminates the need for setting up and manufacturing a silicon interposer, and allows for the inexpensive construction of the information processing device 100 by flexibly combining chiplets.

[0013] Figure 3 is a diagram (part 3) showing an example of a wireless bus between chips in the horizontal direction. As shown in Figure 3, the information processing device 100 can be implemented in various shapes. For example, it is possible to implement chips in a long, narrow arrangement resembling a fiber, to implement chips at an oblique angle to each other, and to implement a system whose shape deforms during operation. One of the multiple chips that make up the information processing device 100 is a CPU (Central Processing Unit). Another of the multiple chips that make up the information processing device 100 is memory. The information processing device 100 is not limited to these. The hardware that makes up the information processing device 100 may consist of one or more chips. For example, the CPU may be made up of at least two or more chips among the multiple chips that make up the information processing device 100. In other words, the chips that make up the information processing device 100 can be flexibly separated. The information processing device 100 does not necessarily have to include a CPU and memory.

[0014] Figure 4 shows an example of a case where wireless power transfer technology is used in combination. In the information processing device 100, by combining a horizontal wireless bus between chips and wireless power supply technology, chips can be mounted on a variety of substrates 400. Furthermore, chips can be easily replaced even after mounting. As shown in Figure 4, multiple chips are integrated horizontally on the substrate 400. Here, the substrate 400 is a variable-shape member. A variable-shape member is a member whose shape can be changed, such as a flexible substrate, plastic, or fiber. The information processing device 100 can be constructed simply by fixing and arranging chips on such a variable-shape member with something like DAF tape, and in the event of a failure or system update, it is only necessary to replace the chips and rearrange them, thus realizing a new information processing device 100.

[0015] 2. Horizontal inductive coupling between coils First, let's explain horizontal inductive coupling between on-chip coils. The degree of coupling between coils is mainly determined by the length of one adjacent side of the two coils and the distance between them. Therefore, the larger the coils and the shorter the distance between adjacent sides, the stronger the coupling. Through this inductive coupling, signals can be transmitted from the transmitting coil to the receiving coil. For example, as shown in Figure 5, when the transmit current Ix flows toward the back of the screen, a corresponding receive voltage Vrx is induced on the receiver side. The characteristics of this coil can be represented by the equivalent circuit shown in Figure 6. The receive voltage is the first derivative waveform of the transmit current Ix. This is the product of the second-order low-pass filter characteristics at the transmitting and receiving ends. Furthermore, the amplitude of the received voltage Vrx is proportional to the transmitted current and the coupling coefficient. Assuming a constant threshold for normal data recovery at the receiving end, if the coupling coefficient is halved, twice the current is required, which determines the power consumption of the transmitting circuit.

[0016] 3. Transceiver Core Circuit Next, the transmit / receive core circuit will be explained using Figures 7 and 8. Figures 7 and 8 are diagrams illustrating the transmit / receive core circuit configured on the chip. Here, two inverters drive the coils. A transmit current Ix flows to the coil in a direction corresponding to the input Txdata, and as a result, a pulse voltage corresponding to the data transition is generated on the receiving side, as shown in Figure 8. At this time, the polarity of the pulse differs depending on whether the data transition is from LOW to HIGH or from HIGH to LOW. The hysteresis comparator on the receiving side reconstructs this pulse voltage into the original NRZ data, and the final Rxdata is obtained as shown in Figure 8.

[0017] 4. Transceiver Circuit Figure 9 shows an example of a transmit / receive circuit configured on a chip. It employs a method of serializing and burst-transmitting parallel signals sent from the core. As shown in Figure 9, the transmit / receive circuit is equipped with a SerDes (SERializer / DESerializer) and a CDR circuit for connection with the digital circuit. The transmit / receive circuit is also equipped with a collision detection circuit. If a collision of transmitted data occurs between chips, the collision detection circuit retransmits the data according to the procedure defined in the higher-level protocol. The transmit coil 801 is a transmit coil, and the receive coil 802 is a receive coil. Figure 10 shows an example of a transmitting coil 801 and a receiving coil 802. In this embodiment, large coils measuring several millimeters square are used, resulting in an extremely large overall interface area. However, because the magnetic field emitted by the on-chip coil has little impact on the internal circuitry, the coils can be formed along the periphery where wiring resources are more abundant than within the core, as shown in Figure 10, and the core circuit, network interface, and transceiver circuits can be formed inside them. Considering the communication characteristics and typical design examples for square chips, the length of each side of the transmitting coil 801 and the receiving coil 802 is at least 90% of the length of each side of the chip. The opening area of ​​the transmitting coil and the opening area of ​​the receiving coil should ideally be 80% or more of the chip's area.

[0018] The transmitting coil 801 and the receiving coil 802 may be formed on different layers of the chip. Furthermore, the transmitting coil 801 and the receiving coil 802 may be formed at approximately the same location on multiple chips.

[0019] 5. Electromagnetic field simulation environment Figure 11 shows an example of an electromagnetic field simulation environment. Based on the manufacturing process parameters, simulation models of the coil and substrate were created, and the coupling coefficient between the coils was investigated using EmPro, a 3D electromagnetic field simulator from Keysight. The S-parameters obtained from the electromagnetic field simulation were fitted to the equivalent circuit, and the resulting coupling coefficient and mutual inductance were adopted as simulation results.

[0020] 6. Mutual inductance of rectangular coils Figures 12 and 13 show examples of the mutual inductance of rectangular coils. Figure 12 shows the change in mutual inductance when the side Dw perpendicular to the side closest to the adjacent coil of the transmitting coil is shortened. The results show that even when Dw is halved, the mutual inductance is 85% of that of a square coil, indicating that the mutual inductance decreases relatively slowly.

[0021] On the other hand, Figure 13 shows the change in mutual inductance when the side closest to the adjacent coil is shortened. As the side shortens, the mutual inductance decreases linearly, and when the side is halved, the mutual inductance is 49% of that of the square case.

[0022] The results revealed that coils couple even in the case of a rectangle, and that the mutual inductance changes depending on the shape. Since the side closest to an adjacent coil strongly contributes to coupling, the mutual inductance decreases linearly as this side becomes shorter. For example, using the case of a square coil as a baseline, to maintain a mutual inductance of 90% or more, the side perpendicular to the side closest to an adjacent coil (Dw) must be at least 60% of the length, and the side closest to an adjacent coil (Dh) must be at least 90% of the length.

[0023] 7. Relationship between relative angle and coupling coefficient Figure 14 shows the simulation results when the relative angle between the coils changes. As shown in Figure 14, the simulation confirmed that when the coils are at an angle, the coupling coefficient increases monotonically as the relative angle decreases. The results showed that even diagonally oriented coils do couple, but the coupling coefficient changes according to the relative angle. Considering the hysteresis comparator in the receiving circuit, its input voltage must be above the comparator threshold and not exceed the power supply voltage. For example, if the amplitude at the lowest signal amplitude, a relative angle of 180 degrees, is 100mV, then the received signal amplitude at a relative angle of 0 degrees will be 760mV. Assuming a core power supply voltage of around 1V, a typical design would be one where even the maximum voltage amplitude does not exceed the power supply voltage, and at the very least, a sufficient amplitude is ensured so that the signal is not buried in the noise floor.

[0024] 8. Circuit Simulation Circuit simulations were used to investigate the performance of the transmit / receive circuits and the impact of ring-shaped wiring on communication characteristics. A 45nm CMOS process was assumed for the manufacturing process, and coil diameters ranging from 100μm to 5mm were investigated in a square configuration. The communication distance was set to 1 / 10 of the coil diameter. Figure 15 illustrates the relationship between coil diameter and communication distance. For the coil and ring-shaped wiring sections, models were created from the results of electromagnetic field simulations and incorporated into the circuit simulation.

[0025] 9. Simulation waveform of the transmit / receive core circuit Figure 16 shows an example of a simulated waveform of the transmit / receive core circuit. Under the condition of a coil diameter of 300 μm, simulation of PRBS31 signal transfer achieved a maximum transfer speed of 14.3 Gb / s and a power consumption of 7.91 mW.

[0026] 10. Relationship between coil diameter and maximum transfer speed Figure 17 shows the relationship between coil diameter and maximum transfer speed. As the coil diameter decreases, the parasitic capacitance decreases, and therefore the maximum transfer speed improves. In the process of this embodiment, the communication speed is limited by the transmitting and receiving circuit, so the transfer speed does not improve with coils of 300 μm or less, but further performance improvements are expected when advanced processes are used. In other words, improvements in the performance of wireless bus technology can be expected through process miniaturization, finer grain size of each chiplet, and advances in mounting technology.

[0027] 11.Performance comparison Figure 18 shows a performance comparison between conventional wired communication technology and wireless bus technology. The three on the left are all high-speed communication technologies using silicon interposers. It can be seen that wireless bus technology can achieve results comparable to wired communication technology using silicon interposers in terms of both data transfer efficiency per interface area and power efficiency.

[0028] 12. Effects of ring-shaped wiring Figure 19 illustrates the effects of ring-shaped wiring. As shown in Figure 19, when ring-shaped wiring of the same size as a coil is present on a chip, eddy currents flow in the opposite direction when the transmit current flows through these ring-shaped wirings, which can adversely affect communication characteristics. Examples of such ring-shaped wiring include power supply rings for power distribution and sealing rings for chip protection.

[0029] 13. Effects of the power ring Figure 20 shows the effect of the power supply ring. When a power supply ring is present on the chip, the received signal amplitude decreases due to the effect of eddy currents. This effect can be mitigated to some extent by making the power supply ring thinner and increasing the distance between the coil and the power supply ring. For example, if the power supply ring is 20 μm thick and an amplitude of about 80% of that without the ring is obtained, the distance d between the coil and the ring needs to be 150 μm or more when the coil diameter is 1 mm.

[0030] 14. Influence of the seal ring Figure 21 shows the effect of the seal ring. Even when a seal ring is present on the chip, the received signal amplitude decreases due to the effect of eddy currents. This effect can be mitigated to some extent by making the seal ring thinner. For example, to obtain an amplitude of about 50% of that without the ring, the thickness of the seal ring needs to be 2 μm or less. On the other hand, even if a part of the seal ring is cut, if the length of the cut portion is sufficiently short, it can still function as a seal ring and prevent moisture penetration and crack propagation without problems. Simulations using a partially cut seal ring showed no effect on the received signal amplitude. Therefore, if possible in the process, using a divided seal ring can be considered as an option.

[0031] 15. Prototype circuit board Figure 22 shows an example of a prototype circuit board. To evaluate the wireless bus technology through actual measurements, a prototype circuit board was designed, fabricated, and measured. A high-speed hysteresis comparator IC was used as the receiving circuit to reconstruct the pulse waveform transmitted via the coil into an NRZ waveform.

[0032] 16.Measurement results Figure 23 shows an example of the measured eye pattern and bathtub curve. A maximum transfer speed of 2.6 Gbps was achieved under the condition that the BER was 10⁻¹² or less when the PRBS7 signal was applied. A sufficiently wide timing margin of 0.71 UI was obtained.

[0033] 17. Effects of Embodiment 1 According to Embodiment 1, it is possible to provide an information processing device that can flexibly adapt to changes in mounting shape and shape.

[0034] <Example 1> 1. Electromagnetic field simulation environment Figure 24 shows an example of an electromagnetic field simulation environment. Simulation models of the coil and substrate were created based on the parameters of the manufacturing process, and the coupling coefficient between the coils was investigated using Momentum, a 3D planar electromagnetic field simulator from Keysight.

[0035] 2. Relationship between communication distance and coupling coefficient Figure 25 shows the relationship between communication distance and coupling coefficient. As shown in Figure 25, the coupling coefficient k decreases monotonically as the communication distance X increases. In horizontal inductive coupling, when the coil diameter D is three times the communication distance X, the coupling coefficient is 0.023, which is less than 1 / 4 of the original value. Now, considering the case where the coil diameter is 5 mm and the communication distance is 800 μm, the coupling coefficient becomes 0.042. In other words, approximately 3.6 times the transmission current is required compared to conventional inductive coupling communication.

[0036] 3. Relationship between coil misalignment and coupling coefficient Figure 26 shows the relationship between coil misalignment and the coupling coefficient. It illustrates the change in the coupling coefficient k according to the misalignment dY under the condition that the coil diameter D is 12 times the communication distance X. Even when the coil diameter is misaligned by about 10%, the coupling coefficient only changes by 3%. For example, if the coil diameter is 5mm, even if the coil position is misaligned by 500μm, the transmission current only needs to be increased by 3%.

[0037] 4. Coupling coefficient when multiple coils are arranged. Figure 27 shows the coupling coefficients when multiple coils are arranged. As shown in Figure 27, the coupling coefficient between diagonally adjacent coils is approximately 20% of the coupling coefficient between coils adjacent in the vertical, horizontal, and vertical directions.

[0038] 5. Circuit Simulation A simulation of the transmit / receive core circuit was created, and power consumption and other factors were investigated. The manufacturing process assumed was a 45nm CMOS process, and the coil diameter was 5mm. The communication distance was assumed to be 0.8mm. Figure 28 is a diagram illustrating the communication distance.

[0039] 6. Simulation waveform of the transmit / receive core circuit Figure 29 shows an example of a simulated waveform of the transmit / receive core circuit. A voltage is generated in the receiving coil according to the transition of the input transmit data, and the original data is restored by the receiving circuit.

[0040] 7. Performance of the transmitting / receiving core circuit Figure 30 shows the eye pattern and bathtub curve when a 1.0 Gb / s PRBS-31 signal is input. BER=10 for the designed transmit / receive core circuit. -12 The timing margin was 0.68UI, confirming that it operates with sufficient margin. In addition, the power consumption of the transmit / receive core circuit was 11.1mW when the communication distance was 0.8mm and 6.41mW when it was 0.5mm.

[0041] The product may be provided in any of the following embodiments. The information processing apparatus wherein the plurality of chips are horizontally integrated on a substrate, and the substrate is a variable-shape member. The information processing device wherein the variable-shape member is a flexible substrate. The information processing device wherein the variable-shape member is made of plastic. The information processing device wherein the variable-shape member is a fiber. The information processing apparatus wherein the transmitting coil and the receiving coil are formed at substantially the same location on each of the plurality of chips. The information processing device wherein the transmitting coil and the receiving coil are formed on different layers of the chip. The information processing apparatus wherein the aperture area of ​​the transmitting coil and the aperture area of ​​the receiving coil are 80% or more of the area of ​​the chip. The information processing apparatus wherein a sealing ring is formed on each of the plurality of chips, and a part of the sealing ring is divided. The information processing apparatus wherein the thickness of the seal ring is 2 μm or less. The information processing apparatus wherein a power ring is formed on each of the plurality of chips, and when the coil diameter of the transmitting coil and the receiving coil is approximately 1 mm, the distance between the transmitting coil and the receiving coil and the power ring is 150 μm or more. The information processing device, wherein one of the plurality of chips is a CPU (Central Processing Unit). The information processing device wherein one of the plurality of chips is a memory. The information processing device wherein the hardware constituting the information processing device is composed of one or more chips from among the plurality of chips. The information processing device wherein the hardware is a CPU (Central Processing Unit). Of course, this is not always the case. Furthermore, the embodiments and modifications described above may be implemented in any combination.

[0042] Finally, various embodiments of the present invention have been described, but these are presented as examples only and are not intended to limit the scope of the invention. Novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. Embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0043] 100: Information Processing Device 110A: Tip 110B: Chip 110C: Chip 110D: Chip 110E: Chip 400: Base material 801: Transmitting coil 802: Receiving coil

Claims

1. A chip with a coil formed on it, At least one of the core circuit, network interface, and transmitting / receiving circuit is formed inside the coil. The coil is at least one of a transmitting coil and a receiving coil. Wireless connection is achieved by utilizing inductive coupling between a coil formed on another horizontally arranged chip and the coil, and the relative angle between the coil formed on the other chip and the coil is configured to be oblique or variable. The coil diameter of the aforementioned coil is longer than the communication distance of the wireless connection.

2. A chip on which a coil is formed, At least one of the core circuit, network interface, and transmitting / receiving circuit is formed inside the coil. The coil is at least one of a transmitting coil and a receiving coil. Wireless connection is made by utilizing inductive coupling between a coil formed on another chip arranged horizontally and the coil, and the coil formed on the other chip is arranged so as to be offset perpendicular to the direction of arrangement of the coil while maintaining a constant communication distance with the coil. The coil diameter of the aforementioned coil is longer than the communication distance of the wireless connection.

3. A chip on which a coil is formed, At least one of the core circuit, network interface, and transmitting / receiving circuit is formed inside the coil. Having the aforementioned transmitting and receiving circuit, The aforementioned transmitting and receiving circuit is equipped with a collision detection circuit. The transmitting and receiving circuit is formed inside the coil, The coil is at least one of a transmitting coil and a receiving coil. Wireless connection is achieved by utilizing the inductive coupling that occurs between the coil formed on other horizontally arranged chips and the coil in question. The coil diameter of the aforementioned coil is longer than the communication distance of the wireless connection.

4. In the chip according to claim 3, If a data collision occurs with the aforementioned other chip, the collision detection circuit retransmits the data.

5. A chip on which a coil is formed, At least one of the core circuit, network interface, and transmitting / receiving circuit is formed inside the coil. The coil is at least one of a transmitting coil and a receiving coil. Wireless connection is achieved by utilizing the inductive coupling that occurs between the coil formed on other horizontally arranged chips and the coil in question. The coil diameter of the aforementioned coil is longer than the communication distance of the wireless connection. The coil has a sealing ring on the outside, The coil has a power ring inside, A chip in which the distance between the coil and the seal ring is shorter than the distance between the coil and the power supply ring.

6. In the chip according to any one of claims 2 to 5, The aforementioned coil is a chip that is arranged so as to be adjacent to the other coils formed on the same plane in an oblique direction.

7. In the chip according to any one of claims 1 to 5, The aforementioned coil is a chip formed using internal wiring.

8. In the chip according to claim 7, Having the transmitting coil and the receiving coil, The transmitting coil and the receiving coil are chips formed on different layers of the chip.

9. In the chip according to any one of claims 1 to 5, The circuit comprises the core circuit and the transmitting / receiving circuit. The aforementioned transmitting and receiving circuit is a chip that serializes and burst-transmits the parallel signals sent from the core circuit.

10. In the chip according to claim 9, The aforementioned transmitting and receiving circuit is a chip having an H-Bridge, SerDes, or CDR circuit.

11. In the chip according to any one of claims 1 to 5, The aforementioned transmitting and receiving circuit is a chip having an inverter or a hysteresis comparator.

12. An information processing device, The device has multiple chips on which coils are formed, and each chip has at least one of the following formed inside the coil: a core circuit, a network interface, and a transmit / receive circuit. The coil is at least one of a transmitting coil and a receiving coil. The coil diameter of the aforementioned coil is longer than the communication distance of the wireless connection. The wireless connection is made by utilizing the inductive coupling that occurs between coils formed on each of the multiple chips arranged horizontally. Having a substrate on which a plurality of the aforementioned chips are provided, The aforementioned substrate is a variable-shape member, and the information processing apparatus is a data processing device.

13. An information processing device, The device has multiple chips on which coils are formed, and each chip has at least one of the following formed inside the coil: a core circuit, a network interface, and a transmit / receive circuit. The coil is at least one of a transmitting coil and a receiving coil. The coil diameter of the aforementioned coil is longer than the communication distance of the wireless connection. The wireless connection is made by utilizing the inductive coupling that occurs between coils formed on each of the multiple chips arranged horizontally. The relative angle between the coil formed on the chip that performs the wireless connection using inductive coupling is configured to be oblique or variable. An information processing device in which multiple chips extend horizontally.

14. A method for providing multiple chips on which coils are formed on a substrate, The chip has at least one of the following formed inside the coil: a core circuit, a network interface, and a transmit / receive circuit. The coil is at least one of a transmitting coil and a receiving coil. Wireless connection is achieved by utilizing the inductive coupling that occurs between the coil formed on other horizontally arranged chips and the coil in question. The coil diameter of the aforementioned coil is longer than the communication distance of the wireless connection. A method for providing a plurality of chips on a substrate such that the relative angle between the coils formed on the other chips and the coils is configured to be oblique or variable.

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