Semiconductor structure and method for manufacturing a semiconductor structure (positioning of source / drain contacts under a power rail)
The semiconductor structure with a gate cut region and dielectric core addresses short circuit issues by precisely positioning S/D contacts, ensuring robust connections to power rails, thus improving transistor performance in advanced integrated circuits.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2022-09-22
- Publication Date
- 2026-07-29
AI Technical Summary
Enlarged source/drain (S/D) contacts in semiconductor devices can cause short circuits due to lithography misalignment errors, particularly when connecting to power rails, leading to weak junctions with vias and increased risk of electrical faults.
A semiconductor structure with a gate cut region featuring a liner and dielectric core is used to precisely position S/D contacts, ensuring self-alignment and isolation, reducing the risk of short circuits by using selective etching to form contacts that connect accurately to power rails.
The solution provides precise S/D contact positioning, enhancing electrical connectivity while minimizing short circuits and ensuring robust connections to power rails, even in the deep submicron and nanometer regimes.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention generally relates to the field of semiconductor device manufacturing, and more particularly to the manufacture of semiconductor structures with accurate and consistent positions for source / drain contacts.
Background Art
[0002] The manufacture of advanced integrated circuits generally involves forming a large number of circuit elements within a chip area. Metal-oxide-semiconductor field-effect transistors (MOSFETs or FETs) are typical of one important type of circuit element that is widely used in these advanced integrated circuits. An FET generally includes a source / drain region, a channel region positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Semiconductor nanosheets are considered a viable option for reducing the gate length within semiconductor devices. Vertically stacked semiconductor nanosheets can provide area efficiency and an increased drive current within a given layout.
Summary of the Invention
Problems to be Solved by the Invention
[0003] Enlarged S / D contacts may narrow the space between the tips of the contacts at the cell boundary, which can cause a short circuit between the tips of the contacts with lithography misalignment errors.
Means for Solving the Problems
[0004] One aspect of one embodiment of the present invention includes a semiconductor structure that reduces short circuits between contacts. The semiconductor structure may comprise a liner and a gate-cut region having a dielectric core confined within a first side surface and a second side surface of the liner. The semiconductor structure may also comprise a first source / drain (S / D) contact overlapping the first side surface and the dielectric core. The first S / D may have a line end in contact with the second side surface of the liner.
[0005] A part of one embodiment of the present invention includes a method for manufacturing a semiconductor structure. The method may include the steps of: forming a gate cut; lining the gate cut with a liner having a first side and a second side; forming a dielectric core between the first side and the second side; cutting a source / drain contact region into the first side so as to at least partially enter the dielectric core; selectively etching the dielectric core in the second side so as to cleanly remove the dielectric core from the liner; and forming a source / drain contact within the source / drain contact region, wherein the line end of the contact is in contact with the second side.
[0006] An embodiment of one invention includes a semiconductor structure in which a first source / drain (S / D) contact is electrically connected between the first source / drain (S / D) and a power rail. The semiconductor structure may also include a second S / D contact electrically connected between the second S / D and a signal rail, and a gate cut region between the first S / D contact and the second S / D contact. The gate cut region may include a liner and a dielectric core. [Brief explanation of the drawing]
[0007] [Figure 1A] This figure shows a top view of the semiconductor structure 100, and illustrates the semiconductor structure 100 in one manufacturing stage of a processing method according to one embodiment of the present invention. [Figure 1B]Figure 1A shows a cross-sectional side view at the position indicated, illustrating a semiconductor structure 100 in one manufacturing stage of a processing method according to one embodiment of the present invention. [Figure 1C] Figure 1A shows a cross-sectional side view at the position indicated, illustrating a semiconductor structure 100 in one manufacturing stage of a processing method according to one embodiment of the present invention. [Figure 1D] Figure 1A shows a cross-sectional side view at the position indicated, illustrating a semiconductor structure 100 in one manufacturing stage of a processing method according to one embodiment of the present invention.
[0008] [Figure 2A] This figure shows a top view of the semiconductor structure 100, and is a diagram of the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 2B] Figure 2A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 2C] Figure 2A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 2D] Figure 2A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention.
[0009] [Figure 3A] This figure shows a top view of the semiconductor structure 100, and is a diagram of the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 3B] Figure 3A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 3C] Figure 3A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 3D] Figure 3A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention.
[0010] [Figure 4A] This figure shows a top view of the semiconductor structure 100, and is a diagram of the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 4B] Figure 4A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 4C] Figure 4A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 4D] Figure 4A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention.
[0011] [Figure 5A] This figure shows a top view of the semiconductor structure 100, and is a diagram of the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 5B] Figure 5A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 5C] Figure 5A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 5D] Figure 5A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention.
[0012] [Figure 6A]A top view of the semiconductor structure 100, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 6B] A cross-sectional side view at the position shown in FIG. 6A, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 6C] A cross-sectional side view at the position shown in FIG. 6A, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 6D] A cross-sectional side view at the position shown in FIG. 6A, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention.
[0013] [Figure 7A] A top view of the semiconductor structure 100, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 7B] A cross-sectional side view at the position shown in FIG. 7A, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 7C] A cross-sectional side view at the position shown in FIG. 7A, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 7D] A cross-sectional side view at the position shown in FIG. 7A, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention.
[0014] [Figure 8A] A top view of the semiconductor structure 100, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 8B] A cross-sectional side view at the position shown in FIG. 8A, showing the semiconductor structure 100 at the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 8C] Figure 8A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Figure 8D] Figure 8A shows a cross-sectional side view at the position indicated, illustrating the semiconductor structure 100 in the next manufacturing stage of the processing method according to one embodiment of the present invention. [Modes for carrying out the invention]
[0015] The following detailed description refers to the accompanying drawings, which illustrate specific examples of embodiments of the present invention. These embodiments are described in sufficient detail to enable those skilled in the art to carry them out, and it should be understood that other embodiments may be utilized, and that structural, logical, and electrical modifications may be made without departing from the embodiments described. Therefore, the following detailed description should not be construed as limiting, and the embodiments included are defined by the appended claims.
[0016] In the context of the manufacture of transistors and integrated circuits, the primary plane refers to a plane of a semiconductor layer on which multiple transistors are manufactured, for example, in a planar process, within and near it. In this specification, terms such as “above,” “below,” “under,” and “over,” which imply a vertical direction, mean substantially perpendicular to the primary plane, while terms such as “laterally,” “adjacent,” and “beside,” which imply a horizontal direction, mean substantially parallel to the primary plane. Generally, the primary plane is a plane of a single-crystal silicon layer that aligns with the plane on which transistor elements are manufactured.
[0017] As the cell height and metal pitch scale at the backend (BEOL) decrease, epitaxy of the source / drain wiring from the element to the power rail becomes more difficult. Enlarged source / drain (S / D) contacts require a robust connection from the via to the S / D contact below the power rail. However, enlarged S / D contacts can reduce the space between the contact tips at the cell boundary, which can lead to short circuits between the contact tips, accompanied by lithographic mismatch errors. This invention teaches a unique method and structure for precisely controlling the S / D contact position below the power rail region (region at the cell boundary) to ensure a good connection from the S / D contact to the via without short circuits between the contact tips.
[0018] Improvements in transistor design have made it possible for feature sizes to fall into the deep submicron and nanometer regimes. However, as feature sizes become smaller, problems that would normally be minor can have a more detrimental effect on the operation of the transistor. For example, if the dimensions of semiconductor components such as source / drain (S / D) contacts are not perfectly matched in the design and manufacture of the semiconductor device, short circuits (i.e., unintended electrical flows) can occur, and the junction with vias can become weak. This can be a particularly difficult problem for S / D contacts connected to power rail vias, because power rail vias may be located closer to adjacent signal vias than the proximity of signal vias themselves. Accordingly, embodiments disclosed herein provide a gate cut region having a liner and a dielectric core that provides self-alignment during the formation of the S / D contacts and isolation during the operation of the S / D contacts connected to the power rails.
[0019] Referring here to the drawings, Figures 1A, 1B, 1C, and 1D show a semiconductor structure 100 in one manufacturing stage of a processing method according to one embodiment of the present invention. Although the illustrated embodiment shows the semiconductor structure 100 as a nanosheet element, in certain embodiments the semiconductor structure 100 described below may be used to connect the source / drain and power rail in various types of transistors, including FinFETs, nanowires, or prana transistors. Figure 1A shows a top view of the semiconductor structure 100, and Figures 1B, 1C, and 1D show cross-sectional side views at the positions shown in Figure 1A. That is, Figure 1B is a diagram at line BB, Figure 1C is a diagram at line CC, and Figure 1D is a diagram at line DD. Figure 1A does not show all features but is included mainly to show a lattice pattern of rows of active nanosheets 102 and columns of high-k metal gate (HKMG) 104 structures.
[0020] As shown in the side views (1B, 1C, 1D), the nanosheets 102 and HKMG 104 are formed alternately and continuously on the substrate 108 as a vertical layer stack 106. The stack 106 is separated from each other in the x-direction 110 by source / drain (S / D) 114 and in the y-direction 112 by shallow trench isolation (STI) 116. The stack 106 also includes internal spacers 118 to insulate the nanosheets 102 from each other and to insulate the S / D 114 from the HKMG 104. Furthermore, in the region above the S / D 114, the semiconductor structure 100 includes an interlayer insulating film (ILD) 120 and spacers 122 to separate the conductive structure from the semiconducting structure. The nanosheets 102, HKMG 104, S / D 114 and spacers 118, 122 can be formed by known deposition, patterning, and etching methods. For example, nanosheet 102 can be formed by using a nanosheet patterning process after epitaxial growth, and S / D114 can be formed by in-situ doped epitaxial growth or by ion implantation. S / D114 can be n-type doped or p-type doped (i.e., PFET source / drain or NFET source / drain).
[0021] The substrate 108 may comprise a single-crystal silicon structure having shallow trench isolation (STI) 116. Alternatively, the substrate 108 may comprise a starting wafer having a semiconductor-on insulator (SOI) substrate, which does not require STI. The nanosheet 102 may be composed of a semiconductor material such as silicon (Si). HKMG 104 may include a material having a relatively higher dielectric constant than silicon oxide (SiOx), such as hafnium oxide. The number of layers of nanosheet 102 and HKMG 104 may differ from the number shown in the typical embodiment (more or fewer layers).
[0022] Figures 2A, 2B, 2C, and 2D show a semiconductor structure 100 in the next manufacturing stage of a processing method according to one embodiment of the present invention. Figure 2A shows a top view of the semiconductor structure 100, and Figures 2B, 2C, and 2D show cross-sectional side views at the positions shown in Figure 2A. These drawings show gate cuts 130 that can be formed using reactive ion etching (RIE). Gate cuts 130 located at cell boundaries (i.e., between NFETs or between PFETs) are etched between stacks 106 so that the nanosheets 102, internal spacers 118, and S / D 114 are unaffected. However, gate cuts 130 cut into HKMG 104 outside stacks 106, and also into ILD 120, spacers 122, and optionally into STI 116 or through it to reach substrate 108. The gate cut 130 can be about 25 to 70 nanometers, or generally about 30 nanometers in the y direction 112, but in the x direction, the gate cut 130 may, in some cases, extend through all of the rows of HKMG 104 in the semiconductor structure 100.
[0023] Furthermore, the semiconductor structure 100 is narrower in the y-direction 112 (e.g., 10 to 22 nm, or about 18 nanometers) and includes a narrow gate cut 132 that is significantly shorter in the x-direction 110. Specifically, as shown in Figure 2A, the narrow gate cut 132 is located within a complementary metal oxide semiconductor (CMOS) cell (between the NFET and PFET) and etches only one or a few rows of HKMG 104, rather than forming a long trench line (or all rows of HKMG 104) that is etched by the gate cut 130. The gate cuts 132 and 130 can be formed together by any well-known lithography and etching process.
[0024] Figures 3A, 3B, 3C, and 3D show a semiconductor structure 100 in the next manufacturing stage of a processing method according to one embodiment of the present invention. Figure 3A shows a top view of the semiconductor structure 100, and Figures 3B, 3C, and 3D show cross-sectional side views at the position shown in Figure 3A. These drawings show a liner 134 lining the gate cut 130. The liner 134 is formed using a blanket deposition process, and the exposed surfaces of the semiconductor structure 100 are lined with the liner 134. These exposed surfaces include the semiconductor structure 100, the gate cut 130, and the top surface 140 of the narrow gate cut 132. The liner 134 includes a first side surface 136 and a second side surface 138 within the gate cut 130. However, within the narrow gate cut 132, the liner 134 connects from the side so that the narrow gate cut 132 is completely filled with the material of the liner 134. The material of the first liner is different from that of the ILD layer 120. For example, liner 134 may contain SiN, SiOC, SiC, SiBCN, SiOCN, AlOx, AlNx, etc. The thickness range of liner 134 is from 5 nm to 15 nm.
[0025] Figures 4A, 4B, 4C, and 4D show a semiconductor structure 100 in the next manufacturing stage of a processing method according to one embodiment of the present invention. Figure 4A shows a top view of the semiconductor structure 100, and Figures 4B, 4C, and 4D show cross-sectional side views at the position shown in Figure 4A. These drawings show a dielectric core 142 confined between a first side surface 136 and a second side surface 138 within a gate cut 130. The dielectric core 142 may be formed as a blanket structure of which etch-back or chemimetric planarization (CMP) is performed after dielectric deposition. The liner 134 may also be planarized so that the top surface 140, including HKMG 104 and ILD 120, is exposed. The liner material may be the same or similar material as ILD 120, such as SiO2. The liner 134 and dielectric core 142 work together to isolate the first stack 106a from the second stack 106b and form a gate cut region 144 that allows for precise S / D contact positioning between the element having the first stack 106a and the power rail, as will be described in detail below.
[0026] Figures 5A, 5B, 5C, and 5D show a semiconductor structure 100 in the next manufacturing stage of a processing method according to one embodiment of the present invention. Figure 5A shows a top view of the semiconductor structure 100, and Figures 5B, 5C, and 5D show cross-sectional side views at the location shown in Figure 5A. These drawings show that after further ILD 120 deposition, a source / drain (S / D) contact region 146 is etched over the S / D 114, and ultimately the S / D contact region 146 will electrically connect the S / D 114 to a higher level circuit using vias. A first S / D contact region 146a is cut into the first side 136 so as to at least partially enter the dielectric core 142 of the gate cut region 144. The S / D contact region 146 can be formed / cut using a non-selective etching process such as RIE that etches the oxide of the ILD 120 and the liner 134.
[0027] Figures 6A, 6B, 6C, and 6D show a semiconductor structure 100 in the next manufacturing stage of a processing method according to one embodiment of the present invention. Figure 6A shows a top view of the semiconductor structure 100, and Figures 6B, 6C, and 6D show cross-sectional side views at the positions shown in Figure 6A. These drawings show selective isotropic etching of the dielectric core 142 with respect to the liner 134. In this specification, the expression “selective” with respect to a material removal process (e.g., etching) means that, if the etchant is appropriately selected, the material removal rate (i.e., etching rate) for the material under consideration is higher than the removal rate for at least other materials subjected to the material removal process. The etching process used to selectively etch the dielectric core 142 may include DHF or SiConi, which do not etch the liner 134, which may be made of SiN. Therefore, in the cleanup region 148 surrounding the S / D contact region 146, the dielectric core 142 is removed until the liner 134, spacer 118, and S / D 114 are exposed without any covering from the dielectric core 142 or ILD 120. This selective etching stop on the liner 134 means that the initial portion of the S / D contact region 146 does not need to be that precise, because as long as the initial cut of the S / D contact 146 includes the dielectric core 142, the S / D contact region 146 will be precisely extended to the liner 134 by lateral dielectric etching. This selective etching means that the lateral edge of the S / D contact region will always end at the second side surface 138 of the liner 134. Furthermore, as shown in Figure 6D, the bottom edge of the cleanup region 148 is etched into the dielectric core 142 and ILD 120, which are lower than the top edge of the first side surface 136.
[0028] Figures 7A, 7B, 7C, and 7D show a semiconductor structure 100 in the next manufacturing stage of a processing method according to one embodiment of the present invention. Figure 7A shows a top view of the semiconductor structure 100, and Figures 7B, 7C, and 7D show cross-sectional side views at the position shown in Figure 7A. These drawings show a source / drain (S / D) contact 150 formed within the S / D contact region 146. The S / D contact 150 comprises a first S / D contact 150a having a line end 152 that contacts a second side surface 138 of the liner 134. The first S / D contact 150a is formed within the dielectric core 142 and ILD 120 such that the bottom edge of the first S / D contact 150a is lower than the top edge of the first side surface 136. Thus, the first S / D contact 150a overlaps laterally with the first side surface 136 and the dielectric core 142. Furthermore, the semiconductor structure 100 includes a second S / D contact 150b located on the opposite side of the first S / D contact 150a of the liner 134. The metal of the contact may include silicide liners (e.g., Ti, Ni, NiPt), adhesive metal liners such as TiN, and conductive metal fillers such as Co, W, Ru. After metal deposition, a chemical mechanical planarization (CMP) process is performed to remove excess metal and ILD on the top surface of the gate.
[0029] Figures 8A, 8B, 8C, and 8D show a semiconductor structure 100 in the next manufacturing stage of a processing method according to one embodiment of the present invention. Figure 8A shows a top view of the semiconductor structure 100, and Figures 8B, 8C, and 8D show cross-sectional side views at the location shown in Figure 8A. These drawings show via levels 160 and a first metal level 170 connecting the S / D contact 150 to the next metal level (not shown) of the semiconductor structure 100. The via level 160 includes (i) a signal via 162 coupled between the S / D contact 150 and a signal rail 172 in the first metal level 170, and (ii) a power rail via 164 coupled between the first S / D contact 150a and a power rail 174 in the first metal level 170. The metal layer dielectric 180 surrounds the vias 162, 164 and rails 172, 174, thereby keeping the vias 162, 164 and rails 172, 174 in an insulated state. The metal layer dielectric 180, vias 162, 164, and rails 172, 174 can be formed using well-known deposition, patterning, and etching techniques. For example, the metal layer dielectric 180 can be formed first, then holes for the vias 162, 164 can be formed and filled with a conductive material such as metal. Similar steps may be employed to form the rails 172, 174. Alternatively, both the vias and metal lines can be formed first, and then the metallization can be formed together using a Cu dual damascene process.
[0030] Advantages of the disclosed embodiment include the precise positioning of the first S / D contact 150a, specifically the line end 152. That is, the line end 152 is positioned such that the first S / D contact 150a has a strong electrical connection with the power rail via 164, but is not too close to short-circuit the second S / D contact 150b. The liner 134 can also define minimal insulation between the contacts 150a and 150b, so by carefully selecting the material or thickness of the liner 134, it is possible to prevent faults such as short circuits, failures, or leaks. In embodiments without the liner 134, lithographic mismatch may cause the line end 152 to shift too close to the second S / D contact 150b, resulting in a short circuit, or the line end 152 may shift too far from the second S / D contact 150b, resulting in the power rail via 164 being connected to only a portion of the first S / D contact 150a.
[0031] The method described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer either as bare dies in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chips are mounted in a single chip package (e.g., a plastic holder with leads secured to a motherboard or other higher-level holder) or in a multi-chip package (e.g., a ceramic holder with surface interconnects, embedded interconnects, or both). In either case, the chips can be integrated with other chips, individual circuit elements, or other signal processing devices, or a combination thereof, as part of an intermediate or final product.
[0032] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be comprehensive or limitless. Those skilled in the art will see many modifications and variations that do not deviate from the scope and spirit of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, the practical applications of the technologies found in the market or technical improvements thereto, or to enable other those skilled in the art to understand the embodiments disclosed herein.
Claims
1. A semiconductor structure that reduces short circuits between contacts, This is a gate cut region, Raina, and Dielectric core confined within the first side surface and the second side surface of the liner A gate cut region having, A first source / drain (S / D) contact overlapping the first side surface and the dielectric core, wherein the first S / D contact has a line end that contacts the second side surface of the liner. A semiconductor structure comprising the features described above.
2. The semiconductor structure according to claim 1, wherein the first S / D contact is electrically connected between the first source / drain and the power rail via.
3. The semiconductor structure according to claim 2, wherein the first source / drain includes one selected from the group consisting of PFETs and NFETs.
4. The semiconductor structure according to any one of claims 1 to 3, wherein the liner comprises an etching-selective liner material resistant to diluted hydrofluoric acid (DHF), and the dielectric core comprises a core material etched by DHF.
5. The semiconductor structure according to any one of claims 1 to 3, comprising a second source / drain contact electrically connected between a second source / drain and a signal rail, wherein the second source / drain contact is located on the liner opposite to the first S / D contact.
6. The semiconductor structure according to any one of claims 1 to 3, wherein the vertical dimension of the gate cut region extends from the shallow trench isolation to the top surface of the first S / D contact.
7. The semiconductor structure according to any one of claims 1 to 3, wherein the gate cut region is located at a cell boundary selected from the group consisting of the boundary between two NFETs and the boundary between two PFETs.
8. A semiconductor structure according to any one of claims 1 to 3, comprising a narrow gate cut region located at the boundary between a PFET and an NFET.
9. The semiconductor structure according to any one of claims 1 to 3, wherein the bottom end of the first S / D contact is lower than the top end of the first side surface.
10. A method for manufacturing a semiconductor structure, The stage of forming the gate cut, A step of lining the gate cut with a liner having a first side and a second side, The steps include forming a dielectric core between the first side surface and the second side surface, The steps include cutting the source / drain contact region so as to enter at least partially into the first side surface and the dielectric core, A step of selectively etching the dielectric core so as to cleanly remove the dielectric core from the liner on the second side, The step of forming a source / drain contact within the source / drain contact region, wherein the line end of the source / drain contact comes into contact with the second side surface. A method for providing this.
11. The method according to claim 10, comprising the step of forming a plurality of nanosheet transistor stacks, wherein the gate cut is formed between a first nanosheet transistor stack and a second nanosheet transistor stack.
12. The method according to claim 10 or 11, further comprising the step of forming a source / drain, wherein the source / drain contact is formed to be electrically connected to the source / drain.
13. The method according to claim 10 or 11, wherein the step of selectively etching the dielectric core includes a step of etching the bottom edge of a cleanup region which is lower than the top edge of the first side surface.
14. The method according to claim 10 or 11, wherein the gate cut is located at a cell boundary selected from the group consisting of (i) the boundary between two NFETs and (ii) the boundary between two PFETs.
15. A first source / drain (S / D) contact is electrically connected between the first source / drain (S / D) and the power rail, A second S / D contact is electrically connected between the second S / D and the signal rail, A gate cut region between the first S / D contact and the second S / D contact, the gate cut region having a liner and a dielectric core Equipped with, The first S / D contact contacts the dielectric core in the gate cut region. Semiconductor structure.
16. The semiconductor structure according to claim 15, comprising an interlayer insulating film (ILD) between the gate cut region and the second S / D contact.
17. The semiconductor structure according to claim 15 or 16, wherein the first S / D includes one selected from the group consisting of PFETs and NFETs.
18. The semiconductor structure according to claim 15 or 16, wherein the liner comprises a liner material resistant to diluted hydrofluoric acid (DHF), and the dielectric core comprises a core material etchable by DHF.
19. The semiconductor structure according to claim 15 or 16, comprising a narrow gate cut region located at the boundary between a PFET and an NFET.
20. The semiconductor structure according to claim 15 or 16, wherein the gate cut region is located at a cell boundary selected from the group consisting of the boundary between two NFETs and the boundary between two PFETs.