Phase-locked loop pulse truncation

Abstract

The phase-locked loop includes a pulse limiter between the phase frequency detector and the charge pump. The phase frequency detector generates and transmits a clock pulse to the pulse limiter. The pulse limiter generates a first signal indicating that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer select signal that selects one of a plurality of buffers in the pulse limiter. The pulse limiter generates a second signal indicating a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period associated with the pulse limiter buffer select signal. The pulse limiter truncates the clock pulse to the truncated pulse width and transmits the truncated clock pulse to the charge pump.

Description

Technical Field

[0001] The present invention generally relates to an electronic system including a processing unit such as a processor and an integrated circuit (IC), and more particularly to a phase-locked loop (PLL) that truncates pulses received from a PLL phase frequency detector.

Background Art

[0002] In one aspect of the present invention, a method for truncating phase-locked loop pulses is presented. The method includes receiving, in a pulse limiter circuit, a delay buffer selection indicating a delay period. The method further includes receiving, in the pulse limiter circuit, a pulse from a phase frequency detector. The method further includes determining, in the pulse limiter circuit, whether the width of the received pulse is greater than the minimum pulse width of the phase frequency detector plus the delay period. The method further includes truncating, in the pulse limiter circuit, the pulse. The method further includes transmitting, in the pulse limiter circuit, the truncated pulse to a charge pump.

Summary of the Invention

[0003] In another aspect of the present invention, a phase-locked loop is presented. The phase-locked loop includes a phase frequency detector adapted to generate a clock pulse and transmit it to a pulse limiter. The pulse limiter is adapted to generate a first signal indicating that the clock pulse is greater than the minimum pulse width of the phase frequency detector. The pulse limiter is adapted to receive a pulse limiter buffer selection signal that selects one of a plurality of buffers within the pulse limiter. The pulse limiter is adapted to generate a second signal indicating the truncated pulse width as the minimum pulse width of the phase frequency detector plus the delay period associated with the pulse limiter buffer selection signal. The pulse limiter is adapted to truncate the clock pulse to the truncated pulse width. The pulse limiter is further adapted to transmit the truncated clock pulse to a charge pump.

[0004] In another aspect of the present invention, a phase-locked loop is presented. The phase-locked loop includes a first delay element that receives an UP_PRE clock pulse from a phase frequency detector and a second delay element that receives a DWN_PRE clock pulse. The phase-locked loop includes an XOR gate that receives the UP_PRE and DWN_PRE clock pulses and generates an XOR output indicating whether the UP_PRE or DWN_PRE clock pulse is greater than the minimum pulse width of the phase frequency detector. The phase-locked loop includes a plurality of delay buffers electrically connected in series with the XOR gate. The phase-locked loop includes a multiplexer that outputs a delay stage signal indicating the truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period associated with a delay buffer selection signal that identifies one of the plurality of delay buffers. The phase-locked loop includes a first AND gate electrically connected to the first delay element that outputs a truncated UP clock pulse containing the truncated pulse width to a charge pump. The phase-locked loop includes a second AND gate that is electrically connected to a second delay element and outputs a truncated DWN clock pulse, including the truncated pulse width, to the charge pump.

[0005] The above and other embodiments, features, aspects and advantages will be better understood by referring to the following description, amended claims and accompanying drawings. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram illustrating a phase-locked loop including a pulse limiter according to one or more embodiments. [Figure 2] This is a block logic diagram illustrating a pulse limiter according to one or more embodiments. [Figure 3] This is a block logic diagram illustrating the features of a pulse limiter according to one or more embodiments. [Figure 4]This is a waveform diagram of a reference clock signal received by a phase-locked loop and a feedback clock signal from the phase-locked loop, according to one or more embodiments. [Figure 5] This is the waveform response of a phase-locked loop without a pulse limiter, as described according to one or more embodiments. [Figure 6] This is the waveform response of a phase-locked loop including a pulse limiter, as described according to one or more embodiments. [Figure 7] This is a block diagram illustrating a phase-locked loop pulse truncation method according to one or more embodiments.

[0007] Following common practice, various features illustrated in the drawings may not be drawn to scale. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Furthermore, some parts of the drawings may not depict all components of a given system, method, or apparatus. Finally, similar reference figures may be used throughout this specification and the drawings to indicate similar features. [Modes for carrying out the invention]

[0008] Computer processing units often obtain their clock source from an external crystal oscillator chip. Errors related to the oscillator clock signal can affect the reliability of the processing unit itself, the reliability of the higher-level computer system that uses the processing unit, or both. Therefore, these computer processing units attempt to synchronize, filter, or minimize the impact of errors on the oscillator clock signal, or a combination of these, which may include phase-locked loops. Ultimately, this error can lead to computer system failure, potentially requiring a restart. Recovery from such disasters, such as downtime, can be time-consuming and costly if it negatively impacts related operations. Therefore, redundant clock switches (RCSs) are sometimes provided. An RCS provides the processing unit with a reference clock output. Initially, the reference clock is generated from a first oscillator clock signal. If the RCS detects an error related to the first oscillator clock signal, the RCS generates a reference clock output from a second redundant oscillator clock signal. This can reduce or avoid disasters caused by oscillator clock signal errors.

[0009] A typical RCS (Radio Controlled System) includes two independent clock sources and a circuit to align and switch between them. If the independent clock sources are not perfectly aligned, this switching event can introduce unwanted jitter into the phase-locked loop, potentially leading to further errors. Known RCSs include complex analog circuitry to align the two clock sources within 312.5 ps. Due to the 312.5 ps uncertainty in clock phase, the phase-locked loop must be configured in a low-gain operating environment to counteract the 312.5 ps transient noise or jitter that may occur, for example, during switching. However, this is not ideal, as phase-locked loops configured for low gain are generally susceptible to noise. Therefore, a noise-responsive phase-locked loop that does not need to be configured for a low-gain operating environment is required.

[0010] Numerous details are described herein to provide a complete understanding of the exemplary embodiments illustrated in the accompanying drawings. However, some embodiments may be carried out without many of the specific details, and the claims are limited only by the features and aspects specifically described in the claims. Furthermore, well-known methods, components, circuits, etc., are not described in comprehensive detail so as not to unnecessarily obscure more suitable embodiments of those described herein.

[0011] Figure 1 shows a block diagram of a phase-locked loop (PLL) 100 according to an embodiment of the present invention, which may include a phase frequency detector 102, a pulse limiter 104, a charge pump 106, a loop filter 108, a voltage-controlled oscillator (VCO) 110, or a feedback frequency divider 112, or a combination thereof. The phase frequency detector 102 is electrically connected to the pulse limiter 104. The pulse limiter 104 is electrically connected to the charge pump 106. The charge pump 106 is electrically connected to the loop filter 108. The loop filter 108 is electrically connected to the VCO 110. The VCO 110 is electrically connected to the feedback frequency divider 112. The feedback frequency divider 112 is electrically connected to the phase frequency detector 102.

[0012] The phase frequency detector 102 compares the phase and frequency of the reference clock signal 16 with the phase and frequency of the feedback clock signal 14 from the feedback frequency divider 112. The phase frequency detector 102 generates an output including an UP_PRE pulse 19 and a DWN_PRE pulse 20. The UP_PRE pulse 19 is sometimes also called an increment (INC) pulse. Similarly, the DWN_PRE pulse 20 is sometimes called a decrement (DEC) pulse.

[0013] The UP_PRE pulse 19 and DWN_PRE pulse 20 represent the phase difference and frequency difference between the reference clock signal 16 and the feedback clock signal 14. If the phase of the feedback clock signal 14 lags behind the phase of the reference clock signal 16, the pulse width of the UP_PRE pulse 19 is set wider than the pulse width of the DWN_PRE pulse 20. If the phase of the feedback clock signal 14 leads the phase of the reference clock signal 16, the pulse width of the DWN_PRE pulse 20 is set wider than the pulse width of the UP_PRE pulse 19. If the phase of the feedback clock signal 14 is approximately equal to the phase of the reference clock signal 16, the pulse width of the DWN_PRE pulse 20 is approximately equal to the pulse width of the UP_PRE pulse 19. In this case, the pulse widths of both the UP_PRE pulse 19 and the DWN_PRE pulse 20 are defined as the "minimum pulse width" generated by the phase frequency detector 102.

[0014] The pulse limiter 104 may reduce, limit, or otherwise truncate the UP_PRE pulse 19 and DWN_PRE pulse 20 generated by the phase frequency detector 102. The pulse limiter 104 generates an output including the UP pulse 21 and the DWN pulse 22. The UP pulse 21 is sometimes called the INC pulse, etc. Similarly, the DWN pulse 22 is sometimes called the DEC pulse, etc.

[0015] When the pulse limiter 104 truncates the UP_PRE pulse 19 and the DWN_PRE pulse 20, the PLL 100 has a response to transient noise that is filtered, limited, suppressed, or throttled, and therefore reduces the PLL gain. The truncation by the pulse limiter 104 can be disabled by a truncation enable signal 29 or a lock signal 30 or both to the AND gate 114. That is, truncation by the pulse limiter 104 occurs when both the truncation enable signal 29 and the lock signal 30 indicate that truncation will occur (for example, when the truncation enable signal 29 is high "1" and the lock signal 30 is high "1"). The truncation enable signal 29 may be generated by a wideband register(s) or latch(s), which may be controlled outside the phase-locked loop 100. The lock signal 30 may be generated by a known lock detector, which is built into the phase-locked loop 100 and indicates that the PLL 100 is locked. The AND gate 114 generates an enable signal 31 indicating whether or not truncation will occur.

[0016] The truncation by the pulse limiter 104 can be configured based on the selection of delay elements, as indicated by the delay selection signal 32 (i.e., the pulse widths of the truncated UP signal 21 and the truncated DWN signal 22 may be indicated). The delay selection signal 32 indicates the amount or number of delay elements in the pulse limiter 104 to which the UP_XOR_DWN signal 207 is delayed, as illustrated in Figure 2.

[0017] Truncation may be disabled when PLL100 is converged to a locked state and enabled when PLL100 is locked. This allows for normal gain operation when PLL100 is converged and low gain (i.e., truncated) operation (e.g., allowing transient noise to pass through) when PLL100 is locked. In other words, the UP pulse 21 or the DWN pulse 22 or both may not be truncated with respect to the UP_PRE pulse 19 and DWN_PRE pulse 20, respectively, while PLL100 is converged to a locked state (for example, the pulse width of UP_PRE pulse 19 is approximately equal to the pulse width of UP pulse 21, or the pulse width of DWN_PRE pulse 20 is approximately equal to the pulse width of DWN pulse 22, or both). Similarly, UP pulse 21, DWN pulse 22, or both may be truncated with respect to UP_PRE pulse 19 and DWN_PRE pulse 20 when PLL 100 is locked (for example, if the pulse width of UP_PRE pulse 19 is wider than the pulse width of UP pulse 21, or if the pulse width of DWN_PRE pulse 20 is wider than the pulse width of DWN pulse 22, or both).

[0018] In this embodiment, the pulse limiter 104 includes a single block or a single set of delay elements for truncating the UP_PRE pulse 19 and the DWN_PRE pulse 20, and a combinational logic element 250 for propagating the minimum phase pulse width of the phase frequency detector 102. The single block or a single set of delay elements may truncate both the UP_PRE pulse 19 and the DWN_PRE pulse 20, but other known truncation systems may include dedicated subsystems for independently truncating the INC pulse and the DEC pulse, respectively. Thus, the single block or a single set of delay elements of the pulse limiter 104 can reduce the size of a known truncation system by half.

[0019] Furthermore, the propagation of the minimum phase pulse width of the phase frequency detector 102 by the pulse limiter 104 may reduce the number of delay elements by a further 2N (where N is the number of delay elements in the phase frequency detector 102) compared to the prior art phase-locked loop. In the phase-locked loop 100, the combinational logic elements 250 may ensure that the minimum pulse width of the phase frequency detector 102 is not truncated, thereby reducing the overall number of delay elements. More specifically, the XOR gate 206 that generates UP_XOR_DWN207 and the NAND gate 200 that generates the non-truncated signal 201 may ensure that the minimum pulse width of the phase frequency detector 102 is not truncated. If both the UP_PRE pulse 19 and the DWN_PRE pulse 20 are true, high, "1", etc., truncation may not occur, as indicated by the XOR gate 206. Thus, both the UP_PRE pulse 19 and the DWN_PRE pulse 20 are high during the minimum pulse width of the phase frequency detector 102. In general, all phase frequency detectors have a minimum pulse width to ensure that the charge pump is actively stimulated. In prior art phase-locked loops, the pulse limiter circuit typically truncates the entire INC pulse or DEC pulse that contains the minimum pulse width portion. To counteract this, prior art phase-locked loops include at least N delay elements, which are replicas of the N delay elements in the phase frequency detector (which generate the minimum pulse width). In this way, the pulse limiting circuit of the prior art phase-locked loop ensures that the minimum pulse width of the phase frequency detector propagates as is (delay elements in the phase frequency detector = delay elements in the pulse limiter). Next, prior art phase-locked loops typically include an additional M delay elements to truncate anything exceeding the minimum pulse width. A total of N+M delay elements are given. To truncate both INC and DEC pulses, prior art phase-locked loops typically double the number of such delay elements (N+M).

[0020] Transistor mismatch can also be eliminated by using a single block or a single set of delay elements in the pulse limiter 104. Prior art phase-locked loops typically include a dedicated INC pulse limiter block and another dedicated DEC pulse limiter block. In this configuration, due to physical manufacturing, there may be transistor mismatch between the two identical blocks. The time delay across the delay elements differs between the two blocks, which may result in the INC pulse being truncated more than the DEC pulse, or vice versa, even with the same pulse width setting. The UP and DWN signals going to the charge pump typically need to have their falling edges aligned, and having two separate limiter blocks makes such alignment difficult, further exacerbating transistor mismatch. Herein, the phase-locked loop 100 uses a single group of delay elements 260 to truncate both the UP and DWN pulses, thereby reducing or eliminating such transistor mismatch.

[0021] The UP pulse 21 and DWN pulse 22 are sent to the charge pump 106. The UP pulse 21 or DWN pulse 22 controls the charge pump 106 to source or sink the FILT-in signal 23 and the inverted FILTN-in signal 24 to or from the loop filter 108. Based on the amount and direction (i.e., source or sink) of the FILT-in signal 23 and the FILTN-in signal 24, the loop filter 108 produces the controlled FILT-out signal 25 and the controlled inverted FILTN-out signal 26.

[0022] The FILT out signal 25 and the FILTN out signal 26 control the VCO 110 to produce an output VCO out signal 27 that tracks the reference clock signal 16 (i.e., the VCO_out signal 27 tracks the phase and frequency of the reference clock signal 16). Generally, the PLL circuit 100 is said to be "locked" when the VCO out signal 27 tracks the phase and frequency of the reference clock signal 16. Due to process mismatches and circuit performance, even when the PLL 100 is locked, there may be a small difference between the phase of the VCO out signal 27 and the phase of the reference clock signal 16.

[0023] In some embodiments, the VCO out signal 27 is the feedback clock signal 14 (i.e., the PLL 100 does not include a feedback divider 112). In other embodiments, the feedback divider 112 may divide the VCO out signal 27 to generate the feedback clock signal 14.

[0024] FIG. 2 is a block logic diagram illustrating a pulse limiter 104 according to one or more embodiments. The pulse limiter 104 may include a serial buffer for propagating the minimum phase pulse width of the phase frequency detector 102 and a single block 260 of a combinational logic element 250.

[0025] To achieve proper or sufficient timing in the combinational logic element 250, the UP_PRE pulse 19 may be sent through the buffer 202 to create an UP delay pulse 203, and the DWN_PRE pulse 20 may be sent through the buffer 204 to generate a DWN delay pulse 205.

[0026] One of the combinational logic elements 250 may be an XOR gate 206. The XOR gate 206 may generate an UP_XOR_DWN signal 207. The UP_XOR_DWN signal 207 may be used whenever the phase frequency detector 102 generates a pulse larger than the minimum pulse width or for illustrative purposes in any example.

[0027] The UP_XOR_DWN signal 207 may be transmitted through N selectable delay buffers, as indicated by the delay selection signal 32, to indicate the selected multiplexer from among several possibility multiplexers for the multiplexer output signal (e.g., signals 235, 237, 239, 241, 243, etc.) selected as the delayed delay stage signal 245. The delayed delay stage signal 245 is used to indicate that the pulse is greater than the desired pulse width, as indicated by the delay selection <0:5> delay selection signal 32. In the example depicted, the pulse limiter 104 includes delay buffers 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, and 232, and multiplexers 234, 236, 238, 240, 242, and 244.

[0028] In the illustrative description, the XOR gate 206 may be electrically connected in series with buffer 212. The XOR gate 206 may send the UP_XOR_DWN signal 207 to buffer 212, which delays the UP_XOR_DWN signal 207 and generates a first-stage buffer output signal 213. Buffer 212 may be electrically connected in series with buffer 214. Buffer 212 may send the first-stage buffer output signal 213 to buffer 214, which delays this received signal and generates a second-stage buffer output signal 215. Buffer 214 may be electrically connected in series with buffer 216. Buffer 214 may send the second-stage buffer output signal 215 to buffer 216, which delays this received signal and generates a third-stage buffer output signal 217. Buffer 216 may be electrically connected in series with buffer 218. Buffer 216 may transmit a third-stage buffer output signal 217 to buffer 218, which delays this received signal to generate a fourth-stage buffer output signal 219. Buffer 218 may be electrically connected in series with buffer 220. Buffer 218 may transmit a fourth-stage buffer output signal 219 to buffer 220, which delays this received signal to generate a fifth-stage buffer output signal 221.

[0029] In a further illustrative description, buffer 220 may be electrically connected in series with buffer 222. Buffer 220 may transmit the fifth-stage buffer output signal 221 to buffer 222, which delays this received signal to generate the sixth-stage buffer output signal 223. Buffer 220 may also be electrically connected in parallel with multiplexer 234. Buffer 220 may transmit the fifth-stage buffer output signal 221 to multiplexer 234. Buffer 222 may be electrically connected in series with buffer 224. Buffer 222 may transmit the sixth-stage buffer output signal 223 to buffer 224, which delays this received signal to generate the seventh-stage buffer output signal 225. Buffer 222 may also be electrically connected in parallel with multiplexer 234. Buffer 222 may transmit the sixth-stage buffer output signal 223 to multiplexer 234. Delayed selection signal <0> Immediately after receiving the signal, the multiplexer 234 outputs either the received fifth-stage buffer output signal 221 or the sixth-stage buffer output signal 223 to the multiplexer 236 as the multiplexer output signal 235.

[0030] In a further illustrative description, buffer 224 may be electrically connected in series with buffer 226. Buffer 224 may transmit the seventh-stage buffer output signal 225 to buffer 226, which delays this received signal to generate the eighth-stage buffer output signal 227. Buffer 224 may also be electrically connected in parallel with multiplexer 236. Buffer 224 may transmit the seventh-stage buffer output signal 225 to multiplexer 236. Delayed selection signal <1> Immediately after receiving the signal, the multiplexer 236 outputs either the received multiplexer output signal 235 or the 7th stage buffer output signal 225 to the multiplexer 238 as the multiplexer output signal 237.

[0031] In the illustrative description, buffer 226 may be electrically connected in series with buffer 228. Buffer 226 may transmit the eighth-stage buffer output signal 227 to buffer 228, which delays this received signal to generate the ninth-stage buffer output signal 229. Buffer 226 may also be electrically connected in parallel with multiplexer 238. Buffer 226 may transmit the eighth-stage buffer output signal 227 to multiplexer 238. Delayed selection signal <2> Immediately after receiving the signal, the multiplexer 238 outputs either the received multiplexer output signal 237 or the 8th stage buffer output signal 227 to the multiplexer 240 as the multiplexer output signal 239.

[0032] In the illustrative description, buffer 228 may be electrically connected in series with buffer 230. Buffer 228 may transmit the ninth-stage buffer output signal 229 to buffer 230, which delays this received signal to generate the tenth-stage buffer output signal 231. Buffer 228 may also be electrically connected in parallel with multiplexer 240. Buffer 228 may transmit the ninth-stage buffer output signal 229 to multiplexer 240. Delayed selection signal <3> Immediately after receiving the signal, the multiplexer 240 outputs either the received multiplexer output signal 239 or the 9th stage buffer output signal 229 to the multiplexer 242 as the multiplexer output signal 241.

[0033] In the illustrative description, buffer 230 may be electrically connected in series with buffer 232. Buffer 230 may transmit the tenth-stage buffer output signal 231 to buffer 232, which delays this received signal to generate the eleventh-stage buffer output signal 233. Buffer 230 may also be electrically connected in parallel with multiplexer 242. Buffer 230 may transmit the tenth-stage buffer output signal 231 to multiplexer 242. Delayed selection signal <4> Immediately after receiving the signal, the multiplexer 242 outputs either the received multiplexer output signal 241 or the 10th-stage buffer output signal 231 to the multiplexer 244 as the multiplexer output signal 243.

[0034] Furthermore, in the illustrative description, buffer 232 may be electrically connected in parallel to multiplexer 244. Buffer 232 may transmit the 11th stage buffer output signal 233 to multiplexer 244. Delay selection signal <5> Immediately after receiving the signal, the multiplexer 244 outputs either the received multiplexer output signal 243 or the 11th stage buffer output signal 233 as a delayed stage signal 245.

[0035] Another combinational logic element 250 may be a NAND gate 200. The NAND gate 200 may NAND a delayed delay stage signal 245, an enable signal 31, and an UP_XOR_DWN signal 207 to generate a non-truncated signal 201.

[0036] Furthermore, other combinational logic elements 250 may be AND gates 208 and 210. The AND gate 208 may logically AND the non-truncate signal 201 and the UP delay pulse 203 to generate the UP pulse 21. Similarly, the AND gate 210 may logically AND the non-truncate signal 201 and the DWN delay pulse 205 to generate the DWN pulse 22.

[0037] In the illustrative description, the pulse limiter 104 truncates both the UP_PRE pulse 19 and the DWN_PRE pulse 20 when the following three criteria are met: (1) the enable signal 31 indicates that truncation is valid. For example, the enable signal 31 is true, high, "1", etc.; (2) either the UP_PRE pulse 19 or the DWN_PRE pulse 20 is true, high, "1", etc. for a time greater than the number of delay elements in one or more delay buffers 280, but not both. For example, the phase frequency detector 102 outputs either the UP_PRE pulse 19 or the DWN_PRE pulse 20 or both, which are wider than the minimum pulse width; and (3) either the UP delay pulse 203 or the DWN delay pulse 205 becomes true, high, "1", etc. before both the UP_PRE pulse 19 and the DWN_PRE pulse 20 become true, high, "1", etc. For example, the UP_PRE pulse 19 or the DWN_PRE pulse 20, or both, is greater than or wider than the minimum pulse with the delay associated with a selected buffer in a single block 260 or a series of delay elements.

[0038] For clarity, the pulse limiter 104 allows for the truncation of both the UP_PRE pulse 19 and the DWN_PRE pulse 20 with a single block 260 or a series of delay elements or buffers (e.g., buffers 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, or 232 or a combination thereof), as opposed to a dedicated block or series of delay elements for truncating the INC pulse and another dedicated block or series of delay elements for truncating the DWN pulse. This not only reduces the total number of delay elements required for the phase-locked loop but also eliminates concerns about transistor mismatch for the UP and DWN truncation signals.

[0039] For further clarity, a single block 260 or a series of delay elements may include one or more delay buffers 270 that are not individually selectable by the delay selection signal 32, and one or more delay buffers 280 that are individually selectable by the delay selection signal 32.

[0040] For further clarity, the pulse limiter 104, in its advantage, allows the minimum pulse width of the phase frequency detector 102 to propagate through the circuit without being truncated, enabling proper charging within the loop filter 108.

[0041] Figure 3 is a block logic diagram illustrating the features of a pulse limiter 104 according to one or more embodiments. In some embodiments, the pulse limiter 104 may further include latches 331 and 333. Latch 331 may determine and indicate whether the UP_PRE pulse 19 has been truncated, and latch 333 may determine and indicate whether the DWN_PRE pulse 20 has been truncated. Latches 331 and 333 can effectively identify which signal, when, or both, or when the UP_PRE pulse 19, the DWN_PRE pulse 20, or both, have been truncated.

[0042] The pulse limiter 104 may further include an inverting buffer 300 and an inverting buffer 310. The inverting buffer 300 may be electrically connected to the NAND gate 200, receive and delay the non-truncate signal 201, and then logically invert the non-truncate signal 201 to a truncate signal 301. The inverting buffer 310 may be electrically connected to the AND gate 114, receive and delay the enable signal 31, and then logically invert the enable signal 31 to a not-enable signal 311.

[0043] Latch 331 may be electrically connected to an inverting buffer 300 and receive a truncation signal 301 from it. Latch 331 may also be electrically connected to an inverting buffer 310 and receive a not_enable signal 311 from it. Latch 331 may also be electrically connected to a phase frequency detector 102 and receive an UP_PRE pulse 19 from it. Latch 331 may be clocked by the rising edge of the truncation signal 301, and the data input may be the UP_PRE pulse 19. Thus, the data input may be latched when the truncation signal 301 is true, high, "1", etc. As a result, the output UP_WAS_TRUNCATED signal 320 reflects that the UP_PRE pulse 19 has been truncated. The UP_WAS_TRUNCATED signal 320 can be used by an external component, for example, to determine whether the phase-locked loop 100 should speed up or slow down.

[0044] Similarly, latch 333 may be electrically connected to an inverting buffer 300 from which it receives a truncation signal 301. Latch 333 may also be electrically connected to an inverting buffer 310 from which it receives a not_enable signal 311. Latch 333 may also be electrically connected to a phase frequency detector 102 from which it receives a DWN_PRE pulse 20. Latch 333 may be clocked by the rising edge of the truncation signal 301, and the data input may be the DWN_PRE pulse 20. Thus, the data input may be latched when the truncation signal 301 is true, high, "1", etc. As a result, the output DWN_WAS_TRUNCATED signal 322 reflects that the DWN_PRE pulse 20 has been truncated. The DWN_WAS_TRUNCATED signal 322 can be used by external components, for example, to determine whether the phase-locked loop 100 should be increased or decreased in speed.

[0045] Figure 4 is an exemplary frequency diagram of a reference clock signal 16 and a feedback clock signal 14 from a phase-locked loop in one or more embodiments. This frequency diagram depicts the response of the exemplary phase-locked loop 100 to a reference clock signal 16 pulse extension of 1 nanosecond per cycle. Such an event may be, for example, a switchover event. Region 400 defines the time domain of the waveform response of the exemplary phase-locked loop 100 depicted in Figure 5.

[0046] Figure 5 shows an exemplary waveform response of the phase-locked loop 100, where the truncation enable signal 29 is logically set to false, low, "0", etc., indicating that truncation is disabled. The phase-locked loop 100 responds to a 1 nanosecond pulse extension of the reference clock signal 16 with a 1 nanosecond DWN_PRE pulse 20 (i.e., arrow 402) and a 40 picosecond (e.g., the minimum pulse width of the phase frequency detector 102) UP_PRE pulse 19 (i.e., arrow 404). This large DWN_PRE pulse 20 results in an exemplary 280 mV control voltage shift of the voltage-controlled oscillator 110 and an exemplary 1 MHz (1%) change in the feedback clock 14 frequency. Known downstream clock and data recovery circuits are unlikely to be able to track a 1% instantaneous change in the feedback clock 14 frequency, and cyclic redundancy check (CRC) is likely to be required.

[0047] Figure 6 shows an exemplary waveform response of the phase-locked loop 100, where the truncation enable signal 29 is logically set to true, high, "1", etc., indicating that truncation is enabled. In the exemplary waveform response, the pulse limiter 104 is configured to tap from the fifth buffer 220 (i.e., the fifth-stage buffer output signal 221 is selected by the delay selection signal 32 to become the delayed-stage signal 245) corresponding to the corresponding delay (e.g., a delay of about 50 picoseconds). Thus, the pulse limiter 104 is configured to truncate any UP_PRE pulse 19 width or any DWN_PRE pulse 20 that is greater than the set corresponding delay plus the minimum pulse width of the phase frequency detector 102. The corresponding delay may be the intended pulse width of the truncated UP pulse 21 and the truncated DWN pulse 22. Therefore, in the described example, the pulse limiter 104 is configured to truncate the UP_PRE pulse 19 width or the DWN_PRE pulse 20 if it is greater than 90 picoseconds (i.e., the set corresponding delay of 50 picoseconds plus the minimum pulse width of the phase frequency detector 102 of 40 picoseconds).

[0048] The DEC_PRE pulse 20 (arrow 402) represents the DEC_PRE pulse 20 output of the phase frequency detector 102, and the DWN pulse 22 (arrow 502) represents the truncated output from the pulse limiter 104. The 1 nanosecond DEC_PRE pulse 20 from the phase frequency detector 102 is transmitted to the pulse limiter 104, and the resulting DWN pulse 22 (arrow 502) is reduced to 50 nanoseconds. Note that the minimum pulse width of the phase frequency detector 102, which is 40 picoseconds, may also propagate through the phase-locked loop 100 as is (e.g., 40 picoseconds). By truncating the DEC_PRE pulse 20 and UP_PRE pulse 19 with the pulse limiter 104 in this manner, the control voltage shift of the voltage-controlled oscillator 110 can be reduced by 27mV (e.g., by several orders of magnitude), which can exemplify a 7kHz or 0.007% change in the feedback clock frequency 14 (e.g., a change of several orders of magnitude).

[0049] Figure 7 is a block diagram illustrating a phase-locked loop pulse truncation method 600 according to one or more embodiments. The method 600 may be utilized by a phase-locked loop 100 including a pulse limiter 104, and may be initiated in block 602. The method 600 may be continued by the phase frequency detector 102 generating and transmitting an UP_PRE pulse 19 or a DWN_PRE pulse 20 or both to the pulse limiter 104, and the pulse limiter 104 receiving the transmitted UP_PRE pulse 19 or the transmitted DWN_PRE pulse 20 or both (block 604).

[0050] Method 600 may continue by determining whether truncation is enabled (block 606). For example, truncation may be enabled by an enable signal 31 indicating that truncation is enabled. The enable signal 31 may indicate that truncation is disabled when the PLL 100 is in a locked state, and enabled when the PLL 100 is locked.

[0051] Method 600 may continue if truncation is disabled (block 608) by having the pulse limiter 104 transmit the received UP_PRE pulse 19 or the received DWN_PRE pulse 20 or both to the charge pump 106. Alternatively, if truncation is enabled, Method 600 may continue by having the pulse limiter 104 determine whether the width of the received UP_PRE pulse 19 or the width of the received DWN_PRE pulse 20 or both is greater than a pre-specified delay period plus the minimum pulse width of the phase frequency detector 102 (block 612). The pre-specified delay period may be associated with a specific delay buffer selected from a single block 260 associated with the delay selection signal 32 or one or more delay buffers 280 of a series of delay elements.

[0052] If the width of the received UP_PRE pulse 19 or the width of the received DWN_PRE pulse 20, or both, is less than or equal to the value obtained by adding the minimum pulse width of the phase frequency detector 102 to the pre-specified delay period, method 600 may return to block 608 and continue. Alternatively, if the width of the received UP_PRE pulse 19 or the width of the received DWN_PRE pulse 20, or both, is greater than the value obtained by adding the minimum pulse width of the phase frequency detector 102 to the pre-specified delay period, method 600 may return to block 608 and continue. 20 The method may continue by truncating the width of the pulses, or both, to a width obtained by adding the minimum pulse width of the phase frequency detector 102 to a pre-specified delay period, or to a width related thereto, thereby generating a truncated UP pulse 21 or a truncated DWN pulse 22 or both, respectively (block 614). The method may continue by the pulse limiter 104 sending the truncated UP pulse 21 or a truncated DWN pulse 22 or both to the charge pump 106 (block 616), or it may end in block 618.

[0053] The flowcharts and block diagrams in the figures illustrate the configuration, functionality, and operation of executable implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction. In some alternative embodiments, the functions shown in the blocks may differ from the order shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or the blocks may be executed in reverse order depending on the functions they relate to.

[0054] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or to limit the disclosed embodiments. It will be apparent to those skilled in the art that many modifications and changes are possible without departing from the scope and spirit of the invention. The terms used herein have been selected to best describe the principles of the embodiments, their practical application to market-based technologies or technical improvements, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. A pulse limiter circuit receives a delay buffer selection indicating a delay period, The pulse limiter circuit receives pulses from the phase frequency detector, The pulse limiter circuit determines whether the width of the received pulse is greater than the minimum pulse width of the phase frequency detector plus the delay period, The pulse limiter circuit discards the pulse, The pulse limiter circuit transmits the truncated pulses to the charge pump, Includes, The aforementioned delay buffer selection involves selecting a delay buffer from a single set of delay buffers. The single set of delay buffers includes a plurality of non-selectable delay buffers and a plurality of selectable delay buffers, Each of the delay buffers in the aforementioned single series of delay buffers is electrically connected in series. The XOR gate is electrically connected in series with the first non-selectable delay buffer of the single set of delay buffers. A method for truncating phase-locked loop pulses.

2. A phase frequency detector is included which generates a clock pulse and is adapted to transmit the clock pulse to a pulse limiter, The pulse limiter is adapted to generate a first signal indicating that the clock pulse is greater than the minimum pulse width of the phase frequency detector, to receive a pulse limiter buffer selection signal to select one of a plurality of buffers in the pulse limiter, to generate a second signal indicating the truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period associated with the pulse limiter buffer selection signal, to truncate the clock pulse to the truncated pulse width, and to transmit the truncated clock pulse to a charge pump. The aforementioned multiple buffers are electrically connected in series. The aforementioned plurality of buffers include a plurality of non-selectable buffers and a plurality of selectable buffers, The pulse limiter includes an XOR gate electrically connected in series with a first unselectable buffer. Phase-locked loop.

3. The pulse limiter described above is A first latch determines and stores an UP truncation signal indicating that the truncated clock pulse is a truncated UP clock pulse. Further including, The phase-locked loop according to claim 2.

4. The pulse limiter described above is A second latch determines and stores a DWM truncation signal indicating that the truncated clock pulse is a truncated DWM clock pulse. including, The phase-locked loop according to claim 3.

5. A first delay element that receives an UP_PRE clock pulse from a phase frequency detector, and a second delay element that receives a DWN_PRE clock pulse from the phase frequency detector, An XOR gate that receives the UP_PRE clock pulse and the DWN_PRE clock pulse and generates an XOR output indicating whether the UP_PRE clock pulse or the DWN_PRE clock pulse is greater than the minimum pulse width of the phase frequency detector, Multiple delay buffers electrically connected in series to the XOR gate, A multiplexer that outputs a delay step signal indicating the truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period associated with a delay buffer selection signal that identifies one of the plurality of delay buffers, A first AND gate is electrically connected to the first delay element and outputs a truncated UP clock pulse, including the truncated pulse width, to a charge pump, A second AND gate is electrically connected to the second delay element and outputs a truncated DWN clock pulse, including the truncated pulse width, to the charge pump, Includes, The NAND gate further includes receiving the delay stage signal, receiving the XOR output, receiving the truncation enable signal, and generating a NAND output to be transmitted to the first AND gate and the second AND gate. The plurality of delay buffers include a plurality of unselectable delay buffers that cannot be selected by the delay buffer selection signal, and a plurality of selectable delay buffers that can be selected by the delay buffer selection signal. The XOR gate is electrically connected in series with the first unselectable buffer. Phase-locked loop.

6. The first AND gate that outputs the truncated UP clock pulse to the charge pump further includes a first latch that determines and stores an UP truncation signal indicating that the UP_PRE clock pulse has been truncated, The phase-locked loop according to claim 5.

7. The second AND gate, which outputs the truncated DWN clock pulse to the charge pump, includes a second latch that determines and stores a DWN truncation signal indicating that the DWN_PRE clock pulse has been truncated. The phase-locked loop according to claim 6.

8. The first latch receives the UP_PRE clock pulse, receives the logical inversion of the NAND output, and receives the logical inversion of the truncation enable signal. The phase-locked loop according to claim 7.

9. The second latch receives the DWN_PRE clock pulse, receives the logic inversion of the NAND output, and receives the logic inversion of the truncation enable signal. The phase-locked loop according to claim 8.

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