Two-metal extra-thick metal (UTM) structure

Abstract

The semiconductor device comprises a conductive line disposed in a dielectric layer, a metal layer disposed over and in direct contact with the conductive line, and a metallization layer disposed over the metal layer such that a protruding segment of the metal layer serves as a junction between the conductive line and the metallization layer. The conductive line is copper (Cu) and the metal layer is ruthenium (Ru). The Ru metal layer includes an upper metal layer section and a lower metal layer section.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to a dual-metal ultra-thick metal (UTM) structure.

[0002] In the semiconductor integrated circuit (IC) industry, a variety of devices have been manufactured to address problems in several different fields, including radio frequency (RF) communication. As RF integrated circuits become more popular, improving them places specific requirements on semiconductor processes. Some RF circuits employ thick metal layers, and in some cases ultra-thick metal layers (UTM), to obtain characteristics such as inductive properties. However, some conventional semiconductor processing technologies are not easily scalable for use with UTM.

Summary of the Invention

[0003] According to one embodiment, a semiconductor device is provided. The semiconductor device includes a conductive line disposed within a dielectric layer, a metal layer disposed on the conductive line and in direct contact therewith, and a metallization layer disposed on the metal layer. A protruding segment of the metal layer is disposed to function as an interface between the conductive line and the metallization layer.

[0004] According to another embodiment, a semiconductor device is provided. The semiconductor device includes a conductive line disposed within a dielectric layer, a first metal layer disposed on the conductive line and in direct contact therewith, a second metal layer disposed on the first metal layer and in direct contact therewith, and a metallization layer disposed on the second metal layer. A protruding segment of the second metal layer is disposed to function as an interface between the conductive line and the metallization layer.

[0005] In yet another embodiment, a method for forming a semiconductor device is provided. The method includes forming a conductive line in a dielectric layer, constructing a first metal layer on the conductive line in direct contact with it, constructing a second metal layer on the first metal layer in direct contact with it, and forming a metallization layer on the second metal layer, wherein a protruding segment of the second metal layer is formed to function as a junction between the conductive line and the metallization layer.

[0006] It should be noted that these exemplary embodiments are described with reference to various subject matter. In particular, some embodiments are described with reference to method-form claims, while others are described with reference to apparatus-form claims. However, those skilled in the art will understand from the above and below descriptions that, unless otherwise stated, any combination of features belonging to a particular form of subject matter, as well as any combination of features relating to different subject matter, particularly between features of method-form claims and features of apparatus-form claims, are deemed to be described herein.

[0007] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which will be read in conjunction with the accompanying drawings.

[0008] The present invention will be further described in the following description of preferred embodiments with reference to the following figures. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of a semiconductor structure including a conductive material formed on a dielectric layer, according to one embodiment of the present invention. [Figure 2] This is a cross-sectional view of the semiconductor structure shown in Figure 1, in which a conductive material is planarized and conductive lines are defined within a dielectric layer, according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view of the semiconductor structure shown in Figure 2, in which the conductive lines are recessed, according to one embodiment of the present invention. [Figure 4] Figure 3 is a cross-sectional view of a semiconductor structure in which a metal layer is formed on a conductive line, according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view of the semiconductor structure shown in Figure 4, to which a lithography stack is attached, according to one embodiment of the present invention. [Figure 6] Figure 5 is a cross-sectional view of a semiconductor structure in which a lithography stack has been patterned according to one embodiment of the present invention. [Figure 7] This is a cross-sectional view of the semiconductor structure shown in Figure 6, in which a metal layer has been etched according to one embodiment of the present invention. [Figure 8] This is a cross-sectional view of the semiconductor structure shown in Figure 7, in which a second metallization layer is formed on the surface, according to one embodiment of the present invention. [Figure 9] This is a cross-sectional view of a semiconductor structure with a recessed conductive line according to another embodiment of the present invention. [Figure 10] This is a cross-sectional view of the semiconductor structure shown in Figure 9, in which a first metal layer is formed on a conductive line, according to one embodiment of the present invention. [Figure 11] This is a cross-sectional view of the semiconductor structure shown in Figure 10, in which a second metal layer is formed on a first metal layer, according to one embodiment of the present invention. [Figure 12] This is a cross-sectional view of the semiconductor structure shown in Figure 11, to which a lithography stack is attached, according to one embodiment of the present invention. [Figure 13] Figure 12 is a cross-sectional view of a semiconductor structure in which a lithography stack has been patterned according to one embodiment of the present invention. [Figure 14] This is a cross-sectional view of the semiconductor structure shown in Figure 13, in which a second metal layer has been etched according to one embodiment of the present invention. [Figure 15] This is a cross-sectional view of the semiconductor structure shown in Figure 14, in which a second metallization layer is formed on the surface, according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] Throughout all the figures, the same or similar reference numerals denote the same or similar elements.

[0011] Embodiments in accordance with the present invention provide a method and device for constructing a two-metal ultra-thick metal (UTM) structure to prevent via-line delamination observed during thermal cycle stress of a module by eliminating via-metal joints.

[0012] Generally, a semiconductor device includes a plurality of circuits that form integrated circuits fabricated on a semiconductor substrate. Typically, a network of complex signal paths for connecting circuit elements dispersed on the surface of the substrate is wired. To efficiently route these signals across the device, a multi-level or multi-layer scheme, such as a single or dual damascene wiring structure, for example an interconnect structure, needs to be formed.

[0013] In a dual damascene interconnect structure, conductive metal vias extend perpendicular to the semiconductor substrate and conductive metal lines extend parallel to the semiconductor substrate. Typically, the conductive metal vias are present under the conductive metal lines, and both mechanisms are embedded within an interconnect dielectric material layer.

[0014] In conventional dual damascene interconnect structures, copper or copper-containing alloys have been used as the material for the vias and lines of conductive metal. In recent years, advanced dual damascene interconnect structures having a combined type conductive via / line mechanism using alternative metals such as cobalt or ruthenium as a liner together with copper or a copper alloy have been developed. In such cases, copper voids are typically formed in the via portion and the line portion of the damascene interconnect structure, and the grain size of copper is often small (e.g., less than 5 nm). However, in such advanced dual damascene interconnect structures, delamination may occur at the landing of the vias on the first (first) ultra-thick metal (UTM).

[0015] Exemplary embodiments of the present invention prevent via-line delamination observed during thermal cycle stress generation of a module by eliminating via-metal joints and replacing copper with ruthenium or cobalt / ruthenium having mechanical properties stronger than those of joints of copper liners (underneath the underlying via-copper).

[0016] The present invention is described from the perspective of a given architecture for illustration purposes, but it should be understood that other architectures, structures, substrate materials, as well as process features and steps / blocks can be changed within the scope of the present invention. It should be noted that certain features may not be shown in all figures for clarity. This is not intended to be construed as a limitation of any specific embodiment, or figure, or the scope of the claims.

[0017] FIG. 1 is a cross-sectional view of a semiconductor structure including a conductive material formed on a dielectric layer according to an embodiment of the present invention.

[0018] In various exemplary embodiments, the structure 5 includes a conductive material 14 formed on and within a trench of an interlayer dielectric (ILD) 10. The metal liner 12 can be formed or attached around the trench of the ILD 10.

[0019] Let the height of the conductive material 14 within the trench be H1, and the height of the conductive material 14 outside the trench be H2. In one example, H1 is about 3 μm and H2 is about 4 μm.

[0020] Examples of the ILD 10 can include any material known in the art, such as porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. The ILD 10 can be formed using any method known in the art, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer growth, or physical vapor deposition. The ILD 10 can have a thickness ranging from about 25 nm to about 200 nm.

[0021] Examples of ILD10 include, but are not limited to, ultra-low k (ULK) materials such as porous silicates, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH), and porous deformed bodies thereof, silsesquioxanes, siloxanes, or other dielectric materials having dielectric constants in the range of about 2 to about 4.

[0022] Non-limiting examples of conductive material 14 include doped polycrystalline or amorphous silicon, germanium, silicon-germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metallic compounds (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silide, tungsten nitride, ruthenium oxide, cobalt silide, nickel silide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. Conductive material 14 may further include dopants incorporated during or after deposition. Conductive material 14 can be deposited by suitable deposition processes, such as CVD, PECVD, PVD, plating, thermal or electron beam deposition, and sputtering.

[0023] The metal liner 12 may be a metal such as tantalum nitride and tantalum (TaN / Ta), titanium, titanium nitride, cobalt, ruthenium, and manganese.

[0024] In one example, the metal liner 12 may be a tantalum (TaN) nitride liner, or in an alternative example, a tantalum (Ta) liner. In one exemplary embodiment, the metal liner 12 may be attached by, for example, electroplating, electroless plating, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), or a combination thereof.

[0025] Figure 2 is a cross-sectional view of the semiconductor structure shown in Figure 1, according to one embodiment of the present invention, in which the conductive material is planarized and conductive lines are defined within the dielectric layer.

[0026] In various exemplary embodiments, the conductive material 14 is planarized, for example by chemical mechanical polishing (CMP), to define conductive lines 18 within the trenches of the ILD 10. The upper surface 11 of the ILD 10 is flush with the upper surface of the conductive lines 18.

[0027] The conductive line 18 may be any conductive material known in the art, such as copper (Cu), aluminum (Al), or tungsten (W).

[0028] Examples of etching methods include wet etching, such as phosphoric acid (H3PO4) (wet chemical) etching or diluted hydrogen fluoride (HF) etching.

[0029] Figure 3 is a cross-sectional view of the semiconductor structure of Figure 2, in which the conductive lines are recessed, according to one embodiment of the present invention.

[0030] In various exemplary embodiments, the conductive line 18 is recessed such that a recessed conductive line 20 remains. The upper side wall 13 of the metal liner 12 is exposed. The conductive line 18 can be recessed by a height H3. H3 can be approximately 0.05 to 1 μm.

[0031] Figure 4 is a cross-sectional view of the semiconductor structure of Figure 3, in which a metal layer is formed on a conductive line, according to one embodiment of the present invention.

[0032] In various exemplary embodiments, a metal layer 22 is formed on the recessed conductive line 20. The metal layer 22 also extends on the ILD 10.

[0033] In one example, the metal layer 22 may be ruthenium (Ru).

[0034] With respect to ruthenium employed in exemplary embodiments, ruthenium is a transition metal, which means it has an imperfect core shell that acts as a bridge between the lowest and highest electronegativity elements in the group. Like other elements in the platinum group (platinum, rhodium, palladium, iridium, osmium), ruthenium is inert, which means that Ru does not react to exposure to most chemicals. Ruthenium is extremely hard. Ruthenium is often used as a hardening agent for platinum and palladium. Ruthenium also does not tarnish at room temperature, and adding small amounts of this substance can improve the corrosion resistance of titanium. Due to its hardness, ruthenium is an excellent choice for improving the wear resistance of electrical contacts and resistors, especially when alloyed with other platinum group metals. Ruthenium plating is also used in semiconductor manufacturing.

[0035] Ruthenium has attracted considerable interest because it can act as both a barrier layer and a seed layer, minimizing the amount of high-resistance material required for semiconductor circuits. However, when line widths are reduced to less than 15 nanometers, even a 1 or 2 nanometer barrier layer may be excessive. As line volume decreases, the resistance of Cu increases sharply due to electron scattering from sidewalls and grain boundaries. This increase in resistance increases the overall delay of the circuit and further promotes electromigration. As a heat-resistant metal, ruthenium has a very high melting point (over 2300°C) and excellent resistance to electromigration. Therefore, the use of ruthenium yields unexpected advantages because delamination of the titanium nitride (TiN) layer during processing does not affect the ruthenium layer (e.g., by etching it).

[0036] Figure 5 is a cross-sectional view of the semiconductor structure of Figure 4 with a lithography stack attached, according to one embodiment of the present invention.

[0037] In various exemplary embodiments, a lithography stack is attached.

[0038] The lithography stack includes an organic planarization layer (OPL) 24, an anti-reflective hard mask layer 26, and a photoresist layer 28.

[0039] OPL24 may contain an organic planarizing material, which is a self-planarizing organic material comprising carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one embodiment, the self-planarizing organic material may be a polymer with sufficiently low viscosity such that the upper surface of OPL24 forms a flat horizontal plane. Exemplary organic planarizing materials include, but are not limited to, NFC (near-frictionless carbon) materials, diamond-like carbon, polyarylene ethers, and polyimides. OPL24 can be attached, for example, by spin coating. The thickness of OPL24 can range from about 100 nm to about 500 nm, but smaller and larger thicknesses are also possible.

[0040] The anti-reflective hard mask layer 26 is formed on the OPL 24. The anti-reflective hard mask layer 26 may include an anti-reflective coating material. The anti-reflective hard mask layer 26 is employed in the lithography process to improve the profile of the photoresist and reduce line width variations caused by light scattering and reflection. The anti-reflective hard mask layer 26 may include silicon-containing anti-reflective coating (SiARC) material, titanium-containing anti-reflective coating (TiARC) material, silicon nitride, silicon oxide, or TiN. In one embodiment, the anti-reflective hard mask layer 26 includes a SiARC material. The anti-reflective hard mask layer 26 can be applied, for example, by spin coating or CVD. The thickness of the anti-reflective hard mask layer 26 can be approximately 10 nm to approximately 150 nm, but smaller and larger thicknesses are also possible.

[0041] The photoresist layer 28 is deposited on the anti-reflective hard mask layer 26 as a blanket layer, for example, by spin coating. The photoresist layer 28 may contain any organic photoresist material, such as methacrylate or polyester. The photoresist layer 28 can have a thickness of about 30 nm to about 500 nm, but smaller or larger thicknesses are also possible. In one example, the thickness of the photoresist layer 28 is 360 nm.

[0042] Figure 6 is a cross-sectional view of the semiconductor structure of Figure 5, with a patterned lithography stack according to one embodiment of the present invention.

[0043] In various exemplary embodiments, the lithography stack is patterned such that the OPL portion 30 remains on top of a portion of the metal layer 22. The upper surface 23 of the metal layer 22 is further exposed.

[0044] Figure 7 is a cross-sectional view of the semiconductor structure of Figure 6, in which the metal layer has been etched according to one embodiment of the present invention.

[0045] In various exemplary embodiments, the metal layer 22 is etched so that a metal layer section 32 remains. The metal layer section 32 includes an upper metal layer section 32A and a lower metal layer section 32B. The upper metal layer section 32A may be referred to as a protruding segment. The recessed conductive line 20 and the metal layer section 32 are part of the first metallization level. Thus, the upper metal layer section 32A of the metal layer section 32 serves as a junction between the recessed conductive line 20 and the second metallization layer (Figure 8).

[0046] The lower metal layer section 32B is in direct contact with the entire upper surface of the recessed conductive line 20.

[0047] The combined height of the recessed conductive line 20 and the lower metal layer section 32B is greater than 1.5 μm.

[0048] Figure 8 is a cross-sectional view of the semiconductor structure of Figure 7, with a second metallization layer formed thereon, according to one embodiment of the present invention.

[0049] In various exemplary embodiments, a second metallization layer is formed thereon.

[0050] In particular, a capping layer 38 is formed on the metal layer section 32. Then an ILD 40 is formed on top of it. A trench is formed in the ILD 40, another metal liner 42 is attached, and a conductive material 44 (or metal line) is formed within the trench. Another capping layer 46 is formed on top of it to complete the second metallization level. The structure 50 is a bimetallic dual damascene integrated structure. Via resistance can be adjusted by using redundant vias and increasing the via limit dimension (CD).

[0051] The thickness of the recessed conductive line 20 is less than the thickness of the conductive material 44 in the second metallization layer.

[0052] The capping layer 38 is in direct contact with both the upper metal layer section 32A and the lower metal layer section 32B of the metal layer section 32.

[0053] The capping layers 38 and 46 may contain nBLOK, but can be any dielectric layer that prevents the diffusion of copper or ruthenium.

[0054] In Figures 1 to 8, etching may include dry etching processes such as reactive ion etching, plasma etching, ion etching, or laser ablation. Etching may further include wet chemical etching processes in which one or more chemical etchants are used to remove portions of the blanket layer that are not protected by the patterned photoresist.

[0055] Dry etching and wet etching processes may have adjustable etching parameters, such as the etchant used, etching temperature, etching solution concentration, etching pressure, power supply, RF bias voltage, RF bias power, etchant flow rate, and other appropriate parameters. Dry etching processes may include bias plasma etching processes using chlorine-based chemicals. Other dry etchant gases include tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), helium (He), and chlorine trifluoride (ClF3). Dry etching can also be performed anisotropically using mechanisms such as DRIE (Deep Reactive Ion Etching). Chemical vapor deposition can be used as a selective etching method, and etching gases include hydrogen chloride (HCl), tetrafluoromethane (CF4), and mixed gases with hydrogen (H2). Chemical vapor deposition can be performed by CVD at appropriate pressure and temperature.

[0056] Figure 9 is a cross-sectional view of a semiconductor structure with a recessed conductive line according to another embodiment of the present invention.

[0057] In various exemplary embodiments, the conductive line 18 is recessed such that a recessed conductive line 20 remains. The upper side wall 13 of the metal liner 12 is exposed. The conductive line 18 can be recessed by a height H3. H3 can be approximately 0.05 to 1 μm.

[0058] Figure 10 is a cross-sectional view of the semiconductor structure of Figure 9, in which a first metal layer is formed on a conductive line, according to one embodiment of the present invention.

[0059] In various exemplary embodiments, a first metal layer 60 is formed on the recessed conductive line 20.

[0060] In one example, the first metal layer 60 may be, for example, cobalt (Co).

[0061] Figure 11 is a cross-sectional view of the semiconductor structure of Figure 10, in which a second metal layer is formed on a first metal layer, according to one embodiment of the present invention.

[0062] In various exemplary embodiments, a second metal layer 62 is formed on top of a first metal layer 60. The second metal layer 62 also extends on top of the ILD 10.

[0063] In one example, the second metal layer 62 may be ruthenium (Ru).

[0064] Figure 12 is a cross-sectional view of the semiconductor structure of Figure 11 with a lithography stack attached, according to one embodiment of the present invention.

[0065] In various exemplary embodiments, a lithography stack is attached.

[0066] The lithography stack includes the aforementioned OPL24, an anti-reflective hard mask layer 26, and a photoresist layer 28.

[0067] Figure 13 is a cross-sectional view of the semiconductor structure of Figure 12, with a patterned lithography stack according to one embodiment of the present invention.

[0068] In various exemplary embodiments, the lithography stack is patterned such that the OPL portion 30 remains on top of a portion of the second metal layer 62. The upper surface 63 of the second metal layer 62 is further exposed.

[0069] Figure 14 is a cross-sectional view of the semiconductor structure shown in Figure 13, in which the metal layer has been etched according to one embodiment of the present invention.

[0070] In various exemplary embodiments, the second metal layer 62 is etched such that the metal layer section 32 remains. The metal layer section 32 includes an upper metal layer section 32A and a lower metal layer section 32B. The upper metal layer section 32A may be referred to as a protruding segment. The recessed conductive line 20, the first metal layer 60, and the lower metal layer section 32B of the metal layer section 32 are part of the first metallization level.

[0071] Thus, the upper metal layer section 32A of the metal layer section 32 functions as a junction between the recessed conductive line 20 and the second metallization layer (Figure 15).

[0072] The lower metal layer section 32B is in direct contact with the entire upper surface of the first metal layer 60, and the first metal layer is in direct contact with the entire upper surface of the recessed conductive line 20.

[0073] The combined height of the conductive line 20, the first metal layer 60, and the lower metal layer section 32B of the second metal layer section 32 is greater than 1.5 μm.

[0074] Etching processes that may be used in embodiments of the present invention include chemicals containing fluorine or chlorine, such as Cl2, F2, C x F y SF6, CHF3, CF x Cl y Examples include plasma etching processes, as well as wet etching processes using acids such as hydrogen fluoride, hydrogen chloride, sulfuric acid, and nitric acid.

[0075] Figure 15 is a cross-sectional view of the semiconductor structure of Figure 14, in which a second metallization layer is formed on the surface, according to one embodiment of the present invention.

[0076] In various exemplary embodiments, a second metallization layer is formed thereon.

[0077] In particular, a capping layer 38 is formed on the second metal layer section 32. Then an ILD 40 is formed on top of it. A trench is formed in the ILD 40, another metal liner 42 is attached, and a conductive material 44 (or metal line) is formed within the trench. Another capping layer 46 is formed on top of it to complete the second metallization level. The structure 70 is a three-metal dual damascene integrated structure. Via resistance can be adjusted by using redundant vias and increasing the via limit dimension (CD).

[0078] The capping layer 38 is in direct contact with both the upper metal layer section 32A and the lower metal layer section 32B of the second metal layer section 32.

[0079] The capping layers 38 and 46 may contain nBLOK, but can be any dielectric layer that prevents the diffusion of copper or ruthenium.

[0080] Therefore, in summary, exemplary embodiments of the present invention prevent via-line delamination observed during thermal cycling stress generation in a module by eliminating via-metal joints and replacing copper with ruthenium or cobalt / ruthenium, both of which have stronger mechanical properties than the copper liner joints (under the via-copper).

[0081] As used throughout this application, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities including native oxides, and copper alloys containing one or more additional elements such as carbon, nitrogen, magnesium, aluminum, titanium, vanadium, chromium, manganese, nickel, zinc, germanium, strontium, zirconium, silver, indium, tin, tantalum, and platinum. In several embodiments, the copper alloy is a copper-manganese alloy. In further embodiments, cobalt metal (Co) or a cobalt metal alloy may be used instead of copper. Copper-containing structures are conductive. As used throughout this disclosure, “conductive” means at least 10 -8(Ω·m) -1 This refers to a material that has a room-temperature conductivity of [value missing].

[0082] With respect to Figures 1 to 15, adhesion refers to any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). As used herein, "adhesion" may include, but is not limited to, any currently known or future-developed techniques suitable for the material to be adhered. Examples include chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-accelerated CVD (PECVD), semi-atmospheric CVD (SACVD), and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited-reaction CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin-on method, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and vapor deposition.

[0083] As used herein, the term “processing” includes, as necessary in forming the structures described, the application, patterning, exposure, development, etching, washing, stripping, injection, doping, stressing, lamination, or removal of material or photoresist, or a combination thereof.

[0084] It should be understood that the present invention will be described in terms of a given exemplary architecture.

[0085] When an element, such as a layer, region, or substrate, is described as existing "on" or "over" another element, it can be understood that the element may exist directly on the other element, or there may be an intervening element. In contrast, when an element is described as existing "directly on" or "directly over" another element, there is no intervening element. Similarly, when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be an intervening element. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there is no intervening element.

[0086] This embodiment may include the design of an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (e.g., a disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the resulting design to such an entity directly or indirectly, either by a physical mechanism (e.g., by providing a copy of the storage medium containing the design) or electronically (e.g., via the internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing a photolithography mask containing multiple copies of the chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer to be etched or otherwise processed.

[0087] The methods described herein may be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as paired dies, or in packaged form. In the latter case, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects or embedded wiring). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products having a central processor and a display, keyboard, or other input device.

[0088] It should also be understood that material compounds, such as SiGe, can be described by an enumeration of elements. These compounds contain elements in varying proportions; for example, SiGe is composed of Si x Ge 1-x This includes, and x is 1 or less, etc. In addition, other elements may be included in the compound, and those elements may still function according to this embodiment. In this specification, a compound containing additional elements is referred to as an alloy. Any reference in this specification to “one embodiment” or “a certain embodiment” of the present invention, and to other variations thereof, means that certain features, structures, properties, etc. described in relation to that embodiment are included in at least one embodiment of the present invention. Thus, although the phrase “in one embodiment” or “in a certain embodiment” and any other variations may appear in various places throughout this specification, they do not necessarily all refer to the same embodiment.

[0089] For example, in the cases of "A / B", "A or B or both", and "at least one of A and B", please understand that the use of any of the following, namely " / ", "...or...or both (and / or)", and "...at least one of...", is intended to encompass the selection of only the first option (A), or only the second option (B), or both options (A and B). As further examples, in the cases of "A, B, or C, or a combination thereof", and "at least one of A, B, and C", such usage is intended to encompass the selection of only the first option (A), or only the second option (B), or only the third option (C), or only the first and second options (A and B), or only the first and third options (A and C), or only the second and third options (B and C), or all three options (A, B, and C). This can be extended to the number of items listed, as will be readily apparent to those skilled in the art of this and related technologies.

[0090] The technical terms used herein are intended solely to describe specific embodiments and are not intended to limit the exemplary embodiments. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless explicitly indicated otherwise in the context. It will be further understood that the terms “comprise,” “comprising,” “include,” or “including,” where used herein, indicate the existence of a mentioned feature, integer, step, action, element, or component, or a combination thereof, but do not exclude the existence or addition of one or more other features, integers, steps, actions, elements, components, or groups thereof, or combinations thereof.

[0091] To facilitate descriptions of the relationship between one element or feature and another, as shown in the diagram, terms describing spatial relationships, such as “beneath,” “below,” “lower,” “above,” and “upper,” may be used herein. It will be understood that these terms describing spatial relationships are intended to encompass various arrangements of the device in use or operation, in addition to the arrangement depicted in the diagram. For example, if the device in the diagram is inverted, an element described as being “below” or “beneath” another element or feature will consequently be positioned “above” the other element or feature. Thus, the term “below” may encompass both above and below arrangements. The device may be positioned otherwise (by rotating it 90 degrees or in other arrangements), and the spatial descriptive terms used herein may be interpreted accordingly. Furthermore, when a layer is referred to as being "between" two layers, it will become clearer that it may be the only layer between the two layers, or there may be one or more intervening layers.

[0092] While terms such as "first," "second," etc., may be used in this specification to describe various elements, it should be understood that these elements are not limited by these terms. These terms are used solely to distinguish one element from another. For example, the first element considered below can be referred to as the second element without deviating from the scope of this concept.

[0093] Preferred embodiments for two-metal extra-thick metal (MTM) structures have been described (these are intended to be illustrative and not limiting), but it should be noted that those skilled in the art may modify and change them in light of the above teachings. Therefore, it should be understood that in the specific embodiments described, modifications may be made that fall within the scope of the invention as defined by the accompanying claims. While aspects of the invention have been described with the detail and specificity required by patent law, the subject matter for which rights are claimed and protection is desired by the patent is described in the accompanying claims.

Claims

1. It is a semiconductor device, Conductive lines arranged within the dielectric layer, A metal layer disposed on the aforementioned conductive line and in direct contact with it, A metallization layer disposed on the aforementioned metal layer, The metal layer includes a lower metal layer section that is in direct contact with the entire upper surface of the conductive line, and an upper metal layer section that protrudes from the upper surface of the lower metal section. The upper metal layer section is disposed as a junction between the conductive line and the metallization layer. A semiconductor device in which the conductive line is made of copper (Cu) and the metal layer is made of ruthenium (Ru).

2. The semiconductor device according to claim 1, wherein the upper metal layer section prevents delamination between via lines.

3. The semiconductor device according to claim 1, wherein the total height of the conductive line and the lower metal layer section is greater than 1.5 μm.

4. The semiconductor device according to claim 1, wherein the thickness of the conductive line is smaller than the thickness of the conductive material in the metallization layer.

5. It is a semiconductor device, Conductive lines arranged within the dielectric layer, A first metal layer is disposed on the aforementioned conductive line and is in direct contact with it, A second metal layer is disposed on top of the first metal layer and is in direct contact with it, The invention comprises a metallization layer disposed on the second metal layer, The first metal layer is in direct contact with the entire upper surface of the conductive line. The second metal layer includes a lower metal layer section that is in direct contact with the entire upper surface of the first metal layer, and an upper metal layer section that protrudes from the upper surface of the lower metal layer section. The upper metal layer section is disposed as a junction between the conductive line and the metallization layer. A semiconductor device in which the conductive line is made of copper (Cu), the first metal layer is made of cobalt (Co), and the second metal layer is made of ruthenium (Ru).

6. The semiconductor device according to claim 5, wherein the upper metal layer section prevents via-line delamination.

7. The semiconductor device according to claim 5, wherein the total height of the conductive line, the first metal layer, and the lower metal layer section of the second metal layer is greater than 1.5 μm.

8. The semiconductor device according to claim 5, wherein the thickness of the conductive line is smaller than the thickness of the conductive material in the metallization layer.

9. It is a method, Forming conductive lines within the dielectric layer, A first metal layer is constructed on the conductive line, in direct contact with the entire upper surface thereof. A second metal layer is constructed on the first metal layer in direct contact with it, This includes forming a metallization layer on the second metal layer, The second metal layer is constructed to include a lower metal layer section that is in direct contact with the entire upper surface of the first metal layer, and an upper metal layer section that protrudes from the upper surface of the lower metal layer section. The upper metal layer section is formed as a junction between the conductive line and the metallization layer. A method wherein the conductive line is made of copper (Cu), the first metal layer is made of cobalt (Co), and the second metal layer is made of ruthenium (Ru).

10. The method according to claim 9, wherein the upper metal layer section prevents delamination between via lines.

11. The method according to claim 9, wherein the total height of the conductive line, the first metal layer, and the lower metal layer section of the second metal layer is greater than 1.5 μm.

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