Memory device

Abstract

A memory device comprises: a word-line selection unit (X decoder) configured to select a word line; a memory cell including cells that are connected to the word line and each bit line and are disposed in a matrix form; a bit detection unit configured to detect, via each bit line, the logical values of bit data stored in the cells connected to the selected word line; a data output unit configured to output data on the basis of the detection result of the bit detection unit; and a control unit. Some of the cells correspond to a predetermined number of bits and accommodate fixed values. The control unit compares, with an expected value, the fixed values read from some of the cells via the bit detection unit and the data output unit.

Description

Technical Field

[0001] The invention disclosed in this specification relates to a memory device.

Background Art

[0002] Conventionally, various memory devices such as OTP (One Time Programmable ROM) have been proposed (for an example of OTP, see Patent Document 1).

Prior Art Documents

Patent Documents

[0003] <00000!6>

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Recently, especially in the in - vehicle field and the like, functional safety has become important, and an improvement in functional safety is also desired in memory devices.

[0005] In view of the above situation, the invention disclosed in this specification aims to provide a memory device with improved functional safety.

Means for Solving the Problems

[0006] For example, the memory device disclosed in this specification includes a word - line selection unit configured to select a word - line, a memory cell having cells connected to the word - line and bit - line units and arranged in a matrix, a bit detection unit configured to detect the logical value of bit data stored in the cell connected to the selected word - line via the bit - line unit, a data output unit configured to output data based on the detection result of the bit detection unit, Control unit and It has, A fixed value is stored in some of the cells corresponding to a predetermined number of bits. The control unit is configured to compare the fixed values ​​read from some of the cells via the bit detection unit and the data output unit with the expected values. [Effects of the Invention]

[0007] The memory devices disclosed herein can improve functional safety. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows the configuration of a power supply device according to an exemplary embodiment of the present disclosure. [Figure 2] Figure 2 is a block diagram showing an example of a memory device configuration. [Figure 3] Figure 3 shows a specific example of a memory cell configuration. [Figure 4] Figure 4 shows an example of the data structure of a memory cell. [Figure 5] Figure 5 is an external view showing an example of the vehicle's configuration. [Modes for carrying out the invention]

[0009] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0010] <1. Applicable to memory devices> Figure 1 shows the configuration of a power supply unit 5 as an example of an application to which a memory device according to an exemplary embodiment of this disclosure may be applied. The power supply unit 5 includes a memory device 10.

[0011] The power supply device 5 is a semiconductor device (IC package) that integrates an OTP block 1, a control unit (controller) 2, DC / DC converter circuits 3A to 3D, and a detection unit 4 on one chip. The power supply device 5 can generate a plurality of output voltages VO1 to VO4 and is mounted on, for example, a vehicle.

[0012] The OTP block 1 is composed of memory cells and their peripheral circuits (both not shown). Various setting information and the like are stored in the memory cells. The detailed configuration of the OTP block 1 will be described later.

[0013] The control unit 2 is a device that controls each part of the power supply device 5. The control unit 2 controls, for example, the OTP block 1. The memory device 10 is composed of the OTP block 1 and the control unit 2. That is, the power supply device 5 has the memory device 10.

[0014] The control unit 2 has a register 21. The data read from the OTP block 1 (memory cells) according to the instruction of the control unit 2 is stored in the register 21.

[0015] Each of the DC / DC converter circuits 3A to 3D performs DC / DC conversion of the input voltage to the output voltages VO1 to VO4 and outputs them. The set values of the output voltages VO1 to VO4 are set according to the data stored in the register 21.

[0016] The detection unit 4 detects, for example, overvoltage or undervoltage of each of the output voltages VO1 to VO4 and outputs a detection signal RST. The detection threshold of the detection unit 4 is set according to the data stored in the register 21.

[0017] <2. Configuration of Memory Device> Next, the configuration of the memory device 10 will be described more specifically. FIG. 2 is a block diagram showing a configuration example of the OTP block 1.

[0018] As shown in FIG. 2, the OTP block 1 includes an input buffer 11, a timing circuit 12, an X decoder 13, a memory cell 14, a bit detection unit 15, and a data input / output unit 16.

[0019] The input buffer 11 stores the address specification information input from the control unit 2. The timing circuit 12 performs timing control of the X decoder 13, the bit detection unit 15, and the data input / output unit 16.

[0020] Based on the address specification information input from the input buffer 11 via the timing circuit 12, the X decoder 13 selects the word line (row) in the memory cell 14.

[0021] The memory cell 14 is composed of a plurality of cells arranged in a matrix. One cell is composed of a transistor.

[0022] The bit detection unit 15 detects the logical value (0 or 1) of the bit data stored in each cell of the word line selected by the X decoder 13 in the memory cell 14. Based on the detection result by the bit detection unit 15, the data input / output unit 16 outputs the data of each cell of the selected word line to the control unit 2. That is, the data of the selected word line is read from the memory cell 14 by the bit detection unit 15 and the data input / output unit 16.

[0023] FIG. 3 is a diagram showing a specific configuration example of the memory cell 14. Note that FIG. 3 shows only a part of the cells of the memory cell 14.

[0024] As shown in FIG. 3, the memory cell 14 has a normal area and a ROM area. In the normal area, OTP cells 141 are arranged in a matrix. In the ROM area, ROM cells 142 are arranged in a matrix.

[0025] The OTP cell 141 consists of two MOS transistors. The gates of the two MOS transistors are commonly connected to the word line WL. The first ends of the two MOS transistors are connected to each other. The second end of one MOS transistor is connected to the bit line BL. The second end of the other MOS transistor is connected to the bit line BLC.

[0026] 32 OTP cells 141 with the above connection configuration are provided for each word line WL. Therefore, in the normal area, it is possible to store 32 bits of data for each word line WL.

[0027] In the normal area, 32 bit line units BU, each consisting of a bit line BL and a bit line BLC, are provided. A sense amplifier 15A is inserted between the bit lines BL and BLC in one bit line unit BU. In other words, 32 sense amplifiers 15A are provided in the normal area. The sense amplifiers 15A constitute the bit detection unit 15.

[0028] A voltage can be commonly applied by the voltage application unit VCC to each node where the first ends of the MOS transistors in each OTP cell 141 connected between bit lines BL and BLC in a single bit line unit BU are connected.

[0029] In the OTP cell 141, charge is injected into the gate of either one of the MOS transistors. Depending on which MOS transistor receives the charge, the value of the bit data stored in the OTP cell 141 (0 or 1) will differ. This injection of charge into the gate of either MOS transistor causes the threshold voltage of each MOS transistor in the OTP cell 141 to differ.

[0030] The X decoder 13 selects a word line WL by applying a predetermined voltage to the word line WL. A voltage is applied to the OTP cell 141 of the selected word line WL by the voltage application unit VCC. In this state, the degree to which each MOS transistor is ON differs due to the difference in the threshold voltage of each MOS transistor in the OTP cell 141 of the selected word line WL. Consequently, a difference in the current flowing through each MOS transistor occurs. The sense amplifier 15A amplifies this difference in current and outputs it. As a result, the sense amplifier 15A detects the logical value of the bit data stored in the OTP cell 141 of the selected word line WL.

[0031] Each bit data of the 32 OTP cells 141 of the selected word line WL in the normal area is detected by each of the 32 sense amplifiers 15A. The data input / output unit 16 then outputs 32 bits of normal area data DOUT based on the detection results of each sense amplifier 15A.

[0032] The ROM cell 142 consists of one MOS transistor. The gate of the MOS transistor is connected to the word line WL. The first end of the MOS transistor is connected to the voltage application terminal of the voltage application section VCC. The second end of the MOS transistor is connected to either the bit line BL or the bit line BLC.

[0033] Eight ROM cells 142 with the above connection configuration are provided for each word line WL. Therefore, the ROM area can store 8 bits of data for each word line WL. Note that the word line WL is common to both the normal area and the ROM area. That is, for one word line WL (one word area W in Figure 3), 32 OTP cells 141 and 8 ROM cells 142 are provided.

[0034] In the ROM area, eight bit line units BU, each consisting of bit line BL and bit line BLC, are provided. A sense amplifier 15B is inserted between bit lines BL and BLC in one bit line unit BU. In other words, eight sense amplifiers 15B are provided in the ROM area. The sense amplifiers 15B, together with sense amplifier 15A, constitute the bit detection unit 15.

[0035] A voltage can be commonly applied to the first end of each ROM cell 142 connected to bit lines BL and BLC in a single bit line unit BU by a voltage application unit VCC.

[0036] The X decoder 13 selects word line WL by applying a predetermined voltage to the word line WL. A voltage is applied to the ROM cell 142 of the selected word line WL by the voltage application unit VCC. In this state, a difference in current flows through bit lines BL and BLC depending on whether the MOS transistor in the ROM cell 142 of the selected word line WL is connected to bit line BL or BLC. The sense amplifier 15B amplifies this difference in current and outputs it. As a result, the sense amplifier 15B detects the logical value of the bit data stored in the ROM cell 142 of the selected word line WL.

[0037] Each bit data of the eight ROM cells 142 of the selected word line WL in the ROM area is detected by each of the eight sense amplifiers 15B. The data input / output unit 16 then outputs 8-bit ROM area data ROMOUT based on the detection results of each sense amplifier 15B.

[0038] In this way, when the X decoder 13 selects a word line WL, data (32 bits + 8 bits) is read from each cell in the normal area and ROM area of ​​the selected word line WL and output.

[0039] Furthermore, the bit data in the normal area is not limited to 32 bits; it may have any other number of bits. Similarly, the bit data in the ROM area is not limited to 8 bits; it may have any other number of bits.

[0040] Furthermore, in the example shown in Figure 3, the fixed values ​​in the ROM area (described later) are structurally held as in the ROM cell 142, but they may also be held by injecting charge into a transistor in a cell similar to the OTP cell 141 shown in Figure 3. Also, the fixed values ​​in the normal area (described later) may be structurally held in the same way as the ROM cell 142 shown in Figure 3.

[0041] <3. Data structure of memory cells> Figure 4 shows an example of the data structure of the memory cell 14. As shown in Figure 4, the memory cell 14 is provided with a standard area and a fixed area. .

[0042] Each standard area and fixed area corresponds to one word line WL and includes a normal area and a ROM area. Each standard area and fixed area is specified by a combination of first address information TXADD and second address information XADD. The first address information TXADD indicates whether it is a standard area or a fixed area. In Figure 3, TXADD=0 indicates a standard area, and TXADD=1 indicates a fixed area. The second address information XADD identifies which word line WL the area specified by the first address information TXADD belongs to.

[0043] In Figure 4, for example, in a fixed area specified by TXADD=1 and XADD=0x1F, 0x89AB (16 bits) and 0xCDEF (16 bits) are stored in the normal area, and 0xE0 (8 bits) is stored in the ROM area.

[0044] Furthermore, as shown in Figure 3, the control unit 2 is connected to the input buffer 11 (in Figure 3, “Digital” refers to Figure 3). The first address information TXADD and the second address information XADD are input to the input buffer 11 and timing circuit 12 shown in 2, which allows the X decoder 13 to select the word line WL.

[0045] In the fixed area, fixed values ​​are stored in both the normal area and the ROM area. In other words, the fixed area is a dedicated area for storing fixed values. These fixed values ​​are data used in the self-diagnostic function (BIST (Built-In Self Test)) of the memory device 10, which will be described later. In Figure 4, the fixed values ​​are indicated by hatching.

[0046] The normal area in the standard area stores data that is read out when the self-diagnosis function determines that the device is functioning normally. This data includes setting values ​​for the normal operation of the power supply unit 5 (such as the output voltage setting). The ROM area in the standard area stores fixed values. These fixed values ​​are the data used by the self-diagnosis function.

[0047] <4. Self-diagnosis function> Next, we will describe the self-diagnostic function of the memory device 10 for improving functional safety.

[0048] The memory device 10 performs a self-diagnostic operation when the power supply device 5 is started. During the self-diagnostic operation, the control unit 2 reads a fixed value (hatching in Figure 4) from the memory cell 14 by specifying an address (word line WL) using the address information TXADD and XADD. The control unit 2 compares the read fixed value with an expected value.

[0049] If all the fixed values ​​to be read (all the hatching in Figure 4) match the expected values, the peripheral circuits of the memory cell 14 (X decoder 13, bit detection unit 15, data input / output unit 16) are determined to be functioning correctly, and the process proceeds to reading data from the normal area in the standard area.

[0050] On the other hand, if a read fixed value does not match the expected value, the startup of the power supply unit 5 is canceled, indicating an abnormality in the peripheral circuitry of the memory cell 14. In this case, the power supply unit 5 may be configured to notify an external party of the abnormality.

[0051] As shown in Figure 4, fixed values ​​used in self-diagnostic operations are stored in the ROM area for all word line WLs. That is, fixed values ​​are stored in the ROM cell 142 (8 bits) connected to each of the word line WLs, which allows verification of whether the X decoder 13 is functioning correctly.

[0052] Furthermore, as mentioned earlier, the ROM cell 142 (Figure 3) is composed of a single MOS transistor with its second terminal connected to either bit line BL or BLC, allowing the sense amplifier 15B to detect bits more accurately. Consequently, the 8-bit fixed values ​​in the ROM area can be read out more accurately.

[0053] Furthermore, as shown in Figure 4, fixed values ​​are stored in both the normal area and the ROM area within the fixed area. For example, in the fixed area shown in Figure 4 (TXADD=1, XADD=0x1F), 0x89AB and 0xCDEF are stored as fixed values ​​in the normal area, and 0xE0 is stored as a fixed value in the ROM area. In other words, the bit line unit BU to which the OTP cells 141 (16 bits x 2) and ROM cell 142 (8 bits) that store fixed values ​​are connected is the entire bit line unit BU. This allows us to confirm whether the bit detection unit 15 (sense amplifiers 15A, 15B), data input / output unit 16, timing circuit 12, and input buffer 11 are functioning correctly.

[0054] Furthermore, as shown in Figure 4, the fixed values ​​of the corresponding bits in the normal area within the two fixed areas invert the logical values ​​of the bit data relative to each other (0x89AB and 0x7654, 0xCDEF and 0x3210, 0x5555 and 0xAAAA shown in Figure 4). In other words, the fixed values ​​stored in the OTP cells 141 (16 bits each) connected to different word lines WL and the same bit line unit BU invert the logical values ​​of the bit data relative to each other. This allows the sense amplifier 15A to detect both 0 and 1 cases, enabling a more accurate determination of whether the sense amplifier 15A is functioning correctly.

[0055] Furthermore, as shown in Figure 4, each fixed value in the ROM area of ​​multiple standard areas having consecutive addresses (XADD=0x00~0x1F) is configured to indicate the above addresses (0x00~0x1F). That is, the fixed values ​​stored in each ROM cell 142 (8 bits) connected to different word lines WL with consecutive addresses and connected to the same bit line unit BU indicate the above consecutive addresses. This increases the variety of fixed values ​​in the ROM area.

[0056] Furthermore, as shown in Figure 4, the addresses of the fixed area (XADD=0x00, 0x01, 0x1E, 0x1F) are the same as a portion of the consecutive addresses mentioned above, and the fixed values ​​of the ROM area in the fixed area (0xFF, 0xFE, 0xE1, 0xE0) are the values ​​obtained by inverting the logical bit values ​​of the addresses in the fixed area. In other words, the fixed values ​​stored in each ROM cell 142 (8 bits), which is assigned the same allocation addresses (0x00, 0x01, 0x1E, 0x1F) as at least a portion of the consecutive addresses mentioned above, is connected to a different word line WL than the word line WL of the consecutive addresses mentioned above, and is connected to the same bit line unit BU, are the values ​​obtained by inverting the logical bit values ​​of the allocation addresses mentioned above. This makes it possible to increase the variations of fixed values ​​in the ROM areas of the standard area and the fixed area.

[0057] <5. Application to Vehicles> Figure 5 is an external view showing one example of a vehicle configuration. In this example, vehicle X is equipped with a battery (not shown in this figure) and various electronic devices X11 to X18 that operate by receiving power voltage from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for illustrative purposes.

[0058] Electronic device X11 is an engine control unit that performs engine-related controls (such as injection control, electronic throttle control, idle control, oxygen sensor heater control, and auto cruise control).

[0059] Electronic equipment X12 includes HID (high-intensity discharged lamp) and DRL (daytime running lights). This is a lamp control unit that controls the on / off state of lights such as running lamps.

[0060] Electronic device X13 is a transmission control unit that performs control related to the transmission.

[0061] The electronic device X14 controls the vehicle X's motion (such as ABS [anti-lock brake system] control, EPS [electric power steering] control, and electronic suspension control). This is a body control unit that performs the function.

[0062] Electronic device X15 is a security control unit that controls the operation of door locks, burglary alarms, and other devices.

[0063] Electronic equipment X16 consists of electronic components that are installed in vehicle X at the factory as standard equipment or manufacturer options, including wipers, power door mirrors, power windows, dampers (shock absorbers), power sunroof, and power seats.

[0064] Electronic equipment X17 is an electronic device that can be optionally installed in vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0065] Electronic equipment X18 is a type of electronic equipment equipped with high-voltage motors, such as automotive blowers, oil pumps, water pumps, and battery cooling fans.

[0066] Furthermore, the power supply unit 5 described earlier can be incorporated into any of the electronic devices X11 to X18.

[0067] <6. Summary> The various embodiments described above will be summarized below.

[0068] For example, the memory device (10) disclosed herein is A wordline selection unit (X decoder 13) configured to select a wordline (WL), A memory cell (14) having cells (141, 142) connected to the word line and bit line units (BU) and arranged in a matrix, A bit detection unit (15) is configured to detect the logical value of bit data stored in the cell connected to the selected word line via the bit line unit, A data output unit (16) configured to output data based on the detection result of the bit detection unit, Control unit (2) and It has, A fixed value is stored in some of the cells corresponding to a predetermined number of bits. The control unit is configured to compare the fixed values ​​read from some of the cells via the bit detection unit and the data output unit with the expected values ​​(first configuration).

[0069] Furthermore, in the first configuration described above, the fixed value may be stored in some of the cells connected to each of the word lines (second configuration).

[0070] Furthermore, in the first or second configuration described above, the bit line unit to which some of the cells are connected may be configured to be all of the bit line units (third configuration).

[0071] Furthermore, in any of the first to third configurations described above, the fixed values ​​stored in some of the cells connected to different word lines and the same bit line unit may be configured such that the logical values ​​of the bit data are inverted from each other (fourth configuration).

[0072] Furthermore, in any of the first to fourth configurations described above, the fixed values ​​stored in some of the cells connected to different word lines with consecutive addresses and connected to the same bit line unit may be configured to indicate the consecutive addresses (fifth configuration).

[0073] Furthermore, in the fifth configuration described above, the fixed value stored in each of the cells that are assigned the same allocation address as at least a portion of the consecutive addresses, connected to a different word line than the word line of the consecutive addresses, and connected to the same bit line unit, may be the value obtained by inverting the logical value of the bits of the allocation address (sixth configuration).

[0074] Furthermore, in any of the above configurations 1 to 6, the bit line unit is composed of two bit lines (BL, BLC), Some of the aforementioned cells may be configured to consist of transistors connected to either of the two bit lines (seventh configuration).

[0075] Furthermore, a memory device with any of the above configurations is, for example, for automotive use (the eighth configuration).

[0076] Furthermore, the power supply device (5) disclosed herein comprises a memory device having any of the above configurations and a power supply circuit (3A to 3D).

[0077] <7. Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above. [Industrial applicability]

[0078] This disclosure can be used, for example, in an in-vehicle power supply unit. [Explanation of Symbols]

[0079] 1 OTP block 2 Control Unit 3A-3D DC converter circuit 4. Detection Unit 5 Power supply 10 Memory devices 11 input buffers 12 Timing Circuits 13 X Decoders 14 memory cells 15-bit detection unit 15A, 15B Sense Amplifier 16. Data Input / Output Section 21 registers 141 OTP cells 142 ROM cells BL, BLC bit line BU (Bitline Unit) VCC voltage application section W 1 word area WL Wardline X Vehicle X11~X18 Electronic Machines

Claims

1. A wordline selection section configured to select a wordline, A memory cell having cells connected to the word line and bit line units and arranged in a matrix, A bit detection unit configured to detect the logical value of bit data stored in the cell connected to the selected word line via the bit line unit, A data output unit configured to output data based on the detection result of the bit detection unit, Control unit and It has, The memory cell is provided with a standard area connected to a first word line and a fixed area connected to a second word line, and fixed values ​​used in the self-diagnostic function are stored in both areas. The standard area includes a first normal area of ​​a first predetermined number of bits and a first ROM area of ​​a second predetermined number of bits, the fixed value is stored in the first ROM area, and the data to be read when the self-diagnostic function determines that the system is normal is stored in the first normal area. The fixed area is a dedicated area for storing the fixed value, and includes the first predetermined number of bits for the second normal area and the second predetermined number of bits for the second ROM area, with the fixed value stored in both areas. The control unit compares the fixed value read from the standard area and the fixed area of ​​the memory cell via the bit detection unit and the data output unit with the expected value. The first ROM area in a plurality of standard areas having consecutive addresses The fixed value in A indicates the consecutive addresses, A memory device in which the fixed area is assigned the same allocation address as at least a portion of the consecutive addresses, and the fixed value of the second ROM area in the fixed area is the value obtained by inverting the logical value of the bits of the allocation address.

2. The memory device according to claim 1, wherein if all of the fixed values ​​to be read match the expected values, the peripheral circuit of the memory cell is determined to be normal, and data is read from the first normal area of ​​the standard area.

3. The memory device according to claim 1, wherein the fixed values ​​are stored in the first ROM area and the second ROM area for all of the word lines.

4. The memory device according to claim 1, wherein the bit line unit to which the cells included in the second normal area and the cells included in the second ROM area are connected is all of the bit line units.

5. The memory device according to claim 1, wherein the fixed values ​​of the corresponding bits in the second normal area in the two fixed areas are inverted versions of the logical values ​​of the bit data.

6. The aforementioned bit line unit is composed of two bit lines, The memory device according to claim 1, wherein the cell is composed of a transistor connected to one of the two bit lines.

7. The memory device according to claim 1, which is for use in a vehicle.

8. A power supply device comprising a memory device according to any one of claims 1 to 7 and a power supply circuit.

9. A wordline selection section configured to select a wordline, A memory cell having cells connected to the word line and bit line units and arranged in a matrix, A bit detection unit configured to detect the logical value of bit data stored in the cell connected to the selected word line via the bit line unit, A data output unit configured to output data based on the detection result of the bit detection unit, Control unit and It has, A fixed value is stored in some of the cells corresponding to a predetermined number of bits. The control unit compares the fixed value read from some of the cells via the bit detection unit and the data output unit with the expected value. The fixed values ​​stored in some of the cells connected to different word lines of consecutive addresses and connected to the same bit line unit indicate the consecutive addresses. A memory device in which the fixed values ​​stored in each of the cells, which are assigned the same allocation addresses as at least a portion of the aforementioned consecutive addresses, are connected to a word line different from the word line of the aforementioned consecutive addresses, and are connected to the same bit line unit, are the values ​​obtained by inverting the logical values ​​of the bits of the allocation addresses.

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