Ring oscillator-based frequency divider

Abstract

An aspect of the disclosure relates to a ring oscillator (RO) divider configured to divide an input clock by a programmable division ratio to generate an output clock. In this regard, the RO divider receives an input clock and, in response to the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time and outputs a second clock from an output of one stage of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another aspect, each stage includes two PMOS FETs and one NMOS FET.

Description

[Technical Field]

[0001] Cross-reference of related applications This patent application claims priority to U.S. Application No. 17 / 361,217, filed on 28 June 2021, titled "RING OSCILLATOR BASED FREQUENCY DIVIDER," which has been assigned to the assignee of this application and is expressly incorporated herein by reference as described below in its entirety and for all applicable purposes.

[0002] The aspects of this disclosure generally relate to frequency dividers, and more specifically to frequency dividers based on ring oscillators. [Background technology]

[0003] A frequency divider is used to divide an input clock to generate an output clock. Some frequency dividers are part of a phase-locked loop (PLL) feedback path, dividing the output clock generated by a voltage-controlled oscillator (VCO) to generate a feedback clock for phase-frequency comparison with a reference clock. The frequency of the VCO's output clock is controlled based on this comparison so that the feedback clock is substantially phase- and frequency-synchronized with the reference clock. In such cases, the frequency divider is sometimes called a frequency prescaler. In other cases, a frequency divider may simply be used to divide a clock, rather than being part of a PLL feedback path. [Overview of the project] [Means for solving the problem]

[0004] The following provides a simplified overview of one or more implementations to provide a basic understanding of such implementations. This overview is not intended to be a comprehensive overview of all intended implementations, nor is it intended to identify the main or important elements of all implementations, nor to define the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to more detailed explanations that will follow.

[0005] One aspect of the present disclosure relates to an apparatus. The apparatus includes a ring of N cascaded inverter stages, where N is a positive integer, and a control circuit that includes a set of N independent outputs coupled to each of the N cascaded inverter stage rings.

[0006] Another aspect of the present disclosure relates to an apparatus. The apparatus includes a ring of N cascaded inverter stages, where N is a positive integer, and each stage of the ring of N cascaded inverter stages comprises a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), a second PMOS FET, and an n-channel metal oxide semiconductor field effect transistor (NMOS FET) coupled in series between a first voltage rail and a second voltage rail, wherein for an integer "i" from 0 to N-1, the second PMOS FET of the i-th cascaded inverter stage includes a gate coupled to the drain of the second PMOS FET of the i-1(mod N)-th cascaded inverter stage, and for i from 0 to N-1, the first PMOS FET of the i-th cascaded inverter stage includes a gate coupled to the drain of the second PMOS FET of the i-2(mod N)-th cascaded inverter stage, and NMOS Each FET contains a gate for receiving the first clock, and the drain of one of the second PMOS FETs in the N cascaded inverter stage outputs the second clock.

[0007] Another aspect of the present disclosure relates to a method. The method includes the steps of: receiving a first clock; enabling each stage of a ring of N cascaded inverter stages substantially one at a time in response to the first clock in a first mode, wherein N is a positive integer; and outputting a second clock from the output of one of the stages of the ring of N cascaded inverter stages.

[0008] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes a phase-locked loop (PLL) including a frequency prescaler, the PLL including a ring of N cascaded inverter stages, where N is a positive integer, and a circuit for enabling each stage of the ring of N cascaded inverters substantially one at a time based on a first clock, wherein the output of one of the stages of the N cascaded inverter stages generates a second clock; an LO configured to generate a local oscillator (LO) signal based on the second clock; and an upconverter or downconverter configured to upconvert or downconvert the frequency of the first signal, respectively, to generate a second signal based on the LO signal.

[0009] To achieve the above and related objectives, one or more implementations include features that are fully described below and particularly pointed out in the claims. The following description and accompanying drawings illustrate in detail several exemplary embodiments of one or more implementations. However, these embodiments represent only a few of the various ways in which the principles of various implementations may be employed, and the description of the implementations shall include all such embodiments and their equivalents. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a schematic diagram of an exemplary ring oscillator (RO) frequency divider according to one aspect of the present disclosure. [Figure 1B] This is a timing diagram illustrating the exemplary operation of the ring oscillator (RO) divider of Figure 1A, according to another aspect of the present disclosure. [Figure 2A] This is a schematic diagram of another exemplary ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 2B]Figure 2A is a timing diagram illustrating an exemplary sequence in which each stage of the ring of the N cascaded inverter stages of the ring oscillator (RO) shown in another aspect of the present disclosure is turned on substantially one at a time. [Figure 3A] This is a schematic diagram of an exemplary control circuit according to another aspect of the present disclosure. [Figure 3B] This is a timing diagram illustrating the exemplary operation of the control circuit of Figure 3A, according to another aspect of the present disclosure. [Figure 3C] This is a schematic diagram of an exemplary control circuit according to another aspect of the present disclosure. [Figure 4A] This is a schematic diagram of another exemplary ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 4B] Figure 4A shows a timing diagram illustrating the exemplary operation of the ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 5A] This is a schematic diagram of another exemplary ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 5B] A table of various operating frequencies and supply voltages according to another aspect of this disclosure. [Figure 6] This is a schematic diagram of another exemplary ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 7] This is a schematic diagram of another exemplary ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 8] This is a schematic diagram of another exemplary ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 9] This is a schematic diagram of another exemplary ring oscillator (RO) divider according to another aspect of the present disclosure. [Figure 10A] This is a block diagram of an exemplary phase-locked loop (PLL) according to another aspect of the present disclosure. [Figure 10B] Figure 10A is a block diagram of an exemplary N-division frequency divider in a phase-locked loop (PLL) according to another aspect of the present disclosure. [Figure 11] This is a block diagram of another exemplary phase-locked loop (PLL) according to another aspect of the present disclosure. [Figure 12] This is a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. [Figure 13] This is a flowchart illustrating an exemplary method, according to another aspect of the present disclosure, for dividing a first clock to generate a second clock. [Modes for carrying out the invention]

[0011] The detailed descriptions below, along with the accompanying drawings, are intended to describe various configurations and are not intended to represent only configurations in which the concepts described herein can be put into practice. The detailed descriptions include specific details for the purpose of providing a complete understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be put into practice without these specific details. In some cases, well-known structures and components are shown in block diagrams to avoid obscuring such concepts.

[0012] Figure 1A is a schematic diagram of an exemplary ring oscillator (RO) divider 100 according to one aspect of the present disclosure. The RO divider 100 is configured to divide an input clock (CLK_IN) and generate an output clock (CLK_OUT) using a division ratio N defined as the frequency of the input clock CLK_IN with respect to the frequency of the output clock CLK_OUT.

[0013] In this example, the RO divider 100 includes a ring of N cascaded inverter stages 105-0 to 105-4 (for example, N is 5, but may be any other positive integer), each cascaded inverter stage including a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET) coupled in series with an n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET) between an upper voltage rail VDD and a lower voltage rail (for example, ground). In this example and the embodiments described below, N may represent a positive integer greater than or equal to 2 or 3. For example, embodiments where N is equal to 3, 5, or 7 are described below, but in the embodiments described, N may be any other positive integer greater than or equal to 2 or 3. Cascaded inverter stage 105-0 includes PMOS FET MP0 and NMOS FET MN0. Cascaded inverter stage 105-1 includes PMOS FET MP1 and NMOS FET MN1. The cascaded inverter stage 105-2 includes PMOS FET MP2 and NMOS FET MN2. The cascaded inverter stage 105-3 includes PMOS FET MP3 and NMOS FET MN3. The cascaded inverter stage 105-4 includes PMOS FET MP4 and NMOS FET MN4. In the round-robin or modulo-N scheme, for all stages (for example, for an integer "i" from 0 to N-1), the gate of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain of the PMOS FET of the i-1(modN)th cascaded inverter stage.

[0014] The RO divider 100 includes an input buffer 110 with an input for receiving the input clock CLK_IN and an output coupled to the gates of the NMOS FETs MN0 to MN4. The RO divider 100 further includes an output buffer 130 with an input coupled to the drain of the PMOS FET MP4 or to the output n4 of the cascaded inverter stages 105-4 and an output for generating the output clock CLK_OUT. As shown, each of the N sets of cascaded inverter stages 105-0 to 105-4 includes its respective input at the gates of the PMOS FETs MP0 to MP4. Each of the N sets of cascaded inverter stages 105-0 to 105-4 includes its respective output at the drains of the PMOS FETs MP0 to MP4 or at nodes n0 to n4.

[0015] Figure 1B shows a timing diagram of exemplary operation of the RO divider 100 according to another aspect of the present disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, the input clock CLK_IN and the voltages V at the outputs n0 to n4 of the cascaded inverter stages 105-0 to 105-4, respectively. n0 From V n4 The following is presented. The left side of the timing diagram (between times t1 and t7) represents an example of normal operation of the RO frequency divider 100. The right side of the timing diagram (between times t8 and t12) represents an example of abnormal operation of the RO frequency divider 100.

[0016] The RO frequency divider 100 operates by substantially simultaneously turning on all of the NMOS FETs MN0 to MN4 (enabling all of the inverter stages 105-0 to 105-4) in response to each rising edge or high state of the input clock CLK_IN. For example, referring to the left side of the timing diagram, at time t1, the rising edge of the input clock CLK_IN turns on the NMOS FET MN0 and turns off the PMOS FET MP0, so a high voltage V n0 Set (for example, the one at VDD) low (for example, to ground). Voltage V n0When it goes low, at time t2, PMOS FET MP1 turns on and raises voltage V n1 to high. The next rising edge of the input clock CLK_IN at time t3 turns on NMOS FET MN2 and PMOS FET MP2 is off, so it lowers the high voltage V n2 to low and voltage V n2 goes low. When voltage V n3 goes low, at time t4, PMOS FET MP3 turns on and raises voltage V n4 to high. The rising edge of the input clock CLK_IN at time t5 turns on NMOS FET MN4 and PMOS FET MP4 is off, so it lowers the high voltage V n4 to low and voltage V n0 goes low. When voltage V n0 goes low, at time t6, PMOS FET MP**0** turns on and raises voltage V

[0017] [[ID=Note that half of the period of voltage V n0 is over 2.5 cycles of the input clock CLK_IN. Thus, the RO divider 100 divides the input clock CLK_IN by 5 or by N. In this implementation, the voltage at one node needs to remain high even when the corresponding NMOS FET is turned on by the input clock CLK_IN. For example, as shown in the timing diagram, voltages V n2 and V n4 remain high from time t1 to t2 during the high state of the input clock CLK_IN when the corresponding NMOS FETs MN2 and MN4 are on. This is because the corresponding PMOS FETs MP2 and MP4 are on during this time interval from t1 to t2. To maintain the output voltage high when the corresponding NMOS FET is on, the PMOS FET may be made stronger or larger than the NMOS FET. As a result, in some embodiments, the RO divider 100 may have some drawbacks.

[0018] Firstly, larger PMOS FETs can introduce additional parasitic capacitance, and smaller NMOS FETs can have weaker pull-downs; both of these can introduce significant delays to the frequency division operation of the RO divider 100. Therefore, the RO divider 100 may have a maximum operating frequency limited by the size difference between the PMOS and NMOS FETs. Secondly, since the PMOS and NMOS FETs are turned on substantially simultaneously, large currents can flow through the cascaded inverter stages. Therefore, the RO divider 100 may consume a large amount of power. Thirdly, at low input frequencies, each cascaded inverter stage of the RO divider 100 can generate multiple pull-downs to lower the corresponding output voltage from a high state (e.g., VDD) to a low state (e.g., ground). Therefore, the lowest operating frequency of the RO divider 100 may also be affected. The right side of the timing diagram illustrates this problem.

[0019] For example, the rising edge of the input clock CLK_IN at time t9 turns on the NMOS FET MN0, and a high voltage V n0 Set (for example, the one at VDD) low (for example, to ground). Voltage V n0 When it goes low, the PMOS FET MP1 turns on and the voltage V n1 Set it to high. Then, voltage V n1 When it goes high, the voltage V n2 The voltage V becomes low to some extent (e.g., VDD / 2), and all of this happens between time t9 and t10, while the input clock CLK_IN is high. This is because the frequency FIN of the input clock CLK_IN is low enough that the corresponding period is when the voltage V is high during the high state of the input clock CLK_IN. n0 From V n2 This is because it is large enough to change. Then, the next rising edge of the input clock CLK_IN at time t11 turns on the NMOS FET MN2, and the voltage V n2 Set it completely low (for example, to ground). Voltage V n2When the voltage goes low, the PMOS FET MP3 turns on, and after time t11, the voltage V n3 Set it to high. Voltage V n3 When it goes high, the PMOS FET MP4 turns off, and the NMOS FET MN4 turns on to voltage V n4 This makes it possible to lower the voltage V. n0 Since half of this period corresponds to approximately 1.5 to 2 clock cycles of the input clock CLK_IN, the RO divider 100 did not divide the input clock CLK_IN by exactly 5. Therefore, the RO divider 100 may have a minimum operating frequency.

[0020] Figure 2A shows a schematic diagram of an exemplary ring oscillator (RO) divider 200 according to another aspect of the present disclosure. In summary, unlike RO divider 100, where the input clock CLK_IN turns on the NMOS FETs of a cascaded inverter stage substantially simultaneously, RO divider 200 includes a control circuit driven by the input clock CLK_IN to turn on the NMOS FETs substantially one at a time (or in a substantially non-overlapping manner). Thus, the NMOS FETs MN0 to MN4 each have different control voltages V generated by the control circuit. A From V E It is driven by.

[0021] More specifically, the RO divider 200 includes a ring of N (for example, N=5 in the example shown) cascaded inverter stages 205-0 through 205-(N-1), each stage including a PMOS FET coupled in series with an NMOS FET between the upper voltage rail VDD and the lower voltage rail (for example, ground). For example, cascaded inverter stage 205-0 includes PMOS FET MP0 and NMOS FET MN0. Cascaded inverter stage 205-1 includes PMOS FET MP1 and NMOS FET MN1. Cascaded inverter stage 205-2 includes PMOS FET MP2 and NMOS FET MN2. Cascaded inverter stage 205-3 includes PMOS FET MP3 and NMOS FET MN3. Cascaded inverter stage 205-4 includes PMOS FET MP4 and NMOS FET MN4. In the round-robin or modN scheme, for every stage (for example, for an integer i from 0 to N-1), the gate of the PMOS FET in the i-th cascaded inverter stage is coupled to the drain of the PMOS FET (and the drain of the NMOS FET) in the i-1(modN)th cascaded inverter stage.

[0022] The RO divider 200 further includes a control circuit 210 which includes an input for receiving an input clock CLK_IN and a set of N (e.g., N=5) independent outputs, each coupled to the gates of NMOS FETs MN0 to MN4. The control circuit 210 controls a set of control voltages V in the set of N independent outputs to turn on each of the NMOS FETs MN0 to MN4 substantially one at a time (e.g., in a substantially non-overlapping manner). A From V E It is configured to generate up to . As shown, the RO divider 200 further includes an output buffer 230 which includes an input coupled to the output (e.g., node n4) of one of the cascaded inverter stages (e.g., stage 205-4), and an output from which the output clock CLK_OUT is generated.

[0023] Figure 2B shows a timing diagram of an exemplary sequence for turning on NMOS FETs MN0 to MN4 of a set of N cascaded inverter stages 205-0 to 205-4 substantially one at a time, according to another aspect of the present disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, the input clock CLK_IN and the control voltage V A , V C , V E , V B , and V D These also represent the voltages Vn0 to Vn4 at nodes n0 to n4 (outputs) of the cascaded inverter stages 205-0 to 205-4, respectively.

[0024] As shown, the control circuit 210 responds to a first positive pulse of the input clock CLK_IN with a control voltage V that is substantially simultaneous with the first positive pulse of the input clock CLK_IN. A During the first positive pulse of the input clock CLK_IN, the control circuit 210 generates the other control voltage V B From V E Maintain the control voltage V in a low logic state (e.g., ground). A This turns on the NMOS FET MN0 of the cascaded inverter stage 205-0, but the control voltage V B From V E These keep the NMOS FETs MN1 to MN4 of the cascaded inverter stages 205-1 to 205-4 turned off, respectively. Therefore, during the first positive pulse of the input clock CLK_IN, the control circuit 210 enables the first cascaded inverter stage 205-0, but disables the remaining cascaded inverter stages 205-1 to 205-4 (for example, enabling one cascaded inverter stage at a time). In response to the NMOS FET MN0 being turned on, the output voltage V of the first cascaded inverter stage 205-0 is turned off, as indicated by the arrow line. n0 The voltage V becomes low. n0In response to the signal going low, the output voltage V of the second cascaded inverter stage 205-1 n1 He gets high.

[0025] Similarly, in response to the second positive pulse of the input clock CLK_IN, the control circuit 210 sets a control voltage V with a positive pulse substantially simultaneous with the second positive pulse of the input clock CLK_IN. C While generating other control voltages V A , V B , V D , and V E Maintain the control voltage V in a low logic state (e.g., ground). C This turns on the NMOS FET MN2 of the cascaded inverter stage 205-2, but the control voltage V A , V B , V D , and V E These keep NMOS FETs MN0 through MN1 and MN3 through MN4 off, respectively. Therefore, during the second positive pulse of the input clock CLK_IN, the control circuit 210 enables cascaded inverter stage 205-2, but disables the remaining cascaded inverter stages 205-0, 205-1, 205-3, and 205-4 (for example, enabling one cascaded inverter stage at a time). In response to the NMOS FET MN2 being turned on, the output voltage V of cascaded inverter stage 205-2 increases as indicated by the arrow line. n2 The voltage V becomes low. n2 In response to the signal going low, the output voltage V of the cascaded inverter stage 205-3 n3 He gets high.

[0026] Similarly, as indicated by the corresponding arrow lines, only the other cascaded inverter stages 205-4, 205-1, and 205-3 are turned on or enabled during the third, fourth, and fifth positive pulses of the input clock CLK_IN, respectively. As shown, the output voltage V of the cascaded inverter stage 205-0n0 This has a period that extends from the first positive pulse to the fifth positive pulse of the input clock CLK_IN. Other output voltage V n1 From V n4 The output voltage V n0 It has essentially the same duration. Therefore, the frequency of the output clock CLK_OUT is 1 / 5 or (1 / N) of the frequency of the input clock CLK_IN (in other words, the division ratio is 5 or N).

[0027] Since the N cascaded inverter stages are enabled one at a time, the PMOS FETs and NMOS FETs in each stage are not turned on simultaneously. Therefore, the PMOS FETs do not need to be configured to be stronger or larger than the NMOS FETs to implement the ratio logic, as in the RO divider 100, and in some embodiments of the RO divider 200, each of the PMOS FETs MP0 to MP(N-1) is approximately the same size as the respective NMOS FETs MN0 to MN(N-1). This reduces the large parasitic capacitance of the PMOS FETs, as well as the relatively weak pull-down of the NMOS FETs. This can reduce the propagation delay of the cascaded inverter stages 205-0 to 205-(N-1), allowing the RO divider 200 to operate at higher frequencies and, in some cases, with less power consumption. At lower frequencies, since there are no turned-on PMOS FETs resisting pull-down, the NMOS FETs can fully pull down the corresponding output voltage during each clock cycle. Therefore, the RO divider 200 can eliminate the multiple pull-downs per clock cycle that may occur in the RO divider 100.

[0028] It should be understood that the timing diagram shown in Figure 2B is merely an example. For example, the diagram in Figure 2B corresponds to a configuration in which a high pulse of the clock triggers a certain operation of the frequency divider (e.g., activation of one stage), but in other embodiments, the operation (e.g., activation of one stage) may be triggered by the clock being a low value or transitioning to a low value. One such embodiment is described below with respect to Figures 3A and 3B. Other such embodiments are described below with respect to subsequent figures.

[0029] Figure 3A shows a schematic diagram of an exemplary control circuit 300 according to another aspect of the present disclosure. The control circuit 300 may be one exemplary implementation of the control circuit 210 discussed previously. The control circuit 300 includes an input buffer 305 and a set of N (for example, N=5 in the example shown) NOR gates 320-0 to 320-4. The input buffer 305 includes an input for receiving the input clock CLK_IN. The set of NOR gates 320-0 to 320-4 includes a first input, each coupled to the output of the input buffer 305. The set of NOR gates 320-0 to 320-4 includes a second input, each coupled to the output nodes n3, n4, n0, n1, and n2 of the cascaded inverter stages 205-3, 205-4, 205-0, 205-1, and 205-2. The set of NOR gates 320-0 to 320-4 includes a set of outputs, in which the control voltage V A , V B , V C , V D , and V E These are generated and coupled to the gates of the NMOS FETs MN0 to MN4 of the cascaded inverter stages 205-0 to 205-4, respectively.

[0030] Generally, for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 320-i) is coupled to the drain (output) of the i-2(modN)th PMOS (and NMOS) FET of the cascaded inverter stage. Considering a few examples, for i=0, the second input of the NOR gate 320-0 is coupled to the output node n3 of the cascaded inverter stage 205-3 (output voltage V n3 It includes (to receive) i-2(mod5)=0-2(mod5)=-2(mod5)=3. Similarly, for i=1, the NOR gate 320-1 is coupled to the second input (output voltage V) of the cascaded inverter stage 205-4 at output node n4. n4 It includes (to receive) i-2(mod5)=1-2(mod5)=-1(mod5)=4. For i=2, the NOR gate 320-2 is coupled to the second input (output voltage V) of the cascaded inverter stage 205-0 output node n0. n0 It includes the condition to receive i-2(mod 5)=2-2(mod 5)=0(mod 5)=0, and so on.

[0031] In other embodiments (not shown), for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 320-i) is coupled to the drain (output) of the i-4(modN)th cascaded inverter stage PMOS (and NMOS) FET. For example, for i=0, the NOR gate 320-0 has a second input (output voltage V) coupled to the output node n1 of the cascaded inverter stage 205-1. n1 It may include a for receiving i-4(mod5)=0-4(mod5)=-4(mod5)=1. In some embodiments, for "i" from 0 to N-1, the second input of the i-th NOR gate is coupled to the drain (output) of the iE(modN)-th cascaded inverter stage PMOS (and NMOS) FET, where E represents a positive even number less than N.

[0032] Figure 3B shows a timing diagram of exemplary operation of the control circuit 300 according to another aspect of the present disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, the input clock CLK_IN and the control voltage V A , V C , V E , V B , and V D These also represent the voltages Vn0 to Vn4 at the output nodes n0 to n4 of the cascaded inverter stages 205-0 to 205-4, respectively.

[0033] As shown, the NOR gate 320-0 of the control circuit 300 receives the first negative pulse of the input clock CLK_IN and the output voltage V n3 In response to being in a low logic state, the control voltage V is accompanied by a positive pulse substantially simultaneous with the first negative pulse of the input clock CLK_IN, as indicated by the arrow line. A During the first negative pulse of the input clock CLK_IN, the other NOR gates 320-1 to 320-4 of the control circuit 300 generate the other control voltage V. B From V E This maintains the logic state as low. Therefore, the control voltage V A This turns on the NMOS FET MN0 of the cascaded inverter stage 205-0, but the control voltage V B From V E This keeps NMOS FETs MN1 through MN4 off. In response to the NMOS FET MN0 being turned on, the output voltage V of the cascaded inverter stage 205-0 n0 The voltage V becomes low. n0 In response to the signal going low, the output voltage V of the cascaded inverter stage 205-1 n1 He gets high.

[0034] Similarly, the NOR gate 320-2 of the control circuit 300 receives the second negative pulse of the input clock CLK_IN and the output voltage V n0In response to being in the low logic state, a control voltage V with a positive pulse substantially simultaneous with the second negative pulse of the input clock CLK_IN is generated as indicated by the arrow line. C During the second negative pulse of the input clock CLK_IN, the other NOR gates 320-0, 320-1, 320-3, and 320-4 of the control circuit 300 maintain the other control voltages V A , V B , V D , and V E in the low logic state. Thus, the control voltage V C turns on the NMOS FET MN2 of the cascade-connected inverter stage 205-2, but the control voltages V A , V B , V D , and V E maintain the NMOS FETs MN0, MN1, MN3, and MN4 off. In response to the turned-on NMOS FET MN2, the output voltage V n2 of the cascade-connected inverter stage 205-2 goes low. Also, in response to the voltage V n2 going low, the output voltage V n3 of the cascade-connected inverter stage 205-3 goes high.

[0035] In a similar manner, as indicated by the corresponding arrow lines, only the other cascade-connected inverter stages 205-4, 205-1, and 205-3 are turned on or enabled during the third, fourth, and fifth negative pulses of the input clock CLK_IN. As shown, the output voltage V n0 of the first cascade-connected inverter stage has a period extending from the first negative pulse to the fifth negative pulse of the input clock CLK_IN. The other output voltages V n1 to V n4 have substantially the same period as the output voltage V n0 . Thus, the frequency of the output clock CLK_OUT is ⅕ or 1 / N of the frequency of the input clock CLK_IN (in other words, the division ratio is 5 or N).

[0036] Voltage V at the second input of NOR gates 320-0 to 320-4 no From V n4 It should be noted that the logic state is low substantially one clock cycle before the NOR gates 320-0 through 320-4 generate their respective positive pulses. Therefore, the control circuit 300 does not introduce any additional delay to the frequency division operation of the RO divider 200.

[0037] Figure 3C shows a schematic diagram of an exemplary control circuit 350 according to another aspect of the present disclosure. The control circuit 350 may be one exemplary implementation of the control circuit 210 discussed previously. In contrast to the control circuit 300, as described, for example, in relation to Figure 2, the control circuit 350 is configured such that a high pulse of the clock triggers some operation of the frequency divider (e.g., activation of one of the stages 205 of the frequency divider 200).

[0038] The control circuit 350 includes an input buffer 305 and a set of N (for example, N=5 in the example shown) AND gates 370-0 to 370-4. The input buffer 305 includes an input for receiving the input clock CLK_IN. The set of AND gates 370-0 to 370-4 each includes a first input coupled to the output of the input buffer 305. The set of AND gates 370-0 to 370-4 each includes a second input coupled to the output nodes n2, n3, n4, n0, and n1 of the cascaded inverter stages 205-2, 205-3, 205-4, 205-0, and 205-1, respectively. The set of AND gates 370-0 to 370-4 includes a set of outputs, in which the control voltage V A , V B , V C , V D , and V E These are generated and coupled to the gates of the NMOS FETs MN0 to MN4 of the cascaded inverter stages 205-0 to 205-4, respectively.

[0039] Generally, for "i" from 0 to N-1, the second input of the i-th AND gate (e.g., 370-i) is coupled to the drain (output) of the i-3(modN)th PMOS (and NMOS) FET of the cascaded inverter stage. Considering a few examples, for i=0, the second input of the AND gate 370-0 is coupled to the output node n2 of the cascaded inverter stage 205-2 (output voltage V n2 It includes a second input (output voltage V) which is coupled to the output node n3 of the cascaded inverter stage 205-3. n3 It includes receiving i-2(mod5)=1-3(mod5)=-2(mod5)=3. For i=2, AND gate 370-2 is coupled to the second input (output voltage V) connected to the output node n4 of the cascaded inverter stage 205-4. n4 This includes the part for receiving i, i-3(mod 5)=2-3(mod 5)=-1(mod 5)=4, and so on.

[0040] In other embodiments (not shown), for "i" from 0 to N-1, the second input of the i-th AND gate (e.g., 370-i) is coupled to the drain (output) of the i-1(mod N)th PMOS (and NMOS) FET of the cascaded inverter stage. For example, for i=0, the second input (output voltage V) of the AND gate 370-0 is coupled to the output node n4 of the cascaded inverter stage 205-4. n4 It may include a for receiving i-1(mod5)=0-1(mod5)=-1(mod5)=4. In some embodiments, for "i" from 0 to N-1, the second input of the i-th AND gate is coupled to the drain (output) of the iR(modN)-th cascaded inverter stage PMOS (and NMOS) FET, where R represents a positive odd number less than N-1.

[0041] Figure 4A shows a schematic diagram of an exemplary RO divider 400 according to another aspect of the present disclosure. The RO divider 400 is similar to the RO divider 200 but includes pre-discharge NMOS FETs to configure the RO divider 400 to its initial state by explicitly pre-discharging the output nodes of every other N cascaded inverter stages at startup. Furthermore, dummy NMOS FETs are coupled to the output nodes of the remaining cascaded inverter stages that do not have pre-discharge NMOS FETs in order to balance the load of each cascaded inverter stage. In addition, the RO divider 400 is configured to divide by 5 or by 4 (e.g., by N or N-1) based on the division ratio mode signal. Thus, the RO divider 400 may be called a dual modulus divider, or more commonly, a multimodulus divider. Although not explicitly shown in some subsequent figures, pre-discharge FETs and dummy FETs may be implemented in any of the RO dividers exemplified and / or described in this application.

[0042] More specifically, the RO divider 400 includes a ring of N (for example, N=5 in the shown embodiment) cascaded inverter stages 405-0 to 405-4, each stage comprising a PMOS FET coupled in series with an NMOS FET between an upper voltage rail VDD and a lower voltage rail (for example, ground). As in the RO divider 200, for all stages (for example, for an integer i from 0 to N-1), the gate of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain of the PMOS FET of the i-1(modN)-th cascaded inverter stage (and the drain of the series NMOS FET).

[0043] In addition to the PMOS FETs coupled in series with the NMOS FETs, the cascaded inverter stages 405-1 and 405-3 each include NMOS FETs MN7 and MN9 coupled between the drains of PMOS FETs MP1 and MP3 and the lower voltage rail (e.g., ground), respectively. The NMOS FETs MN7 and MN9 include gates for receiving a pre-discharge signal P. To ensure that the loads presented to the output nodes n0 to n4 of the cascaded inverter stages 405-0 to 405-4 are substantially balanced, the cascaded inverter stages 405-0, 405-2, and 405-4 each include dummy NMOS FETs MN6, MN8, and MN10 coupled between the drains of PMOS FETs MP0, MP2, and MP4 and the lower voltage rail (e.g., ground), respectively. The dummy NMOS FETs MN6, MN8, and MN10 include gates coupled to the lower voltage rail (e.g., ground) to turn off these devices. A dummy FET as defined herein is a dummy FET that is permanently turned off, for example, by setting the gate-source voltage to 0 or below the threshold voltage of the dummy FET.

[0044] To achieve dual-modulus functionality, the cascaded inverter stages 405-4 further connect the gate of the NMOS FET MN4 to the corresponding output of the control circuit 410 (for example, V E The j-th cascaded inverter stage includes one or more switching devices for selective coupling to the output of the control circuit 410 or the drain (output n3) of the PMOS FET MP3 of the preceding cascaded inverter stage 405-3. Generally, the j-th cascaded inverter stage, which includes one or more such switching devices to achieve dual-modulus or multi-modulus functionality, includes an NMOS FET whose gate is coupled to either the j-th output of the control circuit 410 or the drain of the PMOS FET of the j-1-th cascaded inverter stage, based on the state of one or more switching devices, where "j" is a positive integer less than or equal to N-1 or zero.

[0045] More specifically, in the cascaded inverter stage 405-4 in the shown embodiment, one or more switching devices include a PMOS FET MP6 coupled between the drain of the PMOS FET MP3 of the preceding cascaded inverter stage 405-3 and the gate of the NMOS FET MN4. One or more switching devices further include a V of the control circuit 410. E The configuration includes an NMOS FET MN11 coupled between the output and the gate of an NMOS FET MN4. The PMOS FET MP6 and the NMOS FET MN11 include gates coupled together to receive a ratio divide mode signal. It will be understood that other configurations of one or more switching devices configured to perform the functions described herein may be implemented (for example, as illustrated / described with respect to subsequent figures).

[0046] When the frequency division ratio mode signal is in a high logic state (e.g., VDD), the PMOS FET MP6 is turned off and the NMOS FET MN11 is turned on. Therefore, the gate of the NMOS FET MN4 is connected to the V of the control circuit 410. E Coupled to the output, RO divider 400 operates as a 5 divider (N divider), similar to RO divider 200. When the divider mode signal is in a low logic state, PMOS FET MP6 is turned on and NMOS FET MN11 is turned off. Thus, the gate of NMOS FET MN4 is coupled to the drain of PMOS FET MP3 of the preceding cascaded inverter stage 405-3, and the final stage 405-4 is coupled to the clock phase or V related to the preceding cascaded inverter stage 405-3. DBecause it is enabled by this, the RO divider 400 operates as a 4 divider ((N-1) divider). For example, in this configuration, the last stage 405-4 may be configured to function as an inverter. Thus, the division ratio, which is the frequency of the input clock relative to the frequency of the output clock, is greater when the gate of the NMOS FET of the j-th cascaded inverter stage is coupled to the j-th output of the control circuit than when the gate of the NMOS FET of the j-th cascaded inverter stage is coupled to the drain of the PMOS FET of the (j-1)-th cascaded inverter stage.

[0047] RO divider 400 further includes a control circuit 410, which may be similar to the control circuits 210, 300, or 350 discussed in detail earlier, but includes additional logic circuits for asserting / deasserting a pre-discharge signal P in response to a start signal and an input clock CLK_IN. Similar to RO divider 200, RO divider 400 further includes an output buffer 430, which includes an input coupled to the output (e.g., node n0) of one of the cascaded inverter stages (e.g., stage 405-0) and an output from which the output clock CLK_OUT is generated.

[0048] Figure 4B shows a timing diagram of exemplary operation of the RO divider 400 according to another aspect of the present disclosure. The x-axis or horizontal axis of the timing diagram represents time. The y-axis or vertical axis of the timing diagram represents, from top to bottom, the start signal, pre-discharge signal P, input clock CLK_IN, and control voltage V A , V C , V E , V B , and V D , and the voltage V at output nodes n0 to n4 of the cascaded inverter stages 405-0 to 405-4, respectively. n0 From V n4 This represents the frequency division ratio mode signal being in a low state, so the RO frequency divider 400 is configured to divide the frequency by 4.

[0049] For example, when the start signal is deasserted before the pulse "0" of the input clock CLK_IN, the control circuit 410 isolates the input clock CLK_IN from the logic circuits of the control circuit 410 (e.g., a NOR gate). In response to the assertion of the start signal and the rising edge or pulse "0" of the input clock CLK_IN, the control circuit 410 asserts the pre-discharge signal P (e.g., sets it to a high logic state) to turn on the NMOS FETs MN7 and MN9. As shown by the arrow line in the timing diagram, this is due to voltage V n1 and V n3 Nodes n1 and n3 are clearly discharged, as indicated by the low logical state.

[0050] In response to the rising edge of pulse "1" of the input clock CLK_IN, the control circuit 410 deasserts the pre-discharge signal P to turn off the NMOS FETs MN7 and MN9, allowing nodes n1 and n3 to reach the appropriate voltage level according to the frequency division operation. Also in response to the rising edge of pulse "1", the control circuit 410 sets a control voltage V with a pulse substantially simultaneous with pulse "1" of the input clock CLK_IN. A Generates the control voltage V. A In response to the high state, NMOS MN0 turns on, and the output voltage V of the cascaded inverter stage 405-0 is turned on. n0 When it goes low, the output voltage V n0 When it goes low, the PMOS FET MP1 of the cascaded inverter stage 405-1 turns on, and the output voltage V n1 They get high.

[0051] In response to the rising edge of pulse "2", the control circuit 410 controls the control voltage V with a pulse substantially simultaneous with pulse "2" of the input clock CLK_IN. C Generates the control voltage V. C In response to the high state, NMOS MN2 turns on, and the output voltage V of the cascaded inverter stage 405-2 is turned on. n2 When it goes low, the output voltage V n2When it goes low, the PMOS FET MP3 of the cascaded inverter stage 405-3 turns on, and when the PMOS FET MP3 turns on, the output voltage V n3 When it goes high, the output voltage V n3 When this becomes high, the cascaded inverter stage 405-4 is coupled to node n3 in 4-division mode, so the NMOS FET MN4 of the cascaded inverter stage 405-4 turns on, and when the NMOS FET MN4 turns on, the output voltage V of the cascaded inverter stage 405-4 n4 When it goes low, the output voltage V n4 When the signal goes low, the PMOS FET MP0 turns on, and when the PMOS FET MP0 turns on, the output voltage V n0 They get high.

[0052] In response to the rising edge of pulse "3", the control circuit 410 controls the control voltage V with a pulse substantially simultaneous with pulse "3" of the input clock CLK_IN. B Generates the control voltage V. B In response to the high state, NMOS MN1 turns on, and the output voltage V of the cascaded inverter stage 405-1 is turned on. n1 When it goes low, the output voltage V n1 When it goes low, the PMOS FET MP2 of the cascaded inverter stage 405-2 turns on, thereby changing the output voltage V n2 They get high.

[0053] In response to the rising edge of pulse "4", the control circuit 410 controls the control voltage V with a pulse substantially simultaneous with pulse "4" of the input clock CLK_IN. D Generates the control voltage V. D In response to the high state, NMOS MN3 turns on, and the output voltage V of the cascaded inverter stage 405-3 is turned on. n3 When it goes low, the output voltage V n3 When it goes low, the PMOS FET MP4 of the cascaded inverter stage 405-4 turns on, and the output voltage Vn4 goes high.

[0054] In response to the rising edge of pulse "5", the frequency division process shown for pulses 1-4 is repeated. As shown, the output voltage V of the cascaded inverter stage 405-0 n0 Since this has a period equivalent to substantially four periods of the input clock CLK_IN, the RO divider 400 performs a 4-division operation. In 4-division mode, the control circuit 410 controls the control voltage V in its sequence for each input clock pulse. A , V C , V B , and V D Note that asserting this is required. In some embodiments, the control voltage V E Since it is not used in the 4-division mode, the control circuit 410 controls the control voltage V E Skip (or V E It is configured to output a constant low voltage instead of a regular low voltage. Alternatively, the control circuit 410 may be configured as shown in Figure 3A (or as shown in Figure 3C when a clock high trigger is implemented) to pass an input mode signal to a frequency divider 400, or to generate a mode signal for the frequency divider 400 based on a mode control input to the control circuit 410. In some embodiments, for example, the first input of the NOR gate 320-4 is selectively coupled to either the output of the input buffer 305 or a constant input voltage (e.g., VDD, so that the NOR gate 320-4 outputs a low voltage) based on a mode signal or mode control input received in the control circuit. In other embodiments, a pulse is generated by the NOR gate 320-4 but is substantially interrupted by the NMOS FET MN11.

[0055] Figure 5A shows a schematic diagram of another exemplary RO divider 500 according to another aspect of the present disclosure. The RO divider 500 is similar to the RO divider 400 and includes many of the same elements, indicated by the same markings and reference numbers, except that the most significant digit (MSD) is "5" instead of "4". Subsequent figures also use this numbering convention. The RO divider 500 further includes a low-dropout (LDO) voltage regulator 550 for selectively changing the supply voltage Vreg (the difference in supply voltage between a first voltage rail and a second voltage rail) supplied to a ring of N (for example, N=5 in the shown example) cascaded inverter stages 505-0 to 505-4 using a programmable reference voltage Vref.

[0056] More specifically, the LDO voltage regulator 550 includes an operational amplifier 555 and a PMOS FET MP7. The PMOS FET MP7 is coupled between the upper voltage rail VDD and the intermediate voltage rail at the sources of the PMOS FETs MP0 to MP4 of the cascaded inverter stages 505-0 to 505-4. The operational amplifier 555 includes a first (e.g., negative) input for receiving a programmable voltage Vref, a second (e.g., positive) input coupled to the intermediate voltage rail, and an output coupled to the gate of the PMOS FET MP7. The LDO voltage regulator 550 is configured to generate and control the supply voltage Vreg at the intermediate voltage rail for the cascaded inverter stages 505-0 to 505-4 such that the supply voltage Vreg is substantially the same as the programmable reference voltage Vref.

[0057] The supply voltage Vreg substantially sets the operating frequency range of the RO divider 500. For example, if a relatively high frequency range or highest operating frequency is desired, the programmable voltage Vref can be set relatively high to provide a relatively high supply voltage Vreg for the cascaded inverter stages 505-0 to 505-4. A higher supply voltage Vreg reduces the individual delay of each of the cascaded inverter stages 505-0 to 505-4, allowing the RO divider 500 to operate better at higher frequencies. If a relatively low frequency range or lowest operating frequency is desired, the programmable reference voltage Vref can be set relatively low to provide a relatively low supply voltage Vreg for the cascaded inverter stages 505-0 to 505-4. A lower supply voltage Vreg increases the individual delay of each of the cascaded inverter stages 505-0 to 505-4, allowing the RO divider 500 to operate better at lower frequencies. In some configurations, the shown configuration of the LDO voltage regulator 550 allows for an improvement in the minimum operating frequency without degrading the maximum operating frequency of the RO divider 500. The LDO voltage regulator 550 may be coupled between a voltage rail (e.g., VDD) and the inverter stage of any of the RO dividers exemplified and / or described in this application (e.g., divider 200 or any of the dividers in the subsequent figures).

[0058] Figure 5B shows an exemplary operating frequency and supply voltage table according to another aspect of the present disclosure. The top row represents the supply voltage Vreg in volts (V), the second row from the top represents the exemplary minimum operating frequency when the frequency divider 500 operates in 4-division mode with the supply voltage in the top row, the third row from the top represents the exemplary maximum operating frequency when the frequency divider 500 operates in 4-division mode with the supply voltage in the top row, the fourth row from the top represents the exemplary minimum operating frequency when the frequency divider 500 operates in 5-division mode with the supply voltage in the top row, and the fifth row from the top represents the exemplary maximum operating frequency when the frequency divider 500 operates in 5-division mode with the supply voltage in the top row.

[0059] As shown in the table, the operating frequency and / or range can be changed by adjusting the supply voltage Vreg. In some examples, with a supply voltage of 0.5V, the minimum operating frequency for 4-division and 5-division may be about 17.5GHz, and the maximum operating frequencies for 4-division and 5-division may be about 25GHz and 32.5GHz, respectively. Thus, the operating frequency range with Vreg at 0.5V may be at least 17.5GHz to 25GHz, and in some cases, depending on the mode, it may extend up to 32.5GHz in the examples shown. Considering another example, with a supply voltage of 0.7V, the minimum operating frequency for 4-division and 5-division may be about 27.5GHz to 30GHz, and the maximum operating frequencies for 4-division and 5-division may be about 47.5GHz and 55GHz, respectively. Thus, the operating frequency range with Vreg at 0.5V may be at least 27.5GHz to 47.5GHz, and in some cases, depending on the mode, it may extend up to 55GHz in the examples shown.

[0060] Therefore, it can be seen that the minimum operating frequency of the example shown in Figure 5B can be improved from 30 GHz to 17.5 GHz or less (for example, in a 5-division mode) by adjusting the supply voltage. Furthermore, it can be seen that in some embodiments, the maximum operating frequency may reach 55 GHz or higher. Thus, the minimum and / or maximum operating frequencies (and frequency ranges) can be improved without, for example, one adversely affecting the other. In some such embodiments, this improved performance can be achieved with the same or lower power consumption compared to known configurations. Furthermore, in some embodiments, the improved operating frequency can be achieved at a smaller process node compared to known configurations. For example, embodiments described herein can enable operation at relatively high frequencies (e.g., 50-55 GHz or higher) using processes of 8 nm or less (e.g., 8-nanometer (nm) FinFET process technology, such as 8LPP (Low Power Plus)).

[0061] It will be understood that the values ​​described herein are merely examples of some embodiments, and that frequencies, ranges, supply voltages, process nodes, etc., may differ from those shown in Figure 5B and / or described herein. Furthermore, it will be understood that while some examples are shown in Figure 5B, such examples are not necessarily linked to or associated with the examples shown in Figure 5A. For example, the elements in Figure 5B may be associated with configurations similar to those of frequency dividers 200 and / or 400.

[0062] Figure 6 shows a schematic diagram of another exemplary ring oscillator (RO) divider 600 according to another aspect of the present disclosure. In the previous example, the RO divider was configured to perform a 5-division or 4-division because the RO divider had five cascaded inverter stages, which resulted in a division ratio of 5 or N when all operated with separate clocks, and a division ratio of 4 or N-1 when the last stage was bypassed or operated with the phase of the clock given to the previous stage. However, it should be understood that the RO divider does not have to be limited to N being 5, but can be any other positive integer.

[0063] For example, the RO divider 600 includes a ring of N (N=3 in the shown embodiment) cascaded inverter stages 605-0 to 605-2, each cascaded inverter stage including PMOS FETs (e.g., MP0 to MP2) coupled in series with NMOS FETs (e.g., MN0 to MN2) between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In a round-robin or modN scheme, for all stages (e.g., for "i" from 0 to N-1), the gate (input) of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain (output) of the PMOS FET of the i-1 (modN)th cascaded inverter stage. The RO divider 600 includes an output buffer 630 which includes an input coupled to the output of one of the cascaded inverter stages, such as output node n2 of the cascaded inverter stage 605-2, and an output from which the output clock CLK_OUT is generated.

[0064] The RO divider 600 further includes a control circuit 610 which includes an input buffer 615 and a set of N (N=3) NOR gates 620-0 to 620-2. The input buffer 615 includes an input for receiving the input clock CLK_IN. The set of NOR gates 620-0 to 620-2 each includes a first input which is coupled to the output of the input buffer 615. The set of NOR gates 620-0 to 620-2 each includes a second input (voltage V) which is coupled to the output nodes n1, n2, and n0 of the cascaded inverter stages 605-1, 605-2, and 605-0, respectively. n1 , V n2 , and V n0 The set of NOR gates 620-0 to 620-2 includes a set of outputs, in which the control voltage V A , V B , and V C These are generated and coupled to the gates of the NMOS FETs MN0 to MN2 of the cascaded inverter stages 605-0 to 605-2, respectively.

[0065] Generally, for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 620-i) is coupled to the drain (output node) of the i-2(modN)th PMOS FET in the cascaded inverter stage. For example, for i=0, the second input of the NOR gate 620-0 is coupled to the output node n1 of the cascaded inverter stage 605-1 (output voltage V). n1 It includes (to receive) i-2(mod3)=0-2(mod3)=-2(mod3)=1. Similarly, for i=1, the NOR gate 620-1 is coupled to the second input (output voltage V) of the cascaded inverter stage 605-2 at output node n2. n2 It includes a second input (output voltage V) coupled to the output node n0 of the cascaded inverter stage 605-0. n0It includes the condition to receive i-2(mod3)=2-2(mod3)=0(mod3)=0.

[0066] However, it will be understood that the control circuit 610 may be implemented in a configuration other than that shown in Figure 6. For example, the control circuit 610 may be implemented with AND gates instead of NOR gates, and for "i" from 0 to N-1, the second input of the i-th AND gate may be coupled to the drain (output node) of the i-1(modN)th cascaded inverter stage PMOS FET.

[0067] The cascaded inverter stage 605-2 controls the gate of the NMOS FET MN2 to the corresponding V of the control circuit 610. C The switching device 625 (e.g., a single-pole-double-throw (SPDT)) may be included for selective coupling to the output or the drain (output) of the PMOS FET MP1 of the preceding (i-1) cascaded inverter stage 605-1. More specifically, the SPDT switching device 625 may include a pole coupled to the gate of the NMOS FET MN2, a first throw (labeled "1") coupled to the drain (output) of the PMOS FET MP1 of the preceding (i-1) cascaded inverter stage 605-1, and the V of the control circuit 610. C It includes a second throw (labeled "2") coupled to the output.

[0068] The SPDT switching device 625 includes a control input for receiving a division ratio mode signal. If the mode signal is configured to couple the pole to a second throw, the RO divider 600 divides the frequency of the input clock CLK_IN by 3 or N to produce the output clock CLK_OUT (for example, the division ratio is 3). If the mode signal is configured to couple the pole to a first throw, the RO divider 600 divides the frequency of the input clock CLK_IN by 2 or N-1 to produce the output clock CLK_OUT (for example, the division ratio is 2). Thus, in this example, the RO divider 600 is a dual-modulus divider or a multi-modulus divider.

[0069] Figure 7 shows a schematic diagram of another exemplary ring oscillator (RO) divider 700 according to another aspect of the present disclosure. The RO divider 700 is an example of an implementation of N=7 cascaded inverter stages. Specifically, the RO divider 700 includes a ring of N (N=7 in the shown example) cascaded inverter stages 705-0 to 705-6, each cascaded inverter stage including PMOS FETs (e.g., MP0 to MP6) coupled in series with NMOS FETs (e.g., MN0 to MN6) between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In a round-robin or modN scheme, for all stages (e.g., for "i" from 0 to N-1), the gate (input) of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain (output) of the PMOS FET of the i-1 (modN)th cascaded inverter stage. The RO divider 700 includes an output buffer 730 which includes an input coupled to the output of one of the cascaded inverter stages, such as output node n6 of the cascaded inverter stages 705-6, and an output from which the output clock CLK_OUT is generated.

[0070] The RO divider 700 further includes a control circuit 710 which includes an input buffer 715 and a set of N (N=7) NOR gates 720-0 to 720-6. The input buffer 715 includes an input for receiving the input clock CLK_IN. The set of NOR gates 720-0 to 720-6 each includes a first input which is coupled to the output of the input buffer 715. The set of NOR gates 720-0 to 720-6 each includes a second input which is coupled to the output nodes n5, n6, n0, n1, n2, n3, and n4 of the cascaded inverter stages 705-5, 705-6, and 705-0 to 705-4, respectively. The set of NOR gates 720-0 to 720-6 includes a set of outputs in which the control voltage V A From V G These are generated and coupled to the gates of the NMOS FETs MN0 to MN6 of the cascaded inverter stages 705-0 to 705-6, respectively.

[0071] Generally, as previously discussed, for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 720-i) is coupled to the drain (output node) of the i-2(mod N)th cascaded inverter stage PMOS FET. Considering a few examples, for i=0, the NOR gate 720-0 has its second input (output voltage V) coupled to the output node n5 of the cascaded inverter stage 705-5. n5 It includes (to receive) i-2(mod7)=0-2(mod7)=-2(mod7)=5. Similarly, for i=1, the NOR gate 720-1 is coupled to the second input (output voltage V) of the cascaded inverter stage 705-6 at output node n6. n6 It includes (to receive) i-2(mod7)=1-2(mod7)=-1(mod7)=6. For I=2, the NOR gate 720-2 is coupled to the second input (output voltage V) of the cascaded inverter stage 705-0 at output node n0. n0 It includes the condition to receive i-2(mod7)=2-2(mod7)=0(mod7)=0, and so on.

[0072] However, it will be understood that the control circuit 710 may be implemented in a configuration other than that shown in FIG. 7. For example, in some embodiments, for "i" from 0 to N-1, the second input of the i-th NOR gate (e.g., 720-i) may be coupled to the drain (output) of the PMOS (and NMOS) FET of the (i-4 (mod N))-th cascaded inverter stage. In some embodiments, for "i" from 0 to N-1, the second input of the i-th NOR gate is coupled to the drain (output) of the PMOS (and NMOS) FET of the (i-E (mod N))-th cascaded inverter stage, where E is an even number and 0 < E < N. As another example, the control circuit 710 may be implemented with AND gates instead of NOR gates. The second input of the i-th AND gate may, in some embodiments, for "i" from 0 to N-1, be coupled to the drain (output node) of the PMOS FET of the (i-1 (mod N))-th cascaded inverter stage, in other embodiments, for "i" from 0 to N-1, be coupled to the drain (output node) of the PMOS FET of the (i-3 (mod N))-th cascaded inverter stage, or in yet other embodiments, for "i" from 0 to N-1, be coupled to the drain (output node) of the PMOS FET of the (i-5 (mod N))-th cascaded inverter stage. In some embodiments, for "i" from 0 to N-1, the second input of the i-th AND gate is coupled to the drain (output) of the PMOS (and NMOS) FET of the (i-R (mod N))-th cascaded inverter stage, where R is an odd number and 0 < R < N.

[0073] The cascaded inverter stage 705-6 controls the gate of the NMOS FET MN6 with the corresponding V of the control circuit 710 GThe circuit may include a switching device 725 (e.g., an SPDT) for selective coupling to the output or the drain (output) of the PMOS FET MP5 of the preceding (i-1) cascaded inverter stage 705-5. More specifically, the SPDT switching device 725 may include a pole coupled to the gate of the NMOS FET MN6, a first throw (labeled "1") coupled to the drain (output) of the PMOS FET MP5 of the preceding (i-1) cascaded inverter stage 705-5, and the V of the control circuit 710. G It includes a second throw (labeled "2") coupled to the output.

[0074] The SPDT switching device 725 includes a control input for receiving a division ratio mode signal. If the division ratio mode signal is configured to couple the poles to a second throw, the RO divider 700 divides the frequency of the input clock CLK_IN by 7 or N to produce the output clock CLK_OUT (for example, the division ratio is 7). If the division ratio mode signal is configured to couple the poles to a first throw, the RO divider 700 divides the frequency of the input clock CLK_IN by 6 or N-1 to produce the output clock CLK_OUT (for example, the division ratio is 6). Thus, in this example, the RO divider 700 is a dual-modulus divider or a multi-modulus divider.

[0075] Figure 8 shows a schematic diagram of an exemplary multimodulus RO divider 800 and its associated mode table according to another aspect of the present disclosure. The previous RO dividers discussed were either single-division or dual-modulus dividers, as they provided two selected division ratios N and N-1. In contrast, the RO divider 800 includes N=7 stages, with a subset of stages 4-6 selectively bypassed to achieve additional division ratios of 4-6 or N-3-N-1.

[0076] Specifically, the RO divider 800 includes a ring of N (N=7) cascaded inverter stages 805-0 to 805-6, each cascaded inverter stage including PMOS FETs (e.g., MP0 to MP6) coupled in series with NMOS FETs (e.g., MN0 to MN6) between the upper voltage rail VDD and the lower voltage rail (e.g., ground). In a round-robin or modN scheme, for all stages (e.g., for "i" from 0 to N-1), the gate (input) of the PMOS FET of the i-th cascaded inverter stage is coupled to the drain (output) of the PMOS FET of the i-1 (modN)th cascaded inverter stage. The RO divider 800 includes an output buffer 830 which has an input that is coupled to the output of one of the cascaded inverter stages, such as output node n6 of the cascaded inverter stages 805-6, and an output from which the output clock CLK_OUT is generated.

[0077] The RO frequency divider 800 further has an input for receiving the input clock CLK_IN and a control voltage V, respectively. A From V G The control circuit 810 includes a set of N independent outputs for generating the signal. Each of the N independent outputs of the control circuit 810 is coupled to the gates of NMOS FETs MN0 to MN6 of cascaded inverter stages 805-0 to 805-6.

[0078] In this example, the cascaded inverter stages 805-4 to 805-6 each control the corresponding V of the control circuit 810. E From V GThe circuit includes switching devices 825-2 to 825-0 (each configured as an SPDT) for selectively coupling the gates of NMOS FETs MN4 to MN6 to the outputs, or the drains (outputs) of the PMOS FETs MP3 to MP5 of the preceding (i-1) cascaded inverter stages 805-3 to 805-5. More specifically, the SPDT switching devices 825-2 to 825-0 each couple to the poles of the gates of the NMOS FETs MN4 to MN6, the first throws (labeled "1") coupled to the drains (outputs) of the PMOS FETs MP3 to MP5 of the preceding (i-1) cascaded inverter stages 805-3 to 805-5, and the V of the control circuit 810. E From V G It includes a second throw (labeled "2") coupled to the output.

[0079] In the shown embodiment, SPDT switching devices 825-0 to 825-2 are different bit MV of the division ratio mode signal. <0> From MC <2> Includes a control input for receiving. Referring to the mode table provided in Figure 8, the bit MC of the mode signal <0> From MC <2> If the frequency is 000, the RO divider 800 divides the frequency of the input clock CLK_IN by 7 or by N to generate the output clock CLK_OUT (for example, division ratio N DIV (is 7). The bit MC of the mode signal. <0> From MC <2> If the frequency is 100, the RO divider 800 divides the frequency of the input clock CLK_IN by 6 or N-1 to generate the output clock CLK_OUT (for example, division ratio N DIV (It is 6). The bit MC of the mode signal. <0> From MC <2> If the frequency is 110, the RO divider 800 divides the frequency of the input clock CLK_IN by 5 or N-2 to generate the output clock CLK_OUT (for example, division ratio N DIV (It is 5). The bit MC of the mode signal. <0> From MC <2> If the frequency is 111, the RO divider 800 divides the frequency of the input clock CLK_IN by 4 or N-3 to generate the output clock CLK_OUT (for example, division ratio N DIV(This is 4). In other embodiments (not shown), switching devices 825-0 to 825-2 may each receive separate or independent control signals.

[0080] Figure 9 shows a schematic diagram of another exemplary RO divider 900 according to another aspect of the present disclosure. In summary, the RO divider 900 includes differently configured cascaded inverter stages that substantially eliminate the control circuits of the previous implementation. More specifically, the RO divider 900 includes a ring of N (N=5 in the example shown) cascaded inverter stages 905-0 to 905-4, each stage including a first PMOS FET, a second PMOS FET, and an NMOS FET coupled in series between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In other embodiments, more or fewer stages may be implemented.

[0081] For example, the cascaded inverter stage 905-0 includes a first PMOS FET MP0A, a second PMOS FET MP0B, and an NMOS FET MN0. The cascaded inverter stage 905-1 includes a first PMOS FET MP1A, a second PMOS FET MP1B, and an NMOS FET MN1. The cascaded inverter stage 905-2 includes a first PMOS FET MP2A, a second PMOS FET MP2B, and an NMOS FET MN2. The cascaded inverter stage 905-3 includes a first PMOS FET MP3A, a second PMOS FET MP3B, and an NMOS FET MN3. The cascaded inverter stage 905-4 includes a first PMOS FET MP4A, a second PMOS FET MP4B, and an NMOS FET MN4.

[0082] In the round-robin or modN configuration, for all stages (for example, for i from 0 to N-1), the gate of the second PMOS FET in the i-th cascaded inverter stage is coupled to the drain of the second PMOS FET (and the drain of the NMOS FET) in the i-1(modN)th cascaded inverter stage. In addition, in the round-robin or modN configuration, for all stages (for example, for i from 0 to N-1), the gate of the first PMOS FET in the i-th cascaded inverter stage is coupled to the drain of the second PMOS FET in the i-2(modN)th cascaded inverter stage. In other embodiments (not shown), in the round-robin or modN configuration, for all stages (for example, for i from 0 to N-1), the gate of the first PMOS FET in the i-th cascaded inverter stage may be coupled to the drain of the second PMOS FET in the i-4(modN)th cascaded inverter stage.

[0083] The RO divider 900 includes an input buffer 910 which has an input for receiving the input clock CLK_IN and outputs coupled to the gates of NMOS FETs MN0 through MN4, respectively. Thus, the rising edge or high state of the input clock CLK_IN simultaneously turns on NMOS FETs MN0 through MN4. However, the coupling of the gates of the first PMOS FETs MN0A through MP4A to output nodes n3, n4, n0, n1, and n2, respectively, enables the cascaded inverter stages 905-0 through 905-5 substantially one at a time per clock cycle. The stages enabled per clock cycle are those in which the first and second PMOS FETs are off.

[0084] In addition, the RO divider 900 includes an output buffer 930 which has an input coupled to one of the outputs of N cascaded inverter stages, such as output node n4 of the cascaded inverter stages 905-4. The output buffer 930 has an output which gives rise to the output clock CLK_OUT. The RO divider 900 is configured to divide the input clock CLK_OUT by 5 or by N to produce the output clock CLK_OUT. Although not shown in Figure 9, as described with respect to the various examples above, the RO divider 900 may be implemented as a multimodulus divider using one or more switching devices.

[0085] Figure 10A shows a block diagram of an exemplary phase-locked loop (PLL) 1000 according to another aspect of the present disclosure. Any of the previously discussed ring oscillator (RO) dividers may be used in the feedback loop of a PLL such as PLL 1000. In such cases, the RO divider may be called a frequency prescaler with dual-modulus or multi-modulus division capabilities.

[0086] Specifically, the PLL1000 consists of a phase-frequency detector (PFD) 1010, a charge pump (CP) 1020, a low-pass filter (LPF) 1030, a voltage-controlled oscillator (VCO) 1040, and a frequency divider (÷N). DIV ) includes 1050. The frequency divider 1050 may include any of the RO frequency dividers discussed previously. Thus, the frequency divider 1050 has a frequency division ratio N set by the frequency division ratio mode signal. DIV Therefore, the clock Fvco generated by VCO1040 is divided to generate a feedback clock Ffb that can become the CLK_OUT of frequency divider 1050, and is located within the feedback loop of PLL1000.

[0087] As will be further discussed herein, the frequency divider 1050, based on the frequency division ratio mode signal, N DIVThe system may include a dual modulus divider configured to divide by either 4 or 5. The division ratio mode signal may be generated by a sequence generator, such as a sigma-delta modulator, to achieve fractional division by the divider 1050. For example, if the target division is 4.5, the division ratio mode signal may be a sequence with an average of 0.5 (e.g., the divider 1050 divides by 5 for half of the sequence period and by 4 for the other half). If the target division is 4.2, the division ratio mode signal may be a sequence with an average of 0.2 (e.g., the divider 1050 divides by 5 for 80 percent of the sequence period and by 4 for 20 percent). In other embodiments, the divider 1050 is a single modulus divider.

[0088] PFD1010 compares the phase-frequency of the feedback clock Ffb with the phase-frequency of the reference clock Fref to generate a phase-frequency error signal. CP1020 charges and discharges a capacitor based on the phase-frequency error signal to generate a charge pump voltage related to the phase-frequency error. LPF1030 filters the charge pump voltage to remove high-frequency components and generates a control voltage for VCO1040. VCO1040 generates clock Fvco based on the control voltage. When the loop is synchronized, the phase-frequency of the feedback signal Ffb is substantially the same as the phase-frequency of the reference signal Fref, and the frequency of the VCO clock Fvco is N of the frequency of the reference clock Fref. DIV It is double.

[0089] Figure 10B shows a block diagram of an example of a frequency divider 1050 for a phase-locked loop (PLL) 1000 according to another aspect of the present disclosure. The frequency divider 1050 includes a frequency prescaler 1052 (e.g., DIV4 / 5), which may be composed of one of the previously discussed RO frequency dividers. Thus, the frequency prescaler 1052 is configured to divide the clock Fvco of the VCO 1040 based on a division ratio mode signal to generate an intermediate clock Fint. Thus, the output of the VCO 1040 can become CLK_IN for the frequency divider 1050 / frequency prescaler 1052. The frequency divider 1050 further includes a counter 1054 configured to generate a feedback clock Ffb based on the intermediate clock Fint. The counter 1054 may be a modulo-Q counter, which essentially operates as a frequency divider for dividing the intermediate clock Fint modulo-Q. The CLK_OUT of prescaler 1052 may be provided to counter 1054.

[0090] Figure 11 shows a block diagram of another exemplary phase-locked loop (PLL) 1100 according to another aspect of the present disclosure. PLL 1100 is similar to PLL 1000 discussed previously and includes a phase-frequency detector (PFD) 1110, a charge pump 1120, a low-pass filter 1130, a voltage-controlled oscillator (VCO) 1140, and a frequency divider 1150. As discussed with respect to PLL 1000, the frequency divider 1150 in the feedback loop of PLL 1100 determines a first division ratio N based on a first division ratio mode signal. DIV1 The VCO clock Fvco is divided by frequency to generate the feedback clock Ffb.

[0091] The PLL1100 further determines a second division ratio N based on a second division ratio mode signal. DIV2The system includes an additional frequency divider 1160 configured to divide the clock Fvco of VCO 1140 to produce an output clock Fout. The frequency divider 1160 may be composed of one of the previously discussed RO frequency dividers. Thus, the output of VCO 1140 can become CLK_IN for the frequency divider 1160. In this example, the frequency divider 1160 is not in the feedback loop of PLL 1100. In some such examples, the frequency divider 1160 is included in a local oscillator (LO) frequency divider, and the CLK_OUT of the divider is provided to another part of the LO or a mixer. Thus, the RO frequency dividers described herein may be used in many applications and in various functions or positions throughout the device.

[0092] Figure 12 shows a block diagram of an exemplary wireless communication device 1200 according to another aspect of the present disclosure. As discussed, the RO dividers described herein can be used in many applications, including an application in the transceiver of a wireless communication device such as the wireless communication device 1200. The wireless communication device 1200 includes a digital signal processing core 1202, which includes one or more sets of digital-to-analog converters (DACs) 1204 and 1206, and one or more sets of analog-to-digital converters (ADCs) 1208 and 1210. In some embodiments, the digital signal processing core 1202 may set or adjust a programmable reference voltage Vref.

[0093] The wireless communication device 1200 further includes one or more sets of low-pass filters (LPFs) 1212 and 1214, one or more sets of amplifiers 1224 and 1226, an upconverter 1232, a transmitter (Tx) phase-locked loop (PLL) 1216, a transmitter (Tx) local oscillator (LO) 1234, a radio frequency (RF) filter 1240, a power amplifier (PA) 1244, a duplexer 1248, and at least one antenna 1250.

[0094] The wireless communication device 1200 further includes a low-noise amplifier (LNA) 1246, an RF filter 1242, a downconverter 1238, a receiver (Rx) phase-locked loop (PLL) 1218, a receiver (Rx) local oscillator (LO) 1236, a set of one or more amplifiers 1228 and 1230, and a set of one or more low-pass filters (LPFs) 1220 and 1222.

[0095] Any of the RO dividers described herein may be used in the transmitter (Tx) PLL 1216 and / or receiver (Rx) PLL 1218. For example, the transmitter (Tx) LO 1234 may provide the Tx PLL 1216 with a division ratio mode signal to cause the PLL to generate an output clock with a specific frequency. In other examples, the division ratio mode signal may be provided by another component or circuit, such as the processor / core 1202. The division ratio mode signal controls the division ratio of the RO divider in the Tx PLL 1216. The Tx LO 1234 uses the output clock of the Tx PLL 1216 to generate a transmit LO for the upconverter 1232.

[0096] Similarly, the receiver (Rx) LO 1236 (or processor / core 1202) may provide a division ratio mode signal to the Rx PLL 1218 to cause the PLL to generate an output clock with a specific frequency. The division ratio mode signal controls the division ratio of the RO divider in the Rx PLL 1218. The Rx LO 1236 uses the output clock of the Rx PLL 1218 to generate the receive LO for the downconverter 1238.

[0097] Furthermore, any of the RO dividers described herein may be used in the transmitter (Tx)LO1234 and / or the receiver (Rx)LO1236. The RO divider may also be used in any other circuit of the wireless device 1200 that implements the divider.

[0098] Figure 13 shows a flowchart of an exemplary method 1300 according to another aspect of the present disclosure for dividing a first clock to generate a second clock. Method 1300 includes the steps of: receiving a first clock (block 1310); enabling each stage of a ring of N cascaded inverter stages substantially one at a time in response to the first clock (block 1320); and outputting a second clock from the output of one stage of the ring of N cascaded inverter stages, where N is a positive integer (block 1330).

[0099] The following provides an overview of the aspects of this disclosure.

[0100] Embodiment 1: A device comprising a ring of N cascaded inverter stages, where N is a positive integer, and a control circuit including a set of N independent outputs coupled to each of the N cascaded inverter stage rings.

[0101] Embodiment 2: The apparatus of Embodiment 1, wherein the control circuit is configured to generate N sets of control signals in N independent sets of outputs, each in response to a first clock, in order to enable each of N cascaded inverter stages substantially one at a time, the second clock is generated at the output of one of the N cascaded inverter stages, and the division ratio of the frequency of the first clock to the frequency of the second clock is an integer less than or equal to N.

[0102] Embodiment 3: The apparatus of Embodiment 2, wherein each stage of a ring of N cascaded inverter stages includes a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET) coupled in series with an n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET) between a first voltage rail and a second voltage rail, each NMOS FET having a gate, and the PMOS FET of the i-th cascaded inverter stage includes a gate coupled to the drain of the i-1(mod N)-th cascaded inverter stage PMOS FET for an integer i from 0 to N-1, and each of the N independent sets of outputs of the control circuit is coupled to the gates of the NMOS FETs of the ring of N cascaded inverter stages.

[0103] Embodiment 4: The apparatus of Embodiment 3, wherein the control circuit comprises a set of N NOR gates, each having an output that functions as a set of N independent outputs of the control circuit, each set of N NOR gates having a first input for receiving a first clock, and for i from 0 to N-1, the i-th NOR gate having a second input coupled to the drain of the iE(mod N)-th cascaded inverter stage PMOS FET, where E is a positive even number less than N, or a set of N AND gates, each having an output that functions as a set of N independent outputs of the control circuit, each set of N AND gates having a first input for receiving a first clock, and for i from 0 to N-1, the i-th AND gate having a second input coupled to the drain of the iR(mod N)-th cascaded inverter stage PMOS FET, where R is a positive odd number less than N.

[0104] Embodiment 5: The apparatus of Embodiment 3 or 4, wherein each subset of one or more stages of N cascaded inverter stages includes a switching device for selectively coupling the gate of the j-th cascaded inverter stage of the subset to either the j-th output of a control circuit or the drain of the j-1-th cascaded inverter stage, for an integer j from 0 to the number of one or more cascaded inverter stages in the subset, wherein the switching device selectively couples based on a division ratio mode signal.

[0105] Embodiment 6: The apparatus of Embodiment 5, wherein the frequency division ratio of the frequency of the first clock to the frequency of the second clock is greater when the gate of the NMOS FET of the j-th cascaded inverter stage is coupled to the j-th output of the control circuit than when the gate of the NMOS FET of the j-th cascaded inverter stage is coupled to the drain of the PMOS FET of the (j-1)-th cascaded inverter stage.

[0106] Embodiment 7: The apparatus of Embodiment 5 or 6, wherein the switching device includes a second PMOS FET coupled between the drain of a PMOS FET of the j-1th cascaded inverter stage and the gate of an NMOS FET of the j-th cascaded inverter stage, and a second NMOS FET coupled between the gate of an NMOS FET of the j-th cascaded inverter stage and the j-th output of a control circuit, the gates of the second PMOS FET and the gates of the second NMOS FET being coupled together to receive a frequency divider mode signal.

[0107] Embodiment 8: Any one of embodiments 3 to 7, wherein one or more of every other N cascaded inverter stages include a second NMOS FET coupled between the drain of a corresponding PMOS FET and a second voltage rail, the second NMOS FET including a gate for receiving a pre-discharge signal.

[0108] Embodiment 9: The apparatus of Embodiment 8, wherein one or more of every other N cascaded inverter stages, which do not include a second NMOS FET, each include a dummy NMOS FET coupled between a corresponding PMOS FET and a second voltage rail, and the dummy NMOS includes a gate coupled to the second voltage rail.

[0109] Embodiment 10: Any one of embodiments 1 to 9, wherein N cascaded inverter stages are coupled between a first voltage rail and a second voltage rail, and further include a voltage regulator for selectively changing the difference in supply voltage between the first voltage rail and the second voltage rail.

[0110] Embodiment 11: The apparatus of Embodiment 10, wherein the voltage regulator includes a low-dropout (LDO) voltage regulator.

[0111] Embodiment 12: The apparatus of Embodiment 11, wherein the LDO voltage regulator includes a PMOS FET coupled between a third voltage rail and a first voltage rail, and an operational amplifier having a first input for receiving a programmable voltage, a second input coupled to the first voltage rail, and an output coupled to the gate of the PMOS FET.

[0112] Embodiment 13: Any one of embodiments 2 to 12, further comprising a voltage-controlled oscillator (VCO) having an output for generating a first clock.

[0113] Embodiment 14: The apparatus of Embodiment 13, wherein a ring and control circuit of N cascaded inverter stages are part of a frequency prescaler in the feedback loop of a phase-locked loop (PLL) including a VCO.

[0114] Embodiment 15: A device comprising a ring of N cascaded inverter stages, wherein N is a positive integer, and each stage of the ring of N cascaded inverter stages comprises a first p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET), a second PMOS FET, and an NMOS FET coupled in series between a first voltage rail and a second voltage rail, wherein for an integer i from 0 to N-1, the second PMOS FET of the i-th cascaded inverter stage includes a gate coupled to the drain of the second PMOS FET of the i-1(mod N)-th cascaded inverter stage, and for an i from 0 to N-1, the first PMOS FET of the i-th cascaded inverter stage includes a gate coupled to the drain of the second PMOS FET of the i-2(mod N)-th cascaded inverter stage, and NMOS A device in which each FET includes a gate for receiving a first clock, and the drain of one stage of N cascaded inverter stages is coupled to output a second clock.

[0115] Embodiment 16: The apparatus of Embodiment 15, further comprising a buffer including an input for receiving a first clock and outputs coupled to the gates of each of the NMOS FETs in a ring of N cascaded inverter stages.

[0116] Embodiment 17: The apparatus of Embodiment 15 or 16, further comprising a buffer having an input coupled to the drain of one of N cascaded inverter stages to output a second clock.

[0117] Embodiment 18: Any one of embodiments 15 to 17, wherein the frequency division ratio of the frequency of the first clock to the frequency of the second clock is an integer less than or equal to N.

[0118] Embodiment 19: Any one of embodiments 15 to 18, further comprising a voltage-controlled oscillator (VCO) having an output for generating a first clock.

[0119] Embodiment 20: The apparatus of Embodiment 19, wherein a ring of N cascaded inverter stages is part of a frequency prescaler in a feedback loop of a phase-locked loop (PLL) including a VCO.

[0120] Embodiment 21: A method comprising the steps of receiving a first clock; enabling each stage of a ring of N cascaded inverter stages substantially one at a time in response to a first clock in a first mode, wherein N is a positive integer; and outputting a second clock from the output of one stage of the ring of N cascaded inverter stages.

[0121] Embodiment 22: The method of Embodiment 21, wherein the step of enabling each of the rings of N cascaded inverter stages substantially one at a time includes the step of turning on field-effect transistors (FETs) in the N cascaded inverter stages in response to a set of N pulses of a first clock.

[0122] Embodiment 23: The method of Embodiment 22, wherein each of the turned-on FETs in N cascaded inverter stages includes an n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET).

[0123] Embodiment 24: The method of Embodiment 22, wherein each of the turned-on FETs in N cascaded inverter stages includes a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET).

[0124] Embodiment 25: Any one of embodiments 21 to 24, further comprising the step of enabling two or more of N cascaded inverter stages in response to the same phase of a first clock in a second mode.

[0125] Embodiment 26: The method of Embodiment 25, wherein the division ratio of the frequency of the first clock to the frequency of the second clock is greater in the first mode than the division ratio in the second mode.

[0126] Embodiment 27: Any one of embodiments 21 to 26, further comprising the step of changing the supply voltage to a ring of N cascaded inverter stages in order to change the highest or lowest operating frequency of a first clock.

[0127] Embodiment 28: Any one of embodiments 21 to 27, further comprising the step of operating a voltage-controlled oscillator (VCO) to generate a first clock.

[0128] Embodiment 29: A wireless communication device comprising a phase-locked loop (PLL) including a frequency prescaler, the PLL including a ring of N cascaded inverter stages, where N is a positive integer, and a circuit for enabling each stage of the ring of N cascaded inverters substantially one at a time based on a first clock, wherein the output of one of the N cascaded inverter stages generates a second clock; a local oscillator (LO) configured to generate a LO signal based on the second clock; and an upconverter or downconverter configured to upconvert or downconvert the frequency of the first signal, respectively, to generate a second signal based on the LO signal.

[0129] Embodiment 30: A wireless communication device according to Embodiment 29, wherein each of N cascaded inverter stages includes a PMOS FET coupled in series with an NMOS FET between a first voltage rail and a second voltage rail.

[0130] The above descriptions in this disclosure are provided so that any person skilled in the art may create or use this disclosure. Various modifications of this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein may be applied to other modifications without departing from the spirit or scope of this disclosure. Accordingly, this disclosure is not intended to be limited to the examples described herein, but should be given the broadest scope that is consistent with the principles and novel features disclosed herein. [Explanation of Symbols]

[0131] 105 Cascaded Inverter Stages 110 input buffers 130 Output Buffer 205 Cascaded Inverter Stages 210 Control circuits 230 Output buffer 305 Input Buffer 320 NOR gate 370 And Gate 405 Cascaded Inverter Stages 410 Control Circuit 430 Output Buffer 505 Cascaded Inverter Stages 510 Control Circuit 550 LDO Voltage Regulator 555 operational amplifier 605 Cascaded Inverter Stages 610 Control Circuit 615 Input Buffer 620 NOR gate 625 Switching Devices 630 Output Buffer 705 Cascaded Inverter Stages 710 Control Circuit 715 Input Buffer 720 NOR gate 725 Switching Devices 730 Output Buffer 805 Cascaded Inverter Stages 810 Control Circuit 825 Switching Devices 830 Output Buffer 905 Cascaded Inverter Stages 910 Input Buffer 930 Output Buffer 1010 Phase frequency detector 1020 Charge Pump 1030 Low-Pass Filter 1040 Voltage-controlled oscillator 1050 frequency divider 1052 Prisquera 1054 counter 1110 Phase frequency detector 1120 Charge Pump 1130 Low-pass filter 1140 Voltage-controlled oscillator 1150 frequency divider 1160 frequency divider 1202 Digital Signal Processing Core 1204 DAC 1206 DAC 1208 ADC 1210 ADC 1212 LPF 1214 LPF 1216 TX PLL 1218 RX PLL 1220 LPF 1222 LPF 1224 IFA 1226 IFA 1228 IFA 1230 IFA 1232 Upconverter 1234 TX LO 1236 RX LO 1238 Downconverter 1240 filters 1242 filter 1244 PA 1246 LNA 1248 Duplexa 1250 Antenna

Claims

1. A ring oscillator frequency divider, A ring of N cascaded inverter stages, where N is a positive integer, and each stage of the ring of N cascaded inverter stages comprises a first p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET), a second PMOS FET, and an NMOS FET, wherein the first PMOS FET, the second PMOS FET, and the NMOS FET are connected in series between a first voltage rail and a second voltage rail, the drain of the first PMOS FET is connected to the source of the second PMOS FET, the drain of the second PMOS FET is connected to the drain of the NMOS FET, and for an integer i from 0 to N-1, the second PMOS FET of the i-th cascaded inverter stage includes a gate directly connected to the drain of the second PMOS FET of the i-1(mod N)-th cascaded inverter stage, and for an integer i from 0 to N-1, the first PMOS of the i-th cascaded inverter stage A ring oscillator divider in which the FETs include a gate directly connected to the drain of the second PMOS FET of the i-2(mod N)th cascaded inverter stage, each of the NMOS FETs includes a gate for receiving a first clock, and the drain of one of the N cascaded inverter stages is coupled to the input of a buffer for outputting a second clock having a divided frequency of the first clock.

2. The ring oscillator divider according to claim 1, further comprising a buffer including an input for receiving the first clock and outputs coupled to the gates of each of the NMOS FETs of the ring of N cascaded inverter stages.

3. The control circuit further comprises a first clock and a control circuit configured to receive the first clock and generate k control voltages for controlling k switching circuits, wherein the kth switching circuit is included in the (N-k+1)th inverter stage, and k is an integer between 1 and N-1, The k-th switching circuit is configured to switch the input of the NMOS FET included in the (N-k+1)-th inverter stage to either the output of the (Nk)-th inverter stage or the k-th control voltage in response to receiving a frequency division ratio mode signal. The ring oscillator frequency divider according to claim 1, wherein the frequency division ratio of the frequency of the first clock to the frequency of the second clock is an integer less than N.

4. The ring oscillator divider according to claim 1, further comprising a voltage-controlled oscillator (VCO) having an output for generating the first clock.

5. The ring oscillator divider according to claim 4, wherein the ring of N cascaded inverter stages is part of a frequency prescaler in the feedback loop of a phase-locked loop (PLL) including the VCO.

6. A method for dividing a first clock into a second clock, The steps of receiving the first clock using the ring oscillator frequency divider described in claim 1, A method comprising the step of outputting the second clock using the ring oscillator frequency divider.

7. A phase-locked loop (PLL) including a ring oscillator divider as described in claim 1, A local oscillator (LO) is configured to generate a local oscillator (LO) signal based on the second clock, A wireless communication device comprising an upconverter or a downconverter, each configured to upconvert or downconvert the frequency of a first signal in order to generate a second signal based on the LO signal.

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