Semiconductor equipment

Abstract

To provide a transistor having an excellent electric characteristic, suitable for refining, and having a high switching speed.SOLUTION: A semiconductor device has a transistor including an oxide semiconductor, a gate electrode, a gate insulator, and the oxide semiconductor has a first region in which the oxide semiconductor and the gate electrode are overlapped each other via the gate insulator. In the transistor, a threshold voltage is larger than 0 V, and the switching speed is less than 100 nano seconds.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a product, a method, or a method of manufacturing; or to a process, a machine relating to manufactures or compositions of matter. In particular, The present invention relates to, for example, semiconductors, semiconductor devices, display devices, light-emitting devices, lighting devices, energy storage devices, and Related to memory devices or processors. Or semiconductors, semiconductor devices, display devices, light-emitting devices, This relates to a method for manufacturing lighting devices, energy storage devices, memory devices, or processors. Or, semiconductor devices. A method for driving a device, display device, light-emitting device, lighting device, energy storage device, memory device, or processor. To relate to.

[0002] In this specification and other documents, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of equipment, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. The device may contain semiconductor equipment. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on a substrate having an insulating surface. It is attracting attention. The transistor in question is used in integrated circuits (ICs) and image display devices (simply as a display device and It is widely applied to electronic devices such as (also written as) transistors. Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxidative materials. Semiconductors are attracting attention.

[0004] For example, transistors are fabricated using zinc oxide or In-Ga-Zn oxide semiconductors. The technology is disclosed (see Patent Documents 1 and 2).

[0005] Furthermore, an oxide semiconductor with a crystal structure oriented along the c-axis was used as the active layer of the transistor. A high-resolution, low-power display device has been disclosed (see Non-Patent Document 1).

[0006] Furthermore, in recent years, with the increasing performance, miniaturization, and weight reduction of electronic devices, miniaturized transistors have become more common. There is a growing demand for integrated circuits that densely integrate semiconductor elements such as zistas.

[0007] For example, using an oxide semiconductor having a crystal structure in which the c-axis is oriented perpendicular to the surface as the active layer The transistor used has an extremely low off-current (see Non-Patent Document 2), and this characteristic is utilized. Applications to LSIs such as non-volatile memory, CPUs, and image sensors have been proposed. (See Non-Patent Documents 3 to 5). [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., The Society for Information Display 2012 International Symposium Digest, pp. 183-186 [Non-Patent Document 2] K. Kato et al., Japanese Journal of Applied Physics 2012, volume 51, 021201 [Non-Patent Document 3] H. Inoue et al., The Institute of Electrical and Electronics Engineers Journal of Solid-State Circuits 2012, volume 47, pp. 2258-2065 [Non-Patent Document 4] T. Ohmaru et al., Extented Abstract, Solid State Devices and Materials 2012, pp. 1144-1145 [Non-Patent Document 5] T. Aoki et al., Symposia on VLSI Technology Digest of Technical Papers, 2011, pp. 174-175 [Overview of the project] [Problems that the invention aims to solve]

[0010] One of the objectives is to provide a transistor with good electrical characteristics. Alternatively, miniaturization One of the challenges is to provide a transistor suitable for modification. Alternatively, switching transistor One of the challenges is to provide a transistor with high current. Alternatively, the current during conduction is large. One of the objectives is to provide a transistor, or a device having such a transistor. One of the objectives is to provide a semiconductor device, or a device having such a transistor. One of our objectives is to provide a semiconductor device with high processing speed.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention relates to a transient having an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor has a gate insulator and the oxide semiconductor is connected to the gate insulator. The transistor has a first region where the gate electrode and the other overlap each other, and the threshold voltage is This is a semiconductor device that has a voltage greater than 0V and a switching speed of less than 100 nanoseconds.

[0013] Alternatively, in one aspect of the present invention, when a voltage equal to or greater than a threshold voltage is applied to the gate electrode, This is a semiconductor device in which electric current flows throughout the oxide semiconductor.

[0014] Alternatively, in one aspect of the present invention, the carrier density of the first region is 1 × 10⁻⁶ 15 cm -3 less than It is a semiconductor device.

[0015] Alternatively, in one aspect of the present invention, the oxide semiconductor is connected to the gate insulator. The semiconductor device has a second region that faces the side surface and the gate electrode.

[0016] Alternatively, one aspect of the present invention comprises a conductor in contact with an oxide semiconductor, wherein the oxide semiconductor is conductive. It has a third region that is in contact with the body, and the third region has an oxygen-deficient site, and the oxygen-deficient site The device is a semiconductor device containing hydrogen.

[0017] Alternatively, one aspect of the present invention is a semiconductor device in which the third region is an n-type conductive region. [Effects of the Invention]

[0018] It is possible to provide transistors with good electrical characteristics, or transistors suitable for miniaturization. We can provide transistors. Or, transistors with high switching speeds. It can provide a transistor. Or, it can provide a transistor with a large current when conducting. This is possible. Alternatively, a semiconductor device having the transistor can be provided. This can provide a high-speed semiconductor device having the transistor. [Brief explanation of the drawing]

[0019] [Figure 1] A top view and a cross-sectional view showing a transistor according to one aspect of the present invention. [Figure 2] A cross-sectional view showing a transistor according to one aspect of the present invention. [Figure 3] A cross-sectional view showing a transistor according to one aspect of the present invention. [Figure 4] A top view and a cross-sectional view showing a transistor according to one aspect of the present invention. [Figure 5] A top view and a cross-sectional view showing a transistor according to one aspect of the present invention. [Figure 6] A top view and a cross-sectional view showing a transistor according to one aspect of the present invention. [Figure 7] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 8] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 9] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 10] A cross-sectional view and a circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 11] A cross-sectional view and a circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 12] Configuration of a semiconductor device according to one aspect of the present invention. [Figure 13] A CPU configuration according to one aspect of the present invention. [Figure 14] A chip and module configuration according to one aspect of the present invention. [Figure 15] An electronic device according to one aspect of the present invention. [Figure 16] A schematic diagram, a cross-sectional view, and a cross-sectional STEM image showing a transistor according to one aspect of the present invention. [Figure 17] X-ray diffraction spectrum, unit cell structure, high-resolution TEM image in cross-section, and high-resolution TEM image on the surface of CAAC-IGZO. [Figure 18] High-resolution TEM image of single-crystal IGZO. [Figure 19] Electrical characteristics of a transistor according to one aspect of the present invention. [Figure 20] Dependence of the turn-on voltage of a transistor and the drain voltage of SS according to one aspect of the present invention. [Figure 21] Channel width dependence of the electrical characteristics of a transistor according to one aspect of the present invention. [Figure 22] Channel width dependence of the turn-on voltage and SS of a transistor according to one aspect of the present invention. [Figure 23] Channel length dependence of the electrical characteristics of a transistor according to one aspect of the present invention. [Figure 24] The channel length dependence of the turn-on voltage and SS of a transistor according to one aspect of the present invention. [Figure 25] A memory circuit according to one aspect of the present invention. [Figure 26] A timing chart for the writing operation of a memory circuit according to one aspect of the present invention. [Figure 27] Write time characteristics of a memory circuit according to one aspect of the present invention. [Figure 28] Relationship between retention capacity and write time of a memory circuit according to one aspect of the present invention. [Figure 29] Characteristics of a memory circuit according to one aspect of the present invention. [Figure 30] Electron current density distribution of the active layer obtained by device calculations. [Figure 31]Electron current density distribution of the active layer obtained by device calculations. [Figure 32] Channel length dependence of the drain current of a transistor according to one aspect of the present invention. [Figure 33] Relationship between off-current and on-current of a transistor according to one aspect of the present invention. [Figure 34] A cross-sectional STEM image of a transistor according to one aspect of the present invention. [Figure 35] Electrical characteristics of a transistor according to one aspect of the present invention. [Figure 36] Electrical characteristics of a transistor according to one aspect of the present invention. [Figure 37] Electron current density distribution of the active layer obtained by device calculations. [Figure 38] High-resolution TEM images and local Fourier transform images of a cross-section of an oxide semiconductor. [Figure 39] An example of a nanobeam electron diffraction pattern of an oxide semiconductor and a transmission electron diffraction measurement device. [Figure 40] An example of structural analysis by transmission electron diffraction measurement, and a high-resolution TEM image in a planar view. [Figure 41] A cumulative frequency distribution of the threshold value of a transistor according to one aspect of the present invention. [Figure 42] A cumulative frequency distribution of the threshold value of a transistor according to one aspect of the present invention. [Figure 43] A cumulative frequency distribution of the threshold value of a transistor according to one aspect of the present invention. [Modes for carrying out the invention]

[0020] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described below. It is not limited to the above, and its form and details can be easily changed in various ways, as can be easily seen by those skilled in the art. It is understood that the present invention is to be interpreted as being limited to the embodiments described below. No. Furthermore, when explaining the structure of the invention using drawings, the same reference numerals may refer to different things. It is used consistently across drawings. Furthermore, when referring to similar items, the hatch pattern is the same. Furthermore, sometimes no symbol is assigned.

[0021] Note that in the diagram, the size, thickness of the film (layer), or area has been exaggerated for clarity. They may exist.

[0022] Furthermore, voltage is defined by a certain potential and a reference potential (e.g., ground potential (GND) or source potential). It often refers to the potential difference between two points. Therefore, it is possible to rephrase voltage as potential. .

[0023] The ordinal numbers "1st" and "2nd" are used for convenience only and do not necessarily indicate the order of processes or layering. It does not indicate order. Therefore, for example, "the first" could be "the second" or "the third." It can be explained by substituting it as appropriate. Also, the ordinal numbers and The ordinal numbers used to specify one aspect of the present invention may not always coincide.

[0024] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it can be referred to as an "insulator." They may have the following characteristics. Also, the boundary between "semiconductors" and "insulators" is ambiguous, and strictly speaking... In some cases, it may be impossible to distinguish between them. Therefore, the term "semiconductor" as used in this specification is used interchangeably with "insulator". In some cases, it can be rephrased. Similarly, the term "insulator" as used herein may be interpreted as "semiconductor." In some cases, this can be rephrased as "...".

[0025] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently high, it can be referred to as a "conductor." They may have certain characteristics. Also, the boundary between "semiconductors" and "conductors" is ambiguous, and strictly speaking... In some cases, it may be impossible to distinguish between them. Therefore, the term "semiconductor" as used in this specification is used interchangeably with "conductor". In some cases, it can be rephrased. Similarly, the term "conductor" as used herein means "semiconductor." In some cases, this can be rephrased as "...".

[0026] Furthermore, semiconductor impurities refer to components other than the main components that make up the semiconductor, for example, concentration. Elements present in less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, affect semiconductors. The formation of Density of State (DOS) in the body, and carrier mobility In some cases, the quality may decrease, or the crystallinity may decrease. In the case of semiconductors, impurities that alter the properties of semiconductors include, for example, Group 1 elements and Group 2 elements. These include elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, and in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen These are some examples. In the case of oxide semiconductors, for example, the inclusion of impurities such as hydrogen can form oxygen vacancies. This can occur. Also, if the semiconductor is silicon, impurities can change the properties of the semiconductor. In terms of substances, for example, Group 1 elements (excluding oxygen and hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements. There are group elements, etc.

[0027] In the embodiments shown below, unless otherwise specified, the insulator is, for example, boron. , carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, A Lugon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, An insulator containing one or more types of hafnium or tantalum can be used in a single layer or in a multilayer structure. Alternatively, a resin may be used as an insulator. For example, polyimide, polyamide, acrylic resin. A resin containing ylyl or silicone can be used. By using a resin, the top surface of the insulator can be In some cases, planarization treatment may not be necessary. Also, resins can form thick films in a short amount of time. Therefore, productivity can be increased. As an insulator, aluminum oxide is preferred. Silicon nitride, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide An insulator containing um, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide It can be used in a single layer or in a laminated configuration.

[0028] Furthermore, in the embodiments shown below, unless otherwise specified, the conductor is, for example, boron. Nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, corn Bals, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ru A conductor containing one or more of thenium, silver, indium, tin, tantalum, or tungsten. It can be used in a single layer or in a laminated form. For example, it may be an alloy or compound, aluminum Conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, Conductors containing zinc, tin, and oxygen, or conductors containing titanium and nitrogen may also be used. stomach.

[0029] In this specification, when it is stated that A has a region of concentration B, for example, A If the entire depth direction in a region is concentration B, then the average depth direction in a certain region of A If the value is concentration B, then if the median value in the depth direction in a certain region of A is concentration B, then A If the maximum value in the depth direction in a certain region is concentration B, then in a certain region of A, If the minimum value in the direction is concentration B, then the convergence value in the depth direction in a certain region of A is concentration B. This includes cases where the region in which a reliable value of A itself can be obtained through measurement is the region where the concentration is B.

[0030] Furthermore, in this specification, A has an area of ​​size B, length B, thickness B, width B, or distance B. When describing it as "doing," for example, if the entire area of ​​A has size B, length B, and thickness B, then... If the width is B or the distance is B, then the average value in a region of A is size B, length B, thickness If B is the width B or distance B, then the median value in a region of A is the size B, length B, and thickness B. If the size B is the width B or the distance B, then the maximum value in a region of A is the size B, length B, If the thickness is B, the width is B, or the distance is B, then the minimum value in a region of A is the size B, the length B If the thickness is B, the width is B, or the distance is B, then the convergence value in a region of A is the magnitude B, the length When B is thickness B, width B, or distance B, a reliable value of A itself can be obtained through measurement. This includes cases where the region has size B, length B, thickness B, width B, or distance B.

[0031] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0032] In the following, unless otherwise specified, the example refers to a semiconductor containing an oxide semiconductor in the channel formation region. This section describes conductive devices.

[0033] Figure 1(A) is a top view, and the cross-section in the direction of the dashed line A1-A2 shown in Figure 1(A) is shown in Figure 1(B) ) corresponds to. Also, the cross section in the direction of the dashed line A3-A4 shown in Figure 1(A) corresponds to Figure 1(C). This is correct. Note that in Figures 1(A), (B), and (C), some elements have been enlarged for clarity. The diagrams are reduced in size or abbreviated. Also, the dashed line A1-A2 indicates the channel length direction. The direction of the dashed line A3-A4 is sometimes referred to as the channel width direction.

[0034] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the gate electrode overlaps with the part of the semiconductor through which current flows when the zistor is ON. , or the source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the other element. In a zista, the channel length is not necessarily the same across all regions. That is, one channel The channel length of a transistor may not be fixed to a single value. Therefore, in this specification... The channel length is one of the following values ​​in the region where the channel is formed: maximum value, minimum value. Alternatively, use the average value.

[0035] Channel width refers to, for example, the channel width of a semiconductor (or transistor) when it is in the ON state. In the region where the current flows and the gate electrode overlap, or in the region where the channel is formed This refers to the length of the part where the source and drain face each other. In a stylus, the channel width is not necessarily the same across all regions. That is, one channel The channel width of a transistor may not be fixed to a single value. Therefore, in this specification... The channel width is any one value, maximum value, or minimum value in the region where the channel is formed. Alternatively, use the average value.

[0036] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. In some cases, such as in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor may be The ratio of channel regions formed on the side surface of the semiconductor to the ratio of channel regions formed In some cases, the apparent channel width shown in the top view may become larger. However, the effective channel width actually formed is larger.

[0037] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0038] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel is the length of the portion in the region where the source and drain face each other. Channel width is defined as "Surrounded Channel Width (SCW)". It is sometimes referred to as "channel width." Also, in this specification, when simply referred to as channel width, This may refer to the enclosed channel width or the apparent channel width. Or, this detail In some documents, when simply referred to as "channel width," it may refer to the effective channel width. Oh, channel length, channel width, effective channel width, apparent channel width, enclosure channel Channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. The value can be determined.

[0039] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0040] The transistor 101 has an insulator 120 on the substrate 110 and an oxide semiconductor on the insulator 120. The conductor 130, the source electrode 140 and the drain that are electrically connected to the oxide semiconductor 130 The in electrode 150, the oxide semiconductor 130, the source electrode 140 and the drain electrode 150 The gate insulator 160, the oxide semiconductor 130, part of the source electrode 140 and the drain It has a gate electrode 170 that overlaps with a portion of the electrode 150 via a gate insulator 160. Furthermore, an insulator 180 may be provided on the gate insulator 160 and the gate electrode 170. Furthermore, an insulator 185 formed of oxide material may be formed on the insulator 180. However, the insulator 185 is not required. Furthermore, another insulator may be formed on top of it. stomach.

[0041] A transistor according to one aspect of the present invention has a top channel length of 10 nm to 300 nm. It has a t-type structure. Also, the gate electrode 170 and the source electrode 140 overlap region 1 Region 1 where 91(LovS) and the gate electrode 170 and drain electrode 150 overlap each other. It has 92 (LovD). The width in the channel length direction of region 191 and region 192 is parasitic To reduce capacitance, it is preferable to have a wavelength of 3 nm or more and less than 300 nm.

[0042] Furthermore, in the region where the channel is formed, the film thickness of the oxide semiconductor 130 is 30 nm or more. It is preferable to set it to 0 nm or less. For example, it can also be set to 100 nm or more and 200 nm or less. Yes, it is possible. Note that the height of the protrusions formed by over-etching of the insulator 120 is also considered in relation to the above value. It may include the height of the protrusion and the film thickness of the oxide semiconductor 130. It is also acceptable to specify a range of 30nm to 300nm (for example, 100nm to 200nm). do not have.

[0043] Furthermore, it is preferable that the value obtained by dividing the film thickness of the oxide semiconductor 130 by the channel width be 0.5 or greater. It is preferable that the value be between 0.5 and 5 or between 1 and 3.

[0044] Furthermore, the thickness of the gate insulator 160 shall be between 2 nm and 30 nm in terms of oxide film thickness. This is preferable. Also, the thickness of the insulator 120 is 10 nm or more and 1000 nm in terms of oxide film thickness. It is preferable to keep it at m or less.

[0045] In the transistor 101 shown in Figure 1, the gate electrode 170 is connected to the channel of the oxide semiconductor 130. The structure is electrically surrounded in the width direction. In particular, as shown in Figure 2, the gate electrode 17 0 surrounds the oxide semiconductor 130 not only on the top surface but also on the sides, and the oxide semiconductor 13 The structure may extend below 0. In this way, oxidation by the gate electrode is also possible. The structure of a transistor in which the channel width direction of a semiconductor is electrically surrounded is called a surround. This is called a ded channel (s-channel) structure.

[0046] Transistor 101 has a surround channel structure, and the channel width is narrowed. By doing so, it becomes easier to control carriers by the gate electric field with respect to the side surface of the oxide semiconductor 130. Therefore, a transistor 101 having good subthreshold characteristics and an extremely small off-current can be obtained. Also, by adopting such a structure, a channel may be formed in the entire (bulk) of the oxide semiconductor 130. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current ) during conduction can be increased. Moreover, at least a part ( ) or all of the source electrode 140 (and / or the drain electrode 150) is in contact with at least a part (or all) of the surface, side surface, upper surface, and / or

[0047] lower surface of a semiconductor such as the oxide semiconductor 130. In the oxide semiconductor 130 in contact, hydrogen can enter the oxygen-deficient sites to form donor levels, and it has an N-type conductive region. Note that the state where hydrogen has entered the oxygen-deficient sites may be denoted as V H . As a result, by allowing current to flow through the N-type conductive region, a good on-current can be obtained. O H Furthermore, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor 130 and make the oxide semiconductor intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor is 1×10 or less, preferably 1×10

[0048] or less, more preferably 1×10 or less, even more preferably 1×10 or less, and still more preferably 1×10 17 per cm 3 or less, preferably 1×10 15 per cm 3 or less, even more preferably 1×10 13 per cm 3 or less, and still more preferably 1×10 11 per / cm 3 The following is particularly preferable: 1 × 10 10 pieces / cm 3 The following is true: 1 × 10 -9 pcs / c m 3 This refers to the above. In oxide semiconductors, hydrogen, nitrogen, carbon, silicon, and Metal elements other than the main component become impurities. For example, hydrogen and nitrogen are involved in the formation of donor levels. This contributes to and increases carrier density.

[0049] Transistors using this oxide semiconductor have a low carrier density in the channel formation region. Therefore, it is rare for the threshold voltage to be negative in electrical characteristics. Transistors using semiconductors have fewer carrier traps in oxide semiconductors, thus providing electrical characteristics This results in transistors with small fluctuations in performance and high reliability. Furthermore, using this oxide semiconductor... Transistors can achieve very low off-currents.

[0050] Furthermore, if transistor 101 is a storage type with electrons as the majority carrier, then an oxide semiconductor... Channel formation region from the region of 130 in contact with source electrode 140 and drain electrode 150 The electric field extending to it is easily shielded, and even with short channels, carrier control is performed by the gate electric field. It's cheap.

[0051] Furthermore, by forming transistors on an insulating surface, the semiconductor substrate can be used directly for channel formation. Unlike when used as a region, between the gate electrode and the oxide semiconductor or semiconductor substrate Because parasitic capacitance is not formed, carrier control by the gate field becomes easier. Good switching characteristics can be obtained.

[0052] This structure allows for good electrical characteristics. Specifically, it provides excellent sub-threads. It offers excellent balance characteristics, extremely low off-current, and good on-current.

[0053] This structure allows for good electrical characteristics even in minute transistors. The miniaturization of transistors reduces the various parasitic capacitances in the transistors, resulting in improved performance. Excellent switching characteristics can be obtained.

[0054] For example, the channel length and channel width can be set to 50 nm. In the region formed, the thickness of the oxide semiconductor 130 is set to 40 nm, and the gate insulator 160 The thickness is set to 11 nm in terms of oxide film thickness, and the thickness of the insulator 120 is set to 390 nm in terms of oxide film thickness. It can be expressed as m.

[0055] As a result, the channel width at a gate voltage of 3V, drain voltage of 1V, and source voltage of 0V is specified. The graded on-current can be 58 μA / μm, and the off-current can be 0.1 pA or less. It is possible. Furthermore, the threshold voltage can be set to a positive value (also known as the normally-off electrical characteristic). Furthermore, it is also possible to set the gate voltage at which the drain current becomes 1 pA to 0 V or higher. Also, DIBL (Drain Induced Barrier Lowering) ) is between 45mV / V and 100mV / V, typically 67mV / V, SS (Subt). The hourly swing value is 60mV / dec to 120mV / dec. Below c, excellent electrical characteristics of 92mV / dec can be obtained, which is typical.

[0056] By using a transistor with this structure, it is possible to have a normally off state and a transistor The switch speed of the inverter should be less than 100 ns, preferably less than 10 ns, and 10 ps or more. It is possible.

[0057] As an example, a transistor with a channel length of 64 nm and a channel width of 68 nm is programmed into a transistor. When used as a zista and charging its capacity, a capacity of 14fF is charged in approximately 60ns. It can be charged to 0%.

[0058] Furthermore, the transistor switching speed is less than 10 ns, 10 ps or more, preferably less than 3 ns. It can be set to 100 hp or more.

[0059] Furthermore, a fast switching speed (also called the switching speed) of a transistor means that... This refers to the short switching time required for a transistor. For example, the switching time of a transistor The term "transistor speed" refers to the time it takes for the gate capacitance of a single transistor to reach 90% charge. This represents the time it takes for a single transistor to transition from a non-conductive state to a conductive state when there is no load. This means that when the gate voltage changes, the increment in the transistor's drain current corresponds to the gate capacitance. The increment of accumulated charge can be interpreted as the charging time. Alternatively, the transistor The time required for switching is the current gain when using a transistor as an amplifier. The maximum frequency f that is greater than or equal to 1 T Using (also called the cutoff frequency), 1 / (2×f T ) There are cases where this occurs. Or, the maximum frequency f at which the power gain is 1 or greater. max (Maximum oscillation frequency) Using (also called a number), 1 / (2 × f max It is sometimes expressed as ). Power gain is simply Directional power gain and maximum capable power gain can be used.

[0060] The switch speed can be measured or verified by calculation. Therefore, SPICE can be used for verification. Transistor model parameters The data is preferably extracted from the electrical characteristics of the transistor that were actually measured. Measurements can be taken at room temperature, or at low temperatures (e.g., -40°C) or high temperatures (e.g., 125°C). The electrical characteristics may also be measured together. As an example of a transistor model, RPI(Re Using the NNSSelaer Polytechnic Institute model This is possible. Furthermore, based on the layout, parasitic elements such as parasitic capacitance and parasitic resistance can be extracted. It is preferable to do so.

[0061] As an example, a transistor with a channel length of 64 nm and a channel width of 68 nm was extracted. In SPICE calculations using the generator model parameters, a capacity of 1 fF or less is charged. In this case, it can be charged to 90% in less than 5ns.

[0062] Furthermore, by using transistors with this structure, the oxide film thickness can be reduced to 11 nm. Even with a relatively thick gate insulator, the channel length remains extremely low even when shortened to about 50 nm. This results in very good subthreshold characteristics.

[0063] Furthermore, by using transistors with this structure, the oxide film thickness can be reduced to 11 nm. Despite being a relatively thick gate insulator and having a gate overlap structure, the channel Even when the thread length is shortened to about 50nm, it exhibits extremely low off-current and very good subthreshold. The characteristics can be obtained.

[0064] By using a relatively thick gate insulator, leakage current through the gate insulator is reduced. Furthermore, compared to forming a thin gate insulator, it can be manufactured more easily and has less variation in film thickness. This makes it possible to form small gate insulators.

[0065] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner.

[0066] Furthermore, at least a portion of the source electrode 140 (and / or drain electrode 150) (or all) the surface, sides, top surface, and / or of a semiconductor such as oxide semiconductor 130. It is provided on at least part (or all) of the lower surface.

[0067] Alternatively, at least a portion of the source electrode 140 (and / or drain electrode 150) (or all) refers to the surface, sides, top, and / or other surfaces of semiconductors such as oxide semiconductor 130. Alternatively, it is in contact with at least part (or all) of the lower surface. Or, source electrode 14 At least part (or all) of 0 (and / or the drain electrode 150) is oxidized. It is in contact with at least a part (or all) of the semiconductor, such as semiconductor 130.

[0068] Alternatively, at least a portion of the source electrode 140 (and / or drain electrode 150) (or all) refers to the surface, sides, top, and / or other surfaces of semiconductors such as oxide semiconductor 130. Or, it is electrically connected to at least part (or all) of the underside. Or, At least a portion (or all) of the drain electrode 140 (and / or drain electrode 150) ) is electrically connected to at least a part (or all) of the semiconductor, such as the oxide semiconductor 130. It continues.

[0069] Alternatively, at least a portion of the source electrode 140 (and / or drain electrode 150) (or all) refers to the surface, sides, top, and / or other surfaces of semiconductors such as oxide semiconductor 130. Or, it is positioned in close proximity to at least part (or all) of the underside. At least a portion (or all) of the drain electrode 140 (and / or drain electrode 150) ) is distributed in close proximity to at least a part (or all) of the semiconductor, such as the oxide semiconductor 130. It is placed there.

[0070] Alternatively, at least a portion of the source electrode 140 (and / or drain electrode 150) (or all) refers to the surface, sides, top, and / or other surfaces of semiconductors such as oxide semiconductor 130. Alternatively, it is located on the side of at least part (or all) of the bottom surface. At least part (or all) of electrode 140 (and / or drain electrode 150) , disposed on the side of at least a portion (or all) of the semiconductor, such as the oxide semiconductor 130. Yes, they are.

[0071] Alternatively, at least a portion of the source electrode 140 (and / or drain electrode 150) (or all) refers to the surface, sides, top, and / or other surfaces of semiconductors such as oxide semiconductor 130. Or, it is positioned diagonally upward on at least part (or all) of the underside. Or, At least a portion (or all) of the drain electrode 140 (and / or drain electrode 150) ) is positioned diagonally above at least a portion (or all) of the semiconductor, such as the oxide semiconductor 130. It is placed there.

[0072] Alternatively, at least a portion of the source electrode 140 (and / or drain electrode 150) (or all) refers to the surface, sides, top, and / or other surfaces of semiconductors such as oxide semiconductor 130. Alternatively, it is located on the upper side of at least part (or all) of the lower surface. At least part (or all) of electrode 140 (and / or drain electrode 150) , disposed on top of at least a portion (or all) of the semiconductor, such as the oxide semiconductor 130. Yes, they are.

[0073] Furthermore, as shown in Figure 3, transistor 101 is connected between the oxide semiconductor 130 and the substrate 110. A conductor 172 may be provided in between. The conductor may be the second gate electrode (back gate). By using it in this way, it is possible to further increase the on-current and control the threshold voltage. To increase the on-current, for example, the gate electrode 170 and the conductor 172 are brought to the same potential. To drive transistor 101, you need to use the gate. A constant potential different from that of electrode 170 should be supplied to the conductor 172.

[0074] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 4(A), 4(B), and 4(C). This configuration is also acceptable. Figure 4(A) is a top view, and the dashed line B1-B shown in Figure 4(A) The cross-sections in two directions correspond to Figure 4(B). Also, the dashed line B3-B4 direction shown in Figure 4(A) The cross-section corresponds to Figure 4(C). Note that in Figures 4(A), 4(B), and 4(C), For clarity, some elements of the diagram have been enlarged, reduced, or omitted. Also, one point The direction from the dashed line B1 to B2 is called the channel length direction, and the direction from the dashed line B3 to B4 is called the channel width direction. It may happen.

[0075] The transistor 102 shown in Figures 4(A), 4(B), and 4(C) is made of an oxide semiconductor 1 30 is the first oxide semiconductor 131, the second oxide semiconductor 132, and so on from the insulator 120 side. The fact that the third oxide semiconductor 133 is formed in that order is different from transistor 101.

[0076] For example, a first oxide semiconductor 131, a second oxide semiconductor 132, and a third oxide semiconductor The conductor 133 can be an oxide semiconductor or the like with a different composition. However, For example, if the first oxide semiconductor 131 and the third oxide semiconductor 133 are the same or different It may also be a composition in the vicinity of [the specified value].

[0077] Furthermore, the explanation regarding the shape of the oxide semiconductor 130 in transistor 101 is provided below. It can also be applied to ST102, and the same effect can be obtained. Furthermore, the configuration shown in Figure 3 can be used to It can also be applied to the Radista 102.

[0078] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 5(A), 5(B), and 5(C). This configuration is also acceptable. Figure 5(A) is a top view, and the dashed line C1-C shown in Figure 5(A) The cross-sections in two directions correspond to Figure 5(B). Also, the dashed line C3-C4 direction shown in Figure 5(A) The cross-section corresponds to Figure 5(C). Note that in Figures 5(A), 5(B), and 5(C), For clarity, some elements of the diagram have been enlarged, reduced, or omitted. Also, one point The direction from the dashed line C1 to C2 is called the channel length direction, and the direction from the dashed line C3 to C4 is called the channel width direction. It may happen.

[0079] The transistors 103 shown in FIGS. 5(A), 5(B), and 5(C) have a stack in which an oxide semiconductor 1 30 is formed in the order of a first oxide semiconductor 131 and a second oxide semiconductor 132 from the insulator 120 side, and a third oxide semiconductor 133 covering a part of the stack, which is different from the transistors 101 and 102.

[0080] For example, oxide semiconductors with different compositions can be used for the first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 133, respectively. However, for example, the first oxide semiconductor 131 and the third oxide semiconductor 133 may have the same or similar compositions.

[0081] Specifically, the transistor 103 includes an insulator 120 on a substrate 110, a stack formed in the order of a first oxide semiconductor 131 and a second oxide semiconductor 132 on the insulator 120, source electrodes 140 and drain electrodes 150 electrically connected to a part of the stack, a third oxide semiconductor 133 covering a part of the stack, a part of the source electrodes 140, and a part of the drain electrodes 150, a gate insulator 160 and a gate electrode 170 overlapping with a part of the stack, the third oxide semiconductor 133, a part of the source electrodes 140, and a part of the drain electrodes 150. An insulator 180 may be provided on the source electrodes 140, the drain electrodes 150, and the gate electrode 170. An insulator 185 formed of an oxide may be formed on the insulator 180. The insulator 185 may not be provided. Further, another insulator may be formed on the upper part thereof.

[0082] ​​​​​​​​​​​ In the transistor 101 shown in Figure 1, the oxide semiconductor 13 is present in the region where the channel is formed. 0 is a single layer. On the other hand, in the transistor 102 shown in Figure 4, the oxide semiconductor 130 is on substrate 1 From side 10, the first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor It has a three-layer structure in which 133 is stacked. Also, in transistor 103 shown in Figure 5, It has a three-layer oxide semiconductor 130, similar to transistor 102. On the other hand, channel In the formation region, the second oxide semiconductor 132 is formed by the first oxide semiconductor 131 and the third It has a structure surrounded by oxide semiconductor 133.

[0083] Furthermore, in the structure of transistors 102 and 103, the oxide semiconductor 13 By appropriately selecting the three materials that make up 0, the current is distributed throughout the second oxide semiconductor 132. Current can flow through the second oxide semiconductor 132 inside the oxide semiconductor 130. This makes it less susceptible to interfacial scattering and allows for a high on-current. Increasing the thickness of the oxide semiconductor 132 can improve the on-current.

[0084] Next, the components of a transistor according to one embodiment of the present invention will be described in detail.

[0085] The substrate 110 is not merely a support material, but also has other devices such as transistors formed on it. A circuit board may also be used. In this case, the gate electrode 170 and source electrode 140 of the transistor, And one of the drain electrodes 150 may be electrically connected to the other devices mentioned above. stomach.

[0086] The insulator 120 has the role of preventing the diffusion of impurities from the substrate 110, as well as oxide semiconductors. It can play a role in supplying oxygen to the conductor 130. Therefore, the insulator 120 is oxygen It is preferable that the insulator contains oxygen in a quantity greater than the stoichiometric composition. This is more preferable. For example, thermal desorption gas spectroscopy (TDS) In spectrometry, the amount of oxygen released, converted to oxygen atoms, is 1 .0 × 10 19 atoms / cm 3 The membrane is defined as described above. Furthermore, during the above TDS analysis... The surface temperature of the film is between 100°C and 700°C, or between 100°C and 500°C. A range is preferred. Also, as mentioned above, the substrate 110 is a substrate on which other devices are formed. In this case, the insulator 120 also functions as an interlayer insulator. In that case, the surface becomes flat. Methods such as CMP (Chemical Mechanical Polishing) It is preferable to perform a planarization treatment.

[0087] In this embodiment, we will primarily describe in detail the case where the oxide semiconductor 130 has a three-layer structure. To clarify, the number of layers does not matter. Like transistor 101, the oxide semiconductor 130 is one layer. In that case, a layer corresponding to the second oxide semiconductor 132 described in this embodiment may be used. Furthermore, if the oxide semiconductor 130 is a two-layer structure, for example, transistor 102 or transistor In the configuration of the oxide semiconductor 130 shown in ZISTA 103, a third oxide semiconductor 133 is provided. A configuration that does not involve this is acceptable. In this configuration, the second oxide semiconductor 132 and the first oxide semiconductor The conductor 131 can also be replaced. Also, if the oxide semiconductor 130 has four or more layers. For example, this involves stacking other oxide semiconductors on top of the three-layer structure described in this embodiment. It is configured to insert another oxide semiconductor into the interface of any of the layers or the three-layer structure. This can be achieved.

[0088] As an example, for the second oxide semiconductor 132, an oxide semiconductor with a larger electron affinity (energy from the vacuum level to the bottom of the conduction band) than that of the first oxide semiconductor 131 and the third oxide semiconductor 133 is used. The electron affinity can be obtained as a value obtained by subtracting the energy difference (energy gap) between the bottom of the conduction band and the top of the valence band from the energy difference (ionization potential) between the vacuum level and the top of the valence band. The first oxide semiconductor 131 and the third oxide semiconductor 133 contain one or more metal elements constituting the second oxide semiconductor 13 2. For example, the energy of the bottom of the conduction band is any one of 0.05 eV, 0.07 eV, 0.1 eV, 0.15 eV or more

[0089] higher than that of the second oxide semiconductor 132 and is preferably formed of an oxide semiconductor close to the vacuum level in the range of any one of 2 eV, 1 eV, 0.5 eV, 0.4 eV or less.

[0090] In such a structure, when an electric field is applied to the gate electrode 170, a channel is formed in the second oxide semiconductor 132 having the smallest energy at the bottom of the conduction band among the oxide semiconductors 130.

[0091] In addition, since the first oxide semiconductor 131 is composed of one or more metal elements constituting the second oxide semiconductor 132, when the second oxide semiconductor 132 and the insulator 120 are in contact compared with the interface in this case, it is less likely to form interface levels at the interface between the second oxide semiconductor 132 and the first oxide semiconductor 131. Since the interface levels may form a channel, the interface between the second oxide semiconductor 13 interface levels are less likely to be formed at the interface between the second oxide semiconductor 132 and the first oxide semiconductor 131 compared to the interface between the second oxide semiconductor 132 and the insulator 120. Since the interface levels may form a channel, the The threshold voltage of the inverter may fluctuate. Therefore, the first oxide semiconductor 131 By providing this feature, variations in electrical characteristics such as the threshold voltage of transistors are reduced. This can be done. Furthermore, the reliability of the transistor can be improved.

[0092] Furthermore, the third oxide semiconductor 133 contains the same metal elements as the second oxide semiconductor 132. Because it is composed of more than one species, the second oxide semiconductor 132 and the gate insulator 160 are in contact. Compared to the interface in the case of the second oxide semiconductor 132 and the third oxide semiconductor 133, This makes carrier scattering less likely. Therefore, a third oxide semiconductor 133 is provided. This allows for an increase in the field-effect mobility of the transistor.

[0093] The first oxide semiconductor 131 and the third oxide semiconductor 133 are, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf is used as the second oxide semiconductor 132. Materials containing a high atomic ratio can be used. Specifically, the atomic ratio can be increased by 1.5 times or more. Preferably, the amount is 2 times or more, and more preferably 3 times or more. The aforementioned elements bond strongly with oxygen. Therefore, it has the function of suppressing the occurrence of oxygen vacancies in oxide semiconductors. The first oxide semiconductor 131 and the third oxide semiconductor 133 are connected to the second oxide semiconductor 13 It can be said that oxygen deficiency is less likely to occur than in scenario 2.

[0094] Furthermore, the first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 13 3 contains at least indium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr, Sn When it is an In-M-Zn oxide containing a metal (such as La, Ce or Hf), the first oxidation The first is a crystalline semiconductor 131 with In:M:Zn=x1:y1:z1 [atomic ratio], and the second is an oxide semiconductor 132 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor 133 is If we set In:M:Zn=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 It is preferable that y1 / x1 and y3 / x3 are greater than y2 / x It should be 1.5 times or more than 2, preferably 2 times or more, and even more preferably 3 times or more. In the second oxide semiconductor 132, if y2 is greater than or equal to x2, the electrical characteristics of the transistor The properties can be stabilized. However, if y2 becomes more than 3 times x2, the transistor Because the field-effect mobility decreases, it is preferable that y2 be less than three times x2.

[0095] I excluding Zn and O from the first oxide semiconductor 131 and the third oxide semiconductor 133 The atomic ratio of n and M is preferably less than 50 atomic% for In and 50 atomic% for M. Higher than mic%, and more preferably In is less than 25 atomic%, and M is 75 atomic. Make it higher than ic%. Also, remove In from the second oxide semiconductor 132, excluding Zn and O. The atomic ratio of In and M is preferably such that In is higher than 25 atomic%, and M is 75 atomic%. Less than mic%, more preferably In is higher than 34 atomic%, and M is 66 atomic. It should be less than ic%.

[0096] The thickness of the first oxide semiconductor 131 and the third oxide semiconductor 133 is 3 nm or more. The wavelength should be less than or equal to nm, preferably between 3 nm and 50 nm. Also, the second oxide semiconductor 132 The thickness is 3 nm to 200 nm, preferably 10 nm to 100 nm, and further Preferably, the wavelength is 10 nm or more and 80 nm or less. Also, the second oxide semiconductor 132 is the first It is preferable that the oxide semiconductor 131 and the third oxide semiconductor 133 are thicker than the first oxide semiconductor 131.

[0097] Furthermore, in order to impart stable electrical characteristics to an oxide semiconductor channel transistor This reduces the impurity concentration in oxide semiconductors, making the oxide semiconductor intrinsically or substantially intrinsically This is effective. Here, "substantially true" means that the carrier density of the oxide semiconductor is 1 × 10 17 pieces / cm 3 The following is preferably 1 × 10 15 pieces / cm 3 More preferably, 1 ×10 13 pieces / cm 3 More preferably 1 × 10 11 pieces / cm 3 The following are particularly preferred is 1 x 10 10 pieces / cm 3 The following is true: 1 × 10 -9 pieces / cm 3 This refers to something that is greater than or equal to the above.

[0098] Furthermore, in oxide semiconductors, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component These elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, and carrier density This increases the amount of impurities. Furthermore, silicon contributes to the formation of impurity levels in oxide semiconductors. These impurity levels can act as traps, potentially degrading the electrical characteristics of the transistor. Therefore, the first oxide semiconductor 131, the second oxide semiconductor 132 and the third oxide semiconductor It is preferable to reduce the impurity concentration in the layers of the conductor 133 and at each interface.

[0099] To make oxide semiconductors intrinsically or substantially intrinsically, SIMS (Secondary In ion mass spectrometry analysis, for example, in oxide semiconductors, At a certain depth, or in a certain region of an oxide semiconductor, the silicon concentration is 1 × 1 0 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 less than, further Preferably 1 × 10 18 atoms / cm 3 It shall be less than . Also, the hydrogen concentration shall be, for example, At a certain depth in an oxide semiconductor, or in a certain region of an oxide semiconductor, 2 × 10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The following are better Mashiku is 1 x 10 19 atoms / cm 3 More preferably 5 × 10 18 Atom s / cm 3 The following applies. Furthermore, the nitrogen concentration is, for example, at a certain depth in the oxide semiconductor. Alternatively, in a region of an oxide semiconductor, 5 × 10 19 atoms / cm 3 Less than preferred Or 5x10 18 atoms / cm 3 More preferably 1 × 10 18 atom / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0100] Furthermore, if an oxide semiconductor contains crystals, and if silicon or carbon is present in high concentrations, the oxide semiconductor... This can reduce the crystallinity of conductors. To avoid reducing the crystallinity of oxide semiconductors, For example, at a certain depth in an oxide semiconductor, or in a certain region of an oxide semiconductor, silicon concentration 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 Atom s / cm 3 Less than 1 × 10 18 atoms / cm 3 You should use "less than". Furthermore, for example, at a certain depth in an oxide semiconductor, or in a certain region of an oxide semiconductor And the carbon concentration is 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 ato ms / cm 3 Less than 1 × 10 18 atoms / cm 3 You should use "less than". .

[0101] Furthermore, as mentioned above, a transistor using a highly purified oxide semiconductor in the channel formation region The off-current of the transistor is extremely small. For example, if the voltage between the source and drain is 0.1V, 5V Alternatively, if the voltage is set to approximately 10V, the off-current normalized by the transistor's channel width is It becomes possible to reduce the level from several yA / μm to several zA / μm.

[0102] Furthermore, as mentioned above, highly purified oxide semiconductors have fewer carrier sources, so The rear density can be reduced. Therefore, transistors using this oxide semiconductor It rarely exhibits electrical characteristics where the threshold voltage is negative. The body has few carrier traps. Therefore, transistors using this oxide semiconductor are This results in transistors with small fluctuations in electrical characteristics and high reliability.

[0103] Furthermore, silicon-containing insulators are often used as gate insulators for transistors. Therefore, for the reasons stated above, the region that becomes the channel of the oxide semiconductor is the transient of one aspect of the present invention It can be said that a structure that does not come into contact with the gate insulator, as shown in the example, is preferable. When a channel is formed at the interface between the edge material and the oxide semiconductor, carrier scattering occurs at the interface. This can lead to a decrease in the field-effect mobility of the transistor. From this perspective as well, acid It is preferable to keep the region that forms the channel of the semiconductor away from the gate insulator.

[0104] Therefore, the oxide semiconductor 130 is divided into the first oxide semiconductor 131 and the second oxide semiconductor 13 2. By creating a stacked structure of the third oxide semiconductor 133, the second oxide semiconductor 132 is connected to A channel can be formed, and it has high field-effect mobility and stable electrical characteristics. It can form an inverter. Furthermore, good switching characteristics can be obtained.

[0105] The first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 133 In the ND structure, the energy at the lower end of the conduction band changes continuously. This is due to the first oxidation The compositions of the material semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 133 are similar. This can be understood from the fact that oxygen molecules diffuse easily to each other. Therefore, the first oxidation The material semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 133 have different compositions. Although it is a laminate of layers, it can also be said to be continuous in terms of physical properties, as shown in the drawings of this specification. Each interface of the laminate is represented by a dotted line.

[0106] The oxide semiconductor 130, which is stacked with a common main component, is not simply stacked layer by layer, but rather connected A continuum (here, a U-shaped well where the energy at the lower end of the conduction band changes continuously between each layer) It is constructed so that a door structure (U-shaped well) is formed. That is, each layer The concentration of impurities that form defect levels such as trap centers and recombination centers at the interface is low. A layered structure is formed in such a way. If impurities are present at a high concentration between the layers of the stacked oxide semiconductor If present, the continuity of the energy band is lost, and carriers are trapped at the interface. It may disappear due to recombination.

[0107] For example, the first oxide semiconductor 131 and the third oxide semiconductor 133 have In:Ga:Z n=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4 or 1:9:6( (Atomic ratio), the second oxide semiconductor 132 has In:Ga:Zn=1:1:1, 5:5:6 Alternatively, In-Ga-Zn oxides such as 3:1:2 (atomic ratio) can be used. Furthermore, the first oxide semiconductor 131 has In:Ga:Zn=1:6:4 or 1:9:6 (Atomic ratio), the third oxide semiconductor 133 has In:Ga:Zn=1:3:2, 1:3:3 Alternatively, an In-Ga-Zn oxide with an atomic ratio of 1:3:4 may be used. First oxide semiconductor 131, second oxide semiconductor 132, and third oxide semiconductor 133 For film deposition, it is preferable to use a sputtering method using an oxide target with the atomic ratio described above. It seems that when using the sputtering method, the deposited oxide semiconductor film is also affected by the substrate heating temperature. The ratio of zinc to the conductor's composition is reduced by approximately 20% to 60% compared to the target composition. In some cases, this may occur. Also, the ratio of gallium to the composition of the deposited oxide semiconductor may be The composition may be reduced by 1% to 20% compared to that of GET.

[0108] In oxide semiconductor 130, the second oxide semiconductor 132 becomes a well, and oxide In a transistor using semiconductor 130, the channel is formed in the second oxide semiconductor 132. This is achieved. Furthermore, the energy at the lower end of the conduction band of the oxide semiconductor 130 changes continuously. Therefore, it can also be called a U-shaped well. Furthermore, channels formed in this configuration It can also be called an embedded channel.

[0109] Furthermore, the first oxide semiconductor 131 and the third oxide semiconductor 133, and the silicon oxide film Trap levels can form near the interface with any insulator due to impurities or defects. Due to the presence of the first oxide semiconductor 131 and the third oxide semiconductor 133, the second oxide The material semiconductor 132 and the trap level can be kept apart.

[0110] However, the energy at the lower end of the conduction band of the first oxide semiconductor 131 and the third oxide semiconductor 133 When the difference between the energy and the energy at the lower end of the conduction band of the second oxide semiconductor 132 is small, Electrons in oxide semiconductor 132 exceed the energy difference and reach the trap level. Electrons, which have a negative charge, are trapped in trap levels, thus creating a transistor barrier. The positive voltage will shift in the positive direction.

[0111] Therefore, in order to reduce the fluctuation of the transistor threshold voltage, the first oxide semiconductor 1 The energy of the lower end of the conduction band of 31 and the third oxide semiconductor 133, and the energy of the second oxide semiconductor It is preferable to create a difference of a certain amount or more between the energy of the lower end of the conduction band of 132 and the other energy. The energy difference in question is preferably 0.1 eV or more, and more preferably 0.15 eV or more. .

[0112] First oxide semiconductor 131, second oxide semiconductor 132, and third oxide semiconductor 133 Preferably, the crystal portion is included. In particular, using crystals oriented along the c axis allows for a translucency. This allows for the provision of stable electrical properties to the zista.

[0113] The source electrode 140 and the drain electrode 150 have the property of extracting oxygen from oxide semiconductors. It is preferable to use a conductor having the following properties: For example, Al, Cr, Cu, Ta, Ti, Mo, W These can be used. Among the above materials, Ti, which readily bonds with oxygen, and the later P It is preferable to use W, which has a high melting point, as this allows for setting the process temperature to be relatively high.

[0114] Due to the action of a conductor that has the property of extracting oxygen from oxide semiconductors, the oxygen in the oxide semiconductor The element is removed, and an oxygen vacancy is formed in the oxide semiconductor. The region becomes significantly n-type when the hydrogen atom present combines with the oxygen vacancy. The n-type region can be used as the source or drain of a transistor. Cut.

[0115] The gate insulator 160 contains aluminum oxide, magnesium oxide, silicon oxide, and nitrile oxide. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulator containing one or more types of tantalum oxide can be used. Also, the gate insulator 160 is The above materials may be laminated. Furthermore, the gate insulator 160 may contain lanthanum (La) and nitrogen. It may also contain impurities such as zirconium (Zr).

[0116] Furthermore, an example of the laminated structure of the gate insulator 160 will be described. The gate insulator 160 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide. , and preferably containing silicon oxide or silicon oxide nitride.

[0117] Hafnium oxide has a higher dielectric constant compared to silicon oxide and silicon oxide nitride. Therefore Therefore, the physical film thickness can be made larger than the oxide film thickness, so the oxide film thickness can be increased to 10n Even when the size is less than m or less than 5 nm, the leakage current due to tunnel current is reduced. This makes it possible to realize a transistor with a small off-current. Furthermore, Hafnium oxide with a crystalline structure has a higher specific induction compared to hafnium oxide with an amorphous structure. It possesses a high power rating. Therefore, in order to make a transistor with a low off-current, the crystal structure is It is preferable to use hafnium oxide containing [specific material]. Examples of crystal structures include monoclinic and cubic. Examples include crystal systems. However, one aspect of the present invention is not limited to these.

[0118] Incidentally, the surface of hafnium oxide having a crystalline structure has interface states due to defects. This may occur. The interface level may function as a trap center. Therefore, When hafnium oxide is placed in close proximity to the channel formation region of a transistor, the interface level The electrical characteristics of a transistor may deteriorate depending on the interface state. Therefore, the influence of the interface state is To reduce this, another film is placed between the transistor's channel formation region and hafnium oxide. In some cases, it is preferable to space them apart by arranging them. This membrane has a buffering function. It has. The film having a buffering function may be a film included in the gate insulator 160, It may also be a film contained in an oxide semiconductor. That is, as a film having a buffering function, it may be an oxide semiconductor. Recon, silicon oxide nitride, oxide semiconductors, etc., can be used. For example, the film has a larger energy gap than the semiconductor that forms the channel formation region. A semiconductor or insulator is used. Alternatively, a film having a buffering function may be used, for example, a channel A semiconductor or insulator with a lower electron affinity than the semiconductor forming the region is used. For example, a film with a buffering function has a higher ionization rate than the semiconductor that forms the channel formation region. Use a semiconductor or insulator with high energy.

[0119] On the other hand, the interface state (trap) on the surface of hafnium oxide having the above-described crystal structure By trapping charge at the center, the threshold voltage of the transistor can be controlled. There is a combination. In order to keep the charge stable, for example, a channel-forming region and an oxide layer If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium and the insulator... Alternatively, a semiconductor or insulator with a lower electron affinity than hafnium oxide can be placed. That would be sufficient. Alternatively, a membrane with a buffering function should have a higher ionization energy than hafnium oxide. A semiconductor or insulator with a large interface can be placed there. By using such an insulator, the interface can be opened. This makes it less likely for the charge trapped in the energy level to be released, allowing the charge to be retained for a longer period of time. It is possible.

[0120] Examples of such insulators include silicon oxide and silicon oxide-nitride. In order to trap charges in the interface levels within the insulator 160, charges are trapped from the oxide semiconductor 130. To move electrons toward electrode 170, a specific example would be to use a high temperature (for example) If the temperature is between 125°C and 450°C (typically between 150°C and 300°C), the gate Maintain a potential at electrode 170 that is higher than the potentials of source electrode 140 and drain electrode 150 for 1 second. In summary, you should maintain the position for at least one minute.

[0121] In this way, a transient is created in which a desired amount of electrons are trapped at the interface level of the gate insulator 160. The threshold voltage shifts to the positive side. The voltage of the gate electrode 170, and the voltage applied... By adjusting the time, the amount of electrons captured (the amount of variation in the threshold voltage) can be controlled. This is possible. Furthermore, if charge can be captured, not within the gate insulator 160 It is permissible to do so. A laminated film having a similar structure may also be used as an insulator for other materials.

[0122] The gate electrode 170 contains Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Conductors such as Ag, Ta, and W can be used. Furthermore, the gate electrode is as described above. The materials may be laminated. Furthermore, a nitrogen-containing conductor may be used for the gate electrode. good.

[0123] The gate insulator 160 and the insulator 180 formed on the gate electrode 170 contain aluminum oxide. It is preferable to include an aluminum film. The aluminum oxide film contains impurities such as hydrogen and water. It has a high barrier effect that prevents both oxygen and other elements from passing through the membrane. Therefore, aluminum oxide The film prevents changes in the electrical characteristics of the transistor during and after the transistor fabrication process. Prevention of contamination of oxide semiconductor 130 with impurities such as hydrogen and water that act as dynamic factors, oxide semiconductor 130 is a component material that prevents the release of oxygen from oxide semiconductors, and an insulator 120 It is suitable for use as a protective film that has the effect of preventing the unnecessary release of oxygen. Furthermore, it is possible to diffuse the oxygen contained in the aluminum oxide film into the oxide semiconductor.

[0124] Furthermore, it is preferable that an insulator 185 is formed on the insulator 180. Insulator 185 This includes magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride Licon, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, oxide An insulator containing one or more of lanthanum, neodymium oxide, hafnium oxide, and tantalum oxide is used. It is possible for it to be there. Also, the insulator 185 may be a laminate of the above materials.

[0125] Here, insulator 185, like insulator 120, has more oxygen than its stoichiometric composition. This is preferable. The oxygen released from the insulator 185 passes through the gate insulator 160 and becomes an oxide. Since it can be diffused into the channel formation region of semiconductor 130, the channel formation region Oxygen can be supplied to the oxygen deficiency formed therein. Therefore, a stable transient The electrical properties of the object can be obtained.

[0126] Furthermore, miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization of transistors degrades their electrical characteristics.

[0127] Therefore, in the transistor according to one embodiment of the present invention shown in Figure 5, as described above, the channel is shaped A third oxide semiconductor 133 is formed so as to cover the second oxide semiconductor 132 that is formed. Therefore, the channel forming layer and the gate insulator are not in contact. This can suppress carrier scattering at the interface between the cambium and the gate insulator, and transient The on-current of the switch can be increased. As a result, good switching characteristics can be obtained. .

[0128] In one embodiment of the present invention, the channel width of the oxide semiconductor 130 is as described above. Since the gate electrode 170 is formed so as to electrically surround the direction, the oxide semiconductor 13 For a value of 0, in addition to the gate electric field from the vertical direction, a gate electric field from the lateral direction is applied. In other words, a gate electric field is applied to the entire oxide semiconductor 130, and current The current now flows throughout the second oxide semiconductor 132, which acts as a channel, and furthermore, the on-current It can be improved. As a result, good switching characteristics can be obtained.

[0129] Furthermore, in one aspect of the present invention, the transistor comprises a second oxide semiconductor 132 and a first oxide semiconductor Forming it on body 131 has the effect of making it difficult to form interface states, and the second oxide semiconductor 1 By placing layer 32 in the middle of the three-layer structure, the influence of impurities from above and below can be eliminated. It also has the effect of improving the on-current of the transistor as described above. This allows for stabilization of the threshold voltage and improvement of SS. Therefore, the gate voltage V The current can be reduced when g is 0V, thereby reducing power consumption. When controlling the charge (or information) held by the transistor over a long period of time... It can hold (or store) the data. Also, the threshold voltage of the transistor is low. By standardizing the process, the long-term reliability of semiconductor devices can be improved.

[0130] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0131] (Embodiment 2) In this embodiment, the method for manufacturing the transistor 490 shown in Figure 6, which is one aspect of the present invention, is described below. Let me explain. Figure 6(A) is a plan view showing an example of the configuration of transistor 490. 6(B) shows a cross-sectional view in the direction of the dashed line E1-E2 in Figure 6(A), and the dashed line E3-E Cross-sectional views in four directions are shown.

[0132] First, the insulator 442 is deposited. The insulator 442 is deposited by sputtering, chemical vapor deposition (C VD (Chemical Vapor Deposition) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method or pulsed laser deposition (PLD:Pulsed Laser Deposition) method, atomic layer deposition (ALD) method The film can be deposited using methods such as Atomic Layer Deposition.

[0133] The insulator 442 is deposited using a metal or alloy target by DC sputtering. This is preferable. In particular, in the DC sputtering method using oxygen as the reactive gas, Because the reaction on the surface is insufficient, an insulating film containing a suboxide can be formed in some cases. Suboxides can be stabilized by capturing hydrogen, oxygen, etc. Therefore, they are insulators. If 442 is an insulator containing a suboxide, it will have high blocking properties against hydrogen, oxygen, etc. It can be seen that it is a related body.

[0134] Furthermore, the CVD method is a plasma CVD (PECVD) method that utilizes plasma. Processed CVD (CVD), thermal CVD (TCVD) which utilizes heat. It can be further classified into methods such as D) method. al CVD) method, Metal Organic CVD (MOCVD) It can be divided into laws.

[0135] Plasma CVD can produce high-quality films at relatively low temperatures. Thermal CVD uses plasma... Because there are no particles present, plasma damage does not occur, resulting in a film with fewer defects.

[0136] The CVD method allows for control over the composition of the resulting film by adjusting the flow rate ratio of the source gas. Example For example, in the MCVD and MOCVD methods, the flow rate ratio of the raw material gases can be used to create membranes of any composition. It is possible to deposit a film. Also, for example, in the MCVD method and MOCVD method, film deposition is possible. Furthermore, by changing the flow rate ratio of the raw material gas, a film with a continuously changing composition is formed. This is possible. When forming a film while changing the flow rate ratio of the raw material gas, multiple deposition chambers can be used. Compared to conventional film deposition, the time required for transport and pressure adjustment is reduced, thereby shortening the film deposition time. This is possible. Therefore, the productivity of transistor 490 can be increased.

[0137] Next, a conductive material to become conductive material 413 is deposited. The conductive material to become conductive material 413 is deposited by sputtering The film can be deposited using methods such as CVD, MBE, PLD, or ALD.

[0138] Next, a portion of the conductor that will become the conductor 413 is etched to form the conductor 413.

[0139] Next, the insulator 402 is deposited (see Figure 7(A)). The insulator 402 is deposited by sputtering. The film can be deposited using methods such as CVD, MBE, PLD, or ALD. This section describes the case where insulator 402 is flattened from the top surface by methods such as CMP. To clarify, flattening the upper surface of the insulator 402 makes subsequent processes easier, and the transistor The yield of 490 can be increased. For example, by the CMP method, the insulator 402 RMS (Root Mean Square) roughness of 1 nm or less is preferred. Or, 0.5 nm or less, more preferably 0.3 nm or less. Alternatively, 1 μm × 1 μm The average surface roughness (Ra) in the range of m is less than 1 nm, preferably less than 0.6 nm, and further Preferably less than 0.5 nm, more preferably less than 0.4 nm. Alternatively, 1 μm × 1 The Peak Valley in the μm range is less than 10 nm, preferably less than 9 nm. More preferably, the wavelength is less than 8 nm, and more preferably less than 7 nm. However, in one embodiment of the present invention The transistor 490 is not limited to the case where the upper surface of the insulator 402 is flattened.

[0140] The insulator 402 can be formed by depositing a film containing excess oxygen. Alternatively, the formation of the insulator 402 Oxygen can be added after the film is formed. Oxygen can be added, for example, by ion implantation, using accelerated electrophoresis. The pressure should be between 2kV and 100kV, and the dose should be 5 × 10⁻¹⁰ 14 ions / cm 2 The above 5x 10 16 ions / cm 2 You can do it as follows:

[0141] Furthermore, when the insulator 402 is constructed as a multilayer film, each film is formed using the above-described film deposition method. The method may be used to deposit films using different deposition methods. For example, the first layer may be deposited using the CVD method, and the second layer may be deposited using the CVD method. The first layer may be deposited by the ALD method. Alternatively, the first layer may be deposited by sputtering, and the second layer The film may also be deposited using the ALD method. In this way, by using different film deposition methods, This allows each layer of the film to have different functions and properties. And these films can be stacked. By doing so, a more appropriate film can be constructed as a whole.

[0142] In other words, the nth layer (where n is a natural number) is made using sputtering, CVD, MBE, or P The film is deposited using at least one method such as the LD method or ALD method, and the (n+1)th layer is spat At least one of the following methods: tarring, CVD, MBE, PLD, ALD, etc. The film is formed using two methods. Note that even if the deposition method is the same, the nth layer and the (n+1)th layer may differ. It is acceptable if it is the case. Furthermore, the deposition method for the nth layer and the (n+2)th layer may be the same. Alternatively, the film deposition method may be the same for all films.

[0143] Next, semiconductor 436a which will become semiconductor 406a, and semiconductor 436 which will become semiconductor 406b The film b is deposited in this order. Semiconductor 436a, which will become semiconductor 406a, and semiconductor 406b and The semiconductor 436b is produced by sputtering, CVD, MBE, or PLD, or ALD. The film can be deposited using methods such as [specific methods].

[0144] Furthermore, the In-Ga-Zn oxide layer is used as semiconductor 436a and semiconductor 436b. When forming films using the VD method, trimethylindium and trimethylgalium are used as raw material gases. You may use materials such as methyl zinc and dimethyl zinc. However, this is not limited to the above combination of raw material gases. Furthermore, triethylindium or other similar substances may be used instead of trimethylindium. Triethylgallium or other alternatives may be used instead of methylgallium. Dimethylzinc may also be used. Diethylzinc or the like may be used instead.

[0145] Next, it is preferable to perform a first heat treatment. The first heat treatment is performed at a temperature of 250°C to 650°C. Preferably, this should be carried out at a temperature of 300°C to 500°C. The first heat treatment is performed in an inert gas atmosphere. The process is carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The first heat treatment may be carried out under reduced pressure. Alternatively, the first heat treatment may be carried out using an inert gas After heat treatment in an atmosphere, an oxidizing gas of 10 ppm or more is added to replenish the desorbed oxygen. Heat treatment may be carried out in an atmosphere containing % or more or 10% or more. This is to improve the crystallinity of semiconductor 436a and semiconductor 436b, and to remove impurities such as hydrogen and water. It can remove objects, etc.

[0146] Next, the conductive film 416 is deposited (see Figure 7(B)). The conductive film 416 is deposited by sputtering. The film can be deposited using methods such as CVD, MBE, PLD, or ALD.

[0147] Conductors 416a and 416b are formed after the conductor 416 is formed. It is formed by etching a portion of it. Therefore, when forming the conductive film 416, the semiconductor It is preferable to use a film deposition method that does not damage 406b. That is, the deposition of the conductor 416. For this purpose, it is preferable to use methods such as MCVD.

[0148] Furthermore, when the conductive 416 is constructed as a multilayer film, each film is treated by sputtering. CVD methods (plasma CVD, thermal CVD, MCVD, MOCVD, etc.), MBE method Alternatively, the film may be deposited using different film deposition methods, such as the PLD method or ALD method. For example, the first layer may be deposited using the MOCVD method, and the second layer may be deposited using the sputtering method. Alternatively, the first layer may be deposited using the ALD method, and the second layer using the MOCVD method. Alternatively, the first layer may be deposited by ALD and the second layer by sputtering. The first layer is deposited using the ALD method, the second layer using the sputtering method, and the third layer using the ALD method. This is also possible. In this way, by using different film deposition methods for each layer, It is possible to give them different functions and properties. And by stacking these films... This allows for the formation of a more appropriate film as a whole.

[0149] In other words, when the conductor 416 is constructed as a multilayer film, for example, the nth layer of film is sputtered CVD methods (plasma CVD, thermal CVD, MCVD, MOCVD, etc.), The film is deposited using at least one of the following methods: MBE, PLD, ALD, etc., and the (n+1)th layer The film is processed using sputtering, CVD (plasma CVD, thermal CVD, MCVD, M At least one of the following methods (such as OCVD), MBE, PLD, or ALD: The film is deposited, and the deposition method may differ between the nth layer and the (n+1)th layer (where n is natural). (Number). Note that the deposition method may be the same for the nth layer and the (n+2)th layer. Or, all The film deposition method may be the same for each film.

[0150] Furthermore, the conductor 416, or at least one of the films in the multilayer film of the conductor 416, and a semiconductor The semiconductor 436a that becomes 406a, or the semiconductor 436b that becomes semiconductor 406b, are the same A film deposition method may be used. For example, ALD method may be used for both. This will result in a large The film can be formed without exposure to air. As a result, the inclusion of impurities can be prevented.

[0151] Furthermore, the conductor 416, or at least one of the films in the multilayer film of the conductor 416, and a semiconductor A semiconductor 436a which becomes semiconductor 406a, or a semiconductor 436b which becomes semiconductor 406b, and an insulator 402, or at least one of the films in the laminate of the insulator 402, is formed using the same film deposition method. It is also possible to use the sputtering method for all of them. This will allow contact with the atmosphere It is possible to form a film without causing deterioration. As a result, the inclusion of impurities can be prevented. However, However, the method for manufacturing a semiconductor device according to one aspect of the present invention is not limited to these.

[0152] Next, a mask 426 is formed (see Figure 8(A)). The mask 426 is photosensitive. A photoresist can be used. Furthermore, as mask 426, an anti-reflective coating is applied to the photoresist base. A bottom anti-reflective coating (BARC) It may be provided. By providing an anti-reflective coating, defects caused by halation can be suppressed. This allows for the creation of fine shapes.

[0153] Next, using mask 426 as a mask, the conductor 416 is etched, and the conductor 417 is shaped To achieve this, in order to form the conductor 417 having a fine shape, This will form a mask 426. If the mask 426, which has a fine shape, is too thick... Since it may fall over, it is preferable to have an area of ​​sufficient thickness to stand on its own. Also, the mask The conductor 416, which is etched using 426 as a mask, is etched under conditions that the mask 426 can withstand. It is preferable that it be thin enough to be worn. However, the conductor 416 is later used in transistors. Conductors 416a and 490 that function as source and drain electrodes Since body 416b is used, in order to increase the on-current of transistor 490, a certain amount of A certain thickness is preferable. Therefore, for example, 5 nm to 30 nm, preferably. Having a region with a thickness of 5 nm to 20 nm, more preferably 5 nm to 15 nm. The conductive material 416 can be used.

[0154] Next, the semiconductors 436b and 436a are etched using the conductor 417 as a mask. This process forms semiconductors 406a and 406b. At this time, the insulator 402 is also formed. When the material is tangled, s-channel structures are more easily formed (see Figure 8(B)).

[0155] Next, a portion of the conductor 417 is etched to form conductors 416a and 416b. (See Figure 9(A)). In this way, semiconductors 436a and 436b are etched. The conductive material 416, formed as a mask for ignition, is the source power of transistor 490. Conductors 416a and 416b function as electrodes and drain electrodes, respectively. The conductor 416, which will become conductors 416a and 416b, will also be used as a mask. Therefore, the number of steps required to manufacture transistor 490 can be reduced. Also, transistor 4 90 is because it can reduce the occupied area of ​​conductors 416a and 416b. This structure is suitable for miniature semiconductor devices.

[0156] Next, a semiconductor that will become semiconductor 406c is deposited. The semiconductor that will become semiconductor 406c is spa The film can be deposited using methods such as taring, CVD, MBE, PLD, or ALD. .

[0157] Furthermore, the semiconductor that will become semiconductor 406c is an In-Ga-Zn oxide layer produced by the MOCVD method. Therefore, when forming a film, the raw material gases are trimethylindium, trimethylgallium and Dimethyl zinc, etc., can be used. Note that the combination of raw material gases is not limited to the above, Triethylindium may be used instead of methylindium. Triethylgallium may be used instead of gallium. Also, dimethylzinc can be used instead. Diethylzinc may also be used.

[0158] Next, a second heat treatment may be performed. For example, semiconductor 406a may be semiconductor 40 A semiconductor with higher oxygen permeability than a semiconductor with a 6c capacitance is selected. That is, a semiconductor with a 406c capacitance is selected. As the semiconductor, we select one with lower oxygen permeability than semiconductor 406a. In other words, Furthermore, a semiconductor having the function of permeating oxygen is selected as semiconductor 406a. As the semiconductor that will become 406c, we select a semiconductor that has the function of blocking oxygen. At that time, by performing a second heat treatment, the insulator 402 is contained in the semiconductor 406a. Excess oxygen moves to semiconductor 406b. Semiconductor 406b becomes semiconductor 406c. Because it is covered, outward diffusion of excess oxygen is unlikely to occur. Therefore, at this time By performing a second heat treatment, defects (oxygen vacancies) in semiconductor 406b can be efficiently reduced. This can be done. In addition, the second heat treatment removes excess oxygen (oxygen) from the insulator 402 into the semiconductor 40 The procedure should be carried out at a temperature that allows diffusion up to 6b. For example, refer to the description of the first heat treatment. This is also acceptable. Alternatively, the second heat treatment is preferably performed at a lower temperature than the first heat treatment. The temperature range to be lowered is 20°C to 150°C, preferably 40°C to 100°C. This prevents the release of excess oxygen (oxygen) from the insulator 402. It is possible.

[0159] Next, an insulator that will become insulator 412 is deposited. The insulator that will become insulator 412 is sputtered The film can be deposited using methods such as CVD, MBE, PLD, or ALD.

[0160] Furthermore, when the insulator 412 is constructed as a multilayer film, each film is split. Taring method, CVD method (plasma CVD, thermal CVD, MCVD, MOCVD, etc.) ), using film deposition methods such as MBE, PLD, and ALD, A film may be formed. For example, the first layer may be formed by MOCVD and the second layer by sputtering. A film may be formed. Alternatively, the first layer may be deposited by the ALD method and the second layer by the MOCVD method. That's fine. Alternatively, the first layer may be deposited using the ALD method, and the second layer may be deposited using the sputtering method. Alternatively, the first layer can be deposited using the ALD method, the second layer using the sputtering method, and the third layer using A The film may also be deposited using the LD method. In this way, by using different film deposition methods, Each layer of film can be given different functions and properties. Then, these films are stacked. This allows for the formation of a more appropriate film as a whole.

[0161] In other words, when the insulator 412 is constructed as a multilayer film, for example, the nth layer of the film is Sputtering method, CVD method (plasma CVD, thermal CVD, MCVD, MOCV) The film is deposited using at least one of the following methods: D method, MBE method, PLD method, ALD method, etc. The n+1th layer of film is processed using sputtering, CVD (plasma CVD, thermal CVD, M At least one of the following methods: CVD method, MOCVD method, MBE method, PLD method, ALD method, etc. It is acceptable to deposit a film using one method, even if the deposition method differs between the nth layer and the (n+1)th layer. (n is a natural number). Note that the deposition method may be the same for the nth layer and the (n+2)th layer. Alternatively, the film deposition method may be the same for all films.

[0162] Next, a third heat treatment may be performed. For example, semiconductor 406a is semiconductor 40 A semiconductor with higher oxygen permeability than a semiconductor with a 6c capacitance is selected. That is, a semiconductor with a 406c capacitance is selected. As the semiconductor, we select a semiconductor with lower oxygen permeability than semiconductor 406a. As the semiconductor that will become body 406c, we will select a semiconductor that has the function of blocking oxygen. Alternatively, for example, the semiconductor 406a has higher oxygen permeability than the insulator 412. A semiconductor is selected. That is, as an insulator that will become insulator 412, an acid is selected that is better than semiconductor 406a. Select an insulator with low oxygen permeability. In other words, as semiconductor 406a, select one that allows oxygen to pass through. A semiconductor with the desired function is selected. Furthermore, as an insulator 412, oxygen is blocked. An insulator having the function of condensing is selected. At this time, by performing a third heat treatment, the semiconductor Through 406a, excess oxygen contained in the insulator 402 moves to the semiconductor 406b. The conductor 406b is covered with a semiconductor 406c and an insulator 412. Therefore, outward diffusion of excess oxygen is unlikely to occur. For this reason, the third heating is performed at this time. By performing this process, defects (oxygen vacancies) in semiconductor 406b can be efficiently reduced. Furthermore, the third heat treatment involves expanding the excess oxygen (oxygen) in the insulator 402 to the semiconductor 406b. It should be done at a temperature that allows for diffusion. For example, you can refer to the description of the first heat treatment. Alternatively, the third heat treatment is preferably performed at a lower temperature than the first heat treatment. The temperature range is 20°C to 150°C, preferably 40°C to 100°C. If the insulator 412 has the function of blocking oxygen, then semiconductor 406c The semiconductor does not need to have the function of blocking oxygen.

[0163] Next, a conductive film to become conductive material 404 is deposited. The conductive material to become conductive material 404 is deposited by sputtering The film can be deposited using methods such as CVD, MBE, PLD, or ALD.

[0164] The insulator 412 functions as the gate insulator for transistor 490. Therefore, when forming the conductive film that will become the conductive film 404, damage is inflicted on the insulator that will become the insulator 412. It is preferable to use a film deposition method that does not involve microfilming. That is, for the deposition of the conductive film, the MCVD method or the like is used. It would be preferable if that were the case.

[0165] Furthermore, when the conductive material 404 is constructed as a multilayer film, each film is split. Taring method, CVD method (plasma CVD, thermal CVD, MCVD, MOCVD, etc.) ), using film deposition methods such as MBE, PLD, and ALD, A film may be formed. For example, the first layer may be formed by MOCVD and the second layer by sputtering. A film may be formed. Alternatively, the first layer may be deposited by the ALD method and the second layer by the MOCVD method. That's fine. Alternatively, the first layer may be deposited using the ALD method, and the second layer may be deposited using the sputtering method. Alternatively, the first layer can be deposited using the ALD method, the second layer using the sputtering method, and the third layer using A The film may also be deposited using the LD method. In this way, by using different film deposition methods, Each layer of film can be given different functions and properties. Then, these films are stacked. This allows for the formation of a more appropriate film as a whole.

[0166] In other words, when the conductive material 404 is constructed as a multilayer film, for example, the nth layer of the film is Sputtering method, CVD method (plasma CVD, thermal CVD, MCVD, MOCV) The film is deposited using at least one of the following methods: D method, MBE method, PLD method, ALD method, etc. The n+1th layer of film is processed using sputtering, CVD (plasma CVD, thermal CVD, M At least one of the following methods: CVD method, MOCVD method, MBE method, PLD method, ALD method, etc. It is acceptable to deposit a film using one method, even if the deposition method differs between the nth layer and the (n+1)th layer. (n is a natural number). Note that the deposition method may be the same for the nth layer and the (n+2)th layer. Alternatively, the film deposition method may be the same for all films.

[0167] Furthermore, the conductor that becomes the conductor 404, or a small portion of the laminated film of the conductor that becomes the conductor 404 At most, one film and an insulator that becomes an insulator 412, or a lamination of insulators that become an insulator 412. At least one of the films may be deposited using the same method. For example, both may be A The LD method may also be used. This allows for film formation without exposure to the atmosphere. As a result, the inclusion of impurities can be prevented. Alternatively, for example, the insulator 412 can be brought into contact with the insulator. A conductor that becomes a conductor 404 and an insulator 412 that is in contact with the conductor that becomes a conductor 404 The same film deposition method may be used for the insulator. This allows for film deposition in the same chamber. This allows for the prevention of contamination by impurities.

[0168] Furthermore, the conductor that becomes the conductor 404, or a small portion of the laminated film of the conductor that becomes the conductor 404 At most, one film and an insulator that becomes an insulator 412, or a lamination of insulators that become an insulator 412. The same deposition method may be used for at least one of the films. For example, all of them may be processed using a spatula. The taring method may also be used. This allows for film formation without exposure to the atmosphere. As a result, the inclusion of impurities can be prevented.

[0169] Next, a portion of the conductor that will become the conductor 404 is etched to form the conductor 404. The conductor 404 is formed so as to overlap with at least a portion of the semiconductor 406b.

[0170] Next, similar to the conductor 404, a portion of the insulator 412 is etched. This forms an insulator 412.

[0171] Next, similar to the conductor 404 and the insulator 412, the semiconductor 40 A portion of the semiconductor that will become 6c is etched to form semiconductor 406c.

[0172] Furthermore, the conductor 404, the insulator 412, and the semiconductor 406c are... When etching a part of a semiconductor, the same photolithography process may be used. i. Alternatively, an insulator and semiconductor that use the conductor 404 as a mask to form an insulator 412. The semiconductor that becomes 406c may be etched. Therefore, the conductor 404 and the insulator 412 The semiconductor 406c has a similar shape in the top view. Note that the shape shown in Figure 9(C1) As shown in the enlarged cross-section, the insulator 412 and / or semiconductor 406c protrude more than the conductor 404. In cases where the shape is protruding (projecting), or as shown in the enlarged cross-section in Figure 9(C2), the conductor 404 has a shape that protrudes (overhangs) more than the insulator 412 or / and semiconductor 406c. This can sometimes happen. By adopting shapes like those shown, shape defects can be reduced. In some cases, gate leakage current can be reduced.

[0173] Next, the insulator 408 is deposited (see Figure 9(B)). The insulator 408 is deposited by sputtering. The film can be deposited using methods such as CVD, MBE, PLD, or ALD.

[0174] Next, a fourth heat treatment may be performed. For example, semiconductor 406a is semiconductor 40 A semiconductor with higher oxygen permeability than 6c is selected. That is, semiconductor 406c is selected. A semiconductor with lower oxygen permeability than 06a is selected. Also, as semiconductor 406c, oxygen Select a semiconductor that has a blocking function. Or, for example, as semiconductor 406a, A semiconductor with higher oxygen permeability than insulator 412 is selected. That is, as insulator 412, Select a semiconductor with lower oxygen permeability than conductor 406a. Alternatively, for example, semiconductor 406 As a, a semiconductor with higher oxygen permeability than insulator 408 is selected. That is, insulator 408 Therefore, a semiconductor with lower oxygen permeability than semiconductor 406a is selected. In other words, semiconductor As 406a, a semiconductor having the function of permeating oxygen is selected. Also, insulator 408 and Then, an insulator having the function of blocking oxygen is selected. At this time, the fourth heat treatment is performed. By doing so, excess oxygen contained in the insulator 402 is transferred to the semiconductor 406a. Move to b. Semiconductor 406b is one of semiconductor 406c, insulator 412, insulator 408 Because it is covered with something, outward diffusion of excess oxygen is unlikely to occur. Therefore, at this timing By performing a fourth heat treatment in the process, defects (oxygen vacancies) in semiconductor 406b are efficiently reduced. This can be done. Furthermore, the fourth heat treatment is performed to remove excess oxygen (oxygen) from the insulator 402 into the semiconductor. The procedure should be carried out at a temperature that allows diffusion up to 406b. For example, refer to the description of the first heat treatment. It is permissible to do so. Alternatively, the fourth heat treatment is preferably performed at a lower temperature than the first heat treatment. The temperature range to be lowered is 20°C to 150°C, preferably 40°C to 100°C. In addition, if the insulator 408 has the function of blocking oxygen, semiconductor 406c Furthermore, the insulator 412 does not need to have the function of blocking oxygen.

[0175] Furthermore, all of the first, second, third, and fourth heat treatments You don't have to do some of it.

[0176] Next, the insulator 418 is deposited. The insulator 418 is deposited by sputtering, CVD, or MBE. The film can be deposited using methods such as the PLD method or ALD method.

[0177] As described above, the transistor 490 shown in Figure 6 can be fabricated.

[0178] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0179] (Embodiment 3) In this embodiment, an oxide semiconductor that can be used in a transistor according to one aspect of the present invention is provided. Let's explain conductors.

[0180] Oxide semiconductors are broadly classified into non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Oxide semiconductors are CAAC-OS (C Axis Aligned Crystallized) Polycrystalline oxide semiconductor, microcrystalline oxide This refers to material semiconductors, amorphous oxide semiconductors, etc. Note that CAAC-OS is abbreviated as CANC-OS(C Axis Aligned Nano Crystalline Oxide Sem It can also be called i-conductor.

[0181] First, let me explain CAAC-OS.

[0182] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline regions.

[0183] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-angle scope) is obtained. Also called a high-resolution TEM image. By observing this, multiple crystalline regions can be identified. Furthermore, high-resolution TEM images clearly show the boundaries between crystalline regions, i.e., grain boundaries. It is not possible to confirm the crystal grains. Therefore, CAAC-OS is not a crystal grain. It can be said that a decrease in electron mobility due to the field is less likely to occur.

[0184] When observing a high-resolution TEM image of the cross-section of CAAC-OS from a direction approximately parallel to the sample surface, the result is In the crystalline region, it can be confirmed that metal atoms are arranged in layers. Each layer of metal atoms is C The shape reflects the irregularities of the surface (also called the surface to be formed) or upper surface that forms the AAC-OS. They are arranged parallel to the surface or top surface of the CAAC-OS being formed.

[0185] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°.

[0186] On the other hand, a high-resolution TEM image of the CAAC-OS plane is observed from a direction approximately perpendicular to the sample surface. This confirms that in the crystalline region, the metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0187] Figure 38(A) is a high-resolution TEM image of a cross-section of CAAC-OS. Also, Figure 38(B) This is a high-resolution TEM image of a cross-section further enlarged from Figure 38(A), and is intended to facilitate understanding. The atomic arrangement is highlighted for visual purposes.

[0188] Figure 38(C) shows the area enclosed by a circle (diameter approximately 4n) between AO and A' in Figure 38(A). This is the local Fourier transform image of m). From Figure 38(C), the c-axis orientation in each region is It can be confirmed. Also, the orientation of the c-axis is different between A and O and between O and A', so different grades This suggests that it is in. Also, between A and O, the angle of the c axis is 14.3° and 16.6°. It can be seen that it changes gradually and continuously, such as ° and 26.4°. Similarly, O-A' In between, the angle of the c-axis changes gradually and continuously from -18.3°, -17.6°, to -15.9°. It can be seen that it has transformed.

[0189] Furthermore, when electron diffraction is performed on CAAC-OS, oriented spots (bright spots) are observed. For example, an electron beam with a wavelength of, for example, 1 nm to 30 nm is applied to the upper surface of CAAC-OS. When electron diffraction using this method (also called nanobeam electron diffraction) is performed, spots are observed. See Figure 39(A).

[0190] From the high-resolution TEM images of the cross-section and the high-resolution TEM images of the planar section, the crystalline portion of CAAC-OS is It can be seen that it has orientation.

[0191] Furthermore, most of the crystalline parts contained in CAAC-OS are within cubes with sides less than 100 nm long. It is small enough to fit within this size. Therefore, the crystalline portion contained in CAAC-OS has sides of 10n. This also includes cases that fit within a cube smaller than m, smaller than 5 nm, or smaller than 3 nm. Furthermore, multiple crystalline regions contained in CAAC-OS are linked together to form one large crystalline region. It may form. For example, in a planar high-resolution TEM image, at 2500 nm 2 That's all. 5 μm 2 or greater than 1000 μm 2 In some cases, crystal regions exceeding the above size may be observed.

[0192] X-ray diffraction (XRD) instrument for CAAC-OS When structural analysis is performed using this method, for example, CAAC-OS having InGaZnO4 crystals is found to be Analysis using the ut-of-plane method revealed a peak at a diffraction angle (2θ) near 31°. This may be the case. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystals have c-axis orientation, and the c-axis is substantially perpendicular to the surface being formed or the upper surface. It can be confirmed that it is facing the direction.

[0193] On the other hand, for CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plan configuration. In analysis using the e method, a peak may appear when 2θ is around 56°. This peak is I It is attributed to the (110) plane of the nGaZnO4 crystal. If it is a conductor, fix 2θ to around 56° and test with the normal vector of the sample surface as the axis (φ axis). When the material is analyzed while rotating (φ scan), it is attributed to a crystal plane equivalent to the (110) plane. Six peaks are observed. In contrast, in the case of CAAC-OS, 2θ is near 56°. Even when fixed in place and scanned using the φ scan function, no clear peak appears.

[0194] From the above, it can be concluded that in CAAC-OS, the orientation of the a-axis and b-axis is irregular between different crystalline regions. However, it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in that direction. Therefore, it was confirmed by the high-resolution TEM observation of the cross-section mentioned above. Each layer of metal atoms, arranged in a layered fashion, is a plane parallel to the ab-plane of the crystal.

[0195] The crystalline portion is formed when CAAC-OS is deposited or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is on the surface or above the CAAC-OS that is formed. It is oriented in a direction parallel to the normal vector of the surface. Therefore, for example, the shape of CAAC-OS When altered by etching or other means, the c-axis of the crystal becomes the surface on which CAAC-OS is formed. The vector may not be parallel to the normal vector of the top surface.

[0196] Furthermore, the distribution of c-axis oriented crystal regions in CAAC-OS does not need to be uniform. For example, the crystalline portion of CAAC-OS is formed by crystal growth from near the top surface of CAAC-OS. If this occurs, the region near the top surface will have a higher proportion of c-axis oriented crystals than the region near the surface being formed. The value may increase. Also, CAAC-OS with added impurities has added impurities. The affected region may be altered, and regions with a different proportion of partially c-axis-oriented crystals may be formed. ru.

[0197] Furthermore, the out-of-plane method for CAAC-OS containing InGaZnO4 crystals In the analysis, in addition to the peak near 2θ = 31°, a peak also appears near 2θ = 36°. In some cases, peaks near 36° 2θ indicate that a portion of CAAC-OS exhibits c-axis orientation. This indicates the presence of untreated crystals. CAAC-OS shows a peak near 31° at 2θ. It is preferable that the following is observed, and that 2θ does not show a peak near 36°.

[0198] CAAC-OS is an oxide semiconductor with a low impurity concentration. The impurities are hydrogen, carbon, silica. These are elements other than the main components of oxide semiconductors, such as transition metals. In particular, silicon. The element that has a stronger bonding force with oxygen than the metal elements that make up oxide semiconductors is the element that makes up the oxide semiconductor. By removing oxygen, the atomic arrangement of oxide semiconductors is disrupted, leading to a decrease in crystallinity. Furthermore, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular weight). Because of its large radius, when it is contained within an oxide semiconductor, it disrupts the atomic arrangement of the oxide semiconductor. This is a factor that reduces crystallinity. Furthermore, impurities contained in oxide semiconductors are carrier transistors. It can be a source of splatter or carrier activity.

[0199] Furthermore, CAAC-OS is an oxide semiconductor with a low defect level density. For example, oxide semiconductors Oxygen deficiency throughout the body can act as a carrier trap, or by capturing hydrogen, it can lead to the development of carriers. A can be a source of contamination.

[0200] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic are Therefore, because there are few carrier sources, the carrier density can be kept low. The transistor using this oxide semiconductor exhibits an electrical characteristic where the threshold voltage is negative (no Also called Marion.) It rarely becomes high-purity genuine or substantially high-purity genuine. Oxide semiconductors, being of a certain nature, have few carrier traps. Therefore, when using such oxide semiconductors... Transistors with this feature exhibit less variation in electrical characteristics, resulting in highly reliable transistors. Charges trapped in the carrier traps of oxide semiconductors take a long time to release. Furthermore, it can behave as if it were a fixed charge. Therefore, the impurity concentration is high, and defects... Transistors using oxide semiconductors with high energy level density may exhibit unstable electrical properties. ru.

[0201] Furthermore, transistors using CAAC-OS exhibit electrical properties that change with visible light and ultraviolet light irradiation. The fluctuations are small.

[0202] Next, we will explain microcrystalline oxide semiconductors.

[0203] Microcrystalline oxide semiconductors are regions where crystalline parts can be observed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be identified. It is contained in microcrystalline oxide semiconductors. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having nanocrystals (nc) is called nc-OS It is called (nanocrystalline oxide semiconductor). Furthermore, nc-OS cannot clearly identify grain boundaries in high-resolution TEM images, for example. There are cases where this is the case.

[0204] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). It exhibits periodicity in the atomic arrangement in the region of less than nm. Furthermore, nc-OS is a different crystal. No regularity in crystal orientation is observed between parts. Therefore, no orientation is observed throughout the entire layer. In some cases, nc-OS is indistinguishable from amorphous oxide semiconductors depending on the analysis method. Yes, for example, an XRD device that uses X-rays with a diameter larger than that of the crystal region is used for nc-OS. When structural analysis is performed using the out-of-plane method, the crystal planes are shown. No 'k' is detected. Also, for nc-OS, a probe diameter larger than the crystal portion (for example, 5 When electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 0 nm or greater, the halo A diffraction pattern resembling a single pattern is observed. On the other hand, compared to nc-OS, the size of the crystal region When nanobeam electron diffraction is performed using an electron beam with a probe diameter close to or smaller than the crystal region, A spot is observed. Furthermore, when nanobeam electron diffraction is performed on nc-OS, it forms a circle. In some cases, a region of high brightness (ring-shaped) may be observed. Also, compared to nc-OS When nanobeam electron diffraction is performed, multiple spots may be observed within a ring-shaped region. (See Figure 39(B).)

[0205] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than amorphous oxide semiconductors. However, nc-OS In this case, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-OS is CAA Compared to C-OS, the defect level density is higher.

[0206] Oxide semiconductors include, for example, amorphous oxide semiconductors, microcrystalline oxide semiconductors, and CAAC- The laminated film may have two or more types of OS.

[0207] When an oxide semiconductor has multiple structures, structural analysis can be performed using nanobeam electron diffraction. It may be possible.

[0208] Figure 39(C) shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and below the optical system 12. Sample chamber 14, optical system 16 below sample chamber 14, observation chamber 20 below optical system 16, and observation chamber A camera 18 installed in 20 and a film chamber 22 below the observation chamber 20, having a transmission electron The diffraction measuring device is shown. Camera 18 is installed facing the inside of the observation room 20. It is not necessary to have a chamber 22.

[0209] Furthermore, Figure 39(D) shows the internal structure of the transmission electron diffraction measuring device shown in Figure 39(C). Inside the transmission electron diffraction measuring device, electrons emitted from the electron gun installed in the electron gun chamber 10 The light is then irradiated onto the substance 28 placed in the sample chamber 14 via the optical system 12. The electrons are incident on the fluorescent screen 32 installed inside the observation room 20 via the optical system 16. On plate 32, a pattern appears corresponding to the intensity of the incident electrons, forming a transmission electron diffraction pattern. It can be measured.

[0210] Camera 18 is positioned facing the fluorescent screen 32 and captures the patterns that appear on the fluorescent screen 32. It is possible to do so by passing a straight line through the center of the lens of camera 18 and the center of the fluorescent screen 32. The angle between the top surface of the fluorescent board 32 and the top surface of the fluorescent board is, for example, 15° to 80°, or 30° to 7°. The angle should be 5° or less, or between 45° and 70°. The smaller the angle, the more likely it is to be captured by camera 18. The transmission electron diffraction pattern will be highly distorted. However, if the angle is known in advance... If present, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. In some cases, it is acceptable to install camera 18 in film chamber 22. For example, camera 18 is in film chamber 22. The fluorescent panel 3 may be placed in the chamber 22 so as to be opposite to the direction of incidence of the electrons 24. A low-distortion transmission electron diffraction pattern can be captured from the back surface of 2.

[0211] A holder for fixing the sample substance 28 is installed in the sample chamber 14. It has a structure that allows electrons to pass through material 28. The holder is, for example, made of The holder may have a function to move 28 along the X, Y, Z axes, etc. For example, 1nm to 10nm, 5nm to 50nm, 10nm to 100nm Move within ranges such as 50 nm to 500 nm, and 100 nm to 1 μm. It is sufficient to have accuracy. These ranges can be determined by setting the optimal range based on the structure of material 28. good.

[0212] Next, the transmission electron diffraction pattern of the material is measured using the transmission electron diffraction measuring device described above. I will explain the method.

[0213] For example, as shown in Figure 39(D), the irradiation position of electrons 24, which are a nanobeam, in a material By altering (scanning) it, we can observe how the structure of a substance changes. If substance 28 is CAAC-OS, then diffraction will occur as shown in Figure 39(A). A pattern is observed. Alternatively, if substance 28 is nc-OS, it is shown in Figure 39(B). Such diffraction patterns are observed.

[0214] By the way, even if substance 28 is CAAC-OS, it is partially similar to nc-OS, etc. A diffraction pattern may be observed. Therefore, the quality of CAAC-OS is not constant. The percentage of the region within a given range where the CAAC-OS diffraction pattern is observed (also known as the CAAC conversion rate) It can sometimes be expressed as: For example, a good CAAC-OS is CA The AC conversion rate is 50% or more, preferably 80% or more, more preferably 90% or more. The percentage is over 95%. Furthermore, a different diffraction pattern is observed in the region compared to CAAC-OS. The proportion of the region is denoted as the non-CAAC rate.

[0215] For example, immediately after film deposition (indicated as-sputtered), or in an oxygen-containing atmosphere. The upper surface of each sample having CAAC-OS after heat treatment at 450°C was scanned. While scanning, a transmission electron diffraction pattern was acquired. Here, scanning was performed at a speed of 5 nm / second for 60 seconds. The diffraction pattern is observed while the device is running, and the observed diffraction pattern is converted into a still image every 0.5 seconds. The CAAC conversion rate was derived by this conversion. The electron beam used had a probe diameter of 1 nm. A nanobeam electron beam was used. Similar measurements were performed on six samples. Then, CAAC... The average value of six samples was used to calculate the conversion rate.

[0216] The CAAC conversion rate for each sample is shown in Figure 40(A). CAAC-OS immediately after film deposition. The carbon conversion rate was 75.7% (non-CAAC conversion rate was 24.3%). Furthermore, heat treatment at 450°C was performed. The CAAC conversion rate of subsequent CAAC-OS was 85.3% (the non-CAAC conversion rate was 14.7%). It can be seen that the CAAC conversion rate is higher after 450°C heat treatment compared to immediately after film formation. That is, Heat treatment at high temperatures (e.g., 400°C or higher) results in a lower non-CAAC conversion rate. (It can be seen that the CAAC conversion rate increases.) It can be seen that a CAAC-OS with a high CAAC conversion rate can be obtained.

[0217] Here, most of the diffraction patterns that differ from CAAC-OS are similar to those of nc-OS. It was a n-type semiconductor. Furthermore, amorphous oxide semiconductors could not be confirmed in the measurement area. Therefore, by heat treatment, regions having a structure similar to nc-OS are adjacent to each other. This suggests that the region is rearranged and transformed into CAAC under the influence of its structure.

[0218] Figures 40(B) and 40(C) show CAAC-O immediately after deposition and after heat treatment at 450°C. This is a high-resolution TEM image of the plane of S. By comparing Figure 40(B) and Figure 40(C)... Furthermore, it can be seen that the CAAC-OS film after heat treatment at 450°C has a more homogeneous film quality. It can be seen that the film quality of CAAC-OS is improved by heat treatment at high temperatures.

[0219] Using this measurement method, it becomes possible to analyze the structure of oxide semiconductors that have multiple structures. There are cases where this occurs.

[0220] The above describes oxide semiconductors applicable to semiconductors 406a, 406b, 406c, etc. It is the structure of the body.

[0221] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0222] (Embodiment 4) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. Refer to the explanation.

[0223] [Cross-sectional structure] Figure 10(A) shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention. The semiconductor shown in Figure 10(A) The device has a transistor 2200 made of a first semiconductor material at the bottom and a second semiconductor material at the top. It has a transistor 2100 made of a conductive material. Figure 10(A) shows the second semiconductor As the transistor 2100 using the material, the transistor exemplified in the previous embodiment is suitable An example of its use is shown. Note that the area to the left of the dashed line is a cross-section of the transistor in the direction of the channel length. The right side shows a cross-section in the channel width direction.

[0224] It is preferable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). Germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide (e.g., gallium phosphate, indium phosphide, gallium nitride, organic semiconductors), and the second semiconductor The main material can be an oxide semiconductor. Other materials besides oxide semiconductors include single-crystal silicon Transistors using materials such as semiconductors are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors By applying the transistor exemplified in the previous embodiment, an excellent sub A threshold characteristic is obtained, making it possible to create a miniature transistor. The fast switch speed enables high-speed operation, and the low off-current results in low leakage current.

[0225] Transistor 2200 is an n-channel type transistor or a p-channel type transistor. Either type of transistor is acceptable, and the appropriate transistor should be used depending on the circuit. Aside from using a transistor according to one embodiment of the present invention that uses a synthetic semiconductor, the materials and structure used are as follows: However, it is not necessary to limit the specific configuration of the semiconductor device shown here to what is presented.

[0226] In the configuration shown in Figure 10(A), an insulator 2201 and an insulator are placed on top of the transistor 2200. Transistor 2100 is provided via 2207. Also, transistor 2200 Multiple wires 2202 are provided between the transistor 2100 and the transistor. Multiple plugs 2203 embedded in the rim allow wiring to be provided in the upper and lower layers, respectively. The electrodes are electrically connected. Also, the insulator 2204 covering the transistor 2100 and The wiring 2205 is on the insulator 2204 and has the same conductivity as the pair of electrodes of the transistor 2100. A wiring harness 2206 obtained by processing the body is provided.

[0227] In this way, by stacking two types of transistors, the circuit footprint is reduced. Multiple circuits can be arranged at a higher density.

[0228] In this case, if a silicon-based semiconductor material is used for the transistor 2200 located in the lower layer, Hydrogen in the insulator placed near the semiconductor of transistor 2200 is a silicon dandelion This terminates the bonding bond and improves the reliability of transistor 2200. On the other hand, When an oxide semiconductor is used for the transistor 2100 provided in the layer, transistor 210 Hydrogen in an insulator placed near a semiconductor with zero charge generates carriers in the oxide semiconductor. This can be one of the contributing factors, and may reduce the reliability of transistor 2100. Therefore, an oxide semiconductor is applied to the upper layer of the transistor 2200 using silicon-based semiconductor material. When transistors 2100 using conductors are stacked, hydrogen diffusion between them is prevented. It is particularly effective to provide an insulator 2207 that has a stopping function. Furthermore, trapping hydrogen in the lower layer improves the reliability of transistor 2200. By suppressing the diffusion of hydrogen from the lower layer to the upper layer, the reliability of transistor 2100 is improved. It can also improve sexual performance at the same time.

[0229] Examples of insulators 2207 include aluminum oxide, aluminum oxide nitride, and gallium oxide. M, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, acid Hafnium nitride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0230] Furthermore, the transistor 2100, which is composed of an oxide semiconductor, is covered by the transistor A block film 2208 (transistor 1) has the function of preventing hydrogen diffusion on top of the transistor 2100. It is preferable to form an insulator (corresponding to 180 in transistors 01 to 103). The same material as the insulator 2207 can be used for the black film 2208, and in particular, an oxide It is preferable to apply luminium. The aluminum oxide film contains impurities such as hydrogen and water. It has a high blocking effect that prevents both and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the block film 2208 covering the transistor 2100. This prevents the detachment of oxygen from the oxide semiconductor contained in transistor 2100. Furthermore, it is possible to prevent the contamination of oxide semiconductors with water and hydrogen.

[0231] Note that the 2200 transistor is not only a planar type transistor, but also various types It can be a transistor. For example, a FIN type, a TRI-GATE (transistor) It can be a transistor of the lygate type, etc. An example of a cross-sectional view in that case is shown below. As shown in Figure 10(D), an insulator 2212 is provided on the semiconductor substrate 2211. The conductive substrate 2211 has a thin protrusion (also called a fin) at its tip. An insulator may be provided. When forming the protrusions, the insulator is provided on the semiconductor substrate 2 This acts as a mask to prevent the 211 from being etched. The convex part does not have to have a thin tip; for example, it may be a roughly rectangular convex part, or it may have a thick tip. It may also be a protrusion. A gate insulator 2214 is provided on the protrusion of the semiconductor substrate 2211. It is kicked, and a gate electrode 2213 is provided on it. The semiconductor substrate 2211 is The source region and drain region 2215 are formed here. Although 2211 shows an example having a protrusion, the semiconductor device according to one aspect of the present invention is not limited to this. It is not specified. For example, it is acceptable to process an SOI substrate to form a semiconductor region having a protrusion. do not have.

[0232] [Circuit Configuration Example] In the above configuration, the electrodes of transistors 2100 and 2200 are connected as appropriate. This allows for the configuration of various circuits. Below, one embodiment of the present invention of semiconductor equipment This section explains an example of a circuit configuration that can be realized by using this method.

[0233] [CMOS inverter circuit] The circuit diagram shown in Figure 10(B) is a p-channel type transistor 2200 and an n-channel type transistor This is a so-called CMO (Continuously Multi-Motorized) configuration, where two Rangitar 2100s are connected in series, and each gate is connected. This shows the configuration of the S-inverter.

[0234] [CMOS Analog Switch] Furthermore, the circuit diagram shown in Figure 10(C) shows the relationship between transistor 2100 and transistor 2200. This shows a configuration where the source and drain are connected. With this configuration, It can function as a so-called CMOS analog switch.

[0235] [Examples of storage devices] Using a transistor according to one aspect of the present invention, the stored contents can be preserved even when power is not supplied. Figure 11 shows an example of a semiconductor device (memory device) that can be stored and has no limit on the number of write cycles. This will be shown.

[0236] The semiconductor device shown in Figure 11(A) comprises a transistor 3200 using a first semiconductor material and a second It has a transistor 3300 and a capacitive element 3400 made of two semiconductor materials. The transistor 3300 used is the transistor described in the above embodiment. It is possible.

[0237] Figure 11(B) shows a cross-sectional view of the semiconductor device shown in Figure 11(A). Now, the configuration shown has a back gate added to transistor 3300, but the back gate A configuration without this feature is also acceptable.

[0238] In Figure 11(A), the first wiring 3001 is connected to the source electrode of transistor 3200 and electrical The second wire 3002 is electrically connected to the drain electrode of transistor 3200. It is continued. Also, the third wiring 3003 is the source electrode or of transistor 3300. Electrically connected to one of the rain electrodes, the fourth wire 3004 is connected to the gate of transistor 3300. It is electrically connected to the electrode. And the gate electrode of transistor 3200 is The source electrode or drain electrode of the transistor 3300, and the other of the capacitive element 3400 The fifth wire 3005 is electrically connected to one of the electrodes, and the other electrode of the capacitive element 3400 is connected to the other electrode. They are electrically connected.

[0239] In the semiconductor device shown in Figure 11(A), the potential of the gate electrode of transistor 3200 can be maintained. By utilizing its unique characteristics, it is possible to write, retain, and read information in the following ways: ru.

[0240] This section will explain how to write and retain information. First, the potential of the fourth wiring 3004 is set to the traction control. The potential is set to the ON state for transistor 3300, thereby turning on transistor 3300. As a result, the potential of the third wiring 3003 is the same as the gate electrode of transistor 3200, and And is applied to one of the electrodes of the capacitive element 3400. That is, the capacitive element 3400 has a predetermined An electric charge is applied. Here, two potential levels are given: a low level and a high level. The capacitive element 3400 is given one of the charges corresponding to the two potential levels. After that, the potential of the fourth wire 3004 is turned off when transistor 3300 is in the off state. By setting the potential and turning off transistor 3300, the capacitance element 3400 is supplied with voltage. The acquired charge is retained. In this way, the semiconductor device shown in Figure 11(A) is written to. To do so.

[0241] Because the off-current of transistor 3300 is extremely small, the power supplied to capacitive element 3400 The data is retained for extended periods. Therefore, the stored contents remain accessible even when power is not supplied. It becomes possible to retain it.

[0242] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (readout potential) is applied to the fifth wiring 3005, the capacitive element 3 Depending on the amount of charge held in 400, the second wiring 3002 takes on a different potential. In general, If transistor 3200 is an n-channel type, then H is connected to the gate electrode of transistor 3200. Apparent threshold V when a igh level potential is given th_H is a transistor Apparent threshold V when a low-level potential is applied to the gate electrode of a 3200 t h_LThis is because it becomes lower. Here, the apparent threshold voltage is defined as transistor 32 This refers to the potential of the fifth wiring 3005 necessary to bring 00 into the "on state". Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Let V0 be the potential between them. This allows us to determine the potential applied to the gate electrode of transistor 3200. For example, If a high-level potential is applied during writing, the fifth wiring 3005 The potential is V0 (>V th_H In that case, transistor 3200 will be in the "on state". If a low level potential is applied, the potential of the fifth wiring 3005 is V0( <V t h_L Even in this case, transistor 3200 remains in the "off state". Therefore, By determining the potential of wiring 3002, the stored information can be read. .

[0243] When memory cells are arranged in an array, only the information of the desired memory cell is read. It is necessary to be able to output the information. If the information is not read out in this way, the capacitive element 3400 Regardless of the amount of charge held, the potential such that transistor 3200 is in the "off state", In other words, V th_H A smaller potential should be applied to the fifth wiring 3005. Alternatively, capacitance Regardless of the amount of charge held in element 3400, transistor 3200 will be in the "on state". A potential such as V th_L A higher potential should be applied to the fifth wiring 3005. .

[0244] In the semiconductor device shown in this embodiment, the transistor 3300 is a semiconductor having an oxide semiconductor. This is a transistor in which a channel is formed in the conductor. Transistor 3300 has an off current. Because it is small, it can be used to retain memory content over a long period of time. In other words, it does not require a refresh operation, or the refresh operation is extremely infrequent. This makes it possible to use fewer semiconductor memory devices, thus significantly reducing power consumption. Cut.

[0245] In the semiconductor device shown in this embodiment, the transistor 3300 is a semiconductor having an oxide semiconductor. This is a transistor in which a channel is formed in the conductor. Transistor 3300 is a previous implementation. By applying the transistor exemplified in the diagram, excellent subthreshold characteristics can be obtained. This allows for the creation of miniature transistors. Furthermore, the fast switching speed enables high-speed operation. This is possible. On the other hand, transistor 3200 uses a semiconductor material other than an oxide semiconductor as its base material. These transistors use crystalline silicon and other materials, enabling miniature transistors and high-speed operation. Yes. By combining these, a small semiconductor device can be realized. Also, high-speed writing Loading and reading operations become possible.

[0246] The semiconductor device shown in Figure 11(C) is different from the one shown in Figure 11(A) in that it does not have transistor 3200. ) is different. In this case as well, the information writing and retention operations are performed in the same manner as above. It is possible.

[0247] Next, we will explain how to read the information. When transistor 3300 is turned on, floating The third wiring 3003, which is in a idle state, and the capacitive element 3400 become electrically connected, and the third wiring 3003 Charge is redistributed between the associated wiring capacitance and the capacitive element 3400. As a result, the third wiring The potential of 3003 changes. The amount of change in the potential of the third wiring 3003 is measured by the capacitive element 3400. The accumulated charge (or the potential of one of the electrodes of the capacitive element 3400) gives different values. ru.

[0248] For example, let V be the potential of one electrode of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and third The wiring capacitance associated with wiring 3003 is CB, and the third wiring 3003 before the charge is redistributed. The potential of the third wiring 3003 is set to VB0, the potential of the fifth wiring 3005 is set to 0V, and the potential of the third wiring 3003 is set to VB0. Assuming the potential of the other electrode of the wiring capacitance is 0V, the third wiring 300 after the charge has been redistributed The potential of cell 3 is (CB × VB0 + C × V) / (CB + C). Therefore, the memory cell In this state, the potential of one electrode of the capacitive element 3400 is in two states: V1 and V0 (V1 > V0). If we assume that the potential V1 is maintained, then the potential of the third wiring 3003 (=(CB) (×VB0+C×V1) / (CB+C)) is the third wiring when the potential V0 is maintained. It was found that the potential becomes higher than that of 003 (=(CB×VB0+C×V0) / (CB+C)). Light.

[0249] Then, by comparing the potential of the third wiring 3003 with a predetermined potential, the information is read out. It is possible.

[0250] In this case, the first semiconductor material described above was applied to the drive circuit for driving the memory cell. A transistor is used, and a second semiconductor material is applied to transistor 3300. The zistas can be stacked on top of the drive circuit.

[0251] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0252] In the semiconductor device shown in this embodiment, the transistor 3300 is a semiconductor having an oxide semiconductor. This is a transistor in which a channel is formed in the conductor. Transistor 3300 is a previous implementation. By applying the transistor exemplified in the diagram, excellent subthreshold characteristics can be obtained. This allows for the creation of miniature transistors. Furthermore, the fast switching speed enables high-speed operation. This is possible. As a result, a small semiconductor device can be realized. Also, high-speed writing operation, Read operations become possible.

[0253] Furthermore, since this semiconductor device does not require high voltage for writing information, element degradation does not occur. It is difficult. For example, unlike conventional non-volatile memory, the concentration of electrons on the floating gate Because electrons are not drawn in or out from the floating gate, the insulator does not deteriorate. The problem does not arise. That is, the semiconductor device according to one aspect of the present invention is a non-volatile memory Unlike the previous issue, there is no limit to the number of rewrite cycles, and the reliability of the semiconductor has dramatically improved. It is a device. Furthermore, the writing of information depends on the conductive and non-conductive states of the transistor. This allows for high-speed operation.

[0254] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0255] (Embodiment 5) Figure 12 shows an example of the configuration of a semiconductor device according to one aspect of the present invention.

[0256] The semiconductor device 200 shown in Figure 12 includes a first memory circuit 201 and a second memory circuit 202. It has a third memory circuit 203 and a read circuit 204. The semiconductor device 200 has an electric The potential difference between position V1 and potential V2 is supplied as the power supply voltage. One is at a high level, and the other is at a low level. Below, potential V1 is at a low level, and potential V2 is at a low level. Using the high-level case as an example, an example of the configuration of a semiconductor device according to one aspect of the present invention will be explained. It shall be done.

[0257] The first memory circuit 201, during the period when the power supply voltage is supplied to the semiconductor device 200, When a signal D containing data is input, it has the function of holding that data. During the period when power voltage is supplied to the device 200, the first memory circuit 201 transmits: A signal Q containing the retained data is output. Meanwhile, the first memory circuit 201 is semiconductor During periods when power voltage is not supplied to the main unit 200, data can be retained. No. In other words, the first memory circuit 201 can be called a volatile memory circuit.

[0258] The second memory circuit 202, during the period when the semiconductor device 200 is supplied with power voltage, By reading the data held in the first memory circuit 201, the data is saved. It has the function of... The third memory circuit 203 is... During that period, the data held in the second memory circuit 202 is read, It has a function to save data. The read circuit 204 has a power supply voltage that is equal to the semiconductor device 200. During the period of supply, the second memory circuit 202 or the third memory circuit 203 is stored It has the function of reading the stored data.

[0259] As shown in Figure 12, the second memory circuit 202 consists of a transistor 212 and a capacitive element 219 The third memory circuit 203 has transistor 213 and transistor 215. The circuit has a capacitive element 220 and a readout circuit 204 which has a transistor 210 and a transistor It has a transistor 218, a transistor 209, and a transistor 217.

[0260] Transistor 212 charges according to the data held in the first memory circuit 201. The capacitor element 219 has a function of charging and discharging. Transistor 212 is part of the first memory circuit 20 The charge corresponding to the data held in 1 can be rapidly charged and discharged to the capacitive element 219. This is desirable. Specifically, transistor 212 is made of crystalline silicon (preferably It is desirable that the channel-forming region include polycrystalline silicon, and more preferably single-crystal silicon. It seems so.

[0261] Transistor 213 conducts according to the charge held in capacitive element 219. A non-conductive state is selected. Transistor 215 is selected when transistor 213 is in a conductive state. When this occurs, it has the function of charging and discharging the capacitive element 220 with a charge corresponding to the potential of the wiring 244. Transistor 215 should preferably have a very low off-current. Specifically, the transistor Sta215 is used to channel oxide semiconductors (preferably oxides containing In, Ga, and Zn). It is desirable to include it in the flannel-forming region.

[0262] To explain the connection relationships of each element in detail, the source and drain of transistor 212 are One end is connected to the first memory circuit 201. The source and destination of transistor 212 The other side of the rain is one electrode of the capacitive element 219, the gate of the transistor 213, and It is connected to the gate of the transistor 218. The other electrode of the capacitive element 219 is connected to the wiring 24 It is connected to 2. The source and drain of transistor 213 are connected to wiring 244. It is connected to the source and drain of transistor 213, the other side of which is connected to the transistor It is connected to either the source or the drain of transistor 215. The other end of the drain is connected to one electrode of the capacitive element 220 and the gate of the transistor 210. It is connected to the wiring. The other electrode of the capacitive element 220 is connected to the wiring 243. One of the sources and drains of the transistor 210 is connected to wiring 241. The source and drain of transistor 210, the other being the source and drain of transistor 218. It is connected to one side of the rain. The source and drain of transistor 218 are the other side. Transistor 20 is connected to either the source or drain of transistor 209. The other end of the source and drain of transistor 9 is the source and drain of transistor 217. , and connected to the first memory circuit 201. Source and d of transistor 217 The other end of the rain is connected to wiring 240. Also, in Figure 12, the transistor The gate of transistor 209 is connected to the gate of transistor 217, but transistor 20 The gate of transistor 9 does not necessarily have to be connected to the gate of transistor 217.

[0263] Note that in Figure 12, the third memory circuit 203 and the read circuit 204 are connected. Furthermore, the case in which the second memory circuit 202 and the read circuit 204 are connected is illustrated as an example. However, one aspect of the present invention is not necessarily limited to this configuration. That is, the readout circuit 20 If 4 is connected to at least the third memory circuit 203, then it is not connected to the second memory circuit 202. They do not necessarily have to be connected. However, the read circuit 204 is connected to the second memory circuit 20 The configuration connected to 2 reads the data held in the second memory circuit 202. This makes it possible to supply the data to the first memory circuit 201, thus improving the granularity in time. This is preferable for performing fine-grained power gating.

[0264] By applying the transistor exemplified in the previous embodiment to transistor 215, the off-power Not only is the current low, but excellent subthreshold characteristics are also obtained, and miniature transistors and It is possible to do so. Furthermore, high-speed operation is possible due to the fast switching speed. As a result... This enables the realization of a small semiconductor device. Also, the data held in the first memory circuit 201 This allows for rapid evacuation, enabling fine-grained power gating in terms of time. It is possible.

[0265] (Embodiment 6) An example of the configuration of a device using a semiconductor device according to one aspect of the present invention will be shown with reference to Figure 13. I will explain.

[0266] The semiconductor device 300 shown in Figure 13 includes a CPU core 301 and a power management unit 3 It has 21 and peripheral circuits 322. The power management unit 321 is power control It has a controller 302 and a power switch 303. Peripheral circuit 322 is a cache A cache 304 with memory, a bus interface (BUS I / F) 305, It also has a debug interface (Debug I / F) 306. 3 CPU cores 01 is data bus 323, control unit 307, PC (program counter) 308, pi Pipeline register 309, pipeline register 310, ALU (Arithmetic It has a logic unit 311 and a register file 312. CPU core Data exchange between 301 and peripheral circuits 322 such as the cache 304 is via the data bus 3 This is done via 23. A semiconductor device according to one aspect of the present invention is a PC (program counter )308, pipeline register 309, pipeline register 310, or / and This can be applied to register file 312, etc. Note that these are one aspect of the present invention. An example of a circuit to which a semiconductor device can be applied, and which has a register, is a circuit that can be used in other circuits. It can also be applied to circuits. Applying a semiconductor device according to one aspect of the present invention to these circuits. This makes it possible to provide a semiconductor device that can actively suppress power consumption.

[0267] The control device 307 includes PC 308, pipeline register 309, and pipeline register 3 10, ALU311, Register File 312, Cache 304, Bus Interface The operation of S305, debug interface 306, and power controller 302 By providing comprehensive control, the instructions contained within the input application or other program are controlled. It has the functionality to decode and execute.

[0268] The ALU311 has the functionality to perform various arithmetic operations, including basic arithmetic and logical operations.

[0269] Cache 304 has the function of temporarily storing frequently used data. Register 308 is a register that stores the address of the next instruction to be executed. Although not shown in Figure 13, the cache 304 controls the operation of the cache memory. A cache controller is provided.

[0270] Pipeline register 309 is a register that has the function of temporarily storing instruction data. be.

[0271] Register file 312 contains multiple registers, including general-purpose registers, and the control unit Data read from the main memory of the 307, or obtained through the arithmetic processing of the ALU311. It can store data such as [data].

[0272] The pipeline register 310 contains data used for the arithmetic processing of the ALU311, or AL A register that has the function of temporarily storing data obtained as a result of the calculation process of U311. That is the case.

[0273] The bus interface 305 connects the semiconductor device 300 to various external devices of the semiconductor device 300. It functions as a data path between the device and the system. Debug interface 30 6 is a signal path for inputting instructions to the semiconductor device 300 for debugging control. It has the following functions: Bus interface 305 and debug interface 306 Each of them is equipped with a register.

[0274] The power switch 303 is a component of the semiconductor device 300 other than the power controller 302. It has the function of controlling the supply of power voltage to various circuits. The above various circuits have several power Each belongs to a different domain, and various circuits belonging to the same power domain are power Switch 303 controls whether or not the power supply voltage is supplied. Also, power controller 3 02 has the function of controlling the operation of the power switch 303.

[0275] The flow of power gating operation in the semiconductor device 300 having the above configuration. Let me explain with an example.

[0276] First, the CPU core 301 determines the timing for stopping the supply of power voltage, which is controlled by the power controller. Set to register 302. Then, from CPU core 301 to power controller 30 A command is sent to 2 to start power gating. Next, within semiconductor device 300 The various registers and cache 304 begin saving data. The supply of power voltage to various circuits other than the power controller 302 of unit 300 is power - The system is stopped by switch 303. Then, an interrupt signal is sent to power controller 302. Upon input, the supply of power voltage to the various circuits of the semiconductor device 300 begins. Furthermore, a counter is provided in the power controller 302, and when the power supply voltage is started... The timing of this operation is determined using the counter, regardless of the input of the interrupt signal. That's fine too. Next, the various registers and cache 304 begin to restore the data. Then, the execution of instructions in the control device 307 is resumed.

[0277] A transistor according to one aspect of the present invention is used in registers and cache memory of a processor. By using it in storage devices such as the above, the loss of data in the storage device due to the interruption of the power supply voltage can be prevented. This can be prevented. Also, after the power supply voltage is restored, the system will return to its state before the power supply was interrupted in a short time. It can be restored to its original state. Therefore, the entire processor, or one of the components of the processor, can be restored. In addition, in multiple logic circuits, power can be shut off even for a short time, thus reducing consumption It can reduce electricity consumption.

[0278] A transistor according to one aspect of the present invention not only has a low off-current but also excellent subthreading A skell characteristic is obtained, making it possible to create a miniature transistor. Also, the switching speed Because the degree is fast, high-speed operation is possible. As a result, the transistor exemplified in the previous embodiment By applying registers using data, a small semiconductor device can be realized. This allows for rapid evacuation, enabling finer-grained power gating in terms of time. This is possible. As a result, power consumption can be reduced.

[0279] Furthermore, the memory circuit using a transistor according to one aspect of the present invention is not only for the CPU, but also for the DS P (Digital Signal Processor), Custom LSI, PLD ( LSIs such as Programmable Logic Devices, RF (Radio Frequency) o Frequency) tag, GPU (Graphics Processing U It can also be applied to nit.

[0280] (Embodiment 7) This embodiment describes an example of the use of a semiconductor device according to one aspect of the present invention.

[0281] Figure 14(A) shows the cross-sectional structure of a package using a lead frame type interposer. A perspective view is shown. The package shown in Figure 14(A) is a semiconductor device according to one aspect of the present invention. The corresponding chip 751 is bonded to the terminals on the interposer 750 by the wire bonding method. It is connected to 752. Terminal 752 is the mounting point for chip 751 of interposer 750. It is positioned on the surface that is being molded. The tip 751 is then molded by the molding resin 753. The terminals may be sealed, but a portion of each terminal 752 is exposed during sealing.

[0282] The configuration of an electronic device (mobile phone) module with a package mounted on a circuit board is shown in the diagram. This is shown in Figure 14(B). The mobile phone module shown in Figure 14(B) is a printed circuit board 80 Package 802 and battery 804 are mounted on 1. A display element is also installed. A printed circuit board 801 is mounted on the panel 800 by an FPC803. ru.

[0283] (Embodiment 8) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) It can be used in a device that has a display device capable of playing back recording media such as and displaying the images thereof. Yes, it is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention include mobile phones, game consoles including portable models, portable data terminals, e-readers, video cameras, Cameras such as digital still cameras, goggle-type display devices (head-mounted displays) ), navigation systems, sound playback devices (car audio, digital audio players) (e.g., earphones), photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 15. .

[0284] Figure 15(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control Keys 907, Stylus 908 It has the following features. Note that the portable game console shown in Figure 15(A) has two display units 903 and Although it has a display unit 904, the number of display units that a portable game console has is not limited to this. stomach.

[0285] Figure 15(B) shows a portable data terminal, comprising a first housing 911, a second housing 912, and a first display unit 9 13. It has a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 91 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. And the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing in the connection unit 915. The configuration may be such that it switches according to the angle between it and 912. Also, the first display unit 91 At least one of 3 and the second display unit 914 is equipped with a function as a position input device. A display device may be used. Note that the function as a position input device is provided by the display device. It can be added by providing a touch panel. Alternatively, it can function as a position input device. By providing a photoelectric conversion element, also called a photosensor, in the pixel section of the display device, additional features can be added. It is possible.

[0286] Figure 15(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, and a keyboard. It includes a board 923, a pointing device 924, and the like.

[0287] Figure 15(D) shows an electric refrigerator-freezer, consisting of a casing 931, a refrigerator door 932, and a freezer door 93 It has 3, etc.

[0288] Figure 15(E) shows a video camera, comprising a first housing 941, a second housing 942, a display unit 943, It has an operation key 944, a lens 945, a connector 946, etc. The Z945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. Yes. The video in the display unit 943 is connected to the first housing 941 and the second housing 9 in the connection unit 946. The configuration may also be configured to switch according to the angle between 42 and 42.

[0289] Figure 15(F) is a regular passenger car, consisting of the body 951, wheels 952, dashboard 953, and It includes Ito 954, etc.

[0290] By using a semiconductor device according to one aspect of the present invention in these electronic devices, L in the electronic device This makes it possible to reduce the power consumption of the SI. In other words, the LSI is configured to use a transient according to one aspect of the present invention. By using a stator, a memory circuit capable of retaining stored data even when power is not supplied is employed. Therefore, when the LSI is temporarily not in use, the power supplied to the LSI is cut off. This becomes possible. Before shutting off the power, the state of the logic circuit is saved to the memory circuit. This makes it possible. As a result, it becomes possible to reduce power consumption and the power supply By quickly returning to the state before the power was cut off after being turned on, a high-speed recovery is possible.

[0291] By applying the transistor exemplified in the previous embodiment, excellent subthreshold characteristics can be achieved. This allows for the creation of miniature transistors. Furthermore, it enables fast switching speeds. This enables high-speed operation. As a result, it is possible to realize a small semiconductor device. Also, high-speed writing Loading and reading operations become possible. As a result, the power can be shut off quickly, Furthermore, it can quickly recover after being powered on.

[0292] This embodiment may be combined with other embodiments or examples shown herein as appropriate. It is possible. [Examples]

[0293] In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0294] The channel-forming region is C-axis aligned crystalline In dium-Gallium-Zinc Oxide (CAAC-IGZO) Island A transistor with a structure in which the gate electrode surrounds not only the top surface but also the sides, i.e., Surro Unded channel (s-channel) CAAC-IGZO transistor By fabricating the substrate, good subthreading can be achieved even when the channel length is miniaturized to about 50 nm. The shoulder properties can be maintained.

[0295] Figures 16(A) and 16(B) show s-channel CAAC-IGZO transistors. A schematic diagram and a plan view are shown, respectively. The transistor consists of an insulator BI and a CAA on the insulator BI. An oxide semiconductor OS containing C-IGZO, and an electrode M electrically connected to the oxide semiconductor OS. E (source electrode and drain electrode), oxide semiconductor OS, gate insulator on electrode ME GI, oxide semiconductor OS, part of electrode ME and gate electric field overlap via gate insulator GI It has a top gate GE and a top contact structure. The transistor in Figure 16 has a top gate GE structure. The source electrode GE has a structure in which it overlaps with the source electrode and drain electrode ME. As shown in Figure 16(B), the channel length L ch W is the distance between electrodes ME and the channel width. island This represents the width of the oxide semiconductor OS.

[0296] Figures 16(C) and 16(D) show the cross-section of the actually fabricated transistor using STEM (Scan). (Ning Transmission Electron Microscope) Images As shown in the diagram, a transistor consists of an insulator BI, an oxide semiconductor OS, and an electrode ME (solar). It has a drain electrode and a gate insulator GI and a gate electrode GE, It can be confirmed that the desired device structure has been created.

[0297] Oxide semiconductor OS is formed on an insulator BI in an atmosphere containing gaseous Ar and O2. Using a polycrystalline target with a Ga:Zn=1:1:1 (atomic ratio), DC spa The film was deposited using the tailing method at a substrate temperature of 300°C. Figure 17(A) shows the oxide semiconductor OS. Out-of-plane X-ray diffraction spectrum is obtained using a unit cell as shown in Figure 17(B). shows a (009) diffraction peak due to the InGaZnO4 crystal. In fact, Fig. 17(C) Looking at the high-resolution TEM image of the cross-section of the oxide semiconductor OS shown in , a structure in which atoms are arranged in layers in the direction perpendicular to the substrate is observed. Also, as shown in Fig. 17(D), looking at the high-resolution TEM image of the surface of the oxide semiconductor O S, triangular and hexagonal atomic arrangements are observed . From these characteristics, it can be seen that the oxide semiconductor OS is CAAC-IGZO . For reference, Fig. 18 shows the high-resolution TEM image of single crystalline Indium-Gal lium-Zinc Oxide (single crystalline IGZO). Note that Fig. 18(A) is the high-resolution TEM image of the cross-section, and Fig. 18(B) is the high-resolution TEM image of the surface. It can be seen that the structures of single crystalline IGZO and CAAC-IGZO are different .

[0298] The electrical characteristics of the transistor were examined when the film thickness of the oxide semiconductor OS was 40 nm, the thickness of the gate insulator GI was 11 n m in terms of oxide film thickness, and the thickness of the insulator BI was 390 nm in terms of oxide film thickness . Figs. 19(A) and (B) show the I island -V ch characteristics and the I -V d characteristics of the transistor with W d = 47 nm and L d = 56 nm g respectively. Note that I d is the drain current of the transistor, V d is the drain voltage, and V g is the gate voltage, respectively . Also, Figs. 19(A) and (B) show the median value of the 9 samples measured [[ID=​​​The on-current at 1V is 58μA. The value is / μm. Also, the transistor characteristics are normally off. The off-current is typical for semiconductors. The parameter analyzer's lower limit of measurement (less than 0.1 pA) is exceeded. Turn-on voltage V turn-on (I d =V at 1pA g ) and V for 9 samples of SS d dependence The characteristics are shown in Figure 20. According to Figure 20, despite the short channel, the subthreshold is excellent. It can be seen that this is a characteristic. That is, DIBL (Drain Induced Barr ier Lowering) and SS(Subthreshold swing value e) The median values ​​are 67mV / V and 92mV / dec(V). d It was 1V.

[0299] This is because the channel width is sufficiently narrow, and the gate electric field from the side of the oxide semiconductor OS is channel This is because the impact becomes stronger. In fact, as shown in Figures 21 and 22, when the channel width is large The subthreshold characteristics worsen as the channel length L decreases. Figure 21 shows the channel length L. ch to 5 V with channel width changed while fixed at 6nm d I at =1V d -V g The characteristics are shown in the figure. Figure 22 shows the channel width dependence of the turn-on voltage and SS. , SS increases and the turn-on voltage shifts in the negative direction. Conversely, the channel width W isl and However, the characteristic values ​​begin to saturate below 100nm.

[0300] We will use device calculations to investigate the reason why the signal-to-speech (SS) improved with the reduction in channel width. 3D device calculations were performed using Opsys' Sentaurus. Device structure This structure mimics the fabricated s-channel CAAC-IGZO transistor. Figures 30(A) and (B) show W, respectively. island = 50nm and 90nm, L ch Electron current density of the active layer in the channel width cross-section of a 56nm transistor The distribution is shown. The active layer corresponds to an oxide semiconductor. V g is -1V, V d The voltage was set to 1V. As shown in Figure 30(B), W island However, a 90nm transistor has a gate electrode or It can be seen that the electron current density is higher on the back channel side of the active layer, which is further away. On the other hand, as shown in Figure 30(A), W island However, 50nm transistors have a bucking The electron current density on the channel side is greatly reduced. Thus, W island Narrow This improves the controllability of the electron current density on the back channel side. As a result, SS It can be said that it has improved.

[0301] The results of the 3D device calculation when the upper edge of the active layer is rounded are shown in Figure 31(A) and This is shown in Figure 31(B). As a result, in device structures with narrow channel widths, Figures 23 and 31(B) are shown. As shown in Figure 24, it becomes more resistant to short-channel effects. Figure 23 shows the channel width fixed at 47 nm. Then, channel length L ch V changed d I at =1V d -V g The characteristics are shown in Figure 24. The turn-on voltage and the channel length L of SS ch It shows a dependency. Channel width is 47nm. When fixed, channel length L chResults up to 56nm show characteristic degradation due to short-channel effects. They are rarely seen.

[0302] Figure 32 shows two types of transistors (labeled as Transistor A and Transistor B in the figure). Drain current I d Channel length L ch It shows dependence. Drain current I d V d = 1V , V g This is the current at 2.7V. The channel width is approximately 50nm. Transistor A This is shown in Figure 23. d -V g This is a transistor that has achieved its characteristics. Transistor B is a transistor. Compared to DISTRA A, this transistor has thicker source and drain electrode films. The drain current I of transistor B. d The mean of 6 samples was used. From Figure 32, In any transistor, the drain current I d The channel length is L ch As the reduction increases It is confirmed that the drain current I of transistor B is added. d This is the Dre of transistor A. In current I d Compared to that, it is higher, and the channel length L ch The increase is significant due to the contraction. This is because the film thickness of the source electrode and drain electrode was increased, This is because the resistance of the electrodes has been reduced.

[0303] Figure 33 shows V d = 1V, V g =Drain current at 2.7V (in the figure, on-current I on and (as described) and V d = 1V, V g =Drain current at 0V (off-current I in the figure) off It is written The relationship shown is as follows. The data is shown in Figure 23. d -V g Obtained from the transistor whose characteristics were obtained. From Figure 33, V d = 1V, V g The drain current at 0V is V d = 1V, V g Regardless of the drain current at 2.7V, the lower limit of measurement is 10 -13 A or less, low It was confirmed that the value was positive.

[0304] As an example of an application using an s-channel CAAC-IGZO transistor, see Figure 25. The memory circuit shown in Figure 25 is an example of a memory circuit using Si transistors and s-channels. It has an annel CAAC-IGZO transistor and a capacitive element Cs. The capacitance value of element Cs is 14 fF.

[0305] In Figure 25, the source electrode of the Si transistor is electrically connected to the source wire SL, The rain electrode is electrically connected to the bit line RBL. Also, s-channel CAA The gate electrode of the C-IGZO transistor is electrically connected to the word line WWL, and the source power One of the electrodes, either the pole or the drain electrode, is electrically connected to the bit wire WBL. Then, the Si Tra The gate electrode of the transistor and the s-channel CAAC-IGZO transistor The source electrode or the other drain electrode is electrically connected to one of the electrodes of the capacitive element Cs. The other electrode of the capacitive element Cs is electrically connected to the word line RWL.

[0306] W island =64nm, L ch =68nm s-channel CAAC-IGZ Memory cells were fabricated using O transistors, and the write time was measured and determined using SPICE (T wr ite A comparison of the writing time (T) was performed. write ) is shown in Figure 26 Timing From the chart, the WWL line moves from a low potential (L potential) to a high potential ( After raising it to the H potential, the potential of the floating node (FN) (V FN ) is bit line WBL This was defined as the time it took for the potential to reach 90%.

[0307] Figure 26 shows an example of a timing chart for writing to the memory circuit. Bit lines With WBL at high potential (1.1V here), the word line WWL is at high potential (3V here). Then the s-channel CAAC-IGZO transistor turns on, and the bit line One electrode of the WBL and the capacitive element Cs conducts, and the potential of one electrode of the capacitive element (the potential of FN) V FN ) approaches the potential of the bit line WBL and is written. The word line WWL is at an L potential ( When the voltage is 0V (in this case), the s-channel CAAC-IGZO transistor turns off. The writing process is then complete. After that, the bit line WBL becomes low potential (0V in this case). During the writing operation, the word line RWL is at low potential (0V in this case), and the source line SL is at low potential. The voltage is set to 0V (here), and the bit line RBL is set to high potential (here, 1.1V).

[0308] Figure 27 shows the writing time and the potential of one electrode of the capacitive element (the potential of FN, V). FN This shows the relationship between ) As shown in Figure 27, the actual writing time was 60ns, while the SPICE method showed 50ns. It was confirmed that they were generally in agreement.

[0309] Also, in Figure 28, the s-channel CAAC-IGZO transistor and W=9 Writing to a 0nm, L=45nm Si transistor with conditional capacitance values. Time fluctuations were confirmed using SPICE. s-channel CAAC-IGZO The writing time T is approximately 30 times longer for a transistor than for a rangitor. write The difference was confirmed. However, the off-current of the s-channel CAAC-IGZO transistor is V g When it is 0V, 10 -19 It is estimated to be less than A, with a holding capacity of 1 fF and a lead of FN node Allowing a voltage drop of up to 0.1V due to the circuit results in a retention time longer than 1,000 seconds. In this case, the writing time will be less than 5ns.

[0310] Furthermore, Figure 29(A) shows the time at room temperature and the potential of one electrode of the capacitive element (potential V of FN). FN This shows the relationship between the potentials V. FN The data retention period will be the time it takes for the value to decrease by 10%. As shown in Figure 29(A), the actual measurement was approximately 3 × 10 5 Data up to s (3.5 days) It was found that it could be retained.

[0311] Furthermore, Figure 29(B) shows the potential V at room temperature. FN And the bit line RBL and the source line SL This shows the relationship between the current flowing between and . Note that the potential V of FN is FN is s-channel The CAAC-IGZO transistor is put into a conducting state, and the potential applied to the bit line WBL is changed. It was changed by transforming it. Potential V FN Between the change in and the aforementioned current, the potential V F NA positive correlation was observed in the range from 0V (more precisely, around 0.02V) to 1.1V. It was found that by monitoring the aforementioned current, the memory circuit Retained data (potential V FN It can be seen that it is possible to read the data.

[0312] These characteristics can be applied to high-speed, low-power LSIs, particularly to memory applications. This is possible. [Examples]

[0313] In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0314] A detailed examination of the characteristics of miniaturized s-channel CAAC-IGZO transistors. This is extremely important for applications in LSIs and the like. Therefore, with various channel widths Fabrication of s-channel CAAC-IGZO transistors with channel length at the 50nm level. We manufactured these and investigated the effect of the s-channel structure by comparing their current characteristics.

[0315] The structure of the fabricated s-channel CAAC-IGZO transistor is shown in Figure 16(A). This is similar to the schematic and plan view of the transistor shown in Figure 16(B), and is similar to Figure 16(A) and Figure Refer to the explanation in 16(B) as appropriate. s-channel CAAC-IGZ The O transistor has a top gate, top contact structure, and the gate electrode GE is the source electrode. It overlaps with the electrode ME that constitutes the electrode and drain electrode. Also, the channel side The gate electrode GE, located on the surface, covers a portion of the sidewall of the insulator BI beneath the oxide semiconductor OS. It has the following structure. As shown in Figure 16(B), the channel length L chThis is the distance between electrodes ME. Channel width W island This represents the width of the oxide semiconductor OS.

[0316] The fabrication process is as follows: On the insulator BI formed on the Si substrate, the oxide semiconductor OS is formed A 15nm film was deposited using a DC sputtering system. The target material was In:Ga:Zn=1: A polycrystalline target with a 1:1 (atomic ratio) composition was used. The deposition conditions were Ar The atmosphere was also O2-containing, and the substrate temperature during film deposition was 300°C. Oxide semiconductors deposited under these conditions are subjected to structural analysis using an XRD device and high-resolution TEM. Observation confirmed that it was CAAC-IGZO. After CAAC-IGZO film deposition, C An island is formed using AAC-IGZO, and then the source electrode and drain electrode are connected via CA It was formed on top of the AC-IGZO island. Subsequently, a gauge with an oxide film thickness of 11 nm was applied. A metal insulator and a metal gate electrode were formed.

[0317] Figures 34(A) and (B) show the channel of an s-channel CAAC-IGZO transistor. Cross-sectional STEM images in the channel length direction and channel width direction are shown, respectively. Figures 34(A) and (B) This indicates that the desired structure has been obtained.

[0318] Figure 35(A) shows W island =110nm, L ch =51nm s-channel V of CAAC-IGZO transistor d =I at 0.1V and 1V d -V g Special It shows the sex. Figure 35(B) shows W island =50nm, L ch =51nm s-ch V of the CAAC-IGZO transistord =I at 0.1V and 1V d -V g The characteristics are shown. From Figure 35(A), W island When the range is wide at 110nm, V d When I d -V g The characteristics shift in the negative direction of the gate voltage, resulting in a DIBL effect. This can be confirmed. The DIBL at this time is 0.59V / V. On the other hand, as shown in Figure 35(B) ni W island When the range is narrow at 50nm, V d Even when I grow up d -V g Characteristic game The negative shift in the voltage is small, indicating that the DIBL effect is suppressed. The DIBL at this time is small, at 0.14V / V.

[0319] Let me explain the reason. The drain electric field affects the potential in the channel. The distance is called the natural length and is expressed by equation (1).

[0320]

number

[0321] Here, .'' n ε is the natural length. act The relative permittivity of the active layer is ε ox The relative permittivity of the gate insulator is , t act is the film thickness of the active layer, t ox n represents the thickness of the gate insulator. n is relative to the channel. This represents the number of effective gates. The material layer is an oxide semiconductor in the s-channel CAAC-IGZO transistor. This corresponds to, for example, a transistor with a single gate (single-gate structure). In this case (also called), n is 1. Two gates are provided with a semiconductor on either side. In a semiconductor (also called a dual-gate structure), n is 2. The top and side surfaces of the semiconductor are 3 A transistor (also called a tri-gate structure) in which the gate is positioned to cover the direction n is 3. A transistor in which the gate is provided so as to encircle the semiconductor. In a quadruple gate structure (also called a quadruple gate structure), n is 4. λ n The shorter the drain electric field, This means that the influence on the potential in the channel is small. (s-channel) In CAAC-IGZO transistors, W island If the channel is wide, The gate electrode's contribution is dominant, and n in equation (1) is close to 1. On the other hand, W island It gets narrower Then, the contribution of the gate electrode on the channel side also increases, so n in equation (1) approaches 3. λ n The length becomes shorter. Therefore, W island They say that the narrowing of the field of view improved DIBL. It is possible.

[0322] Figure 36 shows L ch At 51nm, W island Multiple s-chans with various values I of CAAC-IGZO transistor d -V g Shows the characteristics. V d It is 1V. Furthermore, the linear field effect mobility μ can be obtained from equation (2). FE_lin It also shows.

[0323]

number

[0324] Here, g m is I d-V g Transconductance and C determined from the characteristics. ox gate insulation This is the body volume. The W was used for comparison. island These are 50nm, 90nm, 210nm, and 510nm. It is m.

[0325] First, let's focus on the region where it is in the OFF state. From Figure 36, W island As it gets narrower SS has improved, W island At 50nm, the SS is 103mV / dec. This can be seen. On the other hand, W island Widening the gap worsens the SS, but the gate voltage is reduced. If you increase it to 10, the lower limit of measurement will be 10 -13 An off-current of less than A is obtained. In particular, W island In the case of 50nm and 90nm, the normally-off characteristics are also satisfied simultaneously.

[0326] For example, W island If =510nm, then V g If it is below -1.5V, 10 - 13 An off-current of less than A is obtained. For example, W island 50nm and 90nm In that case, V g If it is 0V or less, 10 -13 An off-current of less than A is obtained.

[0327] We will use device calculations to investigate the reason why the signal-to-speech (SS) improved with the reduction in channel width. 3D device calculations were performed using Opsys' Sentaurus. Device structure This structure mimics the fabricated s-channel CAAC-IGZO transistor. Figures 37(A) and (B) show W, respectively. island = 50nm and 90nm, L chElectron current density of the active layer in the channel width cross-section of a 51nm transistor The distribution is shown. The active layer corresponds to an oxide semiconductor. V g is -1V, V d The voltage was set to 1V. Figure 3 As shown in 7(B), W island However, in a 90nm transistor, the gate electrode is far away It can be seen that the electron current density on the back channel side of the active layer is increasing. On the other hand, As shown in Figure 37(A), W island However, 50nm transistors have back channels The electron current density on the W side is significantly reduced. island To narrow the area As a result, the controllability of the electron current density on the back channel side is improved. Consequently, SS is improved. It can be said that it was done.

[0328] Next, let's focus on the region that is in the ON state. μ FE_lin It is inherently independent of the channel width. However, W island It can be seen that it is rising as it shrinks. The reason for this is W i sland As the channel shrinks, the contribution of the current flowing along the side of the channel increases, and the contribution of the current flowing along the top of the channel decreases. This is because it has become larger in relation to W. island The reduction of transistors This allows for an increase in the current that can flow through each individual element. In other words, the s-channel structure W island By narrowing the gap, it is possible to improve the on-current characteristics.

[0329] As described above, narrowing the channel width improves DIBL, SS, and on-current characteristics. This was found to be because W island As the size decreases, relative to the top surface of the channel This is because the contribution of the gate electrode on the channel side becomes larger. Also, s-channel In CAAC-IGZO transistors, W island By narrowing the channel length, Even in the fine region at the 0nm level, it is normally off, and in the region where it is in the off state, a small S A small off-current of S is obtained, and in the region where it is on, excellent on-current characteristics are obtained. It was found that by utilizing these characteristics, it is possible to achieve things that cannot be realized with Si-LSI. This could potentially enable the creation of LSIs and other components for low power consumption. [Examples]

[0330] In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0331] A detailed examination of the characteristics of miniaturized s-channel CAAC-IGZO transistors. This is extremely important for applications in LSIs, etc. Therefore, various channel widths, We fabricated an s-channel CAAC-IGZO transistor with a channel length, and sc The property stability of the hannel structure was investigated. The fabrication process was the same as in Example 2. A 15nm oxide semiconductor OS film was deposited, and a 9.5nm gate insulator GI film was deposited. A film-like material was used.

[0332] Figures 41, 42, and 43 show 234 s-channel C cells fabricated on a single substrate. AAC-IGZO transistor, I d -V g Cumulative frequency of the threshold Vth obtained from the characteristics The distribution is shown. The size of the transistor in Figure 41 is W island =54nm, L ch =1 The wavelength is 18 nm, and the measurement conditions were V d The voltage was set to =1V. The size of the transistor in Figure 42 is , W island=54nm, L ch =518nm, and the measurement conditions were V d = 1V The size of the transistor in Figure 43 is W island =94nm, L ch =118 The measurement is in nm, and the measurement conditions are V d We set = 1V. From Figures 41 to 43, various sizes The Vth characteristic variation (σVth) of the CAAC-IGZO transistor is between 43 and 70. It was mV. By using CAAC-IGZO in the transistor, high on-current and low It not only has excellent transistor characteristics such as SS and extremely low off-current, but Furthermore, it was confirmed that the transistor characteristics had little variation and were stable. Therefore By combining these features with those obtained in other embodiments, This enables the stable fabrication of LSIs for low power consumption and other applications that cannot be achieved with Si-LSI. It is possible. [Explanation of Symbols]

[0333] 10 Electronic gun chamber 12 Optical system 14 Sample Room 16 Optical system 18 Cameras 20 Observation Room 22 Film Room 24 electronic 28 Substance 32 Fluorescent board 101 Transistors 102 transistors 103 Transistors 110 circuit boards 120 Insulator 130 Oxide semiconductor 131 Oxide semiconductor 132 Oxide semiconductor 133 Oxide semiconductor 140 source electrodes 150 Drain electrode 160 Gate Insulator 170 Guard Letters 172 Conductors 180 Insulator 185 Insulator 191 areas 192 areas 200 Semiconductor Equipment 201 Memory circuit 202 Memory circuit 203 Memory circuit 204 circuits 209 transistors 210 transistors 212 transistors 213 transistors 215 transistors 217 transistors 218 transistors 219 Capacitive elements 220 capacity 240 Wiring 241 Wiring 242 Wiring 243 Wiring 244 Wiring 300 semiconductor equipment 301 CPU cores 302 Power Controller 303 Power Switch 304 Cache 305 Bus Interface 306 Debug Interface 307 Control device 308 PC 309 Pipeline Register 310 Pipeline Registers 311 ALU 312 Register File 321 Power Management Unit 322 Peripheral Circuits 323 Databus 402 Insulator 404 Conductors 406a Semiconductor 406b Semiconductor 406c semiconductor 408 Insulator 412 Insulator 413 Conductors 416 Conductors 416a Conductor 416b Conductor 417 Conductors 418 Insulator 426 masks 436a Semiconductor 436b Semiconductor 442 Insulator 490 transistors 750 Interposer 751 chips 752 terminals 753 Mold resin 800 panels 801 Printed Wiring Board 802 Package 803 FPC 804 Battery 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 cabinet 912 cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 2100 transistors 2200 transistors 2201 Insulator 2202 Wiring 2203 Plug 2204 Insulator 2205 Wiring 2206 Wiring 2207 Insulator 2208 Blocking membrane 2211 Semiconductor substrate 2212 Insulator 2213 Terminal 2214 Gate Insulator 2215 Source area and drain area 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitive element

Claims

1. A first transistor containing silicon in the channel formation region, The device has a second transistor containing an oxide semiconductor in the channel formation region, The gate of the first transistor is electrically connected to the gate of the second transistor. One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor, in a semiconductor device. A first insulating layer having a region located above the gate electrode of the first transistor, A first conductive layer located above the first insulating layer and functioning as the first gate electrode of the second transistor, A second insulating layer having a region located above the first conductive layer, An oxide semiconductor layer having a region in contact with the upper surface of the second insulating layer and having a channel formation region for the second transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and functioning as one of the source electrode and drain electrode of the second transistor, It has a third conductive layer located above the oxide semiconductor layer and functioning as the second gate electrode of the second transistor, The first conductive layer has a region that overlaps with the channel formation region of the first transistor. The length of the first gate electrode in the first direction is greater than the length of the second gate electrode in the first direction, and greater than the length of the gate electrode of the first transistor in the second direction. The first direction is the channel length direction of the second transistor, The second direction is the channel length direction of the first transistor, The second insulating layer has a first thickness in the first portion that is in contact with the lower surface of the oxide semiconductor layer, and a second thickness in the second portion that does not overlap with the oxide semiconductor film and is adjacent to the first portion. The second film thickness is smaller than the first film thickness. A semiconductor device in which, in a cross-sectional view of the channel width direction of the second transistor, the third conductive layer has a portion facing the side surface of the oxide semiconductor layer via a third insulating layer that functions as a gate insulating layer, and a portion facing the side surface of the second insulating layer in the first portion via the third insulating layer.

2. In claim 1, The oxide semiconductor layer has a crystalline portion in which multiple spots are observed within a ring-shaped region in nanobeam electron diffraction, and is a semiconductor device.

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