Transistor structure

Abstract

To provide a transistor structure that can prevent a fin structure from collapsing.SOLUTION: A transistor structure includes a substrate, an insulating wall, and a gate region. The substrate has a fin structure. The insulating wall clamps side walls of the fin structure. The gate region is above the fin structure and the insulating wall, and the insulating wall is configured to prevent the fin structure from collapsing.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a transistor structure, and more particularly to a transistor structure in which a solid wall is formed to clamp the active region or narrow fin structure, especially the sidewall of the fin structure (additional beam-like structures may be provided to reinforce the solid wall), the relative position or distance between the source / drain edge and the gate edge can be controlled, the source / drain resistance can be improved, and most of the source / drain region can be isolated by an insulating material. [Background technology]

[0002] Figure 1 shows an example of a state-of-the-art field-effect transistor (e.g., an NMOS (N-type metal-oxide-semiconductor) transistor) with a FIN structure (FinFET or tri-gate). The gate structure 10 of the NMOS transistor is formed on a three-dimensional (3D) silicon surface with sidewalls insulated from the sidewalls of other transistors using an insulating material (e.g., oxide, or oxide / nitride, or some high-k dielectric). The source 11 and drain 12 of the NMOS transistor are formed by implanting a high concentration of n-type (n+) dopant into a p-type substrate (or p-well) using a technique that combines ion implantation with thermal annealing, thereby creating two separated n+ / p junction regions.

[0003] Furthermore, in order to reduce collisional ionization and hot carrier implantation, it is common practice to form low-concentration doped drains (n-type LDDs) 13 in front of the source 11 and drain 12 by a technique that combines ion implantation with thermal annealing prior to the high-concentration doped n+ / p junction. Such a technique of combining ion implantation with thermal annealing often results in LDDs 13 that penetrate into the 3D active region beneath the gate structure 10 (as shown in Figure 1). Consequently, the effective channel length 14 between the LDDs 13 inevitably becomes shorter.

[0004] On the other hand, advances in manufacturing process technology continue to progress rapidly by scaling down the geometry of NMOS transistors in both horizontal and vertical dimensions (for example, reducing the minimum feature size called lambda (λ) from 28 nm to 5 nm or 3 nm). However, scaling such FinFET or tri-gate geometries introduces or exacerbates numerous problems: (1) As dimensions in both horizontal and vertical directions are scaled down, conventional self-alignment methods using gates, spacers, and ion implantation formation alone are insufficient to perfectly align the LDD junction edge (or source / drain edge) with the edge of the gate structure 10. Furthermore, thermal annealing techniques to remove ion implantation damage must rely on high-temperature processing techniques, such as rapid thermal annealing, using various energy sources or other thermal processes. Thus, one problem arises: gate-induced drain leakage (GIDL) current, which, despite the fact that it should be minimized to reduce leakage current, is difficult to control. Another problem arises: it is difficult to control the length of the effective channel 14, and therefore the short channel effect (SCE) is hardly minimized. Moreover, it is difficult to adjust the relative position between the source / drain edge and the edge of the gate structure 10 so that GIDL can be controlled; (2) Furthermore, ion implantation for forming LDD13 (or n+ / p junction in NMOS, or p+ / n junction in PMOS (p-type metal-oxide-semiconductor)) acts like a cannonball, inserting ions straight down into the substrate from the silicon surface. As a result, the dopant concentration is unevenly distributed vertically from the top surface with a higher doping concentration to the junction region with a lower doping concentration. Therefore, it is difficult to create a uniform material interface with few defects from the source 11 and drain 12 to the effective channel 14 and the substrate body region. (3) Furthermore, when the horizontal dimensions are scaled down to 7nm, 5nm, or 3nm, the height (vertical dimension) of the NMOS transistor fin structure (e.g., 60-300nm) becomes much larger than the width (horizontal dimension) of the NMOS transistor fin structure (e.g., 3-7nm), resulting in the fin structure becoming fragile or even collapsing during subsequent processes (e.g., source / drain formation, gate formation).

[0005] Therefore, the present invention provides a transistor structure for solving the problems described in 1)-3) above. [Overview of the project]

[0006] One embodiment of the present invention provides a transistor structure. The transistor structure includes a substrate, an insulating wall, and a gate region. The substrate has a fin structure. The insulating wall clamps the side walls of the fin structure. The gate region rests on the fin structure and the insulating wall, and the insulating wall is configured to prevent the fin structure from collapsing.

[0007] According to one aspect of the present invention, the insulating wall clamps the four side walls of the fin structure.

[0008] According to one aspect of the present invention, the transistor structure further includes an STI layer surrounding an insulating wall.

[0009] According to one aspect of the present invention, the transistor structure further includes a sheet channel layer disposed between the side wall and the insulating wall of the fin structure, the sheet channel layer being formed by selective epitaxial growth.

[0010] According to one aspect of the present invention, the gate region includes a gate dielectric layer on a fin structure, a gate conductive layer on the gate dielectric layer, and a cap layer on the gate conductive layer.

[0011] According to one aspect of the present invention, the insulating wall is configured to prevent the fin structure from collapsing during the formation of the gate dielectric layer, the gate conductive layer, and the cap layer.

[0012] According to one aspect of the present invention, the transistor structure further includes a spacer layer on the side wall of the gate region.

[0013] According to one aspect of the present invention, a first conductive region is formed in a first recess beneath the initial surface of the substrate.

[0014] Another embodiment of the present invention provides a transistor structure comprising a substrate, a composite structure, and a gate region. The substrate has a fin structure. The composite structure clamps the side walls of the fin structure. The gate region rests on the fin structure and the composite structure, and the composite structure is configured to prevent the fin structure from collapsing.

[0015] According to one aspect of the present invention, the composite structure includes a support wall that clamps the side wall of the fin structure and a support beam that supports the support wall.

[0016] According to one aspect of the present invention, the support wall extends in a first direction from the bottom of the fin structure, and the support beam extends in a second direction different from the first direction of the support wall.

[0017] According to one aspect of the present invention, the support wall and the support beam are made of nitride.

[0018] According to one aspect of the present invention, the support beam is in contact with the support wall.

[0019] According to one aspect of the present invention, the composite structure includes a support wall that clamps the side wall of the fin structure, and a plurality of support beams that support the support wall.

[0020] Another embodiment of the present invention includes a transistor structure, which includes a substrate having an initial surface, a channel region, a gate region over the channel region, a shallow trench isolation region, a first conductive region between the gate region and the shallow trench isolation region and in electrical contact with the channel region, a metal region between the gate region and the shallow trench isolation region, and at least two surfaces of the first conductive region are in contact with the metal region.

[0021] According to one aspect of the present invention, the shallow trench isolation region extends above the initial surface, and the first conductive region is not above the shallow trench isolation region.

[0022] According to one aspect of the present invention, the metal region is in contact with the top surface and the side walls of the first conductive region.

[0023] According to one aspect of the present invention, the transistor structure further includes an L-shaped isolator under the bottom of the first conductive region.

[0024] Another embodiment of the present invention includes a transistor structure, which includes a substrate having an initial surface, a channel region, a gate region over the channel region, a shallow trench isolation region surrounding the channel region, and a first conductive region in electrical contact with the channel region, and the bottom surface of the gate region is below the bottom surface of the first conductive region.

[0025] According to one aspect of the present invention, the bottom surface of the gate region is above a part of the shallow trench isolation region.

[0026] After reading the following detailed description of the preferred embodiments shown in various figures and drawings, these and other objects of the present invention will become apparent to those skilled in the art.

Brief Description of the Drawings

[0027] [Figure 1]This is a diagram showing a FinFET that conforms to prior art. [Figure 2A] This is a flowchart showing a method for manufacturing a Finn field-effect transistor (FinFET) according to the first embodiment of the present invention. [Figure 2B] Figures 2B, 2C, and 2D are diagrams that explain Figure 2A. [Figure 2C] Figures 2B, 2C, and 2D are diagrams that explain Figure 2A. [Figure 2D] Figures 2B, 2C, and 2D are diagrams that explain Figure 2A. [Figure 3] This diagram shows that a pad oxide layer is grown, a pad nitride layer is deposited, trenches and semiconductor layers are formed, oxide spacers are deposited on the semiconductor layer, and nitride spacers are deposited on the oxide spacers. [Figure 4] This diagram shows that a shallow trench isolation (STI) is formed, defining a gate area that spans the active region and the isolation region. [Figure 5] This figure shows the formation of the gate material, the deposition of the composite cap layer, the etching of the STI, and the removal of the pad nitride layer. [Figure 6] This figure shows that the pad oxide layer is etched away, part of the STI is etched back, oxide 2-spacers and nitride 2-spacers are formed, and some exposed silicon areas are etched away to create shallow trenches for the source and drain. [Figure 7] This figure shows that three oxide layers are thermally grown. [Figure 8] This figure shows that the three oxide layers are etched away, and the source and drain are formed by SEG technology. [Figure 9] This figure shows a cross-section of an SCBFET and the corresponding doping concentrations in the Y and X directions. [Figure 10] This diagram shows a cross-section of an SCBFET, which has a trapezoidal shape. [Figure 11]This figure shows a cross-section of an SCBFET without a thin sheet channel layer. [Figure 12A] Figures 12A and 12B are flowcharts showing a method for manufacturing a FinFET according to a second embodiment of the present invention. [Figure 12B] Figures 12A and 12B are flowcharts showing a method for manufacturing a FinFET according to a second embodiment of the present invention. [Figure 13] This diagram shows the process of depositing an oxide layer, removing the excess oxide layer using CMP (Chemical Polymer Measure) technology to form a STI (Steel Tin), and then depositing a nitride film on the STI. [Figure 14] This figure shows the process of forming an STI on a nitride film to define a gate area spanning an active region and an isolation region, etching away the pad oxide layer and pad nitride layer corresponding to the gate area, etching back the STI corresponding to the gate area to form a gate dielectric material, depositing the gate material in the recess, then etching back the gate material to form a composite cap layer, and polishing the composite cap layer. [Figure 15] This figure shows the process of etching a portion of the STI to remove the pad nitride layer, etching off the pad oxide layer, etching back the STI, and forming oxide 2-spacers and nitride 2-spacers on the edges of the gate material and composite cap layer. [Figure 16] This figure shows the process of etching away exposed silicon and then thermally growing three layers of oxide. [Figure 17] This figure shows the process of etching away a portion of the three oxide layers, then forming an n-type low-concentration doped drain (LDD), and subsequently forming an n+ doped source and an n+ doped drain. [Figure 18] This diagram shows that a nitride film is deposited several times. [Figure 19] This figure shows the formation of a fused semiconductor junction-metal conductor (MSMC) structure. [Figure 20A] This figure shows a structure in which a fused semiconductor junction metal conductor (MSMC) structure is formed according to another embodiment of the present invention. [Figure 20B] This figure shows a structure in which a fused semiconductor junction metal conductor (MSMC) structure is formed according to another embodiment of the present invention. [Modes for carrying out the invention]

[0028] First Embodiment Please refer to Figures 2A, 2B, 2C, 2D, 3, 4, 5, 6, 7, 8, 9, 10, and 11. Figure 2A is a flowchart showing a method for manufacturing a fin field-effect transistor (FinFET) according to the first embodiment of the present invention. The FinFET manufacturing method in Figure 2A can reduce the gate-induced drain leakage (GIDL) current and short-channel effect (SCE) of the FinFET, and can also form a solid wall that clamps the active region or narrow fin structure of the FinFET. The detailed procedure is as follows.

[0029] Step 10: Start.

[0030] Step 20: Define the active region based on the p-type well 202 and form a fin structure.

[0031] Step 30: Form the gate of the FinFET on the original horizontal surface (OHS) of the p-type well 202.

[0032] Step 40: Form the source and drain of the FinFET.

[0033] Step 50: Complete.

[0034] Please refer to Figures 2B and 3. Step 20 may include the following:

[0035] Step 102: The pad oxide layer 204 is grown and the pad nitride layer 206 is deposited.

[0036] Step 104: Define the active region, remove the portion of silicon material outside the active region to create a trench 210, and form a fin structure.

[0037] Step 106: Form an oxide spacer 304, etch back the oxide spacer 304, and form a nitride spacer 306.

[0038] Next, please refer to Figures 2C, 4, and 5. Step 30 may include the following:

[0039] Step 108: Deposit an oxide layer and remove the excess oxide layer using chemical mechanical polishing (CMP) technology to form STI402.

[0040] Step 110: Define a gate area spanning the active region and the isolation region, etch off the pad oxide layer 204 and pad nitride layer 206 corresponding to the gate area, and etch back the STI 402 corresponding to the gate area.

[0041] Step 112: Form the gate dielectric material 502, deposit the gate material 504 in the recess 404, and then etch back the gate material 504.

[0042] Step 114: A composite cap layer 506 is formed, and the composite cap layer 506 is polished using CMP technology.

[0043] Please refer to Figures 2D, 6, 7, and 8. Step 40 may include the following:

[0044] Step 116: Etch back the STI402, nitride spacer 306, and remove the pad nitride layer 206.

[0045] Step 118: Etch off the pad oxide layer 204 and etch back the STI 402.

[0046] Step 120: Oxide 2-spacer 802 and nitride 2-spacer 804 are formed on the edges of the gate material 504 and composite cap layer 506.

[0047] Step 122: Etch and remove the exposed silicon.

[0048] Step 124: Thermally grow three oxide layers 1002.

[0049] Step 126: The oxide 3 layer 1002 is etched away, then n-type low-concentration doped drains (LDDs) 1102 and 1104 are formed, and then n+ doped source 1106 and n+ doped drain 1108 are formed.

[0050] A detailed description of the above manufacturing method is as follows: Starting with a well-designed doped p-type well 202, which is located within a p-type substrate 200 (in other embodiments of the invention, the process may begin with the p-type substrate 200 rather than the p-type well 202), in one example, the p-type well 202 is doped at a lower concentration (even including the punch-through injection dopant profile) than the substrate used in state-of-the-art FinFETs, with its top surface counted down approximately 500 nm from the OHS, and doped to a higher concentration (e.g., 5 × 10⁻¹⁰) than the concentration used in state-of-the-art FinFETs. 18 Dopant / CM 3 It has a concentration close to . Also, for example, p-type substrate 200 is 1 × 10 16 Dopant / CM 3 It has a lower concentration, close to that. The actual dopant concentration will be determined by the final optimization for mass production. As a result, instead of producing a fin substrate that is largely depleted (which behaves like a voltage-floating body that is hardly controlled or stabilized, and is less desirable than a semiconductor transistor with a voltage-stabilized body), a p-type substrate voltage (usually grounded, i.e., 0V) can be supplied across most of the FinFET body.

[0051] In step 102, as shown in Figure 3(a), a pad oxide layer 204 of a well-designed thickness is grown over the OHS, and then a pad nitride layer 206 of a well-designed thickness is deposited on the top surface of the pad oxide layer 204.

[0052] In step 104, as shown in Figure 3(a), the active region of the FinFET is defined by anisotropic etching using photolithography masking technology. This anisotropic etching technology removes the portion of silicon material corresponding to the OHS outside the active region, creating trenches 210 (e.g., approximately 300 nm deep) for subsequent STI (shallow trench isolation) needs, and as a result, the fin structure of the FinFET is also created. Figure 3(b) is a top view corresponding to Figure 3(a), and Figure 3(a) is a cross-sectional view along the cutting line in the X direction shown in Figure 3(b).

[0053] In step 106, as shown in Figure 3(a), a semiconductor layer 302 is grown using a selective growth method, such as selective epitaxial growth (SEG) technology, to cover the exposed silicon surface (the two side walls of the fin structure and the top surface of the bottom region of the trench 210). (Hereinafter referred to as a sheet channel layer (SCL), the SCL may be a monolithic p-type doped silicon approximately 1-2 nm thick, which should be adjusted to suit the detailed device design.) In another example, this sheet channel layer (SCL) is optional. An oxide spacer 304 is deposited on the semiconductor layer 302, and the oxide spacer 304 is etched back using anisotropic etching technology to bring the top surface of the oxide spacer 304 to a height matching the OHS. Next, a nitride spacer 306 is deposited on the oxide spacer 304, bringing the top surface of the nitride spacer to a height matching the top surface of the pad nitride layer 206. In addition, the oxide spacer 304 and nitride spacer 306 are located outside the active region of the FinFET. Therefore, the important point here is that the oxide spacer 304 and nitride spacer 306 form a solid wall that clamps the active region or the narrow fin structure, particularly the side walls of the fin structure. This solid clamping wall can be a single layer or other composite capping layer to protect the narrow fin structure from collapsing during the formation of the FinFET's source / drain or gate.

[0054] Another important point here is that the semiconductor layer 302 is used for the channel region of the FinFET (which will be converted into a depletion region until it is completely inverted into a channel conduction region, depending on how the gate voltage is applied). Therefore, the doping concentration of the semiconductor layer 302 affects the threshold voltage of the FinFET and forms the main conductive layer with electron carriers under inversion, connecting both the n-type source and n-type drain. Since the SEG layer 302 is formed separately from the bulk body of the FinFET, the most desirable design is to use a doping concentration (e.g., 1 × 10⁻¹⁶) that is lower than the doping concentration of the fin body, so that the off-to-on channel conduction condition, which is converted from depletion to inversion, occurs almost entirely within the semiconductor layer 302, with less influence from the more stable voltage conditions of the FinFET bulk body. 16 From 3 x 10 18 This is because it has the following characteristics. Furthermore, as the feature size (i.e., the dimensions of the lines) continues to scale down horizontally, the fins are made proportionally thinner and taller, so the semiconductor layer 302 also enhances the mechanical stability of the fins. Taller fins can increase the device width (to compensate for the decrease in carrier mobility due to undesirable channel collisions as the fins become narrower), but this can lead to the physical collapse of some narrow fins.

[0055] In step 108, as shown in Figure 4(a), a thick oxide layer is deposited to completely fill the trench 210, and the excess oxide layer is removed using CMP technique to form the STI402. The top surface of the STI402 is at the same height as the top surface of the pad nitride layer 206. The STI402 further surrounds or clamps the active region or narrow fin structure, particularly the side walls of the fin structure, protecting the narrow fin structure from collapse when forming the source / drain or gate of the FinFET. Figure 4(b) is a top view corresponding to Figure 4(a), and Figure 4(a) is a cross-sectional view along the X-direction cutting line shown in Figure 4(b).

[0056] Next, in step 110, as shown in Figure 4(a), a gate area spanning the active region and the STI isolation region is defined using photolithographic masking technology, and the pad oxide layer 204 and pad nitride layer 206 corresponding to the gate area are removed to create a recess 404. Furthermore, the STI 402 corresponding to the gate area is also etched down by a certain amount (e.g., 40-80 nm depth) to form a stepped structure between the etched STI region corresponding to the gate area and the fin surface. The oxide spacer 304 and nitride spacer 306 corresponding to the gate area may also be removed. Thus, the upper part of the semiconductor layer 302 is exposed, providing a smooth line edge roughness for the gate of the FinFET.

[0057] In step 112, as shown in Figure 5(a), a gate dielectric material 502 (composite material or oxide) is formed in the recess 404 (including the stepped structure between the etched STI 402 corresponding to the gate area and the fin surface), and a gate material 504 (for example, a metal such as tungsten 5044 covering TiN 5042) is deposited on top of the gate dielectric material 502. Then, the gate material 504 is polished by CMP technique to bring its top surface to a height matching the top surface of the remaining pad nitride layer 206, and the gate material 504 is etched back so that its top surface is below the top surface of the remaining pad nitride layer 206. Thus, a tri-gate structure may exist.

[0058] Next, in step 114, as shown in Figure 5(a), a composite cap layer 506, consisting of a nitride layer 5062 and a hard mask oxide layer 5064, is deposited in the recess 404 on the top surface of the gate material 504. The composite cap layer 506 is used to protect the gate material 504. Then, the composite cap layer 506 is polished by CMP technique to bring its top surface to a height that matches the top surface of the pad nitride 206. Figure 5(b) is a top view corresponding to Figure 5(a), and Figure 5(a) is a cross-sectional view along the cutting line in the X direction shown in Figure 5(b).

[0059] In step 116, as shown in Figure 6(a), the STI402 and nitride spacer 206 are etched to remove the pad nitride layer 206, and the top surface of the STI402 is brought to the same height as the top surface of the pad oxide layer 204.

[0060] Similarly, up to step 116, two semiconductor layers 302 (sheet channel layers, SCLs) are formed on the two sidewalls of the fin (these two semiconductor layers 302 are named Qleft and Qright, respectively), but the top surface of the fin structure does not have an SCL, and therefore the threshold voltage of the upper MOSFET (Qtop) with a higher doping concentration may be higher than that of the two sidewalls of the FinFET).

[0061] In step 118, as shown in Figure 6(a), the pad oxide layer 204 is etched off and a portion of the STI 402 is etched back.

[0062] Next, in step 120, as shown in Figure 6(a), two oxide layers are deposited on the edges of the gate material 504 and the composite cap layer 506 to form an oxide 2-spacer 802, and two nitride layers are deposited to form a nitride 2-spacer 804. Figure 6(b) is a top view corresponding to Figure 6(a), and Figure 6(a) is a cross-sectional view along the cutting line in the X direction shown in Figure 6(b).

[0063] In another example, by retaining the STI402 and removing the pad nitride layer 206, it is possible to ensure that the STI402 still surrounds the fin structure. Then, as shown in Figure 6(c), the pad oxide layer 204 is etched away, and a portion of the STI402 is etched away so that the remaining STI402 still has a top surface higher than the OHS. Thus, the fin structure is surrounded by the remaining STI402 with a top surface higher than the OHS.

[0064] Next, in step 122, as shown in Figure 7(a), some of the exposed silicon area is etched away to create shallow trenches 902 (for example, about 50 nm deep) for the source and drain of the FinFET.

[0065] In step 124, as shown in Figure 7(a), oxide layer 3 1002 is grown using a thermal oxidation process called the oxide 3 process (including both oxide layer 3V 10022 that penetrates the vertical sidewalls of the FinFET bulk body (assuming it has a sharp crystal orientation (110)) and oxide layer 3B 10024 on the top surface of the bottom of the shallow trench 902). Since the two sidewalls of the shallow trench 902 have a vertical composite material of oxide 2 spacer 802 and nitride 2 spacer 804, and the other sidewall of the shallow trench 902 is in contact with oxide spacer 304 and nitride spacer 306, the source / drain width of the FinFET is not affected at all by this thermal oxidation process. Also, the thicknesses of oxide layer 3V 10022 and oxide layer 3B 10024 shown in Figure 7 and subsequent figures are shown for illustrative purposes only, and their geometry is not proportional to the dimensions of the STI 402 shown in those figures. For example, the thickness of the oxide 3V layer 10022 and the oxide 3B layer 10024 is approximately 20-30 nm, but the vertical height of STI402 can be approximately 200-250 nm.

[0066] However, it is crucial to design the oxidation process so that the thickness of the oxide 3V layer 10022 can be controlled very precisely under precisely controlled thermal oxidation temperature, timing, and growth rate. Thermal oxidation on a well-defined silicon surface should result in 40% of the thickness of the oxide 3V layer 10022 being carried away from the exposed (110) silicon surface thickness of the vertical wall of the FinFET body, and the remaining 60% of the thickness of the oxide 3V layer 10022 being considered an addition to the outside of the vertical wall of the FinFET body (these 40% and 60% distributions of oxide 3V layer 10022 to oxide 2 spacer 802 / nitride 2 spacer 804 are particularly clearly depicted by dashed lines in Figure 7, so as its importance will be clearly stated in the following text). Also, Figure 7(b) is a top view corresponding to Figure 7(a), and Figure 7(a) is a cross-sectional view along the X-direction cutting line shown in Figure 7(b). Furthermore, Figure 7(c) shows another example of the oxidation-3 process based on the structure in Figure 6(c).

[0067] In step 126, as shown in Figure 8(a), the oxide 3 layer 1002 is first etched off. Then, using a selective growth method such as SEG technology, n-type LDDs 1102 and 1104 are formed, followed by the formation of the n+-doped source 1106 and n+-doped drain 1108. Thus, the main part of the FinFET is completed. Figure 8(b) is a top view corresponding to Figure 8(a), and Figure 8(a) is a cross-sectional view along the cutting line in the X direction shown in Figure 8(b). Figure 8(c) shows another example of a selective growth process based on the structure of Figure 7(c). As shown in Figure 8(c), the fin structure is surrounded by residual STI 402 which has a higher top surface than the OHS, so in the selective growth of the source / drain region, the source / drain region to be selectively grown is not on top of the residual STI 402 but is confined by the residual STI 402.

[0068] Also, it should be noted that, in one example, the bottom surface (not shown) of the gate structure on the STI region can be about 10 - 20 nm lower than the bottom surface of the drain / source region.

[0069] Please refer to FIG. 9. FIG. 9(a) is a cross-sectional view taken along the cutting line in the Y direction shown in FIG. 8(b). As shown in FIG. 9(a), both Qleft and Qright, which are SEG-grown p-type doped silicon channel regions, are clearly visible in the cross-sectional view. As shown in FIG. 9(b), there are a prior art Y-direction concentration profile LYN and a Y-direction concentration profile LYP, and the Y-direction concentration profile LYN corresponds to the dashed line L1 shown in FIG. 9(a). Similarly, as shown in FIG. 9(c), there are a prior art X-direction concentration profile LXN and an X-direction concentration profile LXP, and the X-direction concentration profile LXN corresponds to the dashed line L2 shown in FIG. 9(a). It is clear that the doping concentrations of Qleft and Qright (e.g., 1×10 16 to 3×10 18 ) are lower than that of the fin body of the FinFET (e.g., 5×10 18 ). Also, in another embodiment, as shown in FIG. 10, the fin structure can be etched into a trapezoidal shape for better short-channel effect control. Further, in another embodiment, the fin body may be undoped.

[0070] The main points of the invention are described below. Since both the drain and source of the FinFET are formed by SEG technology, except that they are doped with n-type dopants at concentrations higher than those of Qleft and Qright, seamless contact regions are clearly formed between the drain and channel and between the source and channel, respectively. The formation of the channel, drain, and source is completed without ion implantation, and high-temperature thermal annealing is not required to remove damage caused by the violent impact of forming the drain and source. In addition, the active region or narrow fin structure, particularly the side walls of the fin structure, is clamped by solid walls (e.g., oxide spacers 304 and nitride spacers 306 shown in Figure 3). These solid clamping walls can be a single layer or other composite capping layer that protects the narrow fin structure from collapse during the formation of the FinFET source / drain or gate. Furthermore, STI 402 (shown in Figure 4) further surrounds or clamps the active region or narrow fin structure, particularly the side walls of the fin structure, to protect the narrow fin structure from collapse during the formation of the FinFET source / drain or gate. Therefore, even if the height of the fin structure (e.g., 60-300 nm) is much greater than the width of the fin structure of a FinFET (e.g., 3-7 nm), the fin structure protected by the solid wall of the present invention is less likely to become fragile during subsequent processes (e.g., source / drain formation, gate formation, etc.).

[0071] As shown in Figure 6, another advantage of the present invention is that the thicknesses of the oxide 2 spacer 802 and nitride 2 spacer 804 formed on the edges of the gate region (i.e., the gate material 504 and the composite cap layer 506) are controllable, as are the thicknesses of the oxide 3V layer 10022 and oxide 3B layer 10024 formed by the thermal oxidation process (shown in Figure 7), so that the source / drain edges can be aligned or substantially aligned with the edges of the gate region (as shown in Figure 8), in particular, since the source / drain is formed by SEG technology. Thus, according to the present invention, the relative position or distance between the source / drain edges and the edges of the gate region is controllable and may depend on the thickness of the spacers formed on the edges of the gate region, and / or the thickness of the oxide layers (e.g., oxide 3V layer 10022 shown in Figure 7, but oxide 3V layer 10022 is removed in Figure 8). Thus, the effective channel length Leff (shown in Figure 8) can be controlled so that the gate-induced drain leakage (GIDL) current problem can be improved.

[0072] In another embodiment, the selective epitaxial growth (SEG) technique for growing the thin sheet channel layer (semiconductor layer 302) of monolithic p-type doped silicon shown in Figure 3 is not required, but solid walls (e.g., oxide spacers 304 and nitride spacers 306 shown in Figure 3) are still formed to clamp the active region or narrow fin structure, particularly the sidewalls of the fin structure. Then, without the thin sheet channel layer (semiconductor layer 302), a different fin structure (as shown in Figure 11) can be formed by performing the same process as in Figures 4 to 8. Naturally, in another embodiment, the fin structure can be etched into a trapezoidal shape for better control of short channel effects. Again, as shown in Figure 11, even if the height of the fin structure (e.g., 60-300 nm) is much greater than the width of the fin structure (e.g., 3-7 nm), the fin structure of this embodiment, protected by solid walls, is less likely to become fragile during subsequent processes (e.g., source / drain formation, gate formation, etc.). The relative position or distance between the source / drain edge and the gate region edge can be controlled and may depend on the thickness of the spacer formed on the gate region edge, and / or the thickness of the oxide layer (e.g., oxide 3V layer 10022 shown in Figure 11). Thus, the effective channel length Leff can be controlled so that the GIDL current problem can be improved.

[0073] Second Embodiment Please refer to Figures 12A, 12B, 13, 14, 15, 16, and 17. Figures 12A and 12B are flowcharts showing a method for manufacturing a FinFET according to a second embodiment of the present invention. The FinFET manufacturing method in Figures 12A and 12B can also reduce the gate-induced drain leakage (GIDL) current and short-channel effect (SCE) of the FinFET, and can form a solid wall that clamps the active region or narrow fin structure of the FinFET. The detailed procedure is as follows.

[0074] Process 1200: Start.

[0075] Step 1202: A pad oxide layer 204 is grown based on the p-type well 202, and a pad nitride layer 206 is deposited (shown in Figure 3).

[0076] Step 1204: Define the active region of the FinFET and remove the portion of silicon material corresponding to the OHS outside the active region to create the trench 210 and fin structure (shown in Figure 3).

[0077] Step 1206: An oxide spacer 304 is formed, and the oxide spacer 304 is etched back to form a nitride spacer 306 (shown in Figure 3).

[0078] Step 1208: An oxide layer is deposited, and the excess oxide layer is removed using chemical mechanical polishing (CMP) technology to form STI402 (shown in Figure 13).

[0079] Step 1210: A nitride film 1302 is deposited on STI402 (shown in Figure 13).

[0080] Step 1212: STI402 is formed again on the nitride film 1302 to define a gate area spanning the active region and the isolation region, the pad oxide layer 204 and pad nitride layer 206 corresponding to the gate area are etched off, and the STI402 corresponding to the gate area is etched back (shown in Figure 14).

[0081] Step 1214: Form the gate dielectric material 502, deposit the gate material 504 in the recess 404, and then etch back the gate material 504 (as shown in Figure 14).

[0082] Step 1216: A composite cap layer 506 is formed, and the composite cap layer 506 is polished using CMP technology (shown in Figure 14).

[0083] Step 1218: A portion of STI402 is etched to remove the pad nitride layer 206 (shown in Figure 15).

[0084] Step 1220: The pad oxide layer 204 is etched off and STI402 is etched back (shown in Figure 15).

[0085] Step 1222: Oxide 2-spacer 802 and nitride 2-spacer 804 are formed on the edges of the gate material 504 and composite cap layer 506 (shown in Figure 15).

[0086] Step 1224: Etch off the exposed silicon (shown in Figure 16).

[0087] Step 1226: The oxide 3 layer 1002 is thermally grown (shown in Figure 16).

[0088] Step 1228: The oxide 3 layer 1002 is etched away, then n-type low-concentration doped drains (LDDs) 1102 and 1104 are formed, and then n+ doped source 1106 and n+ doped drain 1108 are formed (shown in Figure 17).

[0089] Process 1230: Completed.

[0090] The differences between the second embodiment and the first embodiment are as follows: 1) In step 1208, as shown in Figure 13, a thick oxide layer is deposited to completely fill the trench 210, the excess oxide layer is removed using CMP technique, and the oxide layer is etched back to form STI402, where the top surface of STI402 is made to a specific height lower than OHS; 2) Next, in step 1210, a nitride film 1302 of appropriate thickness is deposited on the STI 402, as shown in Figure 13. Notably, the direction of extension of the nitride film 1302 (e.g., horizontal) differs from the direction of extension of the nitride spacer 306 that clamps the fin structure (e.g., vertical), allowing the nitride film 1302 to act as a support beam for the nitride spacer 306.

[0091] Accordingly, a second embodiment of the present invention provides a composite structure for clamping a fin structure. The composite structure includes a support wall (i.e., a semiconductor layer 302, an oxide spacer 304, and a nitride spacer 306) that clamps the fin structure, the support wall extending in a first direction (i.e., vertical direction) from the bottom of the fin structure. The composite structure further includes a support beam (i.e., a nitride film 1302) extending in a second direction (i.e., horizontal direction) different from the first direction of the support wall. The support beam can abut against the support wall and support it, thereby further reinforcing the fin structure and preventing collapse.

[0092] Furthermore, the STI402 (shown in Figure 13) further surrounds or clamps the active region or narrow fin structure, particularly the sidewalls of the fin structure, preventing the narrow fin structure from collapsing during the formation of the FinFET source / drain or gate.

[0093] Furthermore, the objective of the second embodiment is to ensure even greater fin protection against bending and drop effects.

[0094] Furthermore, in another embodiment, in step 1210, the nitride film 1802 may be deposited several times (as shown in Figure 18). These multiple deposited nitride films 1802, in combination with the nitride spacer, can reinforce the fin structure and prevent its collapse. Similarly, in another embodiment, as shown in Figure 19, the nitride film 1904 may be deposited several times, and the resistance of the source / drain region may be improved by forming a metal-semiconductor junction in the source / drain region. In addition, most of the source / drain area can be isolated by insulating material including a bottom structure of oxide layer 3B 2304 and / or nitride layer 3 2402, which can significantly reduce junction leakage. Furthermore, in Figure 19, a merged semiconductor junction and metal conductor (MSMC) structure is used to form the source and drain directly connected to the p-type well 202 of the FinFET in this case (disclosed in U.S. Patent Application No. 17 / 983,348 filed on November 8, 2022, the corresponding content of which is incorporated here, and for simplicity, further explanation is omitted).

[0095] As shown in Figure 19, (1) the fin structure of the second embodiment (shown in Figures 12A and 12B) is protected by a solid wall, and (2) the relative position or distance between the source / drain edge and the gate region edge is controllable and may depend on the thickness of the oxide 3V layer 2302 (and / or the thickness of the spacer formed on the gate region edge). Furthermore, the resistance of the source / drain can be improved by forming a fused metal-semiconductor junction in the source / drain as shown in Figure 19. Moreover, most of the source / drain region is isolated by insulating material including a bottom structure of oxide 3B layer 2304 and / or nitride 3 layer 2402, and therefore junction leakage can be significantly reduced.

[0096] In another embodiment, as shown in Figure 20A, the top surface of the STI region surrounding the fin structure is higher than the top surface of the fin structure, resulting in the selectively grown source / drain region being confined by the STI region rather than being above it. A metal contact plug can be deposited in the hole between the STI region and the gate region without using a separate contact mask to create such a hole. Furthermore, the top, bottom, and sidewalls of the source (drain) region can be in direct contact with the metal, dramatically reducing the contact resistance of the source / drain region. In addition, the bottom surface (not shown) of the gate structure on or covering the STI region surrounding the fin structure can be about 10-20 nm lower than the bottom surface of the drain / source region. In Figure 20A, the metal material surrounds or contacts the top, bottom, and one sidewall of the n+ doped drain 2806.

[0097] Furthermore, in another embodiment (as shown in Figure 20B), the difference between Figure 20A and Figure 20B is that the deposited TiN2502 and deposited metal (e.g., tungsten 2504) can be omitted, and a portion of the oxide 3V layer 2302 is simply etched down using the top surface of the nitride 3 layer 2402 as a reference to expose the silicon sidewall 2702, and then the n-type low-concentration doped drain (NLDD) 2802 and the n+ doped source 2804 and n+ doped drain 2806 are formed using selective growth techniques, and then a metal such as tungsten (e.g., tungsten 2504 as shown in Figure 20B) is deposited. In Figure 20B, the metal plug is in contact with the top surface and one sidewall of the n+ doped drain.

[0098] In summary, the FinFET provided by the present invention has several advantages, which are described as follows: (1) A solid wall is formed to clamp the active region or narrow fin structure, particularly the side walls of the fin structure. Therefore, even if the height of the fin structure (e.g., 60-300 nm) is much greater than the width of the fin structure (e.g., 3-7 nm), the fin structure protected by the solid wall of the present invention is less likely to become fragile. Furthermore, the solid wall can be reinforced by providing an additional beam-like structure; (2) The relative position or distance between the source / drain edge and the gate region edge is controllable and may depend on the thickness of the spacer formed on the gate region edge and / or the thickness of the oxide layer (e.g., the oxide 3V layer in Figure 7 or Figure 16); (3) A gate structure is formed within an etched region with smooth line edge roughness (Figure 4), and therefore the gate structure has smoother edges; (4) The resistance of the source / drain can be improved by forming a metal-semiconductor junction (shown in Figures 20A, 20B, or 19) between the source and drain; (5) Most of the source / drain area is isolated by insulating material including a bottom structure of oxide 3B layer and / or nitride 3 layer (shown in Figure 20A, Figure 20B, or Figure 19), and therefore the junction leakage current can be greatly reduced.

[0099] Furthermore, the technical features shown in Figures 20A, 20B, or 19, the gate formation described herein, and the advantages (2)-(5) above can be applied not only to FinFETs but also to other types of transistors (e.g., planar transistors).

[0100] Furthermore, when forming sources / drains using selective growth techniques, the concentration of the selectively grown sources / drains is not limited to the LDD and the subsequent high-concentration doped region. <110> The profile can be adjusted by gradually increasing from the surface, from n- to n+, or from n- to n++, and then to n+, or other gradually changing or stepwise changing profiles.

[0101] While the present invention has been illustrated and described with reference to embodiments, it should be understood that the present invention is not limited to the disclosed embodiments, but rather is intended to cover a variety of modifications and equivalent configurations that fall within the spirit and scope of the appended claims.

Claims

1. A substrate having a semiconductor surface and a fin structure, A gate structure bonded to the semiconductor surface and spanning the fin structure above the fin structure, the gate structure including a gate extension region, A first epitaxial conductive region adjacent to one side of the gate structure, A second epitaxial conductive region adjacent to the other side of the gate structure, A shallow trench isolation region adjacent to the first epitaxial conductive region and the second epitaxial conductive region, surrounding the fin structure, The bottom surface of the gate extension region, above a portion of the shallow trench isolation region and outside the fin structure, is below the bottom surface of the first epitaxial conductive region or the second epitaxial conductive region, and is also below the top surface of the shallow trench isolation region outside the gate structure. Transistor structure.

2. The transistor structure according to claim 1, further comprising a metal region between the gate structure and the shallow trench isolation region, wherein at least two surfaces of the first epitaxial conductive region are in contact with the metal region.

3. The transistor structure according to claim 2, wherein the metal region is in contact with the top surface and the outermost side wall of the first epitaxial conductive region.

4. The transistor structure according to claim 3, wherein the metal region is further in contact with the bottom surface of the first epitaxial conductive region.

5. The transistor structure according to claim 1, wherein the shallow trench isolation region extends above the semiconductor surface of the substrate, the shallow trench isolation region surrounds the first epitaxial conductive region and the second epitaxial conductive region, and neither the first epitaxial conductive region nor the second epitaxial conductive region lies above the shallow trench isolation region.

6. A first recess located beneath the semiconductor surface of the substrate, which accommodates the first epitaxial conductive region, A metal region surrounded by the shallow trench isolation region and in contact with the first epitaxial conductive region, The L-shaped isolator in the first recess, It further possesses, The bottom surface of the first epitaxial conductive region and the bottom surface of the metal region are insulated from the substrate by the L-shaped isolator. The transistor structure according to claim 5.

7. The transistor structure according to claim 6, wherein the edge of the L-shaped isolator is aligned with one side of the gate structure.

8. The transistor structure according to claim 1, wherein the first epitaxial conductive region extends along a first direction and includes a first surface extending along the first direction, and the first surface of the first epitaxial conductive region is perpendicular to the semiconductor surface of the substrate.

9. The transistor structure according to claim 8, wherein the first epitaxial conductive region further includes a second surface extending along the first direction, and the second surface of the first epitaxial conductive region is perpendicular to the semiconductor surface of the substrate.

10. The transistor structure according to claim 8, wherein the first epitaxial conductive region has a rectangular shape.

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