Indication device

Abstract

To provide a semiconductor device with a transistor using oxide semiconductors that offer higher shock resistance. To provide a reliable semiconductor device that can accommodate increasingly diverse applications, enhancing convenience.SOLUTION: In a semiconductor device, a gate electrode, a first insulating layer, an oxide semiconductor layer, a second insulating layer and a conductive layer are formed on a substrate, the gate electrode and the conductive layer each extend beyond both ends of the oxide semiconductor layer in the channel width direction of the transistor, and in a cross-section of the transistor along the channel width direction, the oxide semiconductor layer is surrounded by the gate electrode, the first insulating layer, the second insulating layer, and the conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This term encompasses a wide range of electronic devices, including electro-optical devices, semiconductor circuits, and electronic equipment. [Background technology]

[0003] Thin-film transistors (TFTs) are constructed using semiconductor thin films formed on a substrate having an insulating surface. The technology that makes it up is attracting attention. Thin-film transistors are used in integrated circuits (ICs) and image display devices. It is widely applied in electronic devices such as display devices.

[0004] Metal oxides are attracting attention as materials that exhibit semiconductor properties applicable to thin-film transistors. Thin-film transistors that use metal oxides exhibiting such semiconductor properties as channel formation regions This is known (see Patent Documents 1 and 2).

[0005] Furthermore, electronic devices using thin-film transistors are used in a variety of places and applications. As a result, the required characteristics and shapes, such as weight reduction, thinning, and impact resistance, are becoming more diverse. Therefore, the development of electronic devices with functionality tailored to specific purposes is progressing.

[0006] For example, as a semiconductor device installed in a gaming machine, the display surface is designed to give players a greater sense of three-dimensionality. A display with a curved surface has been reported (see, for example, Patent Document 3). [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Application Publication No. 7-114347 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] As described above, when semiconductor devices are used in various shapes, the semiconductor device is vulnerable to external shocks. It is necessary to provide them with high resistance.

[0009] Therefore, one embodiment of the present invention relates to a semiconductor device having a transistor made of an oxide semiconductor. One of the objectives is to provide higher impact resistance.

[0010] Furthermore, one embodiment of the present invention can accommodate a wider range of applications and offers improved convenience and high reliability. One of the objectives is to provide semiconductor devices. [Means for solving the problem]

[0011] One embodiment of the invention disclosed herein is a substrate comprising a gate electrode layer and a gate insulating layer A transistor with a bottom gate structure including an oxide semiconductor layer, and an insulating layer on the transistor. The device has a conductive layer on top of an insulating layer, the insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. It is provided in such a way that, in the channel width direction of the oxide semiconductor layer, gate insulation is provided on the gate electrode layer. The edges of the insulating layer and the conductive layer coincide, and the conductive layer is the channel formation region of the oxide semiconductor layer and the gate A semiconductor device that covers the insulating layer and the edges of the insulating layer, and is provided in contact with the gate electrode layer. ru.

[0012] One form of the configuration of the invention disclosed in this specification is a driving circuit part including a transistor with a bottom gate structure on the same substrate, and a pixel part including a transistor for pixels. The transistor for the driving circuit includes a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer. An insulating layer is provided on the oxide semiconductor layer, and a conductive layer is provided on the insulating layer. The insulating layer covers the oxide semiconductor layer and is provided in contact with the gate insulating layer. In the channel width direction of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer coincide on the gate electrode layer. The conductive layer covers the channel formation region of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer, and is provided in contact with the gate electrode layer. It is a semiconductor device. A driving circuit part including a transistor, and a pixel part including a transistor for pixels. The transistor for the driving circuit includes a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer. An insulating layer is provided on the oxide semiconductor layer, and a conductive layer is provided on the insulating layer. The insulating layer covers the oxide semiconductor layer and is provided in contact with the gate insulating layer. In the channel width direction of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer coincide on the gate electrode layer. The conductive layer covers the channel formation region of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer, and is provided in contact with the gate electrode layer. It is a semiconductor device. In the above configuration, the source electrode layer and the drain electrode layer may be provided between the oxide semiconductor layer and the insulating layer, or may be provided between the gate insulating layer and the oxide semiconductor layer. In the above configuration, the channel formation region of the oxide semiconductor layer is surrounded by the gate insulating layer and the insulating layer laminated one above the other, and further by the gate electrode layer and the conductive layer in the channel width direction, so it has excellent impact resistance and the substrate can be freely processed into any shape using a flexible substrate. It can be done.

[0013] When a transistor including an oxide semiconductor layer is provided on a flexible substrate, a semiconductor device having flexibility can be manufactured. The transistor including the oxide semiconductor layer may be directly manufactured on the flexible substrate, or the transistor including the oxide semiconductor layer may be manufactured on another manufacturing substrate and then peeled off and transferred to the flexible substrate. In addition, in order to peel off and transfer from the manufacturing substrate to the flexible substrate, the manufacturing substrate and the oxide semiconductor

[0014] In the above configuration, the channel formation region of the oxide semiconductor layer is surrounded by the gate insulating layer and the insulating layer laminated one above the other, and further by the gate electrode layer and the conductive layer in the channel width direction, so it has excellent impact resistance and the substrate can be freely processed into any shape using a flexible substrate. The channel formation region of the oxide semiconductor layer is surrounded by the gate insulating layer and the insulating layer laminated one above the other, and further by the gate electrode layer and the conductive layer in the channel width direction, so it has excellent impact resistance and the substrate can be freely processed into any shape using a flexible substrate. It has excellent impact resistance and the substrate can be freely processed into any shape using a flexible substrate. It can be done.

[0015] When a transistor including an oxide semiconductor layer is provided on a flexible substrate, a flexible semiconductor device can be fabricated. It can be fabricated.

[0016] The transistor including the oxide semiconductor layer may be directly fabricated on the flexible substrate, or the transistor including the oxide semiconductor layer may be fabricated on another fabrication substrate and then peeled off and transferred to the flexible substrate. It may be peeled off and transferred to the flexible substrate after fabrication. In addition, in order to peel off and transfer from the fabrication substrate to the flexible substrate, the fabrication substrate and the oxide semiconductor It may be peeled off and transferred to the flexible substrate after fabrication. In addition, in order to peel off and transfer from the fabrication substrate to the flexible substrate, the fabrication substrate and the oxide semiconductor It is preferable to provide a delamination layer between the transistor containing the layer and the transistor itself.

[0017] One embodiment of the invention disclosed herein involves forming a gate electrode layer on a flexible substrate, and A gate insulating layer is formed on the gate electrode layer, and an oxide semiconductor layer is formed on the gate insulating layer, and oxidation An insulating layer is formed by covering the semiconductor layer, and an opening is formed in the gate insulating layer and the insulating layer to form the gate electrode. The layer is exposed, and the gate insulating layer and the upper part of the lamination of the gate insulating layer and the insulating layer, and the opening A semiconductor device that covers the end of the lamination with the insulating layer and forms a conductive layer in contact with the gate electrode layer. This is the manufacturing method.

[0018] One embodiment of the invention disclosed herein involves forming a release layer on a fabricated substrate, and applying a gel to the release layer. A gate electrode layer is formed, a gate insulating layer is formed on the gate electrode layer, and an oxide layer is formed on the gate insulating layer. A semiconductor layer is formed, an insulating layer is formed by covering the oxide semiconductor layer, and a gate insulating layer and insulating layer are formed. An opening is formed to expose the gate electrode layer, and the upper part of the lamination between the gate insulating layer and the insulating layer, and the opening In this configuration, the end of the lamination between the gate insulating layer and the insulating layer is covered, and the conductive layer is in contact with the gate electrode layer. A transistor is fabricated by forming a layer, and the transistor is removed from the fabricated substrate to the support substrate using a stripping layer. A semiconductor device is constructed by transposing a transistor onto a support substrate and then transposing the transistor onto a flexible substrate. This is the manufacturing method.

[0019] The ordinal numbers "1st" and "2nd" are used for convenience only and do not represent the order of processes or stacking. This does not indicate that the invention is uniquely named. This does not indicate anything. [Effects of the Invention]

[0020] One embodiment of the present invention involves stacking an oxide semiconductor layer in the channel width direction in the channel formation region. The gate is surrounded by an insulating layer, an insulating layer, a gate electrode layer, and a conductive layer. This allows for added impact resistance.

[0021] One embodiment of the present invention provides flexibility, enabling it to accommodate a wider range of applications and increasing convenience. This enables the provision of highly reliable semiconductor devices. [Brief explanation of the drawing]

[0022] [Figure 1] A diagram illustrating one form of semiconductor device. [Figure 2] A diagram illustrating one form of semiconductor device. [Figure 3] A diagram illustrating one method for fabricating semiconductor devices. [Figure 4] A diagram illustrating one method for fabricating semiconductor devices. [Figure 5] A diagram illustrating one form of semiconductor device. [Figure 6] A diagram illustrating one form of semiconductor device. [Figure 7] A diagram illustrating one form of semiconductor device. [Figure 8] A diagram illustrating one form of semiconductor device. [Figure 9] A diagram illustrating one form of semiconductor device. [Figure 10] A diagram showing electronic equipment. [Figure 11] A diagram showing electronic equipment. [Modes for carrying out the invention]

[0023] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. This is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It's not something that can be done.

[0024] (Embodiment 1) In this embodiment, one form of semiconductor device and a method for manufacturing a semiconductor device is shown using Figures 1 and 3. Let me explain. In this embodiment, a transistor is shown as an example of a semiconductor device. The semiconductor layer in the semiconductor device disclosed in the specification preferably uses an oxide semiconductor layer. can.

[0025] As shown in Figures 1(A) to (C), the oxide semiconductor layer 403 of transistor 410 The channel formation region has a channel length (L) direction and a channel width (W) direction.

[0026] Figure 1(A) is a plan view of transistor 410, and Figure 1(B) is a plan view of the transistor shown in Figure 1(A). Figure 1(C) shows a cross-sectional view of line A1-A2 in the channel length (L) direction of ZISTA 410. This is a cross-sectional view of the line B1-B2 in the direction of the panel width (W).

[0027] As shown in Figures 1(A) to (C), the transistor 410 is mounted on a substrate 40 having an insulating surface. On top of the 0 are a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, and a source electrode. It includes layer 405a and drain electrode layer 405b. On transistor 410 is insulating layer 407 The conductive layer 411 is laminated in that order.

[0028] Furthermore, in the cross-sectional view in the channel width direction of Figure 1(C), the oxide semiconductor layer 403 is gate insulating. The top, bottom and ends are surrounded by layer 402 and insulating layer 407, and the gate insulating layer 402 and insulating Layer 407 is in contact at both ends. A gate electrode layer 401 is provided below the gate insulating layer 402. On the insulating layer 407, there is an oxide semiconductor layer 403, a gate insulating layer 402, and an insulating layer The upper part of 407 and the gate insulating layer 402 and both ends of the insulating layer 407 are covered, and the gate A conductive layer 411 is provided in contact with the polar layer 401.

[0029] Therefore, in the channel width direction, the oxide semiconductor layer 403 is connected to the gate insulating layer 402 and the insulating layer 4 07, and surrounded by the gate electrode layer 401 and the conductive layer 411.

[0030] Thus, the oxide semiconductor layer 403 is surrounded by a gate insulating layer, a gate electrode layer, an insulating layer, and If the structure is protected by laminating conductive layers, then the chain shown by arrow 445 in Figure 1(C) will be formed. Even when a force (externally applied force) is applied in the direction of the flannel width (W), the thick laminated film remains intact. Because the structure is resistant to bending, it reduces the force applied to the oxide semiconductor layer 403 located at the center of the stack. This is possible. Therefore, damage to the oxide semiconductor layer 403 due to external impact is prevented. It is possible.

[0031] Furthermore, the gate insulating layer 402 and the insulating layer 407 have openings that widely expose the gate electrode layer 401. This configuration is formed such that the gate electrode layer 401 and the conductive layer 411 are in contact at the opening. If a conductive film with good adhesion is used as the gate electrode layer 401 and the conductive layer 411, arrow 445 The gate electrode layer 401, gate insulating layer 402, oxide semiconductor layer 403, insulating due to the force shown This prevents delamination of the film at the interface of layer 407 or the conductive layer 411.

[0032] To increase the adhesion between the gate electrode layer 401 and the conductive layer 411, a wide contact area should be provided. Preferably, as shown in Figure 1(A), the gate electrode layer 401 and the conductive layer 411 are in contact. The distance in the channel length direction of the oxide semiconductor layer 403 in the region is defined as the distance of the oxide semiconductor layer 403 It is preferable to make it longer than the channel length distance.

[0033] Furthermore, the oxide semiconductor layer 403 is placed in the center, and both ends are connected to the gate insulating layer 402 and insulating layer 407 is in contact with and sealed, and both ends are in contact with the gate electrode layer 401 and the conductive layer 411. Therefore, to seal it, a structure symmetrical with respect to line C1-C2 can be achieved. Thus, arrow 4 The forces shown in 45 are evenly distributed, and a large localized force is applied in the oxide semiconductor layer 403. This can prevent that from happening.

[0034] Therefore, in transistor 410, the curvature of the oxide semiconductor layer 403 in the channel width direction It can increase resistance to impact and provide shock resistance.

[0035] In the drive circuit, the channel width of the transistor is made longer to allow more current to flow. It is preferable to do so. However, if the transistor has a long channel width, in the channel width direction The influence of external forces also becomes significant. Therefore, the channel width method shown in this embodiment is not suitable. Using transistors with bending resistance in the direction in the drive circuit is more effective, and shock resistance This allows for the creation of highly reliable semiconductor devices with superior performance.

[0036] To provide impact resistance, a flexible substrate is used for the substrate 400, resulting in a flexible semiconductor device. It can also be applied to various applications, accommodating a wider range of uses and improving convenience and reliability. We can provide highly efficient semiconductor devices.

[0037] Furthermore, the transistors disclosed herein are particularly in the channel width direction of the oxide semiconductor layer. Because it has excellent bending resistance, when manufacturing semiconductor devices, the direction in which it is most likely to bend (the frequency of bending) It is preferable to fabricate the transistor with the channel width direction aligned with the higher direction.

[0038] Figures 3(A1)(A2) to (E1)(E2) show an example of a method for fabricating transistor 410. Note that Figures 3(A1) to (E1) correspond to Figure 1(B), and Figures 3(A2) to ( E2) corresponds to Figure 1(C).

[0039] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. The gate electrode layer 401 is formed by the process. The resist mask is made by the inkjet method. It may be formed. If the resist mask is formed by the inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0040] The substrate 400 having an insulating surface can be a flexible substrate, for example, polyethylene Polyester resins such as refthalate (PET) and polyethylene naphthalate (PEN), Polyacrylonitrile resin, polyimide resin, polymethyl methacrylate resin, polycarbonate Polycarbonate resin (PC), polyethersulfone resin (PES), polyamide resin, thic Polyolefin resin, polystyrene resin, polyamide-imide resin, polyvinyl chloride resin, etc. These can be suitably used. A structure in which an organic resin is impregnated into a fibrous material as a flexible substrate. (So-called prepreg) may be used. Also, silicon nitride or oxide may be used on the substrate 400 beforehand. Films containing nitrogen and silicon, such as silicon nitride, and films containing nitrogen and aluminum, such as aluminum nitride. A protective film with low water permeability, such as a film containing the material, may be formed beforehand.

[0041] If the substrate 400 material contains fibrous material, the fibrous material may be an organic or inorganic compound. High-strength fibers are used. Specifically, high-strength fibers are those with a high tensile modulus or Young's modulus. It refers to fibers, and typical examples include polyvinyl alcohol-based fibers and polyester fibers. Polyamide fibers, polyethylene fibers, aramid fibers, poly(p-phenylenebenzo) Examples include soxazole fibers, glass fibers, or carbon fibers. Glass fibers include: Examples include glass fibers using E-glass, S-glass, D-glass, Q-glass, etc. The material is used in the form of a woven or nonwoven fabric, and the organic resin is impregnated into this fiber and then cured. The structure may be used as the substrate 400. The substrate 400 may consist of a fiber and an organic resin. Using a structure improves reliability against failure due to bending and localized pressure, therefore it is preferable. It has a complex structure.

[0042] Furthermore, a glass substrate thinned to a degree that is flexible (for example, barium borosilicate glass or a Luminoborsilicate glass or a film-formed metal substrate may be used. There are no particular limitations on the materials used, but aluminum, copper, nickel, and aluminum alloys are also acceptable. Alternatively, metal alloys such as stainless steel can be suitably used.

[0043] To fabricate a flexible semiconductor device, an oxide semiconductor layer 403 is included on a flexible substrate. The transistor 410 may be fabricated directly, or the oxide semiconductor layer 403 may be included in another fabrication substrate. The transistor 410 may be fabricated, and then peeled off and transferred to a flexible substrate. To peel and transfer from the substrate to the flexible substrate, the fabricated substrate and the transition containing the oxide semiconductor layer It is advisable to provide a release layer between the stud and the stud.

[0044] An insulating film that serves as the underlayer may be provided between the substrate 400 and the gate electrode layer 401. It has the function of preventing the diffusion of impurity elements from the substrate 400, silicon nitride film, silicon oxide One or more films selected from a silicon nitride film, silicon nitride film, or silicon oxide film. It can be formed by a laminated structure.

[0045] Furthermore, the material of the gate electrode layer 401 is molybdenum, titanium, tantalum, tungsten, and Metal materials such as luminium, copper, neodymium, scandium, or alloy materials with these as the main components. It can be formed using a material, either as a single layer or in layers.

[0046] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. Using plasma CVD or sputtering methods, a silicon oxide layer and a silicon nitride layer are created. silicon oxide nitride layer, silicon oxide nitride layer, aluminum oxide layer, aluminum nitride layer , an aluminum oxide nitride layer, an aluminum oxide nitride layer, or a hafnium oxide layer as a single layer It can be formed by stacking layers.

[0047] The oxide semiconductor of this embodiment has impurities removed, and carriers other than the main components of the oxide semiconductor are removed. By increasing the purity to minimize the amount of impurities that act as donors, it is made into true (Type I) or This essentially uses an intrinsically modified (Type I) oxide semiconductor.

[0048] In highly purified oxide semiconductor layers, there are extremely few carriers (close to zero), The concentration is 1 × 10 14 / cm 3 Less than 1 × 10 12 / cm 3 Less than, even better ku is 1 x 10 11 / cm 3 It is less than.

[0049] Because there are very few carriers in the oxide semiconductor layer, the transistor reduces the off-current. This is possible. A lower off-current is preferable.

[0050] Such highly purified oxide semiconductors are extremely sensitive to interface states and interface charges. Therefore, the interface between the oxide semiconductor layer and the gate insulating layer is important. Therefore, highly purified acid The gate insulating layer that comes into contact with the synthetic semiconductor requires high quality.

[0051] For example, high-density plasma CVD using μ-waves (e.g., frequency 2.45 GHz) is dense and It is preferable because it can form a high-quality insulating layer with high dielectric strength. The close contact between the high-quality gate insulating layer and the interface reduces the interface state and improves interface characteristics. This is because it can be done that way.

[0052] Of course, if it can form a good insulating layer as a gate insulating layer, sputtering Other film deposition methods such as plasma CVD can be applied. Furthermore, post-deposition heat treatment can be performed. Even if the insulating layer has modified film quality of the gate insulating layer and interface characteristics with the oxide semiconductor, Good. In any case, it is essential that the film quality as a gate insulating layer is good, as well as oxidation Any material that can reduce the interface state density with the semiconductor and form a good interface would be acceptable.

[0053] Furthermore, the gate insulating layer 402 and the oxide semiconductor film 440 contain as much hydrogen, hydroxyl groups, and moisture as possible. To prevent contamination, sputtering is used as a pretreatment for the deposition of the oxide semiconductor film 440. A substrate 400 on which the gate electrode layer 401 is formed in the preheating chamber of the device, or a gate insulating layer 4 The substrate 400, on which layers 02 have been formed, is preheated to remove hydrogen, moisture, etc. adsorbed on the substrate 400. It is preferable to remove impurities and exhaust them. The exhaust means provided in the preheating chamber is cryogenic. A pump is preferred. Note that this preheating process can be omitted. The heat reaches the source electrode layer 405a and drain electrode layer 405b before the insulating layer 407 is formed. The same procedure may be performed on the formed substrate 400.

[0054] Next, a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or less, is applied to the gate insulating layer 402. An oxide semiconductor film 440 with a wavelength of 30 nm or less is formed (see Figure 3(A1)(A2)).

[0055] Furthermore, before depositing the oxide semiconductor film 440 by sputtering, an argon gas is introduced. Reverse sputtering is performed to generate plasma by introducing material, and the material adheres to the surface of the gate insulating layer 402. It is preferable to remove the powdery material (also called particles or debris). Reverse sputtering is Without applying voltage to the target side, an RF power supply is used to apply voltage to the substrate side in an argon atmosphere. This method involves applying an argon atmosphere to form a plasma near the substrate and modify the surface. Nitrogen, helium, oxygen, etc., may be used instead of ambient air.

[0056] The oxide semiconductor used in the oxide semiconductor film 440 is an In-S quaternary metal oxide. n-Ga-Zn-O oxide semiconductors and ternary metal oxides such as In-Ga-Zn-O Oxide semiconductors, In-Sn-Zn-O based oxide semiconductors, In-Al-Zn-O based oxide semiconductors Conductors, Sn-Ga-Zn-O oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, S n-Al-Zn-O oxide semiconductors and binary metal oxides such as In-Zn-O oxides Semiconductors, Sn-Zn-O oxide semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg- O-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, Using In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. This is possible. Furthermore, the oxide semiconductor may also contain SiO2. Here, for example, In-Ga-Zn-O oxide semiconductors are composed of indium (In), gallium (Ga), and sub-zinc. This refers to an oxide film containing lead (Zn), and its stoichiometric ratio is not particularly relevant. Furthermore, it may contain elements other than In, Ga, and Zn.

[0057] Furthermore, the oxide semiconductor film 440 has the chemical formula InMO3(ZnO) m (m>0) A thin film can be used. Here, M is selected from Ga, Al, Mn, and Co. Or it can represent multiple metallic elements. For example, M can be Ga, Ga and Al, Ga and Mn, or Other examples include Ga and Co.

[0058] In this embodiment, the oxide semiconductor film 440 is an In-Ga-Zn-O based oxide target The film is deposited by sputtering using a t. Furthermore, the oxide semiconductor film 440 is formed using a rare gas ( Typically, this occurs under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen. It can be formed by sputtering.

[0059] For example, a target for fabricating oxide semiconductor film 440 by sputtering is The oxide has a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [molar ratio]. An In-Ga-Zn-O film is deposited using a target. Furthermore, the material of this target and The composition is not limited to this; for example, In2O3:Ga2O3:ZnO = 1:1:2 [number of moles] A ratio oxide target may also be used.

[0060] Furthermore, the packing density of the oxide target should be 90% or more and 100% or less, preferably 95% or more and 99% or less. It is less than 0.9%. By using a metal oxide target with a high packing density, the acid film is formed. Ion semiconductor films can be made into dense films.

[0061] The sputtering gas used when depositing the oxide semiconductor film 440 is hydrogen, water, hydroxyl group or hydrogen It is preferable to use a high-purity gas from which impurities such as monoxides have been removed.

[0062] The substrate is held in a film deposition chamber under reduced pressure, and the substrate temperature is kept between 100°C and 600°C. The temperature should be between 200°C and 400°C. By depositing the film while heating the substrate, The concentration of impurities in the deposited oxide semiconductor film can be reduced. Damage caused by rinsing is reduced. And, while removing residual moisture in the deposition chamber, hydrogen and moisture are removed. The removed sputtering gas is introduced, and the oxide semiconductor is placed on the substrate 400 using the target described above. A film 440 is deposited. To remove residual moisture in the deposition chamber, an adsorption-type vacuum pump is used, for example. For example, cryopumps, ion pumps, and titanium sublimation pumps are preferred. It seems so. Also, as an exhaust method, a turbo pump (turbomolecular pump) with cold trap It may also be a mixture to which a p is added. The deposition chamber, which has been evacuated using a cryopump, is, for example, filled with water. Elementary atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably compounds containing carbon atoms) Because (and other substances) are exhausted, the concentration of impurities in the oxide semiconductor film deposited in the deposition chamber It can be reduced.

[0063] An example of film deposition conditions is a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa. The conditions applied are a DC power supply of 0.5kW and an oxygen atmosphere (oxygen flow rate ratio of 100%). It can be done. Furthermore, when using a pulsed DC power supply, powdery substances (particles) generated during film formation can be produced. This method is preferable because it reduces (also known as) the film thickness distribution and becomes more uniform.

[0064] Next, the oxide semiconductor film 440 is transformed into island-shaped oxide semiconductors by a second photolithography process. The material is processed into layers. Additionally, a resist mask is used to form island-shaped oxide semiconductor layers. It may also be formed by the jet method. If the resist mask is formed by the inkjet method, photomask Because no screws are used, manufacturing costs can be reduced.

[0065] Furthermore, when forming contact holes in the gate insulating layer 402, the process is carried out in an oxide semiconductor. This can be done simultaneously with the processing of film 440.

[0066] Note that the etching of the oxide semiconductor film 440 here can be done by dry etching or wet etching. Wetting is also acceptable, and both can be used. For example, wet etching of oxide semiconductor film 440 The etching solution used for chipping is a mixture of phosphoric acid, acetic acid, and nitric acid, and ammonia hydrogen water. (31% by weight hydrogen peroxide solution: 28% by weight ammonia solution: water = 5:2:2) etc. This can be done. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0067] Next, the oxide semiconductor layer is subjected to a first heat treatment. This first heat treatment causes the oxide semiconductor layer The conductive layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C. The temperature shall be 750°C or higher, or 400°C or higher, below the substrate's strain point. Here, the heat treatment equipment The substrate is introduced into an electric furnace, one of the furnaces, and the oxide semiconductor layer is subjected to a nitrogen atmosphere at 450°C. After a 1-hour heat treatment, water and water are removed from the oxide semiconductor layer without exposure to the atmosphere. This prevents the re-incorporation of the element and obtains the oxide semiconductor layer 441 (see Figure 3(B1)(B2)).

[0068] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. A device that heats the object to be processed by radiation may also be used. For example, GRTA(Gas R apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Annealing) devices such as hermal annealing equipment al) equipment can be used. LRTA equipment uses halogen lamps, metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This is a device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp or similar light source. The GRTA device is a device that performs heat treatment using high-temperature gas. Noble gases such as argon, or nitrogen, which do not react with the material being treated by heat treatment. An active gas is used.

[0069] For example, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is moved and placed inside, heated for several minutes, then the substrate is moved and placed in a hot inert gas chamber. You may perform a GRTA (Great Value Analysis) from this source.

[0070] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably) It is preferable that the concentration be 0.1 ppm or less.

[0071] Furthermore, after heating the oxide semiconductor layer in the first heat treatment, high-purity oxygen gas is added to the same furnace. A 10°C N2O gas or ultra-dry air (with a dew point of -40°C or lower, preferably -60°C or lower) is introduced. It may be added. It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment device is preferably 6N or higher. Preferably, the impurity concentration in oxygen gas or N2O gas is 7N or higher (i.e., 1 ppm or less). It is preferable to keep the concentration below 0.1 ppm. Due to the action of oxygen gas or N2O gas, The oxidation that was simultaneously reduced by the process of removing impurities through dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component material that makes up the semiconductor, the oxide semiconductor layer can be improved. Purification and electrical conversion to Type I (intrinsic) are performed.

[0072] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on the semiconductor film 440. In that case, after the first heat treatment, the heating device is used The substrate is removed, and the photolithography process is performed.

[0073] Furthermore, the first heat treatment can also be performed after oxide semiconductor layer deposition, in addition to the above. After stacking the source electrode layer and the drain electrode layer on top of the layer, or the source electrode layer and the drain This can be done either after forming an insulating layer on the rain electrode layer.

[0074] Furthermore, when forming contact holes in the gate insulating layer 402, the process is carried out in an oxide semiconductor. This can be done either before or after the first heat treatment of the film 440.

[0075] Furthermore, by depositing the oxide semiconductor layer in two stages and performing heat treatment in two stages, the substrate Regardless of the material of the component, such as oxides, nitrides, or metals, the crystalline region (single crystal region) with a thick film thickness is a single crystal region. Even if an oxide semiconductor layer is formed having a crystalline region (i.e., a c-axis oriented region perpendicular to the film surface), Good. For example, a first oxide semiconductor film of 3 nm to 15 nm is formed, and nitrogen, oxygen, In an atmosphere of noble gas or dry air, at a temperature of 450°C to 850°C, preferably 550°C or lower. A first heat treatment is performed at a temperature of 750°C or lower, and a crystalline region (including plate-like crystals) is formed in the region including the surface. A first oxide semiconductor film having the following characteristics is formed. Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed. Form an oxide semiconductor film of type 2, and heat at a temperature of 450°C to 850°C, preferably 600°C to 70°C. A second heat treatment is performed at a temperature below 0°C, and the first oxide semiconductor film is used as a seed for crystal growth, and upward Crystal growth is performed to crystallize the entire second oxide semiconductor film, resulting in a thick crystalline region. An oxide semiconductor layer having a region may be formed.

[0076] Next, a source electrode layer and a drain are placed on the gate insulating layer 402 and the oxide semiconductor layer 441. A conductive film is formed to form the electrode layer (including wiring formed from the same layer). Source electrode Examples of conductive films used for the layer and drain electrode layer include Al, Cr, Cu, Ta, and T. A metal film containing an element selected from i, Mo, and W, or a metal composed of the above-mentioned elements. Nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc., can be used. It can also be done by placing Ti, Mo, W on either the underside or upperside of a metal film such as Al or Cu, or on both sides. High melting point metal films such as titanium nitride films, molybdenum nitride films, and other metal nitride films (titanium nitride films, molybdenum nitride films, and other metal nitride films) A configuration in which tungsten film layers are stacked is also possible. Furthermore, the source electrode layer and drain The conductive film used for the electrode layer may be formed from a conductive metal oxide. Examples of oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO2). ), indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), zinc oxide alloy (In2O3-ZnO) or these metal oxide materials with silicon oxide Products containing corn can be used.

[0077] A third photolithography step forms a resist mask on the conductive film, and selectively extracts the residue. After performing ching to form the source electrode layer 405a and the drain electrode layer 405b, the resist Remove the mask.

[0078] For exposure during resist mask formation in the third photolithography process, ultraviolet light and KrF light are used. It is preferable to use laser light or ArF laser light. Adjacent source electrodes on oxide semiconductor layer 441 The gap width between the lower end of the layer and the lower end of the drain electrode layer determines the transistor that is later formed. The channel length L is determined. Note that if exposure is performed with a channel length L less than 25 nm, Extreme ultraviolet light (Ultraviolet) has extremely short wavelengths, ranging from a few nanometers to tens of nanometers. Using et) when exposure is performed during the resist mask formation in the third photolithography step, Good. Exposure with ultra-ultraviolet light has high resolution and a large depth of field. Therefore, later formation It is also possible to set the transistor channel length L to between 10 nm and 1000 nm. The operating speed of the circuit can be increased.

[0079] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, The resist mask formed by a multi-tone mask, which is an exposure mask where the light has multiple intensities, is formed by the light. The etching process may be performed using a mask. A resist mask formed using a multi-gradation mask. The ske will have a shape with multiple film thicknesses, and its shape can be further deformed by etching. Because it can do this, it can be used in multiple etching processes that process different patterns. Therefore, a single multi-tone mask can accommodate at least two different patterns. This allows for the formation of a resist mask. Therefore, the number of exposure masks can be reduced. Furthermore, the corresponding photolithography process can also be reduced, thus simplifying the overall process.

[0080] Furthermore, during the etching of the conductive film, the oxide semiconductor layer 441 is etched and fragmented. It is desirable to optimize the etching conditions to avoid this. However, only the conductive film It is difficult to obtain the condition of etching without etching the oxide semiconductor layer 441 at all. Furthermore, during etching of the conductive film, only a portion of the oxide semiconductor layer 441 is etched, and grooves are formed. It may also become an oxide semiconductor layer having a recessed portion.

[0081] In this embodiment, a Ti film is used as the conductive film, and the oxide semiconductor layer 441 is made of In-Ga- Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (ammonia) was used as the etchant. Use a mixture of water and hydrogen peroxide.

[0082] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar, and the exposed material is then... Adsorbed water and other substances adhering to the surface of the oxide semiconductor layer may be removed. In this case, an insulating layer 407 is formed that is in contact with a portion of the oxide semiconductor layer without being exposed to the atmosphere.

[0083] The insulating layer 407 has a thickness of at least 1 nm, and water is applied to the insulating layer 407 by sputtering or other methods. The insulating layer 407 can be formed using appropriate methods that do not introduce impurities such as hydrogen. When hydrogen is present, the hydrogen penetrates the oxide semiconductor layer, or the hydrogen affects the oxide semiconductor layer. Oxygen is extracted from the layer, and the back channel of the oxide semiconductor layer becomes less resistive (N-type). This may lead to the formation of parasitic channels. Therefore, the insulating layer 407 should be as small as possible. To ensure that the resulting film is hydrogen-free, it is crucial to avoid using hydrogen in the film deposition method.

[0084] Typical examples of insulating layer 407 include silicon oxide film, silicon oxide nitride film, and aluminum oxide film. An inorganic insulating film such as a um film or an aluminum oxide nitride film can be used.

[0085] In this embodiment, a silicon oxide film with a thickness of 200 nm is used as the insulating layer 407, sputtered The film is deposited using the densitometry method. The substrate temperature during film deposition should be between room temperature and 300°C. In this embodiment, the temperature is set to 100°C. The silicon oxide film is deposited by sputtering using a rare gas (substitute). In general, under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen... This can be done. In addition, silicon oxide targets or silicon t A target can be used. For example, a silicon target can be used in an oxygen-containing atmosphere. A silicon oxide film can be formed by sputtering under gas pressure. In contact with the oxide semiconductor layer The insulating layer 407 formed by this process is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as these, An inorganic insulating film is used to block external intrusion, typically a silicon oxide film. Using silicon oxide nitride film, aluminum oxide film, or aluminum oxide nitride film, etc. ru.

[0086] Similar to the deposition of the oxide semiconductor film 440, residual moisture in the deposition chamber of the insulating layer 407 is removed. For this purpose, it is preferable to use an adsorption-type vacuum pump (such as a cryopump). The concentration of impurities in the insulating layer 407 deposited in the deposition chamber, which is evacuated using an op-pump, is reduced. Yes, it is possible. Furthermore, as an exhaust means for removing residual moisture in the deposition chamber of the insulating layer 407, A turbopump (turbomolecular pump) with a cold trap added may also be used.

[0087] The sputtering gas used when forming the insulating layer 407 is hydrogen, water, hydroxyl groups, or hydrides. It is preferable to use a high-purity gas from which impurities have been removed.

[0088] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide semiconductor A portion of the body layer (channel-forming region) is heated while in contact with the insulating layer 407.

[0089] Through the above steps, the oxide semiconductor film is subjected to a first heat treatment to release hydrogen. Impurities such as water, hydroxyl groups, or hydrides (also called hydrogen compounds) are removed from the oxide semiconductor layer. This constructs an oxide semiconductor that is graphically eliminated and simultaneously reduced by the impurity removal process. It can supply oxygen, which is one of the main component materials. Therefore, the oxide semiconductor layer is high Purification and electrical conversion to Type I (intrinsic) are performed.

[0090] Transistor 410 is formed through the above process (see Figure 3(C1)(C2)).

[0091] Furthermore, if a silicon oxide layer containing many defects is used for the insulating layer 407, after the silicon oxide layer is formed... By heat treatment, hydrogen, water, hydroxyl groups or hydrides contained in the oxide semiconductor layer are removed. The impurities are diffused into the oxide silicon layer, further reducing the amount of impurities contained in the oxide semiconductor layer. It produces the effect of causing something to happen.

[0092] A protective insulating layer may be formed on the insulating layer 407. For example, by using the RF sputtering method. A silicon nitride film is formed. RF sputtering is a method for depositing protective insulating layers because it offers good mass production capabilities. It is preferable from a legal standpoint. The protective insulating layer does not contain impurities such as moisture, and these do not penetrate from the outside. An inorganic insulating film is used to block this process, such as a silicon nitride film or an aluminum nitride film. Yes, they are.

[0093] After forming the protective insulating layer, further immerse in air at a temperature between 100°C and 200°C for 1 to 30 hours. The following heat treatment may be performed. This heat treatment may be carried out while maintaining a constant heating temperature. Furthermore, the temperature is raised from room temperature to a heating temperature of 100°C to 200°C, and from the heating temperature back to room temperature. The cooling process can be repeated multiple times.

[0094] Next, the gate insulating layer 402 and the insulating layer 407 are selectively removed, and the gate electrode layer 401 is This forms exposed openings 412a and 412b (see Figure 3(D1)(D2)). Figure 3(D As shown in 2), in the channel width direction of the oxide semiconductor layer 403, the gate insulating layer 40 2 and the insulating layer 407 surround and seal the oxide semiconductor layer 403 in the center, gate insulation Openings 412a and 412b are formed in layer 402 and insulating layer 407. In this embodiment, Since the gate insulating layer 402 and insulating layer 407 were etched using the same mask, the gate insulating layer The edges of layer 402 and the insulating layer 407 are roughly coincidental.

[0095] Next, a conductive film is formed on the insulating layer 407, and the conductive film is processed using a photolithography process. The conductive layer 411 is formed by cutting (see Figure 3(E1)(E2)). The conductive layer 411 is It is formed to cover at least the channel formation region of the oxide semiconductor layer 403.

[0096] As shown in Figure 3(E2), the oxide semiconductor layer 403 provided on the gate electrode layer 401 The upper part of the surrounding gate insulating layer 402 and insulating layer 407 and the gate insulating layer 402 and insulating layer The conductive layer 411 covers both ends of 407 and is in contact with the gate electrode layer 401 that is exposed at the opening. The conductive layer 411 is in contact with the gate electrode layer 401, and therefore the same as the gate electrode layer 401. It becomes an electric potential.

[0097] By providing a conductive layer 411 at the same potential as the gate electrode layer 401, the transistor 4 The goal is to prevent the formation of parasitic channels in the 10 back channels due to leakage current. can.

[0098] Furthermore, the conductive layer 411 shields against external electric fields, that is, external electric fields can enter the interior (transistor It also has a function to prevent it from acting on the circuit section (including the part containing it) (especially an electrostatic shielding function against static electricity). The conductive layer 411 provides shielding, preventing the transistor from being affected by external electric fields such as static electricity. This prevents fluctuations in the electrical characteristics of the 410.

[0099] Transition using the highly purified oxide semiconductor layer 403 fabricated using this embodiment The ST410 sets the current value in the off state (off current value) to 10 per 1 μm of channel width. It can be reduced to less than zA / μm, and even further to less than 100 zA / μm at 85°C.

[0100] Furthermore, the transistor 410 using the oxide semiconductor layer 403 exhibits relatively high field-effect mobility. Therefore, high-speed driving is possible. Thus, the above transient is obtained in the pixel portion of the liquid crystal display device. By using STA, high-quality images can be provided. In addition, highly purified oxidation By using transistors containing a semiconductor layer, the drive circuit section or pixel section is fabricated on the same substrate. Because it can be manufactured in a single step, the number of components in semiconductor devices can be reduced.

[0101] As described above, the channel formation regions of the oxide semiconductor layer are stacked in the channel width direction. By surrounding the gate insulating layer, the insulating layer, and further the gate electrode layer and the conductive layer, Impact resistance can be added.

[0102] Furthermore, by adding flexibility, it can accommodate a wider range of applications, improving convenience and reliability. We can provide highly efficient semiconductor devices.

[0103] (Embodiment 2) In this embodiment, another form of the semiconductor device will be described using Figure 2. A transistor is shown as an example of a semiconductor device. Note that the same part as in Embodiment 1 above or Parts and processes having similar functions can be carried out in the same manner as in the above embodiment and can be repeated. The explanation for "shi" will be omitted. Furthermore, a detailed explanation of the same section will also be omitted.

[0104] Figures 2(A) and 2(B) show transistors 420a, 420b, and 420c connected in parallel. Multiple transistors 420a, 420b, and 420c are connected in parallel, This has the same effect as widening the channel width, allowing more current to flow. This involves combining configurations such as arranging multiple transistors in parallel to divide the channel width. By using it in combination, the degree of freedom in circuit design can be improved. Transistor 420a Configurations that can handle large currents, such as 420b and 420c, are used for driving the drive circuit. It can be suitably used as a transistor for circuits.

[0105] Oxide semiconductor layers 423a, 423b, 423a of transistors 420a, 420b, 420c The channel-forming region of 3c has a channel length (L) direction and a channel width (W) direction. .

[0106] Figure 2(A) is a plan view of transistors 420a, 420b, and 420c, and Figure 2(B) is The channel width (W) direction of transistors 420a, 420b, and 420c shown in Figure 2(A) This is a cross-sectional view of the line B3-B4.

[0107] As shown in Figures 2(A) and 2(B), transistors 420a, 420b, and 420c are insulated. On a substrate 400 having a surface, a gate electrode layer 421 and a gate insulating layer 422 (gate insulating layer 4 22a, 422b, 422c), oxide semiconductor layer 423a, 423b, 423c, source Includes electrode layer 425a and drain electrode layer 425b. Transistors 420a, 420b, 4 On 20c are insulating layers 427 (insulating layers 427a, 427b, 427c) and conductive layer 43 The numbers 1 are stacked in order.

[0108] Transistors 420a, 420b, and 420c are connected in parallel, and gate electrode layer 4 21. The source electrode layer 425a and the drain electrode layer 425b are provided in common.

[0109] Furthermore, in the cross-sectional view in the channel width direction of Figure 2(B), oxide semiconductor layers 423a and 423b ,423c is the gate insulating layer 422a, 422b, 422c and insulating layer 427a, respectively. The gate insulating layers 422a and 422b are surrounded at the top, bottom and ends by 427b and 427c. 422c and insulating layers 427a, 427b, and 427c are in contact at both ends. Gate insulation Below layers 422a, 422b, and 422c, a gate electrode layer 421 is provided, and an insulating layer 42 On 7a, 427b, and 427c are oxide semiconductor layers 423a, 423b, and 423c, On top of insulating layers 422a, 422b, 422c, and insulating layers 427a, 427b, 427c Part and gate insulating layers 422a, 422b, 422c, and insulating layers 427a, 427b, 4 A conductive layer 431 is provided covering both ends of 27c and in contact with the gate electrode layer 421. .

[0110] Therefore, in the channel width direction, the oxide semiconductor layers 423a, 423b, and 423c are Gate insulating layers 422a, 422b, 422c and insulating layers 427a, 427b, 427c It is surrounded by a gate electrode layer 421 and a conductive layer 431.

[0111] Thus, the oxide semiconductor layers 423a, 423b, and 423c are surrounded by a gate electrode layer, and If the structure is protected by lamination of an insulating layer, an insulating layer, and a conductive layer, then in the channel width direction... Even when force is applied, the thick laminated structure is resistant to bending, so the center of the laminate is located This reduces the force applied to the oxide semiconductor layers 423a, 423b, and 423c. This prevents damage to the oxide semiconductor layers 423a, 423b, and 423c due to external impact. It is possible.

[0112] Also, gate insulating layer 422 (gate insulating layers 422a, 422b, 422c) and insulating layer 4 In 27 (insulating layers 427a, 427b, 427c), the gate electrode layer 421 is widely exposed. An opening is formed, and the gate electrode layer 421 and the conductive layer 431 are in contact at the opening. It is stated that if a conductive film with good adhesion is used as the gate electrode layer 421 and the conductive layer 431, External force on gate electrode layer 421, gate insulating layers 422a, 422b, 422c, Oxide semiconductor layers 423a, 423b, 423c, insulating layers 427a, 427b, 427c, Alternatively, delamination of the film at the interface of the conductive layer 431 can be prevented.

[0113] To increase the adhesion between the gate electrode layer 421 and the conductive layer 431, a wide contact area should be provided. Preferably, as shown in Figure 2(A), the gate electrode layer 421 and the conductive layer 431 are in contact. The distance in the channel length direction of the oxide semiconductor layers 423a, 423b, and 423c in the region is The distance between the channels of the oxide semiconductor layers 423a, 423b, and 423c is made longer than the distance between the channels. preferable.

[0114] Furthermore, in transistors 420a, 420b, and 420c, the oxide semiconductor layer 4 23a, 423b, and 423c are placed in the center, with gate insulating layers 422a and 423c at both ends. 2b, 422c and insulating layers 427a, 427b, 427c are in contact and sealed, and further both Since the edges are sealed by contact between the gate electrode layer 421 and the conductive layer 431, they have a line-symmetric structure. This can be achieved. Therefore, the force applied from the outside is evenly distributed, and the oxide semiconductor layer 423a This prevents large localized forces from being applied in 423b and 423c.

[0115] Therefore, in transistors 420a, 420b, and 420c, the oxide semiconductor layer 423a, To enhance the bending resistance in the channel width direction of 423b and 423c and to provide impact resistance. It is possible.

[0116] To provide impact resistance, a flexible substrate is used for the substrate 400, resulting in a flexible semiconductor device. It can also be applied to various applications, accommodating a wider range of uses and improving convenience and reliability. We can provide highly efficient semiconductor devices.

[0117] As described above, the channel formation regions of the oxide semiconductor layer are stacked in the channel width direction. By surrounding the gate insulating layer, the insulating layer, and further the gate electrode layer and the conductive layer, Impact resistance can be added.

[0118] Furthermore, by adding flexibility, it can accommodate a wider range of applications, improving convenience and reliability. We can provide highly efficient semiconductor devices.

[0119] This embodiment can be implemented in appropriate combination with other embodiments.

[0120] (Embodiment 3) In this embodiment, another form of the semiconductor device will be described with reference to Figure 5. A transistor is shown as an example of a semiconductor device. The transistor shown in Embodiment 1 and - This is an example where the formation process and structure of the electrode layer and drain electrode layer are different. Parts identical to or having similar functions to those of the above embodiment, and the process, shall be carried out in the same manner as the above embodiment. This can be done, and repeated explanations will be omitted. Detailed explanations of the same sections will also be omitted.

[0121] In Embodiments 1 and 2, the source electrode layer 405a and the drain electrode layer 405b An example is shown in which it is provided between the oxide semiconductor layer 403 and the insulating layer 407. In this embodiment, The source electrode layer 405a and the drain electrode layer 405b are connected to the gate insulating layer 402 and the oxide semiconductor An example of placement between body layer 403 is shown.

[0122] Figure 5(A) is a plan view of transistor 430, and Figure 5(B) is a plan view of the transistor shown in Figure 5(A). Figure 5(C) shows a cross-sectional view of line A5-A6 in the channel length (L) direction of ZISTA 430. This is a cross-sectional view of the line B5-B6 in the direction of the panel width (W).

[0123] The transistor 430 shown in Figures 5(A) to (C) is a bottom-gate type transistor. On the substrate 400, there is a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 405a, and It includes a rain electrode layer 405b and an oxide semiconductor layer 403. Furthermore, the transistor 430 An insulating layer 407 is provided that covers and is in contact with the oxide semiconductor layer 403.

[0124] In transistor 430, the gate insulating layer 402 is connected to the substrate 400 and the gate electrode layer 40 1 is provided in contact with the gate insulating layer 402, and the source electrode layer 405a and drain electrode layer 405b is provided in contact with it. And the gate insulating layer 402 and the source electrode layer 40 5a. An oxide semiconductor layer 403 is provided on the drain electrode layer 405b.

[0125] Furthermore, in the cross-sectional view in the channel width direction of Figure 5(C), the oxide semiconductor layer 403 is gate insulating. The top, bottom and ends are surrounded by layer 402 and insulating layer 407, and the gate insulating layer 402 and insulating Layer 407 is in contact at both ends. A gate electrode layer 401 is provided below the gate insulating layer 402. On the insulating layer 407, there is an oxide semiconductor layer 403, a gate insulating layer 402, and an insulating layer The upper part of 407 and the gate insulating layer 402 and both ends of the insulating layer 407 are covered, and the gate A conductive layer 411 is provided in contact with the polar layer 401.

[0126] Therefore, in the channel width direction, the oxide semiconductor layer 403 is connected to the gate insulating layer 402 and the insulating layer 4 07, and surrounded by the gate electrode layer 401 and the conductive layer 411.

[0127] Thus, the oxide semiconductor layer 403 is surrounded by a gate insulating layer, a gate electrode layer, an insulating layer, and If the configuration is protected by stacking conductive layers, the force in the channel width (W) direction (external or Even when a force is applied, the thick laminated structure is difficult to bend, so the center of the laminate The force acting on the oxide semiconductor layer 403 located therein can be reduced. Therefore, the force from the outside This prevents damage to the oxide semiconductor layer 403 due to impact.

[0128] Further, an opening is formed in the gate insulating layer 402 and the insulating layer 407, through which the gate electrode layer 401 is widely exposed, such that the gate electrode layer 401 and the conductive layer 411 are in contact with each other in the opening. If conductive films with good adhesion are used for the gate electrode layer 401 and the conductive layer 411, peeling of the films at the interfaces of the gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, the insulating layer 407, or the conductive layer 411 due to an externally applied force can be prevented. To enhance the adhesion between the gate electrode layer 401 and the conductive layer 411, it is preferable to provide a wide contact area. As shown in Fig. 5(A), the distance in the channel length direction of the oxide semiconductor layer 403 in the area where the gate electrode layer 401 and the conductive layer 411 are in contact is preferably longer than the channel length of the oxide semiconductor layer 403.

[0129] Also, the oxide semiconductor layer 403 is disposed in the center, and both ends thereof are sealed by contact with the gate insulating layer 402 and the insulating layer 407. Further, both ends thereof are sealed by contact with the gate electrode layer 401 and the conductive layer 411, so that a line-symmetric structure can be formed. Therefore, the externally applied force is evenly distributed, preventing a large local force from being applied to the oxide semiconductor layer 403.

[0130]

[0131] Thus, in the transistor 430, the bending resistance in the channel width direction of the oxide semiconductor layer 403 can be enhanced, and impact resistance can be imparted.

[0132] Since it has impact resistance, a flexible substrate can be used for the substrate 400, enabling it to be applicable as a flexible semiconductor device, corresponding to more diverse applications, and improving convenience and reliability. A highly reliable semiconductor device can be provided.

[0133] This embodiment can be implemented in appropriate combination with other embodiments.

[0134] (Embodiment 4) In this embodiment, an example of a method for manufacturing a semiconductor device in which a transistor is provided on a flexible substrate through a peeling and transfer process from another manufacturing substrate is shown. A semiconductor device according to one aspect of the present invention will be described with reference to FIG. 4. Since this embodiment is the same as Embodiment 1 except that some of the steps are different, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted. An example of a method for manufacturing a semiconductor device will be described in detail with reference to FIG. 4. Since this embodiment is the same as Embodiment 1 except that some of the steps are different, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted.

[0135] An example of a method for manufacturing a semiconductor device will be described in detail with reference to FIG. 4.

[0136] A release layer 302 is formed on a first manufacturing substrate 300, and a first insulating layer 301 is formed on the release layer 302. Preferably, the first insulating layer 301 is continuously formed without exposing the formed release layer 302 to the atmosphere. By continuously forming, it is possible to prevent the inclusion of dust and impurities between the release layer 302 and the first insulating layer 301. As the first manufacturing substrate 300, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used. As the glass substrate, barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed. A release layer 302 is formed on a first manufacturing substrate 300, and a first insulating layer 301 is formed on the release layer 302. Preferably, the first insulating layer 301 is continuously formed without exposing the formed release layer 302 to the atmosphere. By continuously forming, it is possible to prevent the inclusion of dust and impurities between the release layer 302 and the first insulating layer 301. As the first manufacturing substrate 300, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used. As the glass substrate, barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed.

[0137] As the first manufacturing substrate 300, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used. As the glass substrate, barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed. As the glass substrate, barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed. As the glass substrate, barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed. As the glass substrate, barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed. As the glass substrate, barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed.

[0138] Note that this process shows the case in which the release layer 302 is provided over the entire surface of the first fabricated substrate 300. However, if necessary, a release layer 302 may be applied to the entire surface of the first fabricated substrate 300, and then the release layer 302 may be selectively removed, and a peeling layer may be formed only in the desired region. Also, in Figure 4, A release layer 302 is formed in contact with the fabricated substrate 300 of the first fabrication, but if necessary, the first fabrication Between the substrate 300 and the release layer 302 is a silicon oxide layer, a silicon oxide nitride layer, and a silicon nitride layer. An insulating layer, such as a silicon nitride oxide layer, may be formed.

[0139] The release layer 302 consists of tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum. (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr) ), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os) , elements selected from iridium (Ir) and silicon (Si), or elements that are the main component It consists of an alloy material or a compound material mainly composed of the aforementioned element, and is a single layer or a laminated layer. The crystalline structure of the silicon-containing layer may be amorphous, microcrystalline, or polycrystalline.

[0140] The release layer 302 is formed by sputtering, plasma CVD, coating, printing, etc. Yes. Note that coating methods include spin coating, droplet dispensing, and dispensing.

[0141] When the release layer 302 has a single-layer structure, it is preferably a tungsten layer, a molybdenum layer, or a tan It forms a layer containing a mixture of tungsten and molybdenum, or an oxide of tungsten or This is a layer containing oxidized nitride, a layer containing molybdenum oxide or oxidized nitride, or tungsten A layer containing an oxide or oxidized nitride of a mixture of tene and molybdenum is formed. The mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

[0142] When the release layer 302 has a laminated structure, preferably, a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed as the first layer, and as the second layer, an oxide, nitride, oxynitride, or nitroxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed.

[0143] When forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 302, a layer containing tungsten is formed, and an insulating layer formed of an oxide is formed on the upper layer thereof, so that a layer containing an oxide of tungsten is formed at the interface between the layer containing tungsten and the insulating layer, which may be utilized.

[0144] In addition, when forming a transistor on a production substrate by forming a release layer, the release layer is also heated by heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer, and when peeling from the production substrate to the support substrate in a later process, peeling at the release layer interface becomes easy.

[0145] In addition, the surface of the layer containing tungsten may be treated by heat oxidation treatment, oxygen plasma treatment, treatment with a solution having a strong oxidizing power such as ozone water, etc. to form a layer containing an oxide of tungsten. Also, plasma treatment and heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas atmosphere of the gas and other gases. This is the same when forming a layer containing a nitride, oxynitride, and nitroxide of tungsten. When forming a layer containing tungsten, ​​​​​​​​​​Then, a silicon nitride layer, a silicon oxide nitride layer, and a silicon nitride oxide layer are formed on top of it. good.

[0146] A peelable layer 304 is formed on the peelable layer 302 (see Figure 4(A)). The peelable layer 304 is It has a first insulating layer 301 and a transistor 410.

[0147] First, a first insulating layer 301 is formed on the release layer 302. The first insulating layer 301 is nitrogen Insulating films containing nitrogen and silicon, such as silicon oxide, silicon oxide, and silicon nitride, are used. It is preferable to form it in layers or multiple layers.

[0148] The first insulating layer 301 is applied using sputtering, plasma CVD, coating, printing, etc. It is possible to form it by, for example, by plasma CVD at a deposition temperature of 250°C~ By forming it at 400°C, a dense film with very low water permeability can be created. The thickness of the first insulating layer 301 is 10 nm or more and 1000 nm or less, and more specifically, 100 nm or more. A wavelength of 700 nm or less is preferred.

[0149] By providing the first insulating layer 301, peeling occurs at the interface with the peeling layer 302 during the subsequent peeling process. This makes separation easier. Furthermore, it prevents cracks and damage to semiconductor elements and wiring during the subsequent delamination process. This can prevent this from happening. Also, the first insulating layer 301 functions as a protective layer for the semiconductor device. ru.

[0150] A transistor 410 is formed on the first insulating layer 301, and a peelable layer 304 is formed. Since the abscission layer 304 can be formed by applying the method described in Embodiment 1, a detailed explanation is not provided here. Omit the character for "bright".

[0151] In this embodiment, an example is shown in which a laminated structure is formed with a protective insulating layer 409 on top of the insulating layer 407. In this embodiment, the protective insulating layer 409 is made of the substrate 400 formed up to the insulating layer 407. The mixture is heated to a temperature of 100°C to 400°C and then heated to a spatula containing high-purity nitrogen from which hydrogen and water have been removed. A silicon nitride film is deposited using a silicon semiconductor target after introducing a tatta gas (Figure 4). (See (A).) In this case as well, similar to the insulating layer 407, the residual moisture in the processing chamber is removed. It is preferable to form a protective insulating layer 409 while removing the harmful substances.

[0152] Furthermore, to reduce surface irregularities caused by the transistor on transistor 410, planar insulation is used. A film may be formed. Examples of planarizing insulating films include polyimide, acrylic, and benzocyclobuterol. Organic materials such as n can be used. In addition to the above organic materials, low dielectric constant materials (lo Materials such as wk material can be used. Furthermore, multiple insulating films formed from these materials can be stacked. A planar insulating film may be formed by layering.

[0153] Next, using the removable adhesive layer 305, the second fabricated substrate 306 is temporarily removed from the peelable layer 30 4 is bonded to it. By bonding the second fabricated substrate 306 to the peel-off layer 304, The layer to be peeled 304 can be easily peeled off from the peeling layer 302. Furthermore, the layer to be peeled off can be easily peeled off through the peeling process. The stress applied to 304 is relieved, protecting the transistor. Additionally, a removable adhesive layer 3 Since 05 is used, the second fabricated substrate 306 can be easily removed when it becomes unnecessary. .

[0154] Examples of removable adhesive layers 305 include water-soluble resins. The applied water-soluble resin smooths out the unevenness of the peel-off layer 304 and facilitates bonding with the second fabricated substrate 306. To facilitate removal. Also, as a removable adhesive layer 305, a resin that can be peeled off by light or heat is used. A product in which the adhesive is laminated onto a water-soluble resin may also be used.

[0155] Next, the peelable layer 304 is peeled off from the first fabricated substrate 300 (see Figure 4(B)). Various methods can be used.

[0156] For example, if a metal oxide film is formed as the release layer 302 on the side in contact with the first insulating layer 301. In this process, the metal oxide film is weakened by crystallization, and the peelable layer 304 is made into the first fabricated substrate 30 It can be peeled off from zero. Furthermore, after weakening the metal oxide film by crystallization, A portion of the release layer 302 is removed by a solution or a halogenated fluoride gas such as NF3, BrF3, or ClF3. It may be removed by etching, and the weakened metal oxide film may be peeled off.

[0157] Furthermore, the release layer 302 may be a film containing nitrogen, oxygen, hydrogen, etc. (for example, an amorphous silica containing hydrogen) Using a transparent film (such as a condensate film, hydrogen-containing alloy film, or oxygen-containing alloy film), the first fabricated substrate 300 is made transparent. When a photosensitive substrate is used, laser light is applied to the release layer 302 from the first fabricated substrate 300. By irradiating the first fabricated substrate 300, the nitrogen, oxygen, and hydrogen contained in the exfoliation layer are vaporized. A method of peeling between the peeling layer 302 can be used.

[0158] Furthermore, by removing the peeling layer 302 by etching, the peeled layer 304 is removed from the first fabricated substrate. It's okay to peel it off from 300.

[0159] Furthermore, a method for mechanically polishing and removing the first fabricated substrate 300, or the first fabricated substrate 300 Removed by etching with halogen fluoride gases such as NF3, BrF3, ClF3, or HF. Methods such as the following can be used. In this case, it is not necessary to use the peeling layer 302.

[0160] In addition, laser irradiation, etching with gas or solution, or sharp knives or scalpels are used. Using this, a groove is formed to expose the release layer 302, and the release layer 302 and retaining At the interface of the first insulating layer 301, which functions as a protective layer, the peelable layer 304 is on the first fabricated substrate. It can also be peeled off from 300.

[0161] Methods of removal include, for example, applying mechanical force (such as pulling it off with human hands or gripping tools). This can be done using methods such as a sieve or a process that separates the material while rotating rollers. Also, liquid can be placed in the groove. The liquid is dropped onto the interface between the release layer 302 and the first insulating layer 301, allowing the liquid to penetrate the release layer 302. The peeled layer 304 may be peeled off from it. Alternatively, fluorine such as NF3, BrF3, or ClF3 may be applied to the groove. A fluorine gas is introduced, and the peeling layer 302 is etched and removed with the fluorine gas to obtain an insulating surface. A method for peeling the peelable layer 304 from the first fabricated substrate 300 may also be used. You can also peel it off while applying a liquid such as water during the process.

[0162] Other peeling methods include, if the peeling layer 302 is formed of tungsten, ammonia The peeling layer can be removed while etching it using a mixed solution of water and hydrogen peroxide. .

[0163] Next, the substrate 400 is bonded to the peelable layer 304 using the resin layer 307 (see Figure 4(C)). . ) .

[0164] As the substrate 400, a flexible substrate as shown in Embodiment 1 can be used. Cut.

[0165] The resin layer 307 can be a light-curing adhesive such as an ultraviolet-curing adhesive, a reaction-curing adhesive, Various types of curing adhesives can be used, such as thermosetting adhesives or anaerobic adhesives. These adhesives are made from materials such as epoxy resin, acrylic resin, silicone resin, and phenolic resin. Fat and other substances can be used.

[0166] Furthermore, if a prepreg is used as the substrate 400, the peelable layer 30 is directly applied without using an adhesive. 4 and the substrate 400 are pressed together and bonded. At this time, the organic resin of the structure is, These are materials that harden through additional treatments such as responsive curing, thermosetting, and UV curing. It would be good to use this.

[0167] After setting the substrate 400, the second fabricated substrate 306 and the removable adhesive layer 305 are removed. Expose transistor 410 (see Figure 4(D)).

[0168] Through the above process, the transistor 410 is formed on the substrate 400 using the transposition process. It is possible.

[0169] In this embodiment, a method in which the transistor is provided in the peelable layer is illustrated, but the present invention The inventions disclosed in this document are not limited to these, and include other display elements (for example, light-emitting elements). (e.g.) Peeling and repositioning may be performed.

[0170] According to this embodiment, a transistor made using a heat-resistant substrate is made thin and It can be transferred to a lightweight, flexible substrate. Therefore, it is not limited by the heat resistance of the substrate and can be flexible. A semiconductor device can be formed.

[0171] This embodiment can be implemented in appropriate combination with other embodiments.

[0172] (Embodiment 5) A semiconductor device having a display function using a transistor as an example shown in Embodiments 1 to 4. A display device (also called a display device) can be manufactured. Examples of transistors shown in Embodiments 1 to 4 Transistors are more effective when used in the drive circuit. Part or all of the pixel portion is integrally formed on the same substrate as the pixel portion to form a system-on-panel. It is possible.

[0173] In Figures 6(A) and 6(B), the pixel section 4002 provided on the first substrate 4001 and scanning A sealing material 4005 is provided so as to surround the line drive circuit 4004. A second substrate 4006 is provided on part 4002 and the scan line drive circuit 4004. The pixel section 4002 and the scan line driving circuit 4004 are connected to the first substrate 4001 and the sealing material 4 The display element is sealed together with 005 and the second substrate 4006. Figure 6(A) In B), the region surrounded by the sealing material 4005 on the first substrate 4001 and These are formed in different regions on a separately prepared substrate using a single-crystal semiconductor film or a polycrystalline semiconductor film. A signal line drive circuit 4003 is implemented. In Figures 6(A) and 6(B), separately formed The signal line drive circuit 4003 and the scan line drive circuit 4004 or the pixel unit 4002 are supplied The various signals and potentials are supplied from the FPC4018.

[0174] Furthermore, in Figures 6(A) and 6(B), a signal line drive circuit 4003 is formed separately, and the first substrate 4 An example of implementation in 001 is shown, but the configuration is not limited to this. The scan line drive circuit is separate. You can either create a separate circuit and implement it, or use only a part of the signal line drive circuit or a part of the scan line drive circuit. It may also be formed and implemented separately.

[0175] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG(Ch ip On Glass) method, wire bonding method, or TAB (Tape A Methods such as utmost bonding can be used. Figure 6(A) shows C This is an example of implementing the signal line drive circuit 4003 using the OG method, while Figure 6(B) shows the TAB method. This is an example of implementing the signal line drive circuit 4003.

[0176] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. Includes modules with ICs and other components mounted on them.

[0177] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC or TAB tape. A module with TCP attached, a TAB tape, or a printed circuit board at the end of the TCP. An IC (integrated circuit) is directly mounted to the provided module or display element using the COG method. All modules that have been modified shall also be included in the display device.

[0178] Furthermore, the pixel section and scanning line driving circuit provided on the first substrate have multiple transistors. Examples of transistors in the scan line drive circuit 4004 are shown in Embodiments 1 to 4. A transistor can be applied.

[0179] Display elements provided in a display device include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements ( A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electroluminescent) elements. This includes Luminescence, organic EL, etc. It also includes electronic inks and other electrically powered materials. Display media where the contrast changes depending on the application can also be used.

[0180] One form of a semiconductor device will be explained using Figures 7 to 9. Figures 7 to 9 are the same as Figure 6(A). This corresponds to a cross-sectional view in MN.

[0181] As shown in Figures 7 to 9, the semiconductor device has a connecting terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrodes 4015 and 4016 are connected to the terminals of FPC4018. They are electrically connected via an anisotropic conductive film 4019.

[0182] The connecting terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030, and the terminal electrode 4 016 is the same conductive material as the source electrode layer and drain electrode layer of transistors 4010 and 4011. It is formed of an electrochemical film.

[0183] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple transistors, and in Figures 7 to 9, the transistors included in the pixel section 4002 The example shows transistor 4010 and transistor 4011 included in the scan line drive circuit 4004. In Figure 7, an insulating layer 4020 is provided on transistors 4010 and 4011, and in Figure 8 Furthermore, in Figure 9, an insulating layer 4021 is provided. Note that the insulating film 4023 is the underlayer. It is an insulating film that functions as such.

[0184] In this embodiment, the transistor 4011 of the scan line drive circuit 4004 is, The transistor shown as an example in 1 is being applied. Transistor 4011 is an oxide semiconductor layer In the channel width direction, the channel formation region consists of the upper and lower gate insulating layer, gate electrode layer, and insulating layer. It is a structure surrounded by layers and conductive layers. In drive circuits, to allow more current to flow It is preferable to provide a long channel width for the transistor. Therefore, Embodiments 1 to 4 A transistor with bending resistance in the channel width direction as shown above has shock resistance. This allows for the creation of highly reliable semiconductor devices.

[0185] The transistor 4010 provided in the pixel section 4002 is electrically connected to the display element, and the display The panel is constructed using various display elements, as long as they can display information. It can be used.

[0186] Figure 7 shows an example of a liquid crystal display device using liquid crystal elements as display elements. In Figure 7, the display elements The liquid crystal element 4013 comprises a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer Includes 4008. Furthermore, insulating film 4 functions as an alignment film, sandwiching the liquid crystal layer 4008. Layers 032 and 4033 are provided. The second electrode layer 4031 is provided on the second substrate 4006 side. The first electrode layer 4030 and the second electrode layer 4031 are stacked via the liquid crystal layer 4008. It is structured in this way.

[0187] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. You may use a pacer.

[0188] When using a liquid crystal element as the device element, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on conditions. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when heating cholesteric liquid crystal, it is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only within a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated due to the influence of static electricity and deviate from the design range. Therefore, using a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer is more effective. shown.

[0189] Moreover, the intrinsic resistance of the liquid crystal material is 1×10 Ω·cm or more, preferably 1×10 Ω·cm or more, and more preferably 1×10 Ω·cm or more. When using a liquid crystal element as the device element, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on conditions. Moreover, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when heating cholesteric liquid crystal, it is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only within a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated due to the influence of static electricity and deviate from the design range. Therefore, using a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer is more effective. Moreover, the intrinsic resistance of the liquid crystal material is 1×10 Ω·cm or more, preferably 1×10 Ω·cm or more, and more preferably 1×10 Ω·cm or more. When using a liquid crystal element as the device element, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on conditions. Moreover, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when heating cholesteric liquid crystal, it is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only within a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated due to the influence of static electricity and deviate from the design range. Therefore, using a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer is more effective.

[0190] Ω·cm or more, preferably 1×10 9 Ω·cm or more, and more preferably 1×10 11 Ω·cm or more. 12It is greater than Ω·cm. Furthermore, this specification... The resistivity values ​​in this document shall be those measured at 20°C.

[0191] The size of the retention capacitance provided in a liquid crystal display device depends on the regeneration of the transistors arranged in the pixel area. The system is set to hold the charge for a predetermined period of time, taking into account the current and other factors. The size should be set considering the transistor's off-current, etc. High-purity oxide semiconductor layer By using a transistor having this property, the liquid crystal capacitance in each pixel can be reduced to 1 / 3 or less. Preferably, it is sufficient to provide a holding capacity with a size of 1 / 5 or less of the capacity.

[0192] LCD displays include TN (Twisted Nematic) mode and IPS (In-Place Printed Display). lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0193] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes are possible, For example, MVA (Multi-Domain Vertical Alignment) Mode, PVA (Patterned Vertical Alignment) mode ASV mode and other modes can be used. Furthermore, it can also be applied to VA-type liquid crystal display devices. This is possible. A VA-type liquid crystal display device is a device that controls the arrangement of liquid crystal molecules in a liquid crystal display panel. It is a type of formula. VA-type liquid crystal display devices have a voltage applied to the panel surface when no voltage is applied. This is a method in which the liquid crystal molecules are oriented vertically. Also, pixels are divided into several regions ( The multi-domain is designed to divide the molecules into subpixels and tilt each subpixel in a different direction. Methods known as genization or multi-domain design can be used.

[0194] Furthermore, in a display device, the black matrix (light-shielding layer), polarizing member, phase difference member, and reflector are used. Optical components (optical substrates) such as protective members are provided as appropriate. For example, polarizing substrates and phase difference substrates Circularly polarized light from a plate may be used. Also, backlights, sidelights, etc., may be used as light sources. It's okay to be there.

[0195] Furthermore, the display method used in the pixel area may be a progressive or interlaced method. It is possible. Also, when displaying in color, the color elements controlled by pixels are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (where W represents white). Alternatively, some models use RGB with one or more additional colors such as yellow, cyan, or magenta. The size of the display area for each dot of the color element may differ. However, the present invention is color - Not limited to display devices, it can also be applied to monochrome display devices. can.

[0196] Furthermore, as a display element included in the display device, an electroluminescent light-emitting element is used. It can be applied to light-emitting devices that utilize electroluminescence. They are distinguished by whether they are organic or inorganic compounds, and generally the former are organic E The latter is called an L element, and the latter an inorganic EL element.

[0197] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0198] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transitions of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0199] A light-emitting element only needs to have at least one of its pair of electrodes transparent in order to extract light. Then, a transistor and a light-emitting element are formed on the substrate, and light is extracted from the side opposite to the substrate. Top-side emission, bottom-side emission which extracts light from the substrate side, and the substrate side and the side opposite the substrate. There is a light-emitting element with a double-sided emission structure that extracts light from it, and any light-emitting element with an emission structure is applicable. It is possible.

[0200] Figure 8 shows an example of a light-emitting device using a light-emitting element as a display element. The light-emitting element 4 is the display element. 513 is electrically connected to transistor 4010 located in pixel section 4002. The configuration of the light-emitting element 4513 is a first electrode layer 4030, an electroluminescent layer 4511, and a second electric The stacked structure of the polar layer 4031 is shown, but is not limited to the configuration shown. The configuration of the light-emitting element 4513 can be appropriately changed to match the direction of the emitted light.

[0201] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. Using the material, an opening is formed on the first electrode layer 4030, and the side wall of the opening is a continuous curve It is preferable to form the surface in a way that creates an inclined surface with a certain ratio.

[0202] Even if the electroluminescent layer 4511 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0203] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4513, the second electrode layer A protective film may be formed on 4031 and the partition wall 4510. The protective film may be silicon nitride. Films, silicon nitride films, DLC films, etc. can be formed. Also, the first substrate 400 1. The space sealed by the second substrate 4006 and the sealing material 4005 is filled with a filler material 45 14 is provided and sealed. In this way, it is highly airtight and does not expose to the outside air, and gas removal Protective films with minimal defects (laminated films, UV-curing resin films, etc.) and cover materials It is preferable to package (enclose) them in this way.

[0204] In addition to inert gases such as nitrogen and argon, filler material 4514 can also be UV-curing resin. Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, and poly Mid, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (E Tylene vinyl acetate can be used. For example, nitrogen can be used as a filler. stomach.

[0205] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0206] Furthermore, it is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and it is a paper-like material. It offers the same readability, lower power consumption compared to other display devices, and a thin and light form factor. It has the advantage of being such.

[0207] Electrophoresis display devices can take various forms, but one is a first particle with a positive charge and Multiple microcapsules containing a second particle having a negative charge are in the solvent or solute. It is a dispersed substance, and by applying an electric field to the microcapsules, the microcapsules Move the particles in the cell in opposite directions and display only the color of the particles that have gathered on one side. Furthermore, the first or second particle contains dye and moves in the absence of an electric field. It is immovable. Also, the color of the first particle and the color of the second particle are different (including colorless). )

[0208] Thus, electrophoretic devices can detect the movement of substances with high dielectric constants into high electric field regions. This display utilizes a mild dielectrophoretic effect.

[0209] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0210] Furthermore, the first and second particles in the microcapsules are made of conductive material, insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A type of material selected from trochromic materials, magnetophoretic materials, or a composite material thereof Use it.

[0211] Furthermore, a display device using the twist ball display method can also be applied as electronic paper. Yes, it is possible. The twist ball display method uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, which are electrode layers, and the first electrode layer and the second This method of displaying information involves controlling the orientation of spherical particles by creating a potential difference in the electrode layer. be.

[0212] Figure 9 shows an active-matrix electronic paper as one form of semiconductor device. Figure 9 This electronic paper is an example of a display device that uses a twist-ball display method.

[0213] A first electrode layer 4030 connected to transistor 4010, and provided on the second substrate 4006 Between the second electrode layer 4031 and the first electrode layer 4031, there is a black region 4615a and a white region 4615b. A spherical particle 4613 is provided, which includes a cavity 4612 filled with liquid around it. The spherical particles 4613 are surrounded by a filler material 4614 such as resin. Second electrode Layer 4031 corresponds to the common electrode (counter electrode). The second electrode layer 4031 has a common potential line and It is electrically connected.

[0214] In Figures 7 to 9, the first substrate 4001 and the second substrate 4006 are flexible. A substrate with certain properties can be used, for example, a light-transmitting plastic substrate. It is possible. As for plastics, FRP (Fiberglass Reinforced Plastic) is used. RCED Plastics) sheets, PVF (polyvinyl fluoride) film, polyethylene A sterling film or acrylic resin film can be used. Also, aluminum... It is also possible to use a sheet with a structure in which foil is sandwiched between PVF film or polyester film. Cut.

[0215] The insulating layer 4020 functions as a protective film for the transistor.

[0216] Furthermore, the protective film prevents the intrusion of contaminants such as organic matter, metallic substances, and water vapor suspended in the atmosphere. This is for protection, and a dense film is preferred. The protective film is made using the sputtering method, with silica oxide Silicon film, silicon nitride film, silicon oxide nitride film, silicon oxide nitride film, aluminum oxide film , a single layer of aluminum nitride film, aluminum oxide nitride film, or aluminum nitride oxide film, Alternatively, it can be formed by lamination.

[0217] Furthermore, the insulating layer 4021, which functions as a planar insulating film, is made of acrylic, polyimide, and benzosine. Heat-resistant organic materials such as clobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low-dielectric materials (low-k materials), siloxane resins, and PS are also used. G (phosphorus glass), BPSG (phosphorus boron glass), etc. can be used. An insulating layer may be formed by stacking multiple insulating films made of these materials.

[0218] The method for forming insulating layers 4020 and 4021 is not particularly limited, and depends on the material, spa Droplet method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet) (Printing methods, screen printing, offset printing, etc.), doctor knife, roll coater, curtain A tumble coater, knife coater, etc., can be used.

[0219] A display device displays images by transmitting light from a light source or display element. Therefore, the pixels through which light is transmitted. The thin films provided in the section, such as substrates, insulating films, and conductive films, are all sensitive to light in the visible light wavelength range. It should be translucent.

[0220] A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer, pair) that apply voltage to the display element. In the electrode layer (also called the direct electrode layer), the direction of the light to be extracted, the location where the electrode layer is provided, and Transmittance and reflectivity can be selected based on the pattern structure of the electrode layer.

[0221] The first electrode layer 4030 and the second electrode layer 4031 are made of indium acid containing tungsten oxide. Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO). ), indium zinc oxide, indium tin oxide with added silicon dioxide, etc. A conductive material can be used.

[0222] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N) b) Tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), Alternatively, it can be formed using one or more types of the alloy or metal nitride thereof. Cut.

[0223] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of conductive polymer (conductive polymer It can be formed using a conductive composition containing (also called mer). For example, so-called π-electron conjugated conductive polymers can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, Alternatively, a copolymer or derivative thereof consisting of two or more of aniline, pyrrole, and thiophene. Examples include the body, etc.

[0224] Furthermore, transistors are susceptible to damage from static electricity, etc., therefore, a protection circuit for the drive circuit is necessary. It is preferable to provide this. The protection circuit is preferably constructed using nonlinear elements.

[0225] As described above, by applying the transistors shown in Embodiments 1 to 4, various functions can be achieved. A display device can be provided.

[0226] This embodiment can be implemented in appropriate combination with other embodiments.

[0227] (Embodiment 6) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Cameras such as LA, digital photo frames, and mobile phones (also called mobile phones or mobile phone devices). ), portable game consoles, personal digital assistants, sound playback devices, large game machines such as pachinko machines, etc. These are some examples.

[0228] Figures 10(A) and 10(B) show a flexible semiconductor device formed by applying the above embodiment. This is an example of applying it to an e-book. Figure 10(A) shows the e-book in an open state. 10(B) shows the e-book in the closed state. The first display panel 4311, the second display panel Flexible material formed by applying the above embodiment to the flannel 4312 and the third display panel 4313 A semiconductor device having the following characteristics can be used.

[0229] The first housing 4305 has a first display panel 4311 having a first display unit 4301, The second housing 4306 has an operating section 4304 and a second display panel 4307. The third display panel 4313, which has a 4312 and is a double-sided display panel, has a third display section It has 4302 and a fourth display unit 4310, and the third display panel 4313 is the first display unit It is inserted between the panel 4311 and the second display panel 4312. The first housing 4305, The first display panel 4311, the third display panel 4313, the second display panel 4312, and The second housing 4306 is connected by a binding section 4308 in which a drive circuit is provided inside. The electronic book in Figure 10 has a first display unit 4301, a second display unit 4307, and a third display unit. It has four display screens, including section 4302 and the fourth display section 4310.

[0230] First enclosure 4305, first display panel 4311, third display panel 4313, second display The display panel 4312 and the second housing 4306 are flexible and have flexibility. It is expensive. Also, plastic substrates are used for the first housing 4305 and the second housing 4306, and the third By using a thin film on the display panel 4313, a thin e-book can be created. .

[0231] The third display panel 4313 has both a third display section 4302 and a fourth display section 4310. It is a surface display type panel. The third display panel 4313 uses a double-sided injection type display panel. Alternatively, you can use a combination of single-sided injection-molded display panels.

[0232] Figure 11 shows a semiconductor device formed by applying the above embodiment, connected to an indoor lighting device 3001 This is an example of its use. The semiconductor device shown in the above embodiment can also be made to have a large area. It can be used as a large-area lighting device. The unit can also be used as a table lamp 3000. Note that the lamp is ceiling-mounted. In addition to standard lighting fixtures and desk lamps, we also offer wall-mounted lighting fixtures, vehicle interior lighting, and emergency lights. This is also included.

[0233] As described above, the semiconductor devices shown in Embodiments 1 to 5 are suitable for various electronic devices as described above. It can be arranged in a way that provides highly reliable electronic equipment.

Claims

1. A display device having a pixel section and a scanning line driving circuit on a substrate, The scan line driving circuit comprises a first transistor having a first semiconductor layer and a second transistor having a second semiconductor layer. The channel width direction of the first transistor is the same as the channel width direction of the second transistor. The first conductive layer having a region that functions as one of the source electrode and drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region that functions as one of the source electrode and drain electrode of the second transistor, The second conductive layer having a region that functions as the first gate electrode layer of the first transistor extends in the channel width direction of the first transistor and has a region that functions as the first gate electrode layer of the second transistor, The third conductive layer, having a region that functions as the second gate electrode layer of the first transistor, extends in the channel width direction of the first transistor and has a region that functions as the second gate electrode layer of the second transistor. In the channel width direction of the first transistor, each of the ends of the first semiconductor layer and each of the ends of the second semiconductor layer has a portion that overlaps with the second conductive layer. In the channel width direction of the first transistor, each of the ends of the first semiconductor layer and each of the ends of the second semiconductor layer has a portion that overlaps with the third conductive layer. A display device in which, in each of the first transistor and the second transistor, the channel width is greater than the channel length.

2. A display device having a pixel section and a scanning line driving circuit on a substrate, The scan line driving circuit comprises a first transistor having a first semiconductor layer and a second transistor having a second semiconductor layer. The channel width direction of the first transistor is the same as the channel width direction of the second transistor. The first conductive layer having a region that functions as one of the source electrode and drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region that functions as one of the source electrode and drain electrode of the second transistor, The second conductive layer having a region that functions as the first gate electrode layer of the first transistor extends in the channel width direction of the first transistor and has a region that functions as the first gate electrode layer of the second transistor, The third conductive layer, having a region that functions as the second gate electrode layer of the first transistor, extends in the channel width direction of the first transistor and has a region that functions as the second gate electrode layer of the second transistor. The fourth conductive layer, having a region that functions as the other of the source electrode and drain electrode of the first transistor, extends in the channel width direction of the first transistor and has a region that functions as the other of the source electrode and drain electrode of the second transistor, In the channel width direction of the first transistor, each of the ends of the first semiconductor layer and each of the ends of the second semiconductor layer has a portion that overlaps with the second conductive layer. In the channel width direction of the first transistor, each of the ends of the first semiconductor layer and each of the ends of the second semiconductor layer has a portion that overlaps with the third conductive layer. A display device in which, in each of the first transistor and the second transistor, the channel width is greater than the channel length.

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