Semiconductor and display devices

Abstract

To provide a semiconductor device which suppresses a malfunction in a shift register circuit.SOLUTION: A semiconductor device includes a shift register consisting of a plurality of flip flop circuits. The flip flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. The transistor 13 or the transistor 14 is turned on in a non-selection period and potential of a node A is set, so that the node A is prevented from a floating state.SELECTED DRAWING: Figure 24

Description

Technical Field

[0001] It relates to a drive circuit. It also relates to a display device having the drive circuit. It also relates to an electronic device having the display device in a display unit.

Background Art

[0002] In recent years, display devices such as liquid crystal display devices and light-emitting devices have been actively developed due to the increase in large display devices such as liquid crystal televisions. In particular, a technology for integrally forming a pixel circuit and a drive circuit (also referred to as an internal circuit) including a shift register and the like, which is composed of transistors having a semiconductor layer provided on an insulating substrate, on the same substrate, greatly contributes to power consumption reduction and cost reduction, and thus is actively developed. The internal circuit formed on the insulating substrate is connected to an external circuit including a controller IC or the like disposed outside the insulating substrate via FPC or the like, and its operation is controlled. <000"073>

[0003] <000007​​​​​​​​​​​​​​​​​​​​​​​​​​​​At the timing of the switching operation, a deviation from the desired timing occurs, resulting in a malfunction. There is a problem such that a deviation occurs in the timing of the switching operation of the transistor. As a cause of the deviation in the timing of the switching operation of the transistor, for example, in the flip-flop circuit of the shift register during the non-selection period, the gate terminal of the pull-up transistor becomes floating, and noise generated during the non-selection period affects the potential of the gate terminal of the pull-up transistor.

[0006] Also, the deterioration of the transistor itself is regarded as one of the causes of the deviation in the timing of the switching operation. When the transistor deteriorates, the value of the threshold voltage of the transistor changes, causing a malfunction in the drive circuit. When a transistor with an amorphous semiconductor as the semiconductor layer is applied as the transistor, the transistor with an amorphous semiconductor as the semiconductor layer is prone to deterioration, and thus malfunctions are particularly likely to occur.

[0007] In one aspect of the present invention, in a circuit using a shift register, suppressing malfunctions is one of the problems.

Means for Solving the Problems

[0008] One aspect of the present invention has a shift register including a plurality of flip-flop circuits, and at least one of the plurality of flip-flop circuits is a flip-flop circuit to which a first signal, a second signal, and a third signal are input and outputs an output signal. At least one of the plurality of flip-flop circuits has a gate terminal, a source terminal, and a drain terminal, and the gate terminal is given a first potential which is the potential of the first signal, and one of the source terminal and the drain terminal is given the first potential or the second potential, and a first transistor, and a gate terminal, a source end ​ It has a drain terminal and a gate terminal to which a third potential, which is the potential of the second signal, is applied. Therefore, one of the source terminal and drain terminal is the source terminal and drain terminal of the first transistor. It is electrically connected to the other terminal, and a fourth potential is applied to the other terminals of the source and drain terminals. A second transistor, one of which is the source terminal and the other the drain terminal of the first transistor. Controls whether the other potential is set to the first potential or the fourth potential, and if the other is the first Whether or not to set the potential of the other terminal of the source and drain terminals of the transistor to a fourth potential. Controlled so that when one is on, the other is off, and when the other is on, the other... The third and fourth transistors, which are in the OFF state, and the gate terminal and source terminal. It has a drain terminal, and the gate terminal is the source terminal and drain terminal of the first transistor. It is electrically connected to the other terminal, and the potential of the third signal is connected to one of the source terminal and drain terminal. A fifth potential is given, and the potential of the other terminal of the source terminal and drain terminal is the potential of the output signal. This occurs when the third or fourth transistor is ON and OFF. This is a drive circuit having a fifth transistor.

[0009] One aspect of the present invention has a shift register comprising a plurality of flip-flop circuits, The flop-flop circuit receives a first control signal, a second control signal, a first clock signal, and a second... A flip-flop circuit that takes a clock signal as input and outputs an output signal. The ROP circuit has a gate terminal, a source terminal, and a drain terminal, and the gate terminal has a first A first potential, which is the potential of the control signal, is applied, and the first potential is applied to one of the source terminal and the drain terminal. A first transistor to which a potential of or a second potential is applied, and the gate terminal, source terminal, It has a drain terminal and a third potential, which is the potential of the second control signal, is applied to the gate terminal. Therefore, one of the source terminal and drain terminal is the source terminal and drain terminal of the first transistor. It is electrically connected to the other terminal, and a fourth potential is applied to the other terminals of the source and drain terminals. A second transistor is provided, each having a gate terminal, a source terminal, and a drain terminal. This is a transistor, and one of the source terminals and drain terminals of each transistor The source terminal and the other drain terminal of the first transistor are electrically connected, and one of them A first potential or a fourth potential is applied to the source terminal and the other of the drain terminal of the transistor. Then, a fourth potential is applied to the source terminal and the other drain terminal of the other transistor. When one transistor is ON, the other transistor is OFF, and the other A third transistor where one transistor is in the off state when the other transistors are in the on state. It has a fourth transistor and a gate terminal, a source terminal, and a drain terminal, and The T terminal is electrically connected to the source terminal and the other of the drain terminal of the first transistor. A fifth potential, which is the potential of the first clock signal, is applied to either the source terminal or the drain terminal. The potential of the source terminal and the other drain terminal becomes the potential of the output signal, and the third transistor The fifth transistor is in the off state when the zista or fourth transistor is in the on state. It has a gate terminal, a source terminal, and a drain terminal, and the gate terminal is a third transistor Electrically connected to the other gate terminal of the fourth transistor, and the source terminal and DRE One of the input terminals is electrically connected to the source terminal and the other to the drain terminal of the fifth transistor. A sixth transistor is connected, and a fourth potential is applied to the other of the source and drain terminals. It has a gate terminal, a source terminal, and a drain terminal, and a second clock is connected to the gate terminal. A sixth potential, which is the potential of the signal, is applied, and one of the source terminal and drain terminal is at the fifth potential. It is electrically connected to the source terminal and the other drain terminal of the transistor, and the source terminal and drain A drive circuit having a seventh transistor to which a fourth potential is applied to the other terminal of the rain terminal. be.

[0010] In one embodiment of the present invention, the flip-flop circuit has at least two terminals. A fifth potential is applied to one terminal, and the other terminal is connected to the third transistor and the fourth transistor. A first capacitive element electrically connected to the other gate terminal of the inverter, and the gate terminal, saw It has a drain terminal and a gate terminal, and the gate terminal is connected to the gate terminal of the fifth transistor. They are connected in a specific way, with one of the source and drain terminals being connected to the third transistor and the fourth transistor. It is electrically connected to the other gate terminal of the inverter, and to the other side of the source terminal and drain terminal. An eighth transistor to which a fourth potential is applied, and having at least two terminals, one end A sixth potential is applied to the child, and the other terminals are connected to the third and fourth transistors. A second capacitive element electrically connected to one of the gate terminals, and the gate terminal, source terminal, and It has a drain terminal and its gate terminal is electrically connected to the gate terminal of the first transistor. And, one of the source terminals and drain terminals is connected to the third transistor and the fourth transistor. It is electrically connected to one gate terminal and to the other of the source and drain terminals, providing a fourth potential. A configuration can also be made that includes a ninth transistor, which is given by [a certain value].

[0011] Furthermore, in one embodiment of the present invention, the flip-flop circuit has at least two terminals A fifth potential is applied to one terminal, and the other terminal is connected to the third transistor and the fourth transistor. A first capacitive element electrically connected to the other gate terminal of the inverter, and the gate terminal, saw It has a drain terminal and a gate terminal, and the gate terminal is connected to the gate terminal of the fifth transistor. They are connected in a specific way, with one of the source and drain terminals being connected to the third transistor and the fourth transistor. It is electrically connected to the other gate terminal of the inverter, and to the other side of the source terminal and drain terminal. The configuration may also include an eighth transistor to which a fourth potential is applied.

[0012] Furthermore, in one embodiment of the present invention, the flip-flop circuit has a gate terminal, a source terminal, and It has a drain terminal, a first potential is applied to the gate terminal, and the source terminal and drain terminal One of the child's components is electrically connected to the gate terminals of the third transistor and the other of the fourth transistor. A 10th transistor is connected, and a fourth potential is applied to the other of the source and drain terminals. It is also possible to have a configuration that includes a sta.

[0013] Furthermore, in one embodiment of the present invention, the flip-flop circuit outputs a second output signal. The flip-flop circuit has a gate terminal, a source terminal, and a drain terminal. The gate terminal is electrically connected to either the source terminal or the drain terminal of the first transistor. Then, a fifth potential is applied to one of the source terminal and the drain terminal, and the source terminal and the drain An eleventh transistor whose other terminal potential becomes the potential of the second output signal, and the gate terminal It has a source terminal and a drain terminal, and the gate terminal is connected to the third transistor and the fourth transistor. It is electrically connected to the other gate terminal of the transistor, and to one of the source terminals and drain terminals. The source terminal and the other of the drain terminal of the 11th transistor are electrically connected, A 12th transistor to which a fourth potential is applied to the other terminal of the gate and drain terminal, and It has a gate terminal, a source terminal, and a drain terminal, and the gate terminal is the gate of the seventh transistor. The terminal is electrically connected to the 11th transistor, with either the source terminal or the drain terminal being connected to the 11th transistor. It is electrically connected to the other of the source terminal and drain terminal, and the source terminal and drain terminal The other side of the configuration may also include a 13th transistor to which a fourth potential is applied. ru.

[0014] Furthermore, in one embodiment of the present invention, the first control signal and the second control signal are used as digital signals. The absolute value of the potential difference between the high and low states of the digital signal is measured within the flip-flop circuit. It can also be made larger than the absolute value of the transistor's threshold voltage.

[0015] Furthermore, in one embodiment of the present invention, the fourth potential is controlled by the first control signal or the second control signal. , or the high or low state of the first clock signal or the second clock signal It can also be treated as a value equivalent to the rank.

[0016] Furthermore, in one embodiment of the present invention, the phase of the first clock signal and the second clock signal is Assuming an inverse relationship, the high and low states of the first and second clock signals are... Make the absolute value of the position difference greater than the absolute value of the threshold voltage of the transistor in the flip-flop circuit. It is also possible to do so.

[0017] Furthermore, in one embodiment of the present invention, all transistors in the flip-flop circuit are the same It can also be configured as a single conductive type.

[0018] Furthermore, in one embodiment of the present invention, the transistor in the flip-flop circuit is a gate electric A pole, a gate insulating film provided to cover the gate electrode, and the gate insulating film sandwiched between the gates A first semiconductor layer including a microcrystalline semiconductor layer provided on an electrode, and provided on the first semiconductor layer A buffer layer and a pair of second semiconductor layers provided on the buffer layer and containing impurity elements. , a source electrode provided on one of a pair of second semiconductor layers, and a pair of second semiconductor layers It is also possible to have a structure that includes a drain electrode provided on the other side.

[0019] One aspect of the present invention is a scanning line driving circuit and a signal line driving circuit that include any of the above-described driving circuits. It has a motion circuit, multiple scan lines, multiple signal lines, and a pixel section, and the pixel section has multiple scan lines It is electrically connected to the scan line drive circuit via one of the lines, and is one of the multiple signal lines. This is a display device having multiple pixels electrically connected to a signal line driving circuit via a signal line drive.

[0020] One aspect of the present invention is an electronic device having the above-described display device as a display unit.

[0021] In this specification, a transistor has a gate terminal, a source terminal, and a drain terminal. It has at least three terminals, and the gate terminal is the gate electrode portion (conductive layer, and This refers to a part of the gate electrode that is electrically connected to the gate electrode (including wires, etc.). Furthermore, the source terminal refers to the source electrode portion (including the conductive layer and wiring, etc.) and the source electrode It refers to a part of the part that is electrically connected to the pole (including semiconductor layers, etc.). A drain terminal refers to the drain electrode portion (including the conductive layer and wiring, etc.) or the drain electrode itself. It refers to a part of the electrically connected portion (including semiconductor layers, etc.). A zista has a channel region between the drain region and the source region, and the drain region and the channel Current can be passed through the source region and the recirculation region.

[0022] Furthermore, in this specification, the source terminal and drain terminal of a transistor are defined as the transistor It depends on the structure and operating conditions, so it is not always clear which is the source terminal or the drain terminal. It is difficult to limit the scope of this. Therefore, this document (specification, claims, or drawings) In such cases, either terminal arbitrarily selected from the source terminal and drain terminal is set as the source. One of the terminals is referred to as the source terminal and the other as the drain terminal. This is how it is written.

[0023] Furthermore, if B is formed on top of A, or if B is formed on top of A, When describing this, it is not limited to the case that B is formed in direct contact with A. This also includes cases where this is not the case, that is, when another object is interposed between A and B. Here, A and B are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, and Let's assume that (is a layer, etc.).

[0024] Therefore, for example, explicitly stating that layer B is formed on top of layer A (or on top of layer A) If described, this applies to cases where layer B is formed in direct contact with layer A, and where layer A is formed on top of layer B. Another layer (such as layer C or layer D) is formed in direct contact with it, and layer B is formed in direct contact with it on top of that. This includes cases where a layer is formed. Note that other layers (e.g., layer C or layer D) are: It can be single-layered or multi-layered.

[0025] Furthermore, it is not explicitly stated that B is formed on A or that B is formed on A. This includes cases where B is formed diagonally upwards.

[0026] Furthermore, in this specification, terms using ordinal numbers such as "1st," "2nd," etc., are used to avoid confusion of constituent elements. It should be noted that this is added for the purpose of [specific purpose] and does not mean that the number is limited. [Effects of the Invention]

[0027] According to one aspect of the present invention, malfunctions are suppressed in a circuit using a shift register. It is possible. [Brief explanation of the drawing]

[0028] [Figure 1] This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 1. [Figure 2] Figure 1 is a timing chart showing the operation of the drive circuit. [Figure 3] This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 1. [Figure 4] This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 1. [Figure 5] Figure 4 is a timing chart showing the operation of the drive circuit. [Figure 6] This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 1. [Figure 7] This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 2. [Figure 8] Figure 7 is a timing chart showing the operation of the drive circuit. [Figure 9] This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 2. [Figure 10]This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 2. [Figure 11] Figure 10 is a timing chart showing the operation of the drive circuit. [Figure 12] This is a circuit diagram showing an example of the configuration of the drive circuit in Embodiment 2. [Figure 13] This is a circuit diagram showing an example of the configuration of the display device in Embodiment 3. [Figure 14] Figure 13 is a timing chart showing the operation of the scan line drive circuit 702. [Figure 15] This figure shows an example of the pixel configuration and operation in the liquid crystal display device of Embodiment 3. [Figure 16] This figure shows an example of the pixel configuration and operation in the liquid crystal display device of Embodiment 3. [Figure 17] This is a schematic cross-sectional view showing an example of a transistor configuration applicable to the drive circuit in Embodiment 4. [Figure 18] This is a schematic cross-sectional view showing an example of a transistor configuration applicable to the drive circuit in Embodiment 4. [Figure 19] This is a schematic cross-sectional view showing an example of a method for fabricating a transistor applicable to the drive circuit in Embodiment 4. [Figure 20] This is a schematic cross-sectional view showing an example of a method for fabricating a transistor applicable to the drive circuit in Embodiment 4. [Figure 21] This is a schematic cross-sectional view showing an example of a method for fabricating a transistor applicable to the drive circuit in Embodiment 4. [Figure 22] This figure shows an example of electronic equipment that can be applied to the display unit of the display device in Embodiment 5. [Figure 23] This figure shows an example of electronic equipment that can be applied to the display unit of the display device in Embodiment 5. [Figure 24] This figure shows an example of the configuration of the drive circuit in Embodiment 1. [Figure 25] This figure shows the circuit calculation results for the drive circuit in Embodiment 1. [Modes for carrying out the invention]

[0029] Examples of embodiments of the present invention will be described below with reference to the drawings. However, the present invention is described below. The description is not limited to the present invention, and the form and details may not depart from the spirit and scope of the present invention. Those skilled in the art will readily understand that the parameters can be modified in various ways. Accordingly, the present invention is described below. It is not intended to be interpreted as being limited to the contents described in the embodiment.

[0030] (Embodiment 1) This embodiment describes a drive circuit that is one aspect of the present invention.

[0031] The drive circuit in this embodiment is a shift register including multiple flip-flop circuits. It holds.

[0032] Furthermore, an example of a flip-flop circuit configuration will be explained using Figure 24. Figure 2 4 shows an example of the circuit configuration of the flip-flop circuit in the drive circuit of this embodiment. This is a route map.

[0033] At least one of the multiple flip-flop circuits is a flip-flop with the circuit configuration shown in Figure 24. It can be used as a lop circuit. Note that the flip-flop circuit shown in Figure 24 is just one example. It has the function of receiving a first signal, a second signal, and a third signal as inputs and outputting an output signal. It shall be assumed that...

[0034] The flip-flop circuit shown in Figure 24 consists of transistor 11, transistor 12, and It has a transistor 13, a transistor 14, and a transistor 15.

[0035] Transistor 11 is given a first potential, which is the potential of the first signal, at its gate terminal, and A first potential or a second potential is applied to either the - terminal or the drain terminal.

[0036] Transistor 12 has either its source terminal or drain terminal connected to the source of transistor 11. It is electrically connected to the other terminal and drain terminal. Also, transistor 12 is gate A third potential, which is the potential of the second signal, is applied to the terminal, and in addition to the source terminal and drain terminal, A fourth potential is applied to the side.

[0037] Transistors 13 and 14 are connected to the source terminal of transistor 11 and A device that controls whether or not to set the potential of the other end of the drain terminal to the first potential or the fourth potential. It has the ability to control the potential of the other side of the source terminal and drain terminal of transistor 11 to the fourth It has a function to control whether or not to set the potential.

[0038] Furthermore, transistor 13 has a function that turns off when transistor 14 is ON. It has a feature, and transistor 14 is in the off state when transistor 13 is in the on state. It has the function of [doing something].

[0039] Transistor 15 has a gate terminal that is connected to the source and drain terminals of transistor 11. It is electrically connected to the other side. Also, transistor 15 has source terminal and drain terminal A fifth potential, which is the potential of the third signal, is applied to one side, and the source terminal and drain terminal are also connected. The potential of this terminal becomes the potential of the output signal. Note that the source terminal and drain terminal of transistor 11 The connection point between the other end and the gate terminal of transistor 15 is also called node A.

[0040] Furthermore, transistor 15 is turned on when transistor 13 or transistor 14 is ON. It is in the off state.

[0041] With the above configuration, when transistor 13 or transistor 14 is ON, The potential of circuit A, that is, the potential of the gate terminal of transistor 15, is set to a predetermined value. Since the A-threshold does not remain floating, malfunctions of the flip-flop circuit can be suppressed. Cut.

[0042] Furthermore, regarding an example of the circuit configuration of the flip-flop circuit in the drive circuit of this embodiment... Let's explain using Figure 1. Figure 1 shows the circuit of the flip-flop circuit in this embodiment. This is a circuit diagram showing an example configuration.

[0043] Each of the multiple flip-flop circuits in the drive circuit of this embodiment is shown in Figure 1. It can be a flip-flop circuit with a simple circuit configuration. The flip-flop circuit shown in Figure 1 The path is connected to terminal 100, terminal 101, terminal 102, terminal 103, terminal 104, and terminal 105, transistor 106, transistor 107, capacitive element 108, and transistor 109, transistor 110, transistor 111, capacitive element 112, Transistor 113, transistor 114, transistor 115, and transistor 116 It has, and

[0044] In the flip-flop circuit shown in Figure 1, terminal 102 is defined as terminal 102A and terminal 1 Although 02B is shown, the invention is not limited to this, and the flip-flop in the drive circuit of this embodiment In the lop circuit, terminals 102A and 102B are electrically connected, and one terminal 102 It is also possible to do so. In addition, in the flip-flop circuit shown in Figure 1, terminal 103 is set as terminal Although terminals 103A and 103B are shown, the drive circuit of this embodiment is not limited to these. In the flip-flop circuit in this, terminals 103A and 103B are electrically connected. It can also be represented as a single terminal 103.

[0045] Furthermore, in the flip-flop circuit of the drive circuit of this embodiment, terminal 104 is Although terminals 104A to 104G are shown, the drive of this embodiment is not limited to these terminals. In the flip-flop circuit in the circuit, terminals 104A to 104G are electrically connected. This allows it to be treated as a single terminal 104.

[0046] Transistor 106 has its gate terminal electrically connected to terminal 100, and its source terminal and One of the drain terminals is electrically connected to the gate terminal of transistor 106.

[0047] Transistor 107 has its gate terminal electrically connected to terminal 101, and its source terminal and One of the drain terminals is electrically connected to the source terminal and the other of the drain terminals of transistor 106. It is connected to the source terminal and the other drain terminal is electrically connected to terminal 104A. For convenience, the flip-flop circuit in the drive circuit of this embodiment is not shown in the diagram. In this configuration, transistor 107 can be omitted. By omitting this component, the circuit area can be reduced.

[0048] Capacitive element 108 has at least two terminals, one of which is electrically connected to terminal 102A Connected.

[0049] Transistor 109 has its gate terminal connected to the source and drain terminals of transistor 106. One of the child is electrically connected, and one of the source terminals and drain terminals is the other of the capacitive element 108. One terminal is electrically connected, and the other of the source terminal and drain terminal is electrically connected to terminal 104B. It connects to the target.

[0050] Transistor 110 has its gate terminal connected to the source and drain terminals of transistor 109. One of the child is electrically connected, and one of the source terminals and drain terminals is transistor 106 It is electrically connected to the other of the source terminal and drain terminal, and the source terminal and drain terminal The other end is electrically connected to terminal 104C.

[0051] The capacitive element 112 has at least two terminals, one of which is electrically connected to terminal 103A Connected.

[0052] The gate terminal of transistor 111 is electrically connected to the other terminal of capacitive element 112. , one of the source terminal and drain terminal is the source terminal and drain terminal of transistor 106 The other side of the child is electrically connected, and the other side of the source terminal and drain terminal is electrically connected to terminal 104D. It connects to the target.

[0053] Transistor 113 has its gate terminal connected to the source and drain terminals of transistor 106. The other side is electrically connected, and one of the source terminals and drain terminals is transistor 111 It is electrically connected to the gate terminal, and the other of the source terminal and drain terminal is connected to terminal 104E. It is electrically connected.

[0054] Transistor 114 has its gate terminal connected to the source and drain terminals of transistor 106. The other side is electrically connected, and one of the source terminal and drain terminal is electrically connected to terminal 103B. They are connected in a manner, with the source terminal and the other drain terminal being electrically connected to terminal 105, The potential of the other terminal of the drain terminal becomes the output signal and is output via terminal 105. The flip-flop circuit in the drive circuit of this embodiment is transistor 114 A configuration in which a separate capacitive element is provided between the gate terminal and the source terminal and the other drain terminal. It is also possible.

[0055] Furthermore, the gate terminal of transistor 115 is electrically connected to the gate terminal of transistor 111. The source terminal and drain terminal of transistor 114 are connected, and one of them is connected to the source terminal and drain terminal of transistor 114. The other end of the rain terminal is electrically connected, and the other end of the source terminal and drain terminal is terminal 104 It is electrically connected to F.

[0056] Furthermore, transistor 116 has its gate terminal electrically connected to terminal 102B, and the source One of the terminals and drain terminals of transistor 114 is the source terminal and drain terminal of transistor 114. It is electrically connected to the source terminal and the other drain terminal is electrically connected to terminal 104G. It will be done.

[0057] Furthermore, one of the source terminals and drain terminals of transistor 109 and the capacitive element 108 The connection point to the other terminal or the gate terminal of transistor 110 is also called node 118. Also, the source terminal and the other drain terminal of transistor 106, and transistor 107 One of the source terminals and drain terminals of transistor 110, source terminal and drain terminal On the other hand, one of the source terminals and drain terminals of transistor 111, transistor 113 The gate terminal, or the connection point to the gate terminal of transistor 114, is also called node 117. It is said that the gate terminal of transistor 111 and the other terminal of capacitive element 112, Either the source terminal or drain terminal of transistor 113, or the gate terminal of transistor 115 The connection point with the child is also called node 119.

[0058] Furthermore, the flip-flop circuit shown in Figure 1 receives the first control signal via terminal 100. Then, a second control signal is input via terminal 101. The first control signal and the second control signal The signal may be a digital signal, for example, one that has two states: a high state and a low state. This is possible. When using digital signals, the first control signal or the second control signal that is input When the signal is high (also called high level), it is transmitted via terminal 100 or terminal 101. A first control signal or a second signal that has a predetermined potential value as the first potential (also called V1) When a control signal is input, and the input first control signal or second control signal is in a low state (Also called the low level) has a second potential (V2 and (Also referred to as) The first control is a potential value lower than a predetermined potential value in the above high state. A signal or a second control signal is input. The potential values ​​in the high and low states are, for example, For example, it can be set appropriately considering the threshold voltage value of the transistor. The potential difference between the state and the low state is the absolute value of the threshold voltage of the transistor in the flip-flop circuit. It is preferable to set the potential values ​​in the high and low states to be larger. stomach.

[0059] Furthermore, the flip-flop circuit shown in Figure 1 has terminal 102 (terminal 102A and terminal 102 The first phase clock signal (also called the first clock signal, or CK) is transmitted via B (also called a signal) or a second-phase clock signal (second clock signal, CKB signal) The first clock signal and (also called the inverted signal of the first clock signal) are input. The second clock signal has two potential states, a high state and a low state, and the high state and When the clock signal is at a high level (also called a low level), the potential of the clock signal becomes potential V1, and the low state is In the low-level state, the potential of the clock signal becomes potential V2. The potentials of the first clock signal and the second clock signal are the first control when in the high state. Preferably, the potential of the signal and the second control signal is equivalent to that of the first signal when it is low. The potentials of the first clock signal and the second clock signal are low when the first control signal and It is preferable that the potential of the second control signal is equivalent to that of the high state and the low state. The potential value should be set appropriately, taking into consideration, for example, the threshold voltage value of the transistor. This is possible. For example, the potential difference between the high state and the low state is the transistor within the flip-flop circuit. The values ​​of the potential in the high and low states are set so that they are greater than the absolute value of the threshold voltage. It is preferable to set it.

[0060] The two clock signals, the first clock signal and the second clock signal, are in opposite phases. For example, when the first clock signal is high for a predetermined period, the second The clock signal is low, and when the first clock signal is low, the second clock The buck signal is in a high state.

[0061] Furthermore, the flip-flop circuit is located at terminal 103 (also known as terminals 103A and 103B). The first or second clock signal is input via ). The clock signal input via terminal 2 and the clock signal input via terminal 103 are in phase The inverse relationship is that, for example, when the first clock signal is input via terminal 102, A second clock signal is input via terminal 103, and a second clock signal is input via terminal 102. When a signal is input, a first clock signal is input via terminal 103.

[0062] Furthermore, the flip-flop circuit shown in Figure 1 has terminals 104 (terminals 104A to 104) A predetermined potential is applied via G. At this time, the value of the predetermined potential is, for example, For example, it can be set to V1 or V2, that is, digital signals such as clock signals or control signals The potential value can be made equivalent to the potential value in the high or low state of a Tal signal.

[0063] In the flip-flop circuit shown in Figure 1, the source terminal of transistor 106 and We have described a configuration in which one of the drain terminals is electrically connected to terminal 100, but The flip-flop circuit in the drive circuit of this embodiment may have a separate power supply terminal. It can also be configured to be electrically connected and to be given a potential V1 or potential V2. can.

[0064] Transistor 106 operates according to the signal input via terminal 100. It has the function of controlling the conductivity between it and node 117.

[0065] Transistor 107 operates according to the signal input via terminal 101, at terminal 104 It has a function to control the conductivity between A and node 117, and when terminal 104A and node 117 are conductive When this state is reached, the potential of node 117 is set to either V1 or V2.

[0066] Capacitive element 108 responds to the signal input via terminal 102 (terminal 102A) It has the function of varying the potential of node 118 through capacitive coupling. For example, terminal 102 When the signal input via (terminal 102A) changes from a low state to a high state, the capacitive element Child 108 has the function of setting the potential of node 118 to potential V1 through capacitive coupling. On the other hand, when the signal input via terminal 102 changes from a high state to a low state, the capacitive element Child 108 has the function of setting the potential of node 118 to V1 or V2 by capacitive coupling. do.

[0067] Transistor 109, according to the signal input via terminal 100, controls terminal 104 It has a function to control the conductivity between B and node 118, and when terminal 104B and node 118 are conductive When this state is reached, the potential of node 118 is set to either V1 or V2.

[0068] Transistor 110, according to the potential of node 118, has terminals 104C and node 11 It has a function to control conductivity with 7, so that terminal 104C and node 117 become conductive. This sets the potential of node 117 to V1 or V2. Also, transistor 110 It has the function of being turned off when transistor 111 is turned on.

[0069] Transistor 111, according to the potential of node 119, has terminals 104D and node 11 It has a function to control conductivity with 7, so that terminal 104D and node 117 become conductive. The potential of node 117 is set to V1 or V2. Also, transistor 111 It has the function of being in an off state when transistor 110 is in an on state.

[0070] The capacitive element 112, according to the signal input via terminal 103A, is capacitively coupled This has the function of changing the potential of node 119. For example, input via terminal 103A When the signal being treated changes from a low state to a high state, the capacitive element 112 is activated by capacitive coupling. The potential of node 119 is set to V1. Meanwhile, the signal input via terminal 103A is When the state changes from state I to state L, the capacitive element 112 is coupled to node 119 by capacitive coupling. Set the potential to V2.

[0071] Transistor 113 has the function of controlling the conduction between terminal 104E and node 119. When terminal 104E and node 119 become conductive, the potential of node 119 becomes V1 Alternatively, it will be set to V2.

[0072] Transistor 114, according to the potential of node 117, terminals 103B and 105 By controlling the conductivity between terminals 103B and 105, terminal 10 The potential of the signal input via 3B and the potential of the signal output via terminal 105 are set to be equal. It has the function of setting the value to [value].

[0073] Furthermore, transistor 114 is, for example, an N-type transistor and the potential of node 117 is In the case of V1, the signal input via terminal 103B changes from a low state to a high state. Then, the potential of node 117 is increased in accordance with the increase in potential at the connection point with terminal 105. It has a function. It is a so-called bootstrap. However, a bootstrap is a tiger Parasitic capacitance between the gate terminal of the converter 114 and the other of the source and drain terminals. Therefore, it is often done.

[0074] Transistor 115, according to the potential of node 119, has terminals 104F and 105 It has a function to control the conductivity between terminals, and when terminals 104F and 105 become conductive, Then, the potential of the signal output via terminal 105 is set to either V1 or V2.

[0075] Transistor 116, according to the signal input via terminal 102B, controls terminal 10 It has a function to control the conductivity between terminal 4G and terminal 105, and connects terminal 104G and terminal 105 in a conductive state. The system has a function to set the potential of the signal output via terminal 105 to either V1 or V2. do.

[0076] In this embodiment, the drive circuit is composed entirely of transistors of the same conductivity type. This allows for the simplification of the manufacturing process. Therefore, manufacturing costs This can lead to a reduction in waste and an improvement in yield. Furthermore, it can improve semiconductors such as large display panels. It also becomes easier to manufacture the device. In the drive circuit of this embodiment, all transistors This is an N-type conductive transistor (also called an N-type transistor) or a P-type conductive transistor. It can also be called a transistor (also known as a P-type transistor). In this specification, the same term is used. This also includes things that are essentially identical.

[0077] Next, the operation of the drive circuit shown in Figure 1 will be explained using Figure 2. Figure 2 is shown in Figure 1. This is a timing chart showing an example of the operation of the drive circuit. Note that this embodiment is an example. As such, a second clock signal is input via terminal 102, and the first clock signal is input via terminal 103. A clock signal is assumed to be input. Also, here we will consider one of the operations of the drive circuit shown in Figure 1. For example, consider the case where all the transistors in a flip-flop circuit are N-type transistors. I will explain.

[0078] The operation of the drive circuit shown in Figure 1 is as follows: a predetermined operation is repeated over a certain period of time, as shown in Figure 2. It is repeated. A certain period is mainly divided into an elective period and a non-elective period, and further the elective period The intervals and non-selective periods are the first period, the second period, the third period, the fourth period, and the fifth period. It can be divided into the following. In Figure 2, the first period, the third period, the fourth period, and the fifth period are The first period is a non-selective period, and the second period is an elective period.

[0079] First, during the first period, a first control signal 201, which is in a high state, is input via terminal 100. Then, a second control signal 208, which is in a low state, is input via terminal 101, and terminal 102 A second clock signal 203, which is in a high state, is input via terminal 103, and a low state is input via terminal 103. When the first clock signal 202, which is in this state, is input, transistor 106, Transistor 109 and transistor 116 are turned ON, and transistor 107 is ON It enters a state of "fu".

[0080] When transistor 106 is turned on, the potential 204 at node 117 begins to rise. At this time, the potential of node 117 is from the potential V1 of the first control signal 201 to transistor 106 The threshold voltage (Vth 106 The value obtained by subtracting (also known as) V1-Vth 106 until It rose, V1-Vth 106When this happens, transistor 106 turns off.

[0081] Furthermore, the potential 204 at node 117 is V1-Vth 106 When this happens, transistor 113 It turns ON. At this time, the potential 206 of node 119 is supplied via terminal 104E. The potential V2 will be equivalent to this value.

[0082] Furthermore, when the potential 206 at node 119 becomes V2, transistor 111 and the transistor The Ta115 will be turned off.

[0083] Furthermore, when transistor 109 is turned on, the potential 205 at node 118 is at terminal 1 This will be equivalent to the potential V2 provided via 04B.

[0084] Furthermore, when the potential 205 at node 118 becomes V2, transistor 110 turns off. ru.

[0085] Furthermore, as mentioned above, transistors 106, 107, and 110 And when transistor 111 is turned off, node 117 has a potential of V1-Vth1 06 It remains suspended while maintaining that state.

[0086] Also, the potential 204 at node 117 is V1-Vth 106 When this happens, transistor 114 It turns on.

[0087] Furthermore, at this time, the potential of the output signal 207 output via terminal 105 is, terminal 103B The potential V2 provided via, or the potential V2 equivalent to the potential V2 provided via terminal 104G This is the value. The above describes the operation during the first period.

[0088] Next, in the second period, the first control signal 201, which is in a low state, is input via terminal 100. Then, a second control signal 208, which is in a low state, is input via terminal 101, and terminal 102 A second clock signal 203, which is in a low state, is input via terminal 103, and a high state is input via terminal 103. The first clock signal 202, which is in state, is input. At this time, transistor 106, Transistor 109 and transistor 116 are turned off, and transistor 107 is turned off. It remains in its current state.

[0089] The transistor 109 receives the second clock signal 20 via terminal 102A. In many cases, terminal 3 goes from low to off. This is because input is received via terminal 100. The first control signal 201 is often delayed compared to the second clock signal 203. Therefore, after the second clock signal 203 goes low, transistor 109 turns O By entering this state, node 118 remains in a floating state while being maintained at potential V2, The Rangista 110 remains in the off state.

[0090] Furthermore, the capacitive element 108 receives a second clock signal 20 via terminal 102A. The potential difference between the potential at point 3 and the potential at node 118 (205) is the second clock, which is in a low state. The potential difference between the potential of signal 203 and the potential V2 supplied via terminal 104B is maintained. .

[0091] Furthermore, as described above, transistors 106, 107, and 11 When 0 is in the off state, the potential 204 at node 117 is V1-Vth 106 It remains the same. .

[0092] Furthermore, when the potential 204 of node 117 is V1 - Vth 106 and transistor 11 3 remains in the on state and transistor 113 remains in the on state, the potential 206 of node 1 19 remains at V2, and transistors 111 and 115 remain in the off state.

[0093] When the potential 204 of node 117 remains at V1 - Vth 106 and the potential of one of the source terminal and the drain terminal of transistor 114 becomes the potential V1 of the first clock signal 202 the potential of the output signal 207 output via terminal 105 rises. Then, since node 11 7 is in a floating state, the potential 204 of node 117 rises in accordance with the potential of the output signal 207 due to capacitive coupling by the parasitic capacitance between the gate of transistor 114 and the other of the source terminal and the drain terminal. This is so-called bootstrap. The potential 204 of node 117 rises to a value even greater than the sum of the potential V1 of the first clock signal 202 and the threshold voltage (also referred to as Vth of transistor 114), that is, up to V1

[0094] + Vth + Va (Va is an arbitrary positive value). At this time, transistor 11' 114 [[ID=..]] + Vth 114 + Va (Va is an arbitrary positive value). At this time, transistor 11 4 remains in the on state.

[0095] Furthermore, at this time, the potential of the output signal 207 output via terminal 105 becomes a value equivalent to the potential V1 given via terminal 103B . The above is the operation in the second period.

[0096] Next, in the third period, the first control signal 201 in the low state is input via terminal 100 Then, a second control signal 208, which is in a high state, is input via terminal 101, and terminal 102 A second clock signal 203, which is in a high state, is input via terminal 103, and a low state is input via terminal 103. The first clock signal 202, which is in state, is input. At this time, transistor 107 and Transistor 116 turns ON, and transistors 106 and 109 turn OFF. It remains in its current state.

[0097] When transistor 107 is turned on, the potential 204 at node 117 is at terminal 104A. The potential V2 applied through it will be equivalent to this value.

[0098] Furthermore, the potential 205 at node 118 becomes V2+Vb due to capacitive coupling with the capacitive element 108. It is preferable that Vb is greater than the threshold voltage of transistor 110, and V1-V2 It is preferable that it be smaller than this.

[0099] Furthermore, when the potential of node 118 at potential 205 becomes V2+Vb, transistor 110 turns It enters the ON state. Furthermore, when transistor 110 turns ON, the potential of node 117 is 204 This value is equivalent to the potential V2 supplied via terminal 104C.

[0100] Furthermore, when the potential 204 of node 117 becomes potential V2, transistor 113 and the transistor The transistor 114 is turned off. Note that the transistor 113 is input via terminal 103A. The first clock signal 202 often goes from low to off. Why? Then, the potential 204 at node 117 is delayed or sloppier than the first clock signal 202. This is because in many cases the first clock signal 202 goes low and then the transistor When the zista 113 is turned off, it is equivalent to the potential V2 supplied via terminal 104E. Node 119 remains in a floating state while this state is maintained.

[0101] Furthermore, when node 119 is in a floating state, transistor 111 and transistor 11 5 remains in the off state.

[0102] Furthermore, the capacitive element 112 receives the first clock signal 20 via terminal 103A. The potential difference between the potential at point 2 and the potential at node 119 (206), i.e., the first cross, which is in a low state. The potential difference between the potential of signal 202 and the potential V2 supplied via terminal 104E is maintained. ru.

[0103] Furthermore, at this time, the potential of the output signal 207 output via terminal 105 is terminal 104G This becomes equivalent to the potential V2 supplied through it. The above describes the operation during the third period.

[0104] Next, in the fourth period, the first control signal 201, which is in a low state, is input via terminal 100. Then, a second control signal 208, which is in a low state, is input via terminal 101, and terminal 102 A second clock signal 203, which is in a low state, is input via terminal 103, and a high state is input via terminal 103. The first clock signal 202, which is in state, is input. At this time, transistor 107 and Transistor 116 is turned off, and transistors 106 and 109 are also turned off. It remains in its current state.

[0105] At this time, the potential 205 at node 118 becomes V2 due to the capacitive coupling of the capacitive element 108. Therefore, transistor 110 is in the off state.

[0106] Furthermore, the potential 206 at node 119 is V2+Vc due to capacitive coupling with the capacitive element 112. Yes. Vc is greater than the threshold voltage of transistor 111 or the threshold voltage of transistor 115. It is preferable that it be large, and preferably smaller than V1-V2.

[0107] Furthermore, when the potential 206 of node 119 becomes V2+Vc, transistor 111 and the transistor... The 'njista 115' is turned on.

[0108] Furthermore, when transistor 111 is turned on, the potential 204 at node 117 becomes terminal 10 This will be equivalent to the potential V2 given via 4D.

[0109] Furthermore, when the potential 204 of node 117 becomes V2, transistor 113 and the transistor The Ta114 will be turned off.

[0110] Furthermore, when transistor 115 is turned on, the output signal is output via terminal 105. The potential at terminal 207 is equivalent to the potential V2 supplied through terminal 104F. This is the action during the fourth period.

[0111] Next, in the fifth period, the first control signal 201, which is in a low state, is input via terminal 100. Then, a second control signal 208, which is in a low state, is input via terminal 101, and terminal 102 A second clock signal 203, which is in a high state, is input via terminal 103, and a low state is input via terminal 103. The first clock signal 202, which is in the state, is input. At this time, transistor 116 turns on. In this state, transistors 106, 107, and 109 are turned off. It remains in its current state.

[0112] At this time, the potential of node 118 becomes V2 + Vb due to the capacitive coupling of capacitive element 108. Furthermore, when the potential of node 118 becomes V2+Vb, transistor 110 turns on. Furthermore, when transistor 110 is turned on, the potential 204 at node 117 becomes terminal 10 This will be equivalent to the potential V2 provided through 4C.

[0113] Furthermore, the potential 206 at node 119 becomes V2 due to the capacitive coupling of the capacitive element 112. Furthermore, when the potential 206 at node 119 becomes V2, transistor 111 and transistor 115 will be turned off.

[0114] Furthermore, when the potential 204 of node 117 becomes V2, transistor 113 and the transistor The Ta114 will be turned off.

[0115] Furthermore, at this time, the potential of the output signal 207 output via terminal 105 is terminal 104G This becomes equivalent to the potential V2 supplied through it. The above describes the operation during the fifth period.

[0116] As described above, the drive circuit in this embodiment is configured to perform the following after the reset period (third period): During the selected period, the actions of the fourth and fifth periods are repeated multiple times. Since a predetermined potential is applied to node 117 during any period of the non-selective period, This can suppress node 117 from becoming detached. Therefore, the impact of noise is reduced. Because it can be reduced, malfunctions can be suppressed.

[0117] Furthermore, in the operation of the drive circuit in this embodiment, during the fourth period and the fifth period A predetermined potential is applied to node 117 by turning on different transistors. Therefore, even when applying a transistor that is prone to deterioration, such as a transistor in which a semiconductor layer is an amorphous semiconductor, deterioration in each transistor can be suppressed. Thus, it is possible to reduce a deviation in the timing of the switching operation of the transistor due to deterioration, and therefore it is possible to suppress malfunction. Here, in the fourth period and the fifth period shown in FIG. 2, in the case of a conventional drive circuit that controls the potential of the node 117 by providing only one of the transistors 110 and 111, and in the case of a drive circuit according to an aspect of the present invention that controls the potential of the node 117 by providing both of the transistors 110 and 111, circuit calculation results are shown in FIG. 25. The calculation was performed using a SPICE circuit simulator. Here, as an example, all the transistors in the flip-flop circuit are N-type transistors, and V2 = 0V.

[0118]

[0119]

[0120] <000,0926>

[0121] The noise generated during the fourth and fifth periods after the reset period is mainly shown in Figure 1. The parasitic capacitance of transistor 114 affects node 117. First, the conventional drive cycle In this circuit, a signal synchronized with a single clock signal is used to control the transistor, so After the initial period, the object enters a floating state during either the fourth or fifth period. When this happens, noise is added to the normal potential, and as shown in Figure 25(A), for a certain period of time (Figure In 25(A), the potential (voltage) of node 117 fluctuates by approximately 0.4 every 5th period. cormorant.

[0121] On the other hand, in a drive circuit according to one aspect of the present invention, two clock signals whose phases are in opposition to each other Transistors 110 and 111 are controlled using signals synchronized with each of the numbers. Therefore, during both the fourth and fifth periods, the device does not enter a floating state and a predetermined potential is applied. Therefore, as shown in Figure 25(B), the change in potential at node 117 is less than 0.2. It can be seen that there is little movement, meaning that the effect of noise is minimal. From the above, it can be seen that multiple transistors Using a transistor, in each of the fourth and fifth periods, transistor 110 or a transistor By turning on the station 111, a predetermined potential is applied to the node 117. It can be seen that the effects of isps can be reduced.

[0122] Furthermore, in this embodiment, a drive circuit that is one aspect of the present invention is used with a configuration different from that shown in Figure 1. It is also possible to do so. Other configurations of the drive circuit in this embodiment will be explained using Figure 3. Figure 3 is a circuit diagram showing an example of the configuration of the drive circuit of this embodiment.

[0123] In addition to the circuit configuration shown in FIG. 1, the other configuration of the drive circuit in the present embodiment shown in FIG. 3 has a transistor 120 and a terminal 104H.

[0124] For those parts in FIG. 3 that are marked with the same reference numerals as in FIG. 1, since they are the same as the drive circuit in FIG. 1, the description thereof will be omitted.

[0125] The gate terminal of the transistor 120 is electrically connected to the terminal 100, and one of the source terminal and the drain terminal is electrically connected to the gate terminal of the transistor 111, and the other of the source terminal and the drain terminal is electrically connected to the terminal 104H.

[0126] The same potential as the terminals 104A to 104G in FIG. 1 is applied via the terminal 104H, so the description in FIG. 1 is incorporated herein. Also, the terminals 104A to 104H can be electrically connected to form a single terminal 104.

[0127] The transistor 120 has a function of controlling the conduction between the terminal 104H and the node 119 according to the signal input via the terminal 100, and by making the terminal 104H and the node 119 conductive, the potential of the node 119 is set to V1 or V2.

[0128] Next, the operation of the drive circuit shown in FIG. 3 will be described. Regarding the operation of the drive circuit in FIG. 3, only the operation of the transistor 120 will be described, and for the parts that are the same as the operation of the elements of the drive circuit shown in FIG. 1, the description in FIG. 1 will be incorporated as appropriate. Also, here, as an example of the operation of the drive circuit shown in FIG. 3, the case where all the transistors in the flip - flop circuit are N - type transistors will be described.

[0129]

[0129] During the first period, a first control signal 201, which is in a high state, is input via terminal 100. At this time, transistor 120 turns ON.

[0130] When transistor 120 is turned on, the potential of node 119 is transmitted through terminal 104H. The value becomes equivalent to the given potential V2. Therefore, transistor 111 and transistor 11 5 will be in the off state.

[0131] Subsequently, during the second to fifth periods, the first control, which is in a low state via terminal 100, Signal 201 is input. At this time, transistor 120 is turned off.

[0132] As described above, the drive circuit shown in Figure 3 has the effect of the circuit configuration in Figure 1, in addition to the first During the period, the first control signal 201 is directly input to transistor 120, and transistor 1 By turning on 20, the potential of node 119 is more reliably maintained during the first period. The potential can be set to V2.

[0133] Furthermore, in this embodiment, a different configuration from Figures 1 and 3 is used to represent one aspect of the present invention. It can also be used as a drive circuit. Figure 4 shows other configurations of the drive circuit in this embodiment. Let's use this to explain. Figure 4 is a circuit diagram showing an example of the circuit configuration of the drive circuit in this embodiment. be.

[0134] The drive circuit configuration shown in Figure 4 is the same as the circuit configuration in Figure 1, but with terminals 103C and 104I. terminal 104J, terminal 121, transistor 122, transistor 123, and transistor It has a sta124.

[0135] Note that the elements in Figure 4 that are given the same reference numerals as in Figure 1 are the same as the drive elements in Figure 1. Since it is identical to each element of the dynamic circuit, we will refer to the explanation in Figure 1.

[0136] Transistor 122 has its gate terminal connected to the source and drain terminals of transistor 106. The other side is electrically connected, and one of the source terminal and drain terminal is electrically connected to terminal 103C. They are connected in a specific manner, with the source terminal and the other drain terminal being electrically connected to terminal 121.

[0137] Furthermore, the gate terminal of transistor 123 is electrically connected to the gate terminal of transistor 111. Connected, with one of the source and drain terminals being connected to the source and drain terminals of transistor 122. The other end of the rain terminal is electrically connected, and the other end of the source terminal and drain terminal is terminal 104 It is electrically connected to I.

[0138] Furthermore, transistor 124 has its gate terminal electrically connected to terminal 102B, and its source terminal One of the source and drain terminals of transistor 122 is connected to the other of the source and drain terminals of transistor 122. Electrically connected, the source terminal and the other drain terminal are electrically connected to terminal 104J. It can be done.

[0139] The same signal as terminals 103A and 103B in Figure 1 is input via terminal 103C. Therefore, we will refer to the explanation in Figure 1. Also, terminals 103A to 103C are electrically It can also be connected to form a single terminal 103.

[0140] Through terminals 104I and 104J, terminals 104A to 104 in Figure 1 Since the same potential is given as the potential given via G, we will use the explanation in Figure 1. Terminals 104A to 104G, as well as terminals 104I and 104J, are electrically connected. This allows it to be treated as a single terminal 104.

[0141] Furthermore, the flip-flop circuit is powered by terminal 121 in the flip-flop circuit. Outputs the generated signal.

[0142] Transistor 122, according to the potential of node 117, has terminals 103C and 121 The terminals are made conductive, and the potential of the signal input via terminal 103C and the terminal output via terminal 121 are connected. It has the function of making the potential of the signal being applied equal to the value of V1. In this case, when the signal input via terminal 103C changes from a low state to a high state, Transistor 122 reacts to the rising potential of the signal output through terminal 121. It has the function of raising the potential of the 117. This is what is known as bootstrap. The bootstrap is connected to the gate terminal, source terminal and drain terminal of transistor 122. This is often done by parasitic capacitance between the terminal and the other terminal.

[0143] Transistor 123, according to the potential of node 119, has terminals 104I and 121 It has a function to control the conductivity between terminals, and by making terminals 104I and 121 conductive, Then, the potential of the signal output via terminal 121 is set to either V1 or V2.

[0144] Transistor 124, according to the signal input via terminal 102B, It has a function to control the conductivity between terminal 4J and terminal 121, and connects terminal 104J and terminal 121 in a conductive manner. By doing so, the potential of the signal output via terminal 121 is set to V1 or V2. It will be done.

[0145] Next, the operation of the drive circuit in Figure 4 will be explained using Figure 5. Figure 5 shows this embodiment. This is a timing chart diagram showing an example of the operation of the drive circuit in Figure 4. The operation of the dynamic circuit is as follows: transistor 122, transistor 123, and transistor 1 Only the operation of 24 will be explained, and the parts that are identical to the operation of the elements in the drive circuit shown in Figure 1 will be explained. Refer to the explanation of the operation of the drive circuit in Figure 1 as appropriate. Note that terminal 103C in Figure 5 This will be explained assuming that the first clock signal is input. Also, here we will explain the drive cycle shown in Figure 4. As an example of how the circuit works, all the transistors in a flip-flop circuit are N-type transistors. Let's explain the case.

[0146] During the first period, in addition to the operation of the circuit shown in Figure 1, the terminal 103C is in a low state. The first clock signal 202 is input. At this time, transistor 124 turns on. .

[0147] At this time, the potential 204 at node 117 is V1-Vth 106 Transistor 113 It turns on. Furthermore, when transistor 113 turns on, transistor 123 turns on. It will turn off.

[0148] Also, the potential 204 at node 117 is V1-Vth 106 When this happens, transistor 122 It turns on.

[0149] Furthermore, at this time, the potential of the output signal 209 output via terminal 121 is at terminal 103C. The potential V2 of the first clock signal given via or given via terminal 104J The potential V2 becomes equivalent to the value obtained. This describes the operation during the first period.

[0150] Next, in the second period, in addition to the operation of the circuit shown in Figure 1, the terminal 103C is in a high state. A first clock signal 202 is input. At this time, transistor 124 is turned off. Yes.

[0151] At this time, the potential 204 at node 117 is V1-Vth 106 It remains as is, transistor 113 remains in the ON state. When transistor 113 is in the ON state, the transistor The Ta123 remains in the off state.

[0152] Furthermore, at this time, node 117 remains in a floating state, and the potential 204 of node 117 is, V1-Vth 106 It remains as it is.

[0153] Furthermore, the potential 204 at node 117 is V1-Vth 106 It remains as is, transistor 1 The potential of either the source terminal or drain terminal of 22 is the potential V1 of the first clock signal 202. When this happens, the potential 204 at node 117 becomes the potential of transistor 122 due to bootstrap. Capacitive coupling occurs due to parasitic capacitance between the gate terminal and the other terminals of the source and drain terminals. Then, it rises in accordance with the potential of output signal 209. At this time, the potential 204 of node 117 is The sum of the potential V1 of the first clock signal 202 and the threshold voltage of the transistor 114, and This is the potential V1 of the first clock signal 202 and the threshold voltage (Vth) of transistor 122. 12 A value even greater than the sum of (also called 2), i.e., V1 + Vth 114 +Va, or V1+Vth 122 It increases up to +Va (where Va is any positive value).

[0154] Furthermore, the potential 204 at node 117 is V1+Vth 114 +Va, or V1+Vth1 22 When the value is +Va, transistor 122 remains in the ON state.

[0155] Furthermore, at this time, the potential of the output signal 209 output via terminal 121 is equal to terminal 103C. This becomes equivalent to the potential V1 of the first clock signal 202 input via this. This refers to actions performed over a period of time.

[0156] Next, in the third period, in addition to the operation of the circuit shown in Figure 1, the terminal 103C is in a low state. A first clock signal 202 is input. At this time, transistor 124 turns ON. Yes.

[0157] At this time, the potential 205 at node 118 becomes V2 + Vb, and transistor 110 turns ON. In this state, the potential 204 at node 117 becomes equivalent to the potential V2. Potential of node 117 When 204 reaches potential V2, transistor 122 turns off.

[0158] Furthermore, the potential 206 at node 119 remains at the same value as potential V2. When the potential 206 is V2, node 119 is in a floating state. In this case, transistor 123 remains in the off state.

[0159] Furthermore, at this time, the potential of the output signal 209 output via terminal 121 is terminal 104J The potential V2 supplied through this becomes equivalent to this value. This concludes the operation during the third period.

[0160] Next, in the fourth period, in addition to the operation of the circuit shown in Figure 1, the terminal 103C is in a high state. The first clock signal 202 is input. At this time, transistor 116 is turned off. ru.

[0161] At this time, the potential 206 at node 119 becomes V2+Vc, and the potential 206 at node 119 is When V2+Vc occurs, transistors 123 turn on.

[0162] Furthermore, the potential 204 at node 117 becomes the potential V2 supplied via terminal 104D. When the potential of node 117 reaches V2, transistor 122 turns off.

[0163] Furthermore, at this time, the potential of the output signal 209 output via terminal 121 is, terminal 104I The potential V2 supplied through this becomes equivalent to this value. This concludes the operation during the fourth period.

[0164] Next, in the fifth period, in addition to the operation of the circuit shown in Figure 1, terminal 103C is in a low state. A first clock signal 202 is input. At this time, transistor 124 turns ON. Yes.

[0165] At this point, the potential of node 118 becomes V2 + Vb, and transistor 110 turns on. When transistor 110 is turned on, the potential 204 at node 117 becomes the terminal 104C The value will be equivalent to the potential V2 supplied through it.

[0166] Furthermore, when the potential 204 at node 117 becomes V2, transistor 122 turns off. .

[0167] Additionally, the potential at node 119, 206, becomes V2, and transistor 123 turns off. .

[0168] Furthermore, at this time, the potential of the output signal 209 output via terminal 121 is terminal 104J The potential V2 supplied via this becomes equivalent to this value. This concludes the operation during the fifth period.

[0169] As described above, the drive circuit in Figure 4 has the effect of the circuit configuration shown in Figure 1, in addition to the output By splitting the signal into multiple signals, one output signal is output to the next stage flip-flop circuit. By outputting the other output signal to the gate terminal of the pixel transistor, the flip-flop This allows the rop circuit to output an output signal with minimal deviation, thereby suppressing malfunctions. Cut.

[0170] Furthermore, in this embodiment, a configuration is formed by combining the configuration in Figure 3 and the configuration in Figure 4. It is also possible to do so. Other configurations of the drive circuit in this embodiment will be explained with reference to Figure 6. Figure 6 is a circuit diagram showing another configuration of the drive circuit of this embodiment.

[0171] In addition to the circuit configuration shown in Figure 1, the other configurations of the drive circuit in this embodiment shown in Figure 6 are as follows: Terminals 103D, 104K, 104L, 104M, 125, Transistor It has transistors 126, 127, 128, and 129.

[0172] In Figure 6, elements that are denoted by the same reference numerals as in Figure 1 are defined as the drive cycles in Figure 1. Since it is the same element as the circuit, we will refer to the explanation of each element in Figure 1.

[0173] Furthermore, in Figure 6, terminal 103D corresponds to terminal 103C in Figure 4, and terminal 104K Terminal 104H corresponds to terminal 104H in Figure 3, and terminal 104L corresponds to terminal 104I in Figure 4. Terminal 104M corresponds to terminal 104J in Figure 4, and terminal 125 corresponds to terminal 104J in Figure 4. Transistor 126 corresponds to transistor 120 in Figure 3, and Transistor 127 corresponds to transistor 122 in Figure 4, and transistor 128 corresponds to Figure This corresponds to transistor 123 in 4, and transistor 129 is the transistor in Figure 4. This corresponds to Ta124. For explanations of each element, see the explanations of each element in Figures 3 and 4. We will use the Ming Dynasty as a tool.

[0174] Furthermore, the operation of the drive circuit in Figure 6 is explained by the operation of the drive circuit in Figures 3 and 4. Since this is a combined system, we will refer to the explanation of the operation of the drive circuit shown in Figures 3 and 4.

[0175] By using the configuration shown in Figure 6, the effectiveness of each of the drive circuits in the configurations shown in Figures 3 and 4 is reduced. The same effect as the fruit can be obtained.

[0176] (Embodiment 2) In this embodiment, a drive circuit with a different configuration from that of Embodiment 1 described above will be explained.

[0177] The drive circuit in this embodiment is a shift resistance consisting of multiple flip-flop circuits. It has a ta.

[0178] Furthermore, regarding an example of the circuit configuration of the flip-flop circuit in the drive circuit of this embodiment... This will be explained using Figure 7. Figure 7 shows the flip-flop circuit in the drive circuit of this embodiment. This is a circuit diagram showing an example of the circuit configuration.

[0179] The flip-flop circuit shown in Figure 7 has terminals 500, 501, 502, and Child 503, terminal 504, terminal 505, transistor 506, transistor 507 And transistor 508, transistor 509, capacitive element 510, and transistor 5 It has transistor 11, transistor 512, transistor 513, and transistor 514. ru.

[0180] In this embodiment, terminal 502 refers to terminals 502A and 502B. However, it is not limited to this, and terminals 502A and 502B are electrically connected, It can also be designated as terminal 502. In this embodiment, terminal 503 is designated as terminal 50 Although terminals 3A and 503B are shown, the text is not limited to these, and terminals 503A and 503 B can also be electrically connected to form a single terminal 503.

[0181] Furthermore, in this embodiment, terminals 504A to 504E are shown as terminals 504. However, it is not limited to this, and terminals 504A to 504E are electrically connected, It can also be designated as terminal 504.

[0182] Transistor 506 has its gate terminal electrically connected to terminal 502A, and its source terminal and One of the drain terminals is electrically connected to terminal 500.

[0183] Furthermore, transistor 507 has its gate terminal electrically connected to terminal 500, and its source terminal And one of the drain terminals is electrically connected to the gate terminal of transistor 507, source The other terminal of the source terminal and drain terminal of transistor 506 It is electrically connected to the following. For convenience, it is not shown in the diagram, but in this embodiment, the transistor The circuit area can also be reduced by omitting the TA507 component.

[0184] Furthermore, transistor 508 has its gate terminal electrically connected to terminal 501, and its source terminal And one of the drain terminals is connected to the source terminal and the other of the drain terminals of transistor 507. The source terminal and the other drain terminal are electrically connected to terminal 504A. For convenience, the flip-flop cycle of the drive circuit in this embodiment is not shown in the diagram. By omitting the transistor 508 in the circuit, the circuit area can be reduced. It is also possible.

[0185] The capacitive element 510 has at least two terminals, one of which is electrically connected to terminal 503A Connected.

[0186] Furthermore, the gate terminal of transistor 509 is electrically connected to the other terminal of the capacitive element 510. Furthermore, one of the source terminals and drain terminals of transistor 506 is connected to the source terminal and drain terminal. The other end of the terminal is electrically connected, and the other end of the source terminal and drain terminal is connected to terminal 504B. It is electrically connected.

[0187] Furthermore, transistor 511 has a gate terminal that is connected to the source terminal and slave terminal of transistor 506. The other terminal is electrically connected to the transistor 5, and one of the source terminal and drain terminal is connected to the transistor 5 It is electrically connected to the gate terminal of 09, and the other of the source terminal and drain terminal is terminal 504 It is electrically connected to C.

[0188] Furthermore, transistor 512 has a gate terminal that is connected to the source terminal and drain terminal of transistor 506. The other end of the terminal is electrically connected, and one of the source terminal and drain terminal is connected to terminal 503B. Electrically connected, the source terminal and the other drain terminal are electrically connected to terminal 505. For convenience, the flip-flop cycle of the drive circuit in this embodiment is not shown in the diagram. The path is separate between the gate terminal of transistor 512 and the other of the source and drain terminals. It is also possible to configure the device to include a capacitive element.

[0189] Furthermore, the gate terminal of transistor 513 is electrically connected to the gate terminal of transistor 509. Connected, with one of the source and drain terminals being connected to the source and drain terminals of transistor 512. The other end of the rain terminal is electrically connected, and the other end of the source terminal and drain terminal is terminal 504. It is electrically connected to D.

[0190] Furthermore, transistor 514 has its gate terminal electrically connected to terminal 502B, and its source terminal One of the source and drain terminals of transistor 512 is connected to the other of the source and drain terminals of transistor 512. Electrically connected, the source terminal and the other drain terminal are electrically connected to terminal 504E. It can be done.

[0191] Furthermore, the source terminal and the other drain terminal of transistor 506, and transistor 50 7, transistor 508, transistor 509, transistor 511, and transistor The connection point with 512 is called node 515. Also, the terminals of the capacitive element 510 and the transistor The connection point between transistor 509, transistor 511, and transistor 513 is called node 516. cormorant.

[0192] Furthermore, the first control signal is input to the flip-flop circuit via terminal 500, terminal A second control signal is input via 501. The first control signal and the second control signal are... Digital signals with two potential states, a high state and a low state, can be used. When using digital signals, if the input first control signal or second control signal is high When in this state (also called high level), the first electric current is supplied via terminal 500 or terminal 501. A first control signal or a second control signal, which has a predetermined potential value as a position (also called V1), When the input, the first control signal or the second control signal is in a low state (low level) (Also called the 'V2') has a second potential (also called V2) through terminal 500 or terminal 501. The first control signal is a potential value lower than a predetermined potential value in the above-mentioned high state or A second control signal is input. The potential values ​​in the high and low states are, for example, transistors. The threshold voltage value of the zista can be set appropriately, taking into consideration factors such as the high state and low state. The potential difference with respect to the state is greater than the absolute value of the threshold voltage of the transistor in the flip-flop circuit. It is preferable to set the potential values ​​in the high and low states in such a way.

[0193] Furthermore, the flip-flop circuit shown in Figure 7 has terminal 502 (terminal 502A and terminal 502 The first phase clock signal (also called the first clock signal, or CK) is transmitted via B (also called a signal) or a second phase clock signal (second clock signal, or CK) The B signal (also called the B signal) is input. The first clock signal and the second clock signal are respectively It has two potential values, a high state and a low state, and when it is in the high state (also called high level) When a clock signal, which is the first potential (also called V1), is input, and the state is low (low The bell (also called the bell) receives a clock signal, which is the second potential (also called V2). When the state is high, the potentials of the first clock signal and the second clock signal are... Preferably, the potential of the first control signal and the second control signal are equivalent to that of a waxy substance. The potentials of the first and second clock signals in the low state are the same as the potentials of the first clock signal in the low state. It is preferable that the potential of the first control signal and the second control signal are equivalent in value. Also, the high state The potential value in the low state is determined by considering, for example, the threshold voltage value of the transistor. It can be set as desired. For example, the potential difference between the high state and the low state of a flip-flop circuit The high and low states are set so that the absolute value of the threshold voltage of the internal transistor becomes greater than the absolute value of the threshold voltage. It is preferable to set the potential value.

[0194] Furthermore, the first clock signal and the second clock signal have different phases. Specifically, the phases are different. These are inverse relationships, for example, when the first clock signal is high for a predetermined period of time. When the second clock signal is low, and the first clock signal is low, The second clock signal is in a high state.

[0195] Furthermore, the flip-flop circuit is located at terminal 503 (also known as terminals 503A and 503B). The first or second clock signal is input via terminal 50. The clock signal input via terminal 2 and the clock signal input via terminal 503 are This is a reciprocal relationship; for example, when the first clock signal is input via terminal 502, A second clock signal is input via terminal 503, and a second clock signal is input via terminal 502. When a signal is input, the first clock signal is input via terminal 503.

[0196] Furthermore, the flip-flop circuit has terminal 504 (also known as terminals 504A to 504E) A predetermined potential is applied via (u). At this time, the predetermined potential is, for example, V1 or It can be set to V2, that is, a digital signal such as a clock signal or control signal. The potential value can be made equivalent to the potential value in state A or state L.

[0197] Transistor 506, according to the signal input via terminal 502A, controls terminal 50 It has the function of controlling the conductivity between terminal 0 and node 515, and conducts between terminal 500 and node 515. By setting it to a pass-through state, the potential of the signal input via terminal 500 and node 515 The potential of is set to an equivalent value. Also, transistor 506 is set to the same value as transistor 509. It has a function that turns it off when it is in the "on" state.

[0198] Transistor 507 responds to the signal input via terminal 500, It has a function to control the conductivity with node 515, and connects terminal 500 and node 515. By setting it to this state, the potential of node 515 is set to V1 or V2, and then deconducted. By entering a continuous state, node 515 enters a floating state.

[0199] Transistor 508, according to the signal input via terminal 501, controls terminal 504 It has a function to control the conductivity between A and node 515, and connects terminal 504A and node 515. By setting it to this state, the potential of node 515 is set to either V1 or V2.

[0200] Transistor 509, according to the potential of node 516, has terminals 504B and node 51 It has a function to control conductivity with 5, and to make terminal 504B and node 515 conductive. The potential of node 515 is set to V1 or V2. Also, transistor 509 It has the function of being in the off state when transistor 506 is in the on state.

[0201] The capacitive element 510, according to the signal input via terminal 503A, is capacitively coupled This has the function of changing the potential of node 516. For example, input via terminal 503A When the signal being treated changes from a low state to a high state, the capacitive element 510 undergoes capacitive coupling. The potential of node 516 is set to V1. Meanwhile, the signal input via terminal 503A is When the state changes from state A to state L, the capacitive element 510 is capacitively coupled to node 516. Set the potential to V1 or V2.

[0202] Transistor 511, according to the potential of node 515, has terminals 504C and node 51 It has a function to control conductivity with 6, and to make terminal 504C and node 516 conductive. This sets the potential of node 516 to either V1 or V2.

[0203] Transistor 512, according to the potential of node 515, terminals 503B and 505 It has a function to control the conductivity between terminals, and by making terminals 503B and 505 conductive, This refers to the potential of the signal input via terminal 503B and the signal output via terminal 505. The potential is set to a value equivalent to that. Also, transistor 512 is, for example, an N-type transistor When the potential of node 515 is V1, the signal input via terminal 503B is When the state changes from low to high, the potential of the signal output via terminal 505 increases. Therefore, it has the function of raising the potential of node 515. This is known as bootstrap. However, the bootstrap is connected to the gate terminal and source terminal of transistor 512. This is often done by parasitic capacitance between the drain terminal and the other terminal.

[0204] Transistor 513, according to the potential of node 516, terminals 504D and 505 It has a function to control the conductivity between terminals, and by making terminals 504D and 505 conductive, This sets the potential of the signal output via terminal 505 to either V1 or V2.

[0205] Transistor 514, according to the signal input via terminal 502B, controls terminal 50 It has a function to control the conductivity between terminal 4E and terminal 505, and connects terminal 504E and terminal 505 in a conductive state. By setting it to this state, the potential of the signal output via terminal 505 is set to V1 or V2. It is determined.

[0206] In this embodiment, the drive circuit is composed entirely of transistors of the same conductivity type. This allows for the simplification of the manufacturing process. Therefore, the manufacturing cost is This allows for reductions and improvements in yield. Furthermore, it enables the creation of semiconductor devices such as large display panels. It also becomes easier to manufacture. In the drive circuit of this embodiment shown in Figure 7, all The transistor can also be an N-type transistor or a P-type transistor.

[0207] Next, the operation of the drive circuit shown in Figure 7 will be explained using Figure 8. Figure 8 shows the drive circuit shown in Figure 7. This is a timing chart diagram showing the operation of the dynamic circuit. Note that, as an example, terminal 50 The first clock signal is input via terminal 3, and the second clock signal is input via terminal 502. We will explain it as being driven. Also, here we will use the operation of the drive circuit shown in Figure 7 as an example. This explains the case where all transistors in a pop-flop circuit are N-type transistors. ru.

[0208] As shown in Figure 8, the operation of the drive circuit in Figure 7 is a predetermined operation over a certain period of time. It is repeated. A certain period is mainly divided into an elective period and a non-elective period, and further elective The periods and non-optional periods are the first period, the second period, the third period, the fourth period, and the fifth period. It can be divided into periods. In Figure 8, these are the first period, the third period, the fourth period, and the fifth period. The first period is a non-selective period, and the second period is an elective period.

[0209] First, during the first period, a first control signal 601, which is in a high state, is input via terminal 500. Then, a second control signal 607, which is in a low state, is input via terminal 501, and terminal 502 A second clock signal 603, which is in a high state, is input via terminal 503, and a low state is input via terminal 503. When the first clock signal 602, which is in this state, is input, transistor 506, Transistor 507 and transistor 514 are turned ON, and transistor 508 is ON It enters a state of "fu".

[0210] When transistors 506 and 507 are turned on, the potential of node 515 is 6 04 is a transistor from the potential V1 of the second clock signal 603 input via terminal 502A. Threshold voltage (Vth) of ZISTA 506 506 The value obtained by subtracting (also known as) V1-Vth5 06 , or from the potential V1 of the first control signal 601 input via terminal 500 Threshold voltage (Vth) of ZISTA 507 507 The value obtained by subtracting (also known as) V1-Vth5 07 It rises until the potential at node 515 is V1-Vth. 506 or V1-Vth 507 When this happens, transistor 507 turns off. At this time, the threshold of transistor 506 It is preferable that the value voltage and the threshold voltage of transistor 507 are equivalent. In Figure 8, For example, the potential of node 515 in the second period is V1-Vth 507 Let's explain it as follows: do.

[0211] Furthermore, the potential 604 at node 515 is V1-Vth 507 When this happens, transistor 511 And transistor 512 turns ON.

[0212] Furthermore, when transistor 511 is turned ON, the potential 605 at node 516 becomes terminal 504 The potential V2 given through C becomes equivalent to a value. Furthermore, the potential at node 516 becomes V2. This causes transistors 509 and 513 to turn off.

[0213] Furthermore, at this time, the potential of the output signal 606 output via terminal 505 is, terminal 503B The potential V2 of the first clock signal 602 input via or given via terminal 504E The resulting potential V2 will be equivalent to the value obtained. This concludes the operation during the first period.

[0214] Next, in the second period, the first control signal 601, which is in a low state, is input via terminal 500. Then, a second control signal 607, which is in a low state, is input via terminal 501, and terminal 502 A second clock signal 603, which is in a low state, is input via terminals 503A and 5 The first clock signal 602, which is in a high state, is input via 03B. Transistor 506, transistor 507, and transistor 514 are turned off, The Zista 508 remains in the off state.

[0215] At this time, the potential 604 at node 515 is V1-Vth 507 It remains as is, transistor 511 remains in the ON state. Furthermore, the potential of node 515, 604, is V1-Vth 507 When this remains the case, the potential 605 at node 516 is the potential V given through terminal 504C. The value remains at 2, and transistors 509 and 513 remain in the off state.

[0216] Furthermore, as mentioned above, transistors 506, 507, and 508 When transistors 509 and 513 are in the off state, node 515 It remains in a floating state, and the potential 604 at node 515 is V1-Vth 507 It remains the same. .

[0217] Furthermore, the potential 604 at node 515 is V1-Vth 507 It remains as is, transistor 5 The potential of one of the 12 source and drain terminals is the potential V1 of the first clock signal 602. When this happens, the potential of the output signal 606, which is output via terminal 505, rises. Then, Since node 515 is in a floating state, the potential of node 604 at node 515 is due to bootstrap. , parasitic between the gate terminal of transistor 512 and the other of the source terminal and drain terminal Capacitive coupling increases the potential of the output signal 606 in accordance with the capacitance.

[0218] The potential 604 of node 515 is the same as the potential V1 of the first clock signal 602, and the transistor 512 threshold voltage (Vth 512 A value even greater than the sum of (also known as) V1 +Vth 512It rises to +Va (where Va is any positive value). At this point, transistor 51 2 remains in the ON state.

[0219] Furthermore, at this time, the potential of the output signal 606 output via terminal 505 is equal to terminal 503B. The input potential V1 becomes equivalent to this value. This concludes the operation during the second period.

[0220] Next, in the third period, the first control signal 601, which is in a low state, is input via terminal 500. Then, a second control signal 607, which is in a high state, is input via terminal 501, and terminal 502 A second clock signal 603, which is in a high state, is input via terminals A and 502B, A first clock signal 602, which is in a low state, is input via terminals 503A and 503B. At this time, transistors 506, 508, and 514 are in the ON state. As a result, transistor 507 remains in the off state.

[0221] When transistors 506 and 508 are turned on, the potential of node 515 The potential V2 of the first control signal 601 input via terminal 500 or terminal 504A The potential V2 applied through it will be equivalent to this value.

[0222] Furthermore, when the potential 604 at node 515 becomes V2, transistor 511 and the transistor Transistor 512 is turned off. Note that transistor 511 is input via terminal 502B. The first clock signal 602 often goes low and then turns off. Why? Furthermore, the potential 604 of node 515 is delayed or smudged compared to the first clock signal 602. This is because it is often present. After the first clock signal 602 goes low, the transient When terminal 511 is turned off, a value equivalent to the potential V2 supplied via terminal 504C is obtained. Node 516 remains in a floating state while being held.

[0223] Furthermore, when node 516 is in a floating state, transistors 509 and 51 3 remains in the off state.

[0224] Furthermore, the capacitive element 510 receives the first clock signal 60 via terminal 503A. The potential difference between the potential at point 2 and the potential at node 516, that is, the first clock signal in a low state. The potential difference between the potential at terminal 602 and the potential V2 provided through terminal 504C is maintained.

[0225] Furthermore, at this time, the potential of the output signal 606 output via terminal 505 is, terminal 504E This becomes equivalent to the potential V2 supplied through it. The above describes the operation during the third period.

[0226] Next, in the fourth period, the first control signal 601, which is in a low state, is input via terminal 500. Then, a second control signal 607, which is in a low state, is input via terminal 501, and terminal 502 A second clock signal 603, which is in a low state, is input via terminals A and 502B, terminal A first clock signal 602, which is in a high state, is input via terminals 503A and 503B. At this time, transistors 506, 508, and 514 are turned off. In this state, transistor 507 remains in the off state.

[0227] At this time, the potential 605 of node 516 is V2+Vb due to the capacitive coupling of the capacitive element 510. Vb is less than the threshold voltage of transistor 509 or the threshold voltage of transistor 513. It is preferable that it is large, and preferably smaller than V1-V2.

[0228] Furthermore, when the potential 605 of node 516 becomes V2+Vc, transistor 509 and the transistor When transistor 513 is turned on, transistors 509 and 513 are turned on. When this happens, the potential 604 of node 515 is the potential V2 that is given via terminal 504B, This value is equivalent to the potential V2 supplied via terminal 504D.

[0229] Furthermore, when the potential 604 of node 515 becomes V2, transistor 511 and transistor 512 will be turned off.

[0230] Furthermore, at this time, the potential of the output signal 606 output via terminal 505 is, terminal 504D This becomes equivalent to the potential V2 supplied through it. The above describes the operation during the fourth period.

[0231] Next, in the fifth period, the first control signal 601, which is in a low state, is input via terminal 500. Then, a second control signal 607, which is in a low state, is input via terminal 501, and terminal 502 A second clock signal 603, which is in a high state, is input via terminals A and 502B, A first clock signal 602, which is in a high state, is input via terminals 503A and 503B. At this time, transistors 506 and 514 turn on, and the transistors Transistors 507 and 508 remain in the off state.

[0232] At this time, the potential 605 at node 516 becomes V2 due to the capacitive coupling of the capacitive element 510. Furthermore, when the potential of node 516, 605, becomes V2, transistor 509 and transistor 513 will be turned off.

[0233] Furthermore, when the potential 604 at node 515 becomes V2, transistor 511 and the transistor The Ta512 will be turned off.

[0234] Furthermore, at this time, the potential of the output signal 606 output via terminal 505 is, terminal 504D The potential V2 supplied via this becomes equivalent to this value. This concludes the operation during the fifth period.

[0235] In the operation of the drive circuit in this embodiment, the fourth period and the fifth period are as follows: This is repeated multiple times during the non-selective period following the third period. Since a predetermined potential is applied to node 515 even during the period of misalignment, node 515 This can suppress the floating state. Therefore, the effects of noise can be reduced. Therefore, malfunctions can be suppressed.

[0236] Furthermore, in the operation of the drive circuit in this embodiment, during the fourth period and the fifth period Different transistors (transistors 506 and 509 in this embodiment) By turning it on, a predetermined potential value can be applied to node 515, for example. Even when using transistors in which the semiconductor layer is an amorphous semiconductor, each transistor Degradation can be suppressed. Therefore, the timing shift in transistor operation due to degradation can be reduced. Because it can be reduced, malfunctions can be suppressed.

[0237] Furthermore, the drive circuit in this embodiment uses fewer elements compared to the configuration of the above embodiment. Because it can be configured in this way, the circuit area can be reduced.

[0238] Furthermore, in this embodiment, a drive circuit that is one aspect of the present invention is used with a configuration different from that shown in Figure 7. It is also possible to do so. Other configurations of the drive circuit in this embodiment will be explained with reference to Figure 9. Figure 9 is a circuit diagram showing an example of the configuration of the drive circuit in this embodiment.

[0239] The drive circuit shown in Figure 9 has the same circuit configuration as the drive circuit shown in Figure 7, plus terminal 504F and a transistor It has a 517 radiator.

[0240] Note that in the drive circuit shown in Figure 9, the same reference numerals are used as in the drive circuit shown in Figure 7. Since this is the same as the drive circuit shown in Figure 7, we will omit the explanation.

[0241] Transistor 517 has its gate terminal electrically connected to terminal 500, and its source terminal and One of the drain terminals is electrically connected to the gate terminal of transistor 509, and the source terminal The other end of the drain terminal is electrically connected to terminal 504F.

[0242] In the drive circuit shown in Figure 9, terminal 504F is connected to terminals 504A to terminals shown in Figure 7. A potential equivalent to that of 504E is applied. Also, terminals 504A to 504F are electrically connected. This allows it to be treated as a single terminal 504.

[0243] Transistor 517, according to the signal input via terminal 500, connects terminal 504F and It has a function to control the conductivity with node 516, and connects terminal 504F and node 516 to a conductive state. This sets the potential of node 516 to either V1 or V2.

[0244] Next, the operation of the drive circuit shown in Figure 9 will be explained. This section will only explain the operation of transistor 517, and will not explain the operation of elements other than transistor 517. The operation is identical to that of the drive circuit shown in Figure 7, so the explanation is omitted. Also, here, Figure As an example of the operation of the drive circuit shown in 9, all transistors in the flip-flop circuit are N Let's explain the case of a transistor.

[0245] During the first period, a first control signal 601, which is in a high state, is input via terminal 500. At this point, transistor 517 turns ON.

[0246] When transistor 517 is turned on, the potential of node 516 is supplied via terminal 504F. The resulting potential V2 will be equivalent to a value of the same magnitude.

[0247] Subsequently, during the second to fifth periods, the first control, which is in a low state via terminal 500, When signal 601 is input, transistor 517 turns off.

[0248] As described above, the drive circuit shown in Figure 9 has the effect of the circuit configuration shown in Figure 7, in addition to the first During period 1, the first control signal 601 is directly input to transistor 517, and the transistor By turning on terminal 517, the potential of node 516 can be more reliably determined during the first period. It can indeed be set to potential V2.

[0249] Furthermore, in this embodiment, a different configuration from that shown in Figures 7 and 9 is used to represent one aspect of the present invention. It can also be used as a drive circuit. Figure 10 shows another configuration of the drive circuit in this embodiment. This will be explained using the following. Figure 10 shows an example of the circuit configuration of the drive circuit in this embodiment. This is a diagram.

[0250] The drive circuit configuration shown in Figure 10 is the same as the circuit configuration shown in Figure 7, but with terminals 503C and 50 4G, terminal 504H, terminal 518, transistor 519, transistor 520, and transistor It has a 521 meter.

[0251] Note that for elements in Figure 10 that are given the same reference numerals as in Figure 7, the same reference numerals are used in Figure 7. Since these are the same elements as those in the dynamic circuit, we will refer to the explanation of each element in Figure 7.

[0252] Transistor 519 has its gate terminal connected to the source and drain terminals of transistor 506. The other side is electrically connected, and one of the source terminal and drain terminal is electrically connected to terminal 503C. It connects to the target.

[0253] Furthermore, the gate terminal of transistor 520 is electrically connected to the gate terminal of transistor 509. Connected, with one of the source and drain terminals being connected to the source and drain terminals of transistor 519. The other end of the rain terminal is electrically connected, and the other end of the source terminal and drain terminal is terminal 504. It is electrically connected to G.

[0254] Furthermore, the gate terminal of transistor 521 is electrically connected to the gate terminal of transistor 514. Connected, with one of the source and drain terminals being connected to the source and drain terminals of transistor 519. The other end of the rain terminal is electrically connected, and the other end of the source terminal and drain terminal is terminal 504. Electrically connected to H

[0255] Transistor 519, according to the potential of node 515, has terminals 503C and 518 By making the two terminals conductive, the potential of the signal input via terminal 503C and the output via terminal 518 are connected. It has the function of making the potential of the signal being powered equal to the value of V1. In this case, the potential of the signal input via terminal 503C changes from a low state to a high state. Then, transistor 519 has the source terminal and drain terminal of transistor 519 and the other It has the function of raising the potential of node 515 in accordance with the rise in potential of . This is a bootstrap. The bootstrap connects to the gate terminal of transistor 519 and the saw This is often done by parasitic capacitance between the other terminal of the power supply and the drain terminal.

[0256] Transistor 520, according to the potential of node 516, terminals 504G and 518 Set the terminals to conduct and set the potential of the signal output via terminal 518 to V1 or V2. It has a function.

[0257] Transistor 521 responds to the signal input via terminal 502B, and terminal 50 Connect 4H and terminal 518 to create a conductive state, and set the potential of the signal output through terminal 518 to V1 or It has the function to set to V2.

[0258] Next, the operation of the drive circuit in Figure 10 will be explained using Figure 11. This is a timing chart showing an example of the operation of the drive circuit in this configuration. The operation of the drive circuit is as follows: transistor 519, transistor 520, and This section will only explain the operation of the ZISTA 521, and will focus on the parts that are identical to the operation of the elements in the drive circuit shown in Figure 7. Accordingly, the explanation of the operation of the drive circuit in Figure 7 will be used as appropriate. Note the terminals in Figure 10. The 503C will be described assuming that a first clock signal is input to it. This is shown in Figure 10. As an example of the operation of a drive circuit, all the transistors in the flip-flop circuit are N-type transistors. Let's explain the case of the 'njista'.

[0259] During the first period, in addition to the operation of the circuit shown in Figure 7, the terminal 503C is in a low state. The first clock signal 602 is input. At this time, transistor 521 turns on. .

[0260] At this time, the potential 604 at node 515 is V1-Vth 507 Transistor 511 It turns on. Furthermore, when transistor 511 turns on, transistor 520 It will turn off.

[0261] Also, the potential of node 515 is 604, which is V1-Vth 507 When this happens, transistor 512 It will be turned on.

[0262] Furthermore, at this time, the potential of the output signal 608 output via terminal 518 is the same as terminal 503C. The potential V2 of the first clock signal input via or given via terminal 504H The potential V2 becomes equivalent to this value. The above describes the operation during the first period.

[0263] Next, in the second period, in addition to the operation of the circuit shown in Figure 7, the terminal 503C is in a high state. A first clock signal 602 is input. At this time, transistor 521 is turned off. Yes.

[0264] At this time, the potential 604 at node 515 is V1-Vth 507 It remains as is, transistor 511 remains in the ON state. Furthermore, when transistor 511 remains in the ON state Transistor 520 remains in the off state.

[0265] Furthermore, at this time, node 515 remains in a floating state, and the potential 604 of node 515 is, V1-Vth 507 It remains as it is.

[0266] Furthermore, the potential 604 at node 515 is V1-Vth 507 It remains as is, source terminal and When the potential of one of the drain terminals becomes the potential V1 of the first clock signal 602, the transistor Capacitance due to parasitic capacitance between the gate terminal of 519 and the other of the source and drain terminals. The coupling causes the potential 604 at node 515 to rise in line with the potential of the output signal 608. At this time, the potential 604 of node 515 is the same as the potential V1 of the first clock signal 602, and Threshold voltage (Vth) of ZISTA 512 512 The sum of (also known as) and the first clock signal 6 The potential V1 of 02 and the threshold voltage (Vth) of transistor 519 519 (Also known as) An even larger value, namely V1 + Vth 512 +Va, or V1+Vth 519 +V It increases to a (where Va is any positive value).

[0267] Furthermore, the potential of node 515, 604, is V1+Vth 512 +Va or V1+Vth 51 When the current is 9 + Va, transistor 519 remains ON.

[0268] Furthermore, the value of the output signal 608 output via terminal 518 at this time is transmitted via terminal 503C. This becomes equivalent to the potential V1 of the first clock signal 602 that is input. It is an action that occurs in between.

[0269] Next, in the third period, in addition to the operation of the circuit shown in Figure 7, the terminal 503C is in a low state. A first clock signal 602 is input. At this time, transistor 521 turns ON. Yes.

[0270] At this time, the potential 605 at node 516 remains equivalent to the potential V2. Node 516 When the potential of 605 is V2, node 516 becomes floating. When this is the case, transistor 520 remains in the off state.

[0271] Furthermore, at this time, the potential of the output signal 608 output via terminal 518 is the same as terminal 504H. The value becomes equivalent to the potential V2 supplied through it. This concludes the operation during the third period.

[0272] Next, in the fourth period, in addition to the operation of the circuit shown in Figure 7, the terminal 503C is in a high state. A first clock signal 602 is input. At this time, transistor 521 is turned off. Yes.

[0273] At this time, the potential 605 at node 516 becomes V2+Vb, and the potential 605 at node 516 When V2 + Vb equals the value of transistor 520, transistor 520 turns on.

[0274] Furthermore, the potential 604 at node 515 is equivalent to the potential V2 provided via terminal 504B. The value becomes V2. When the potential 604 at node 515 becomes V2, transistor 519 turns off. ru.

[0275] Furthermore, at this time, the potential of the output signal 608 output via terminal 518 is the same as terminal 504G. The potential V2 supplied through it becomes equivalent to this value. This concludes the operation during the fourth period.

[0276] Next, in the fifth period, in addition to the operation of the circuit shown in Figure 7, terminal 503C is in a low state. A first clock signal 602 is input. At this time, transistor 521 turns ON. Yes.

[0277] At this time, when the potential 604 at node 515 becomes V2, transistor 519 turns off. ru.

[0278] Furthermore, when the potential 605 at node 516 becomes V2, transistor 520 turns off. .

[0279] Furthermore, at this time, the potential of the output signal 608 output via terminal 518 is the same as terminal 504H. The potential V2 supplied through it becomes equivalent to this value. This concludes the operation during the fifth period.

[0280] As described above, the flip-flop circuit in the drive circuit shown in Figure 10 duplicates the output signal. By doing so, one output signal is output to the next stage flip-flop circuit, and the other... By outputting the output signal to the gate terminal of the pixel transistor, the flip-flop circuit It can output an output signal with minimal deviation from the path, thereby suppressing malfunctions.

[0281] Furthermore, the flip-flop circuit in the drive circuit of this embodiment has the configuration shown in Figure 7. A configuration can also be formed by combining the configurations shown in Figure 10. Other configurations of the flip-flop circuit in this book are explained using Figure 12. This is a circuit diagram showing another configuration of the flip-flop circuit in the drive circuit of the embodiment.

[0282] Other configurations of the drive circuit for the flip-flop circuit in this embodiment shown in Figure 12 are shown in Figure In addition to the circuit configuration shown in 7, terminals 503D, 504I, 504J, and 504K are also included. Terminal 522, transistor 523, transistor 524, transistor 525, and transistor It has a 526 meter.

[0283] In Figure 12, elements that have the same reference numerals as those in Figure 7 are the drive elements in Figure 7. Since these are the same elements as those in the circuit, refer to the explanation of each element in Figure 7 as appropriate.

[0284] Also, in Figure 12, terminal 503D corresponds to terminal 503C in Figure 10, and terminal 5 04I corresponds to terminal 504F in Figure 9, and terminal 504J corresponds to terminal 504 in Figure 10. G corresponds to terminal 504K, terminal 504H corresponds to terminal 504H in Figure 10, and terminal 522 corresponds to terminal 504H in Figure 10. It corresponds to terminal 518 in Figure 9, and transistor 523 corresponds to transistor 517 in Figure 9. In this context, transistor 524 corresponds to transistor 519 in Figure 10, and the transistor Transistor 525 corresponds to transistor 520 in Figure 10, and transistor 526 corresponds to in Figure 10. This corresponds to transistor 521. For explanations of each element, please refer to Figure 9 and Figure 9 as appropriate. Refer to the explanation of each element in section 10.

[0285] Furthermore, the operation of the drive circuit in Figure 12 is similar to the operation of the drive circuit in Figures 9 and 10. Since this is a combination of different designs, please refer to the explanation of the operation of the drive circuit in Figures 9 and 10 as appropriate. To use as a reference.

[0286] As described above, by using the configuration shown in Figure 12, the drive circuit shown in Figures 9 and 10 is equivalent to that of the drive circuit shown in Figures 9 and 10. Those effects can be obtained.

[0287] Furthermore, this embodiment can be appropriately combined with other embodiments.

[0288] (Embodiment 3) This embodiment describes the configuration of a display device using a drive circuit, which is one aspect of the present invention. I will reveal it.

[0289] First, the configuration of the display device of this embodiment will be explained using Figure 13. This block diagram shows an example of the configuration of a display device in the form of a device.

[0290] The display device shown in Figure 13 comprises a pixel unit 700, a signal line driving circuit 701, and a scan line driving circuit 702, control circuit 703, clock signal generation circuit 704, signal line 705A, signal scan line 705B, scan line 706A, scan line 706B, scan line 706C, scan line 706 It has D, clock signal line 707, and clock signal line 708. (See Figure 13) In the display device, scan line 706A, scan line 706B, scan line 706C, or scan line 7 06D is also simply called scan line 706. Note that in the display device shown in Figure 13, signal line 705 A or signal line 705B is also simply called signal line 705. Also, in Figure 13, the two signal lines and Although four scan lines are shown in the diagram, the number of signal lines and scan lines in the display device of this embodiment is different. The number of signal lines and scan lines is not particularly limited and can also be configured to have other numbers of signal lines and scan lines. By increasing the number of scan lines, display operation can be performed even when the number of pixels is increased. It is possible.

[0291] Furthermore, the pixel section 700 has multiple pixels 709. Note that in Figure 13, the pixels 709 are 8 Although only one is shown in the illustration, the display device of this embodiment is not limited to this, and may be composed of other numbers. It is also possible to increase the number of pixels in the same pixel area to make it sharper. It can be displayed.

[0292] Furthermore, in the pixel section 700, the pixel 709 is one of the multiple signal lines 705. Electrically connected to the signal line drive circuit 701 via the signal line 705, and multiple scan lines 70 Of the 6, one of the scan lines 706 is electrically connected to the scan line drive circuit 702. It can be done.

[0293] Furthermore, the scan line drive circuit 702 has a shift register, and the shift register is a first A flip-flop that forms a lip-flop circuit (also called a first-stage flip-flop circuit) Circuit 710A and the second flip-flop circuit (also called the second stage flip-flop circuit). ) a flip-flop circuit 710B and a third flip-flop circuit (3rd stage flip The flip-flop circuit 710C (also called a flip-flop circuit) and the fourth flip-flop Flip-flop circuit 71, which is a lop circuit (also called a 4th stage flip-flop circuit) It has 0D and, in addition, flip-flop circuit 710A, flip-flop circuit 710 B. Simply flip the flip-flop circuit 710C or flip-flop circuit 710D Also called a flip-flop circuit 710. In the display device of this embodiment, The number of flip-flop circuits is not limited to the number of flip-flop circuits shown in Figure 13, but can be any other number (N stages). N can also be a natural number. For example, by increasing the number of flip-flop circuits. Therefore, it is possible to control more signal lines, which is useful when increasing the area of ​​the pixel. It is effective.

[0294] Furthermore, in the display device of this embodiment, the flip-flop circuit 710 is configured as described above. The flip-flop circuit configuration of any of Embodiments 1 to 3 can be applied. In the display device shown in Figure 13, as an example, a flip-flop circuit with the configuration of Figure 1 is applied. Let me explain the details. In the display device shown in Figure 13, the scanning line driving circuit is one aspect of the present invention. We will describe an example of applying a drive circuit of this embodiment, but it is not limited to this example. In the display device, a drive circuit according to one aspect of the present invention is also applied to the signal line drive circuit. It is possible.

[0295] For example, in a configuration with N stages (where N is a natural number greater than or equal to 2) of flip-flop circuits 710 The first stage flip-flop circuit has terminal 100 shown in Figure 1 that electrically connects to the control circuit 703. The terminal 105 shown in Figure 1 is connected and electrically contacts the pixel 709 via the first scan line 706. It will continue.

[0296] The N-th stage flip-flop circuit 710 has terminal 100 shown in Figure 1 at the N-1 stage It is electrically connected to terminal 105 of the flip-flop circuit 710, and terminal 105 as shown in Figure 1 The flip-flop circuit 710 in the (N-1) stage is electrically connected to terminal 101 shown in Figure 1. It is also electrically connected to the pixel 709 via the K scan line 706.

[0297] Furthermore, the odd-numbered flip-flop circuits 710 have terminal 102, shown in Figure 1, which is a clock signal. Electrically connected to the clock signal generation circuit 704 via wire 708, terminal 1 shown in Figure 1 03 is electrically connected to the clock signal generation circuit 704 via the clock signal line 707. .

[0298] Furthermore, the flip-flop circuit 710 in even-numbered stages has terminal 102, shown in Figure 1, which is the clock signal Electrically connected to the clock signal generation circuit 704 via wire 707, terminal 1 shown in Figure 1 03 is electrically connected to the clock signal generation circuit 704 via the clock signal line 708. .

[0299] Furthermore, the configuration of the scan line drive circuit 702 shown in Figure 13 will be explained in detail.

[0300] Furthermore, in the scan line drive circuit 702 shown in Figure 13, the flip-flop circuit 710A is Terminal 100 shown in Figure 1 is electrically connected to the control circuit 703, and terminal 102 shown in Figure 1 is It is electrically connected to the clock signal generation circuit 704 via the clock signal line 708, as shown in Figure 1. The terminal 103 shown is electrically connected to the clock signal generation circuit 704 via the clock signal line 707. The terminal 105 shown in Figure 1 is electrically connected to the pixel 709 via the scan line 706A. It can be done.

[0301] Furthermore, the flip-flop circuit 710B has terminal 100 as shown in Figure 1, which is the flip-flop circuit Terminal 105 of 710A is electrically connected, and terminal 102 shown in Figure 1 is the clock signal line 70 It is electrically connected to the clock signal generation circuit 704 via 7, and terminal 103 shown in Figure 1 is It is electrically connected to the clock signal generation circuit 704 via the lock signal line 708, as shown in Figure 1. Terminal 105 is electrically connected to terminal 101 shown in Figure 1 of the flip-flop circuit 710A. Furthermore, it is electrically connected to pixel 709 via scan line 706B.

[0302] Furthermore, the flip-flop circuit 710C has terminal 100 as shown in Figure 1, which is part of the flip-flop circuit. Terminal 105 in 710B is electrically connected, and terminal 102 shown in Figure 1 is the clock signal Electrically connected to the clock signal generation circuit 704 via line 708, terminal 10 shown in Figure 1 3 is electrically connected to the clock signal generation circuit 704 via the clock signal line 707, as shown in Figure Terminal 105 shown in 1 is connected to terminal 101 shown in Figure 1 of the flip-flop circuit 710B. It is electrically connected and also electrically connected to pixel 709 via scan line 706C.

[0303] Furthermore, the flip-flop circuit 710D has terminal 100 as shown in Figure 1, which is the flip-flop circuit. Terminal 105 in the 710C is electrically connected, and terminal 102 shown in Figure 1 is the clock signal Electrically connected to the clock signal generation circuit 704 via line 707, terminal 10 shown in Figure 1 3 is electrically connected to the clock signal generation circuit 704 via the clock signal line 708, as shown in Figure Terminal 105 shown in 1 is connected to terminal 101 shown in Figure 1 of the flip-flop circuit 710C. It is electrically connected and also electrically connected to pixel 709 via scan line 706D.

[0304] The clock signal generation circuit 704 outputs a first clock signal via the clock signal line 707. It outputs the first clock signal and also outputs a second clock signal via the clock signal line 708. The clock signal and the second clock signal are, respectively, the first clock signal in the first embodiment described above. Since the first clock signal and the second clock signal are the same, the description of Embodiment 1 can be adjusted as appropriate. To use as a reference.

[0305] The control circuit 703 sends a first control signal that initiates the operation of the flip-flop circuit. Then a start signal is output. The start signal is the first control in the above embodiment 1. Since it is the same as the signal, we will refer to the explanation of the first control signal in Embodiment 1. Circuit 703 can also be configured to be electrically connected to signal line drive circuit 701. By configuring the circuit 703 and the signal line drive circuit 701 to be electrically connected, The desired operation can also be performed using a control signal in the line drive circuit 701.

[0306] Next, the operation of the display device shown in Figure 13 will be explained.

[0307] First, the operation of the scan line drive circuit 702 will be explained using Figure 14. Figure 14 is the same as Figure 13. This timing chart shows an example of the operation of the scan line drive circuit in the display device shown. Here, as an example, we will describe the case where a flip-flop circuit is constructed using an N-type transistor. I will explain.

[0308] The operation of the scan line drive circuit 702 shown in Figure 13 depends on the number of stages N of the flip-flop circuit. It can be divided into T (where T is a natural number) periods. Here, as an example, let's assume T=8, and Figure 13 shows the result. The four flip-flop circuits 710A to 710D shown The operation of the RIP circuit will be explained.

[0309] First, in the first period, the flip-flop circuit 710A receives a flip-flop signal from the control circuit 703. A start signal 801, which is in a high state, is input via terminal 100 in the rop circuit 710A. Then, a second clock signal 803, which is in a high state, is input via terminal 102, and terminal 10 A first clock signal 802, which is in a low state, is input via 3. The first period here The operation corresponds to the operation during the first period of the timing chart shown in Figure 2 in the above embodiment 1. It corresponds to this.

[0310] Next, in the second period, the flip-flop circuit 710A receives a flip-flop signal from the control circuit 703. The start signal 801, which is in a low state, is input via terminal 100 in the rop circuit 710A. Then, a second clock signal 803, which is in a low state, is input via terminal 102, and terminal 10 The first clock signal 802, which is in a high state, is input via 3. At this time, terminal 105 The terminal 100 of the flip-flop circuit 710B and the scan line 706A are in a high state via this. It outputs a certain output signal 804.

[0311] In the second period, the flip-flop circuit 710B is connected to the flip-flop circuit via terminal 100. The output signal 804 of the rop circuit 710A is input and, via terminal 102, is in a high state. A clock signal 802 is input, and a second clock, which is low, is input via terminal 103. Signal 803 is input.

[0312] Next, in the third period, the flip-flop circuit 710B is in a low state via terminal 100. An output signal 804 is input, and a first clock signal that is low is input via terminal 102. 802 is input, and a second clock signal 803, which is high, is input via terminal 103. At this time, terminal 105 is connected to terminal 100 of the flip-flop circuit 710C, flip The output signal is high at terminal 101 of the pop-flop circuit 710A and at scan line 706B. Output 805.

[0313] In the third period, the flip-flop circuit 710C is in a high state via terminal 100. An output signal 805 is input, and a second clock signal is high via terminal 102. 803 is input, and the first clock signal 802, which is low, is input via terminal 103. It will be done.

[0314] Next, in the fourth period, the flip-flop circuit 710C is in a low state via terminal 100. An output signal 805 is input, and a second clock signal, which is low, is input via terminal 102. 803 is input, and the first clock signal 802, which is high, is input via terminal 103. At this time, terminal 105 is connected to terminal 100 of the flip-flop circuit 710D, flip Output signal 806 is output to terminal 101 of the floppy circuit 710B and scan line 706C. ru.

[0315] Furthermore, during the fourth period, the flip-flop circuit 710D is in a high state via terminal 100. A certain output signal 806 is input as the first control signal and is in a high state via terminal 102. The first clock signal 802 is input, and the second clock signal, which is in a low state, is input via terminal 103. A signal 803 is input.

[0316] Next, in the fifth period, the flip-flop circuit 710D is in a low state via terminal 100. A certain output signal 806 is input as the first control signal, and is in a low state via terminal 102. A first clock signal is input, and a second clock signal, which is in a high state, is input via terminal 103. A number is input. At this time, terminal 105 is used to input terminal 10 of the next stage flip-flop circuit. 0, output signal 807 to terminal 101 of flip-flop circuit 710C, and scan line 706D This outputs [the specified value]. The above describes the operation of the scan line drive circuit.

[0317] Next, we will explain the operation of the pixel section.

[0318] First, the scan line driving circuit 702 selects one of several scan lines 706. Pixel 709, electrically connected to the scanned scan line 706, receives a signal from the signal line drive circuit 701. A signal is input via line 705, a predetermined potential is applied to the display element, and the display operation is performed. Then, as another scan line 706 is selected sequentially, the other pixels perform the same display operation. The above describes the operation of the pixel section.

[0319] As described above, the display device in this embodiment drives a drive circuit which is one aspect of the present invention. By using it as a line drive circuit, after the flip-flop circuit is reset, Therefore, since changes in the signal value can be suppressed, malfunctions can be prevented. It can do this. Furthermore, it can maintain the desired potential in each scan line, thus improving reliability. It is possible.

[0320] Furthermore, a liquid crystal display device can be used as the display device in this embodiment, for example. The following describes its application to liquid crystal display devices.

[0321] The operating modes of the liquid crystal elements applicable to the liquid crystal display device in this embodiment are TN (Twisted Nematic) mode, IPS (In-Plane Switch) ing) mode, FFS (Fringe Field Switching) mode, M VA (Multi-domain Vertical Alignment) mode, P VA(Patterned Vertical Alignment) mode, ASM( Axially Symmetrically aligned Micro-cell) mode , OCB (Optical Compensated Birefringence) FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode You can use things like "do".

[0322] Next, regarding the pixel configuration and pixel operation applicable to the liquid crystal display device in this embodiment... I will explain.

[0323] First, Figure 15(A) shows the pixel configuration applicable to the liquid crystal display device in this embodiment. This will be explained using the following. Figure 15(A) shows the configuration of the pixel section of the liquid crystal display device in this embodiment. This is a circuit diagram showing an example.

[0324] The pixel section shown in Figure 15(A) includes pixel 750, wiring 754, wiring 755, wiring 756, and The pixel 750 has wiring 757, and the pixel 750 has a transistor 751, a liquid crystal element 752, and a capacitance element It has 753 children.

[0325] Transistor 751 has its gate terminal electrically connected to wiring 755, and its source terminal and One of the drain terminals is electrically connected to wiring 754.

[0326] The liquid crystal element 752 has a first terminal, a second terminal, and a liquid crystal layer, and the first terminal is a transistor The second terminal is electrically connected to the source terminal and the other drain terminal of 751, and the second terminal is wired to 757. It is electrically connected to it.

[0327] The capacitive element 753 has at least two terminals, one of which is the first terminal of the liquid crystal element 752. One terminal is electrically connected to the other terminal, which is electrically connected to wiring 756.

[0328] Wiring 754 can function, for example, as a signal line. The signal line is outside the pixel or This is wiring for transmitting a data signal, which is a predetermined potential, to pixel 750.

[0329] Wiring 755 can function as a scan line. The scan line is for transistor 751. This is wiring for controlling the ON and OFF states.

[0330] Wiring 756 can function as a capacitance line. The capacitance line is connected to the terminal of the capacitance element 753. This is wiring for applying a predetermined voltage.

[0331] The transistor 751 can be used as a switch.

[0332] Capacitor element 753 can function as a retaining capacitor. Capacitor element 753 is a transistor When the zista 751 is in the off state, the voltage applied to the liquid crystal element 752 is maintained for a certain period of time. It is a capacitive element for that purpose.

[0333] Wiring 757 can function as a counter electrode for the liquid crystal element 752. The counter electrode is This is wiring for applying a predetermined voltage to the liquid crystal element 752.

[0334] Furthermore, the function of each wire is not limited to these, and various functions can be added. For example, by changing the potential applied to the wiring that functions as a capacitance line, the liquid crystal element 752 The voltage supplied to it can also be adjusted.

[0335] Furthermore, transistor 751 only needs to function as a switch, so transistor 751 The polarity can be P-type or N-type.

[0336] Figure 15 shows other pixel configurations applicable to the liquid crystal display device in this embodiment. Let's explain using Figure B). Figure 15(B) shows the pixel section of the liquid crystal display device in this embodiment. This circuit diagram shows an example of another configuration.

[0337] The pixel configuration shown in Figure 15(B) is different from the pixel configuration shown in Figure 15(A), Line 757 is omitted, and the terminals of the liquid crystal element 752 and the terminals of the capacitive element 753 are electrically connected. Except for the difference in the points of connection, the configuration is the same as the pixel section shown in Figure 15(A). The pixel area shown in Figure 15(B) is particularly characterized by the liquid crystal element being in lateral field mode (IPS mode, FFS). It is preferable to apply this when the liquid crystal element is a transverse electric field mode. In the case of a code, the electrodes that become part of the terminals of the liquid crystal element 752 and the terminals of the capacitive element 753 Since some of the electrodes can be formed on the same substrate, the electrodes of the liquid crystal element 752 and This is because it is easy to electrically connect the electrodes of the capacitive element 753. Also, Figure 1 By using the pixel configuration shown in 5(B), the wiring 757 can be omitted, thus simplifying the manufacturing process. It can be shortened, which can reduce manufacturing costs.

[0338] Note that the pixel section shown in Figure 15(A) or Figure 15(B) has multiple pixels arranged in a matrix. This configuration allows for the placement of various elements. This allows the display unit of the liquid crystal display device to be formed, and Various images can be displayed.

[0339] The configuration of a pixel section having multiple pixels will be explained using Figure 15(C). C) is a circuit diagram showing an example of the configuration of the pixel section of the liquid crystal display device in this embodiment.

[0340] The pixel section shown in Figure 15(C) consists of multiple pixels 750, as shown in Figure 15(A), arranged in a matrix. This is the configuration. In Figure 15(C), four of the multiple pixels in the pixel area are shown. Extract and show the pixel located at column i, row j (where i and j are natural numbers), and define the pixel as pixel 750_i,j This is how it is written. In the pixel section shown in Figure 15(C), pixels 750_i,j are connected to wiring 754_ i is electrically connected to wiring 755_j and wiring 756_j, and pixel 750_i+1,j is, Wiring 754_i+1, wiring 755_j, and wiring 756_j are electrically connected, and pixel 750 _i,j+1 are electrically connected to wiring 754_i, wiring 755_j+1, and wiring 756_j+1. Connected, pixels 750_i+1,j+1 are wired to 754_i+1, wired to 755_j+1, It is electrically connected to wiring 756_j+1. Furthermore, in the pixel section shown in Figure 15(C), Each wiring can also be shared by multiple pixels belonging to the same column or row. (See Figure 15(C)) In the pixel section shown, the wiring 757 is a counter electrode, and the counter electrode is present in all pixels. Since they are common, wiring 757 will not be represented by the natural number i or j. In this embodiment, the liquid crystal display device uses the pixel configuration shown in Figure 15(B). Since it is also possible, even if the configuration lists wiring 757, wiring 757 is not required. Alternatively, it can be omitted by sharing it with other wiring, etc.

[0341] Furthermore, the pixels in the pixel section shown in Figure 15(C) can be driven by various methods. In particular, by driving using a method called AC driving, the deterioration of the liquid crystal elements ( This can suppress burn-in. The pixels in the pixel section shown in Figure 15(C) are driven by AC power. The operation when driven by this method will be explained using Figure 15(D). Figure 15(D) is a reference to Figure 1 This is a timing chart diagram showing the operation of the pixels in the pixel section shown in 5(C). As for the operation of the pixels in the pixel section shown in Figure 15(C), dot inversion drive, which is one type of AC drive, is used. Let me explain the operation used. By using dot inversion drive, the operation that occurs in AC drive is It can suppress flickering.

[0342] In the pixel of the pixel section shown in Figure 15(C), the wiring 755_j is electrically connected. The switch in the pixel is selected during the jth gate selection period of one frame. It enters the "on" state, and remains in the unselected state (off state) during other periods. Then, the jth game After the gate selection period, a gate selection period for the (j+1)th gate is provided. In this way, sequential scanning is performed. This allows all pixels to be selected sequentially within a single frame period. (Figure 15D shows...) In an timing chart, for example, when the potential becomes high (high state), the pixel in question... When the switch in the circuit is selected, the potential becomes low (low state), resulting in a deselective state. This is assumed to be the case where the transistor in each pixel is of type N, and P When a transistor of type N is used, the relationship between voltage and selected state is the opposite of that in the case of N-type transistors. .

[0343] In the timing chart shown in Figure 15(D), the kth frame (where k is a natural number) During the J-gate selection period, a positive potential is applied to the wiring 754_i used as the signal line. A negative potential is applied to wiring 754_i+1. Then, the j+1th gate in the kth frame... During the selection period, a negative potential is applied to wiring 754_i and a positive potential is applied to wiring 754_i+1. A potential is applied. Subsequently, the polarity of each signal line is reversed during each gate selection period. The signals are given alternately. As a result, in the kth frame, pixels 750_i,j Positive potential at , negative potential at pixel 750_i+1,j, negative potential at pixel 750_i,j+1 The potentials at pixels 750_i+1 and j+1 will each be positive. Then, in the k+1th frame, each pixel is written in the kth frame. A potential with the opposite polarity to the written potential is written as data. As a result, the k+1th phase In the frame, pixels 750_i,j have a negative potential, and pixels 750_i+1,j have a positive potential. The potential is positive at pixel 750_i,j+1 and negative at pixel 750_i+1,j+1. However, each will be given. In this way, adjacent pixels in the same frame Each pixel is given a potential with a different polarity, and furthermore, each pixel is given a potential with a different polarity per frame. A driving method in which the polarity of the electric potential is reversed is called dot inversion driving. ...while suppressing the degradation of the liquid crystal elements, the display image is visible when the entire image or a part of it is uniform. This can reduce the flicker. Note that wiring 756_j and wiring 756_j+1 The voltage applied to all wiring 756, including the wiring, can be set to a constant voltage. The timing chart for the 754 only shows polarity, but in reality, the table The polarity shown can take on various potential values. Note that here, each dot (one pixel) We have discussed the case of reversing polarity, but it is not limited to this, and the polarity can be reversed for each of multiple pixels. It can also be reversed. For example, the polarity of the potential written every two gate selection periods can be reversed. This reduces the power consumption required for writing the potential. In addition, each row It is also possible to reverse the polarity (source line inversion), and to reverse the polarity line by line. It can also do this (gate line reversal).

[0344] Furthermore, the capacitive element 753 in pixel 750 has a constant voltage during the frame period. It is sufficient if it is provided. Here, the signal provided to wiring 755 used as a scan line is 1f Since the low state is maintained for most of the Rheh period and a nearly constant voltage is applied, The other terminal of the capacitive element 753 in pixel 750 may also be connected to wiring 755. Figure 15(E) shows the configuration in which the other terminal of element 753 and the wiring 755 are electrically connected. show.

[0345] The pixel configuration of the pixel section shown in Figure 15(E) can be compared with the pixel configuration of the pixel section shown in Figure 15(C). Then, wiring 756 is omitted, and the terminal of the capacitive element 753 in pixel 750 and the previous one The wiring 755 in the row is electrically connected. Specifically, pixels 750_i,j The terminals of the capacitive element 753 at +1 and pixels 750_i+1,j+1 are connected to wiring 755_ It is electrically connected to j. In this way, the terminal of the capacitive element 753 in pixel 750 and the one before it. By electrically connecting wiring 755 in that row, wiring 756 can be omitted. Therefore, the reduced number of wires allows for an improvement in the aperture ratio of the pixels. The connection destination for terminal 753 is not wiring 755 in the previous line, but wiring in another line. 755 is also acceptable. Note that the pixel driving method for the pixel section shown in Figure 15(E) is shown in Figure 15(C). A method similar to the pixel driving method used for the pixel portion shown can be used.

[0346] Furthermore, the wiring electrically connected to the capacitive element 753 and the other terminal of the capacitive element 753 is By using this, the voltage applied to the wiring 754 used as a signal line can be reduced. The configuration and driving method of the pixel section will be explained using Figures 15(F) and 15(G). I will reveal it.

[0347] The pixel configuration shown in Figure 15(F) is compared to the pixel configuration shown in Figure 15(A) in terms of wiring. Two 756s are used per pixel row, and the terminals of the capacitive element 753 at pixel 750 are connected to each other. It is characterized by alternating electrical connections between adjacent pixels. The wiring 756 will be referred to as wiring 756-1 and wiring 756-2, respectively. In the range shown in Figure 15(F), the capacity at pixels 750_i,j is The terminal of element 753 is electrically connected to wiring 756-1_j, and pixel 750_i+1,j The terminals of the capacitive element 753 are electrically connected to the wiring 756-2_j, and the pixel 750 The terminals of the capacitive element 753 at _i,j+1 are electrically connected to the wiring 756-2_j+1. Therefore, the terminal of the capacitive element 753 at pixels 750_i+1,j+1 is connected to wiring 756-1_ It is electrically connected to j+1.

[0348] Also, as shown in Figure 15(G), for example, in the k-th frame, pixels 750_i,j If a positive polarity potential is written, then during the j-th gate selection period, the wiring 756-1_j It is set to a low state, and after the j-th gate selection period ends, it is changed to a high state. Then, for 1 frame Maintain the high state throughout the entire period, and during the selection period of the jth gate in the k+1th frame... After a negative polarity potential is written to it, wire 756-1_j is changed to a low state. Thus, after a positive polarity potential is written to the pixel, electricity is applied to the other terminal of the capacitive element 753. By changing the potential of the connected wiring in the positive direction, the potential applied to the liquid crystal element is changed. It can be changed by a predetermined amount in the positive direction. That is, the voltage written to the pixel can be changed by that amount. Because the size can be reduced, the power consumption required for signal writing can be reduced. Furthermore, if a negative polarity voltage is written during the j-th gate selection period, the negative polarity voltage After the data is written to the pixel, the wiring that is electrically connected to the other terminal of the capacitive element 753 By changing the position in the negative direction, the potential applied to the liquid crystal element is changed in the negative direction by a predetermined amount. Since it can be changed, just like in the case of positive polarity, the voltage written to the pixel can be reduced. This is possible. In other words, the wiring electrically connected to the other terminal of the capacitive element 753 is the same In the same row of the same frame, there are pixels that are given a positive polarity potential and pixels that are given a negative polarity potential. It is preferable that the wiring for each resulting pixel is different.

[0349] The pixel area shown in Figure 15(F) is an image where a positive polarity potential is written in the k-th frame. In the element, wiring 756-1 is electrically connected, and in the k-th frame, a negative polarity potential is written This is an example where wiring 756-2 is electrically connected to the pixel being inserted. However, this is just one example. Yes, for example, pixels on which a positive polarity potential is written and pixels on which a negative polarity potential is written. In the case of a driving method in which the characters appear every two pixels, the power of wiring 756-1 and wiring 756-2 It is preferable that the thermal connections also alternate every two pixels. Furthermore, all pixels in a row In some cases, the same polarity potential is written (gate line inversion), but in that case, wiring 756 only needs to be present once per row. In other words, in the pixel configuration of the pixel section shown in Figure 15(C) Also, as explained using Figures 15(F) and 15(G), the voltage written to the pixel is reduced. A cutting drive method can be used.

[0350] Next, the liquid crystal element is represented by vertical alignment (VA) mode, such as MVA mode or PVA mode. A particularly preferred pixel configuration and its driving method for VA mode will be described. The advantages of this device include the elimination of the rubbing process during manufacturing, minimal light leakage when displaying black, and a low operating voltage. It has some desirable features, but the image quality deteriorates when viewed from an angle (narrow viewing angle). It also has the problem that, in order to widen the viewing angle of VA mode, multiple sub-pixels (s It is effective to have a pixel configuration that has subpixels. The pixel configuration will be explained using Figures 16(A) and 16(B). Figure 16(B) shows an example of a pixel configuration applicable to the liquid crystal display device in this embodiment. This is a circuit diagram.

[0351] In the liquid crystal display device shown in Figures 16(A) and 16(B), pixel 750 of the pixel section is This is an example showing a case that includes two subpixels (subpixel 750-1, subpixel 750-2). Furthermore, the number of subpixels in a single pixel is not limited to two, and various numbers of subpixels can be used. It is possible. The larger the number of subpixels, the wider the field of view can be. Multiple Subpixels can have the same circuit configuration as each other, and here all subpixels are as shown in Figure 15(A The circuit configuration will be explained as being the same as shown in ( ). Note that the first sub-pixel 750-1 is a tra It shall have an inverter 751-1, a liquid crystal element 752-1, and a capacitive element 753-1, The connection relationships shall conform to the circuit configuration shown in Figure 15(A). Similarly, the second sub-division Element 750-2 consists of transistor 751-2, liquid crystal element 752-2, and capacitive element 753-2. It shall be assumed that it has such connections, and the respective connection relationships shall conform to the circuit configuration shown in Figure 15(A). .

[0352] The pixel section shown in Figure 16(A) uses two subpixels that make up one pixel as scan lines. It has two wires 755 (wire 755-1, wire 755-2) and is used as a signal line. It has one 754 wire and one 756 wire used as a capacity line. By sharing signal lines and capacitance lines between two sub-pixels, the aperture ratio can be improved. Furthermore, the signal line driving circuit can be simplified, thus reducing manufacturing costs. Furthermore, since the number of connections between the LCD panel and the drive circuit can be reduced, the yield can be improved. .

[0353] The pixel section shown in Figure 16(B) uses two subpixels that make up one pixel as scan lines. It has one wire 755 and two wires 754 to be used as signal lines (wire 754-1, wire It has a configuration that includes wire 754-2) and one wiring 756 used as a capacity line. Furthermore, by sharing scan lines and capacitance lines between two sub-pixels, the aperture ratio can be improved. This is possible, and furthermore, the total number of scan lines can be reduced, so even on high-resolution LCD panels, 1 The gate line selection period per pixel can be made sufficiently long, and an appropriate voltage can be applied to each pixel. You can write to it.

[0354] Next, the liquid crystal element 752 in the pixel section shown in Figure 16(B) is the pixel electrode of the liquid crystal element 752 Figures 16(C) and 1000 show an example of a schematic representation of the electrical connection state of each element. We will explain using 6(D).

[0355] In Figures 16(C) and 16(D), electrode 758-1 represents the first pixel electrode. Electrode 758-2 represents the second pixel electrode. In Figure 16(C), electrode 758 -1 corresponds to the second terminal of liquid crystal element 752-1 in Figure 16(B), and electrode 758-2 This corresponds to the terminal of liquid crystal element 752-2 in Figure 16(B). That is, electrode 758 -1 is electrically connected to either the source or drain terminal of transistor 751-1. Furthermore, electrode 758-2 is connected to either the source terminal or the drain terminal of transistor 751-2. It is electrically connected to the other side. On the other hand, in Figure 16(D), the pixel electrode and the transistor are connected. Reverse the relationship. That is, electrode 758-1 is the source terminal of transistor 751-2. Alternatively, it is electrically connected to one of the drain terminals, and electrode 758-2 is connected to transistor 751 It shall be electrically connected to either the source terminal or the drain terminal of -1.

[0356] Furthermore, the pixels shown in Figure 16(C) and Figure 16(D) are arranged alternately in a matrix. By placing it, a special effect can be obtained. The configuration of the pixel section and its drive at this time. An example of the method will be explained using Figures 16(E) and 16(F). Note that Figure 16(F) In the timing chart shown, as an example, when the potential is high (high state), When the switch in that pixel is selected, the potential becomes low (low state), and It shall be in a selected state.

[0357] The pixel configuration shown in Figure 16(E) consists of pixels 750_i,j and pixels 750_i+1, The portion corresponding to j+1 is configured as shown in Figure 16(C), and pixels 750_i+1,j and image The part corresponding to element 750_i,j+1 is configured as shown in Figure 16(D). In this configuration, if driven as shown in the timing chart in Figure 16(F), the kth frame During the j-th gate selection period of M, the first pixel electrode of pixels 750_i,j and pixel 75 A positive polarity potential is written to the second pixel electrode of 0_i+1,j, and pixel 750_i,j A negative polarity potential is applied to the second pixel electrode and the first pixel electrode of pixel 750_i+1,j. Furthermore, during the j+1 gate selection period of the k-th frame, pixels 750_i,j The second pixel electrode of +1 and the first pixel electrode of pixels 750_i+1,j+1 have positive polarity. A potential is applied, and the first pixel electrode of pixel 750_i,j+1 and pixel 750_i+1, A negative polarity potential is applied to the second pixel electrode at j+1. In the k+1th frame, The polarity of the voltage is reversed at each pixel. This reverses the pixel configuration including subpixels. In this, while achieving a drive equivalent to dot inversion drive, the polarity of the potential applied to the signal line Since they can be the same within one frame period, the time required to write data to the pixels Power consumption can be significantly reduced. Note that wiring 756_j and wiring 756_j+1 The potential supplied to all wiring 756, including the wiring itself, can be set to a constant potential.

[0358] Furthermore, the pixel configuration and driving method shown in Figures 16(G) and 16(H) This allows us to reduce the magnitude of the potential written to each pixel. This method involves making the capacitance lines electrically connected to the multiple sub-pixels of a pixel different for each sub-pixel. Yes, that is, the configuration of the pixel section and its driving method shown in Figures 16(G) and 16(H). According to the law, subpixels with the same polarity written within the same frame are considered to be within the same row. For subpixels that share a common capacitance line and have different polarities written within the same frame, Use different capacity lines within the same line. Then, once writing to each line is complete, each The potential of the capacitance line is positive in the sub-pixel where a positive polarity voltage is written, and negative polarity voltages are By changing the voltage in the negative direction in the sub-pixels that are written to, the magnitude of the voltage written to the pixel is determined. This can be made smaller. Specifically, two wirings 756 used as capacity lines are used in each row ( Wiring 756-1, Wiring 756-2), the first pixel electrode of pixels 750_i,j, and wiring 756-1_j is electrically connected via a capacitive element, and the second of pixels 750_i,j The pixel electrode and the wiring 756-2_j are electrically connected via a capacitive element, and the pixel 750 The first pixel electrode of _i+1,j and the wiring 756-1_j are electrically connected via a capacitive element. Connected, the second pixel electrode of pixel 750_i+1,j and the wiring 756-2_j are capacitance Electrically connected via the element, the first pixel electrode of pixel 750_i,j+1 and wiring 75 6-2_j+1 is electrically connected via a capacitive element, and the first of pixels 750_i,j+1 Two pixel electrodes and wiring 756-1_j+1 are electrically connected via a capacitive element, The first pixel electrode of element 750_i+1,j+1 and the wiring 756-2_j+1 are capacitive elements Electrically connected via, the second pixel electrode of pixel 750_i+1,j+1 and wiring 75 6-1_j+1 is electrically connected via a capacitive element. However, this is just one example. For example, if there are two pixels where a positive voltage is written and two pixels where a negative voltage is written In the case of a driving method that appears for each pixel, the electrical wiring 756-1 and wiring 756-2 The connections should also be made alternately every two pixels. There are cases where the same polarity potential is written to all pixels in a row (gate line inversion), but In this case, one wire 756 is sufficient per row. That is, the pixel configuration shown in Figure 16(E) In this case, as explained using Figures 16(G) and 16(H), writing to the pixels A driving method that reduces the voltage can be used.

[0359] This embodiment can be combined with other embodiments as appropriate.

[0360] (Embodiment 4) In this embodiment, the present invention is applicable to the transistors constituting the drive circuit. Let's explain the configuration of a transistor.

[0361] First, the transistor configuration applicable to the transistors that constitute the drive circuit of this embodiment. This will be explained using Figure 17. Figure 17 shows the transformer applicable to the drive circuit of this embodiment. This is a schematic cross-sectional diagram showing the configuration of the transistor, and Figure 17(A) shows a top-gate type transistor. Figure 17(B) shows an example of a transistor configuration, specifically an example of a bottom-gate type transistor configuration. vinegar.

[0362] The transistor configuration shown in Figure 17(A) consists of a substrate 900 and a device provided on the substrate 900. A semiconductor layer 902 having an impurity region 901, and a gate provided to cover the semiconductor layer 902. A gate insulating film 903 and a portion of the semiconductor layer 902 are provided with the gate insulating film 903 in between. A gate electrode 904 and an opening provided on the gate electrode 904 and the gate insulating film 903. An interlayer insulating film 906 having an opening and provided so as to be in contact with the impurity region 901 It has a pair of electrodes, electrode 905a and electrode 905b.

[0363] Furthermore, the transistor configuration shown in Figure 17(B) consists of a substrate 907 and a transistor provided on the substrate 907. A gate electrode 908 and a gate insulating film 910 provided to cover the gate electrode 908. And, semiconductors are provided in the portion of the gate insulating film 910 where the gate electrode 908 is not provided. The body layer 911 and a pair of n-type conductive semiconductor layers provided on the semiconductor layer 911. The semiconductor layer 912a and semiconductor layer 912b, and one of the pair of semiconductor layers, i.e., the semiconductor layer An electrode 913a provided on 912a, and the other of the pair of semiconductor layers, i.e., semiconductor layer 9 It has an electrode 913b provided on 12b.

[0364] Examples of substrates 900 and 907 include glass substrates, quartz substrates, silicon substrates, and gold A flexible substrate, such as a stainless steel substrate, can be used. In addition to the above substrates, flexible substrates can also be used. Flexible substrates can also be used. A flexible substrate is one that can be bent (flexible). This refers to a substrate, such as polycarbonate, polyarylate, or polyethere. Examples include plastic substrates made of sulfone and the like. Also, substrate 900 and base For example, the sheet 907 could be a laminated film (polypropylene, polyester, vinyl). Paper made of fibrous materials (such as polyvinyl fluoride and polyvinyl chloride), base material film Materials such as polyester, polyamide, inorganic vapor-deposited film, and paper can also be used. .

[0365] Examples of semiconductor layers 902 and 911 include amorphous semiconductor films and single-crystal semiconductor films. , polycrystalline semiconductor film, or microcrystal (also called semi-amorphous) (c) It can be formed using semiconductor films, and also by stacking these semiconductor films. It is also possible to use oxide semiconductors (for example, IGZO (InGaZn)) as semiconductor layers. O) etc. can be used. Also, the semiconductor layer can be made by, for example, sputtering or LPCV. It can be formed by the D method or plasma CVD method, etc. Furthermore, amorphous semiconductor films can be formed. By known techniques (solid-phase growth method, laser crystallization method, crystallization method using catalyst metal, etc.) A semiconductor film having a crystalline structure formed by crystallization (crystalline semiconductor film), for example, polycrystalline silicon A film can also be used.

[0366] Examples of gate insulating films 903 and 910 include nitride insulating films and oxide insulating films. For example, an oxide insulating film containing nitrogen can be applied. Examples include silicon oxide films. Note that silicon oxide nitride films, in terms of their composition, are composed of more nitrogen than... It also has a high oxygen content, with a concentration range of 55-65 atomic percent oxygen and 1 atomic percent nitrogen. It contains approximately 20 atomic percent of silicon, 25-35 atomic percent of silicon, and 0.1-10 atomic percent of hydrogen. It refers to a material that has a higher nitrogen content than oxygen content. In large quantities, the concentration range is 15-30 atomic percent for oxygen and 20-35 atomic percent for nitrogen. This refers to materials containing 25-35 atomic percent silicon and 15-25 atomic percent hydrogen.

[0367] The semiconductor layers 912a and 912b have an n-type conductivity and contain impurity elements. A semiconductor layer containing phosphorus or the like can be used.

[0368] Examples of gate electrodes 904 and 908 include gold, silver, platinum, nickel, Silicon, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, carbon, One element selected from aluminum, manganese, titanium, and tantalum, or the same Materials consisting of alloys containing multiple elements can be used, and these can be used in single layers or in layers. It can be formed by [method]. Examples of alloys containing multiple of the above elements include aluminum and Titanium-containing alloys, aluminum, titanium, and carbon-containing alloys, aluminum and Nickel-containing alloys, aluminum and carbon-containing alloys, aluminum, nickel, And alloys containing carbon, or alloys containing aluminum and molybdenum, etc. It is possible to do so. Also, indium tin oxide (ITO), indium tin oxide containing silicon oxide. Use a translucent material such as (ITSO) or indium zinc oxide (IZO). This can be done. For gate electrode 904 and gate electrode 908, vapor deposition, sputtering, CV It can be formed using the D method, printing method, or droplet ejection method.

[0369] Examples of interlayer insulating films 906 include nitride insulating films, oxide insulating films, and nitrogen-containing oxide insulating films. These can be applied.

[0370] Electrodes 905a and 905b, and electrodes 913a and 913b are source electrodes. Alternatively, it functions as a drain electrode. Electrodes 905a and 905b, and electrode 913 Examples of a and electrode 913b include gold, silver, platinum, nickel, silicon, and tungsten. Chromium, molybdenum, iron, cobalt, copper, palladium, carbon, aluminum, manganese From one element selected from titanium and tantalum, or from an alloy containing multiple such elements. These materials can be used, and they can be formed in a single layer or in a laminated form. Examples of alloys containing multiple of the above elements include alloys containing aluminum and titanium, and Alloys containing luminium, titanium, and carbon, alloys containing aluminum and nickel, Aluminum and carbon alloys, aluminum, nickel and carbon alloys, Alternatively, alloys containing aluminum and molybdenum can be applied. Dium tin oxide (ITO), silicon dioxide-containing indium tin oxide (ITSO), or acid Translucent materials such as indium zinc oxide (IZO) can be used. Electrode 905a And electrode 905b, and electrodes 913a and 913b are each made of different materials. It can also be formed by Electrode 905a and Electrode 905b, and Electrode 913a and Electrode 913b is shaped using vapor deposition, sputtering, CVD, printing, or droplet ejection. It is possible.

[0371] As described above, by applying any of the transistors with the above configurations, the present invention can be realized. It is possible to configure various drive circuits.

[0372] Next, as a transistor applicable to a drive circuit according to one aspect of the present invention, a bottom-gate type transistor Other configurations of the transistor will be explained using Figure 18. Figure 18 shows the configuration of the transistor in this embodiment. A schematic cross-sectional diagram showing an example of a transistor structure applicable to transistors that constitute a drive circuit. This is a diagram.

[0373] The transistor configuration shown in Figure 18 consists of a substrate 1000 and a gate provided on the substrate 1000. A gate electrode 1001 and a gate insulating film 1002 provided to cover the gate electrode 1001. And, a microcrystalline semiconductor layer 1 is provided on the gate electrode 1001 with the gate insulating film 1002 in between. 003, a buffer layer 1004 provided on the microcrystalline semiconductor layer 1003, and buffer layer 1 A pair of semiconductor layers, semiconductor layer 1005a and semiconductor layer 1005b, are provided on 004. And, electrode 1006 provided on one of the pair of semiconductor layers, i.e., semiconductor layer 1005a a and electrode 100 provided on the other of the pair of semiconductor layers, i.e., semiconductor layer 1005b It has 6b and .

[0374] As for substrate 1000, a substrate applicable to substrates 900 and 907 in Figure 17 above. A board can be used.

[0375] The gate electrode 1001 is the gate electrode 904 and gate electrode 9 in Figure 17 above. Materials and configurations applicable to 08 can be applied.

[0376] The gate insulating film 1002 is the gate insulating film 903 and gate insulating film shown in Figure 17 above. Applicable materials can be used for the border film 910.

[0377] The microcrystalline semiconductor layer 1003 has an intermediate structure between amorphous and crystalline (including single crystal and polycrystalline) materials. This is a semiconductor layer. This semiconductor has a third state that is stable in terms of free energy. A conductor, crystalline with short-range order and lattice distortion, with a grain size of 0.5~ Columnar or needle-shaped crystals, 50 nm in size, preferably 1 nm to 20 nm in size, are arranged in a direction normal to the substrate surface. This structure is growing in the direction of growth. For example, the microcrystalline semiconductor layer 1003 is made of microcrystalline silicon. These can be applied.

[0378] Furthermore, the microcrystalline semiconductor layer 1003 is intentionally doped with impurity elements for the purpose of controlling valence electrons. When not performing this action, it exhibits weak n-type electrical conductivity, and therefore the channel formation region of the thin-film transistor and For microcrystalline semiconductor films that function in this way, impurity elements that impart p-type properties are added simultaneously with the film formation, or during the formation process. It is preferable to control the threshold voltage Vth by adding it after the film is made. Impurities that impart p-type properties As for physical elements, boron is a typical example, and impurity gases such as B2H6 and BF3 are present at 1 ppm. By mixing it into silicon hydride at a ratio of ~1000 ppm, preferably 1 to 100 ppm It is preferable to form it. And the boron concentration is, for example, 1 × 10 14 ~6×10 16 a toms / cm 3 It is preferable to do so.

[0379] Furthermore, the oxygen concentration of the microcrystalline semiconductor layer 1003 is 1 × 10⁻⁶. 19 cm -3 The following, preferably 5 x 10 18 cm -3 Below, the concentrations of nitrogen and carbon are 5 × 10 18 cm -3 The following are preferable is 1 x 10 18 cm -3 The following is preferable: The microcrystalline semiconductor layer 1003 is mixed with By reducing the concentrations of oxygen, nitrogen, and carbon, channels are formed in the microcrystalline semiconductor layer 1003. This prevents the region from becoming an n-type semiconductor. Furthermore, the concentration at which these materials are mixed in is important. Variations among the offspring result in variations in the threshold voltage Vth. Therefore, these concentrations need to be reduced. This reduces variations in the threshold voltage Vth within the substrate.

[0380] Furthermore, the carrier mobility of the microcrystalline semiconductor layer 1003 is higher compared to the buffer layer 1004. It is expensive. For this reason, the channel formation region of the transistor in the drive circuit of the display device is When using thin-film transistors composed of microcrystalline semiconductors, the area of ​​the channel formation region, i.e. It is possible to reduce the area of ​​thin-film transistors. Therefore, the circuit area can be reduced. This allows you to narrow the frame.

[0381] The buffer layer 1004 is provided on the microcrystalline semiconductor layer 1003, thereby forming a transistor The value of the off-current can be made lower than in the case of a single-layer structure of microcrystalline semiconductor layer 1003. For the buffer layer 1004, for example, amorphous silicon can be used.

[0382] The semiconductor layer 1005a and the semiconductor layer 1005b are impurities having an n-type or p-type conductivity. It is composed of semiconductor layers containing material elements. An example of a semiconductor layer containing impurity elements is amorphous. Examples include high-quality silicon. Furthermore, as for impurity elements, for example, phosphorus is added in the case of n-type silicon. In addition, in the case of p-type, boron should be added. Also, semiconductor layer 1005a and semiconductor layer 1 005b can be formed using a microcrystalline semiconductor material or an amorphous semiconductor material. The semiconductor layer 1005a and semiconductor layer 1005b are formed with a thickness of 2 nm to 50 nm. Preferably, the thickness of the semiconductor layer 1005a and semiconductor layer 1005b is reduced. This can improve throughput.

[0383] Electrodes 1006a and 1006b function as source electrodes or drain electrodes. Electrodes 1006a and 1006b are electrodes 905a and 1006b in Figure 17 above. Materials applicable to electrodes 905b, as well as electrodes 913a and 913b, can be applied. ru.

[0384] Next, the method for fabricating the transistor shown in Figure 18 will be explained using Figures 19 to 21. Figures 19 to 21 are schematic cross-sectional diagrams showing the method for fabricating the transistor according to this embodiment. Furthermore, thin-film transistors with microcrystalline semiconductor films exhibit higher mobility in the n-type than in the p-type. By unifying the polarity of all thin-film transistors formed on the same substrate, the number of manufacturing steps can be reduced. This is preferable. Therefore, in this embodiment, the method for manufacturing an n-type transistor is I will explain this.

[0385] First, as shown in Figure 19(A), a conductive film 1007 is formed on the substrate 1000. In this configuration, a laminated film of an aluminum film and a molybdenum film is formed as the conductive film 1007. The conductive film 1007 can be formed, for example, by sputtering or vacuum deposition. Cut.

[0386] Next, as shown in Figure 19(B), a portion of the conductive film 1007 is etched, and the gate electrode 1 Forms 001. More specifically, the gate electrode 1001 is photolithographic on the conductive film 1007. A resist is formed by sography technology or inkjet method, and the resist is used as a mask. This can be formed by selectively etching the conductive film 1007. For example, scan lines (such as scan line 706 in Figure 13) can also be formed at the same time. Furthermore, it is preferable that the resist be removed after etching.

[0387] Furthermore, the ends of the gate electrode 1001, which are formed by etching, are tapered. It is preferable that the tapered shape is formed on these in a later process. This can improve the coverage of the layer being treated.

[0388] Next, as shown in Figure 19(C), the gate insulating film 100 covers the gate electrode 1001. Form 2. The gate insulating film 1002 is formed by, for example, CVD or sputtering. It can be formed by using an acid. In this embodiment, as an example, a nitride film or a nitride oxide film and an acid The gate insulating film 1002 is formed by forming a laminated film of a nitrided film or an oxidized film.

[0389] Furthermore, a microcrystalline semiconductor film 1008 is formed on the gate insulating film 1002. Film 1008 is produced, for example, by high-frequency plasma CVD with frequencies of tens of MHz to hundreds of MHz, Alternatively, it can be formed using a microwave plasma CVD apparatus with a frequency of 1 GHz or higher. The plasma generated by a microwave plasma CVD device with a frequency of 1 GHz or higher is electron Because the density is high and many radicals are generated from the source gas and supplied to the substrate 1000, This promotes radical reactions on the substrate surface, thereby increasing the deposition rate of the microcrystalline semiconductor film 1008. Furthermore, a microwave system consisting of multiple microwave generators and multiple dielectric plates can be used. Plasma CVD equipment can stably generate large-area plasma. Therefore, It is possible to deposit films with high uniformity in terms of film quality even on large-area substrates. This also allows for increased mass production (productivity). In this embodiment, as an example, micro-compression This section describes the process of fabricating microcrystalline silicon as a crystalline semiconductor film. The specific method for fabricating film 1008 will be explained.

[0390] The microcrystalline semiconductor film 1008 is made by diluting silicon hydride, such as SiH4 or Si2H6, with hydrogen. , or, in addition to silicon hydride and hydrogen, selected from helium, argon, krypton and neon. It can be formed by diluting with one or more noble gas elements. Dilution is done with silicon hydride. The hydrogen flow rate ratio to the element is 5 to 200 times, preferably 50 to 150 times. More preferably, the dilution should be 100 times. Note that instead of silicon hydride, SiH2Cl2, SiH Cl3, SiCl4, or SiF4 can be used.

[0391] Furthermore, when forming the microcrystalline semiconductor film 1008, crystal growth is performed from the bottom of the film upwards. Needle-shaped crystals are formed. This is because the crystal grows in a way that increases the size of the crystal faces. However, even when crystal growth occurs in this manner, the rate at which the microcrystalline semiconductor layer is deposited is, The rate at which the amorphous semiconductor layer is deposited is approximately 1% to 10%.

[0392] Furthermore, in this embodiment, after forming the microcrystalline semiconductor film 1008, Laser process (LP) treatment, which involves irradiating the surface of 1008 with laser light. It is preferable to perform the LP treatment (also known as the LP treatment). The LP treatment will be explained in detail below.

[0393] In LP processing, the laser light is at an energy density that does not melt the microcrystalline semiconductor film 1008. It is preferable that it be irradiated. That is, LP treatment is performed by radiant heating of the microcrystalline semiconductor film 100 This is achieved by solid-phase crystal growth without melting 8. In other words, the deposited microcrystalline semiconductor This method utilizes the critical region in which the conductive film 1008 does not enter the liquid phase, and in that sense, it is called "critical". It could also be called "global growth."

[0394] The laser light described above acts even at the interface between the microcrystalline semiconductor film 1008 and the gate insulating film 1002. This can be done. This allows the crystals on the surface side of the microcrystalline semiconductor film 1008 to be used as seeds. Then, solid-phase crystal growth progresses from the surface toward the interface of the gate insulating film 1002, forming a roughly columnar structure. Crystals grow. Solid-phase crystal growth by LP treatment does not increase the crystal grain size, but rather the film To improve crystallinity in the thickness direction.

[0395] Furthermore, the above LP processing involves focusing the light into a rectangular, elongated shape (forming it into a linear laser beam), for example A microcrystalline semiconductor film 1008 on a 730mm x 920mm glass substrate is subjected to a single laser beam. This can be done by processing with Muscan. In this case, the linear laser beam is superimposed. The mixing ratio (overlap rate) is set to 0-90%, preferably 0-67%. This reduces the processing time per circuit board, thereby improving productivity. However, the laser beam shape is not limited to linear; it can also be processed in a planar shape. It is possible to perform LP processing on various sizes of substrates, not just glass substrates. This can be used. By performing LP treatment, the microcrystalline semiconductor film 1008 and the gate insulating film can be processed. The crystallinity of the interface region with 1002 is improved, and the power of the transistor having a bottom gate structure is improved. It can improve aerodynamic properties.

[0396] According to this "critical growth," the surface irregularities that occurred in conventional low-temperature polysilicon ( Ridges (convex structures) are not formed, and the semiconductor film surface remains smooth after LP treatment. .

[0397] Therefore, the microcrystalline semiconductor film 1008 obtained by directly applying laser light after film formation is, Conventional microcrystalline semiconductor films that are simply deposited and microcrystalline semiconductor films that have been modified by conductive heating after deposition. Crystalline semiconductor films differ from other types of films in their growth mechanism and the quality of the resulting film. Yes.

[0398] Next, as shown in Figure 20(D), an amorphous semiconductor film 1009 is placed on the microcrystalline semiconductor film 1008. It forms.

[0399] The amorphous semiconductor film 1009 is plasma-based due to silicon hydride such as SiH4 and Si2H6. It can be formed using the CVD method. Alternatively, helium and algonium can be added to the silicon hydride. It is used diluted with one or more noble gas elements selected from fluorine, krypton, and neon. It can be formed by the following: 1 to 20 times the flow rate of silicon hydride, preferably 1 Using hydrogen at a flow rate of more than twice but less than 10 times, and more preferably more than 1 time but less than 5 times, An amorphous semiconductor film 1009 can be formed. In addition, silicon hydride and nitrogen or By using ammonia, it is possible to form an amorphous semiconductor film 1009 containing nitrogen. It can be done. Also, the above silicon hydride and a gas containing fluorine, chlorine, bromine or iodine (F2, C By using (I2, Br2, I2, HF, HCl, HBr, HI, etc.), fluorine, chlorine, An amorphous semiconductor film 1009 containing bromine or iodine can be formed. Instead of silicon dioxide, SiH2Cl2, SiHCl2, SiCl2, SiF2, etc. can be used. This can be done. Furthermore, the thickness of this amorphous semiconductor film 1009 is 100 nm to 500 nm. The wavelength should be below, preferably 150 nm to 400 nm, and more preferably 200 nm to 30 The size should be 0 nm or less. At this time, hydrogen is supplied to the microcrystalline semiconductor film 1008. By depositing an amorphous semiconductor film 1009 on a microcrystalline semiconductor film 1008, microcrystalline Hydrogen can be diffused into the crystalline semiconductor film 1008 to terminate the dangling bond.

[0400] Furthermore, the amorphous semiconductor film 1009 uses an amorphous semiconductor as a target, and hydrogen or It can also be formed by sputtering in a noble gas. In this case, ammonia By incorporating nitrogen or N2O into the atmosphere, an amorphous semiconductor film containing nitrogen is formed. It is possible to also include gases containing fluorine, chlorine, bromine, or iodine in the atmosphere (F2, C By including (I2, Br2, I2, HF, HCl, HBr, HI, etc.), fluorine, An amorphous semiconductor film containing chlorine, bromine, or iodine can be formed.

[0401] Furthermore, after forming the amorphous semiconductor film 1009, the surface of the amorphous semiconductor film 1009 is treated with hydrogen. The amorphous semiconductor film 1009 is treated with a rasma, nitrogen plasma, or halogen plasma. The surface may be hydrogenated, nitrogenated, or halogenated. Alternatively, the surface of amorphous semiconductor film 1009 may be treated. The surface is covered with helium plasma, neon plasma, argon plasma, or krypton plasma, etc. You can process it this way.

[0402] Furthermore, it is preferable that the amorphous semiconductor film 1009 does not contain crystal grains. Therefore, frequency This is for high-frequency plasma CVD methods or microwave plasma CVD methods in the range of tens to hundreds of MHz. When forming, the deposition conditions should be such that the amorphous semiconductor film 1009 does not contain crystal grains. It is preferable to control this.

[0403] Furthermore, the amorphous semiconductor film 1009 contains impurities such as phosphorus and boron that impart a single conductivity type. Formed in such a way that it does not get damaged. In particular, added to the microcrystalline semiconductor film 1008 to control the threshold. It is preferable that boron or phosphorus is not mixed into the amorphous semiconductor film 1009. For example, If the amorphous semiconductor film 1009 contains phosphorus, then the microcrystalline semiconductor layer 1003 and the amorphous semiconductor A PN junction is formed between the body film 1009 and the amorphous semiconductor film 1009. If included, amorphous semiconductor film 1009, semiconductor layer 1005a and semiconductor layer 1005b A PN junction is formed between them. Alternatively, recombination occurs when both boron and phosphorus are mixed together. A center is formed, causing leakage current. The amorphous semiconductor film 1009 imparts a single conductivity type. By excluding these impurities, the region where leakage current occurs is eliminated, resulting in a lower leakage current. This can reduce the amount of semiconductor material. In addition, semiconductor layer 1005a and semiconductor layer 1005b and microcrystalline semiconductor No impurities that impart a single conductivity type, such as phosphorus or boron, are added between the conductive layer 1003 and the other layer. The amorphous semiconductor film 1009 is present, which forms the channel-forming region of the microcrystalline semiconductor layer 10 03. Semiconductor layer 1005a and semiconductor layer 100 which form part of the source region and drain region. This prevents the diffusion of impurities contained in each of 5b.

[0404] Furthermore, a semiconductor film 1010 is formed on the amorphous semiconductor film 1009. An n-type conductivity type is attached. When adding phosphorus, for example, phosphorus is added as an impurity element. Phosphorus can be added to silicon hydride by adding a gas such as pH3. To impart a p-type conductivity, an impurity element such as boron is added. When adding boron, impurity gases such as B2H6 are added to silicon hydride to produce boron. It can be added.

[0405] In this embodiment, the gate insulating film 1002, the microcrystalline semiconductor film 1008, and non It is preferable to continuously deposit the crystalline semiconductor film 1009. More preferably, gate insulation Film 1002, microcrystalline semiconductor film 1008, amorphous semiconductor film 1009, and semiconductor film 1010 It is preferable to deposit the film continuously. By depositing the film continuously, each film is not exposed to the atmosphere. Therefore, each layer interface is formed without being contaminated by atmospheric components or impurity elements suspended in the atmosphere. Therefore, the variation in the electrical characteristics of thin-film transistors formed using each film is possible. This reduces friction and allows for the high-yield production of reliable drive circuits. .

[0406] Next, the microcrystalline semiconductor film 1008, the amorphous semiconductor film 1009, and the semiconductor film 1010 are selected. Etch it.

[0407] Specifically, first a resist is formed on a part of the semiconductor film 1010. The resist is, for example, It is formed using photolithography or inkjet technology.

[0408] Next, using the resist as a mask, a microcrystalline semiconductor film 1008, an amorphous semiconductor film 1009, and The semiconductor film 1010 is selectively etched. At this time, etching results in Figure 20(E) As shown, a microcrystalline semiconductor layer 1003 is formed. Note that the resist is removed after etching. It is preferable to do so.

[0409] In this etching process, microcrystalline semiconductor films, amorphous semiconductor films, and impurity semiconductor films are used. It is preferable to perform etching so that the edges of the stacked layers have a tapered shape. The taper angle is controlled to be in the range of 30° to 90°, preferably 40° to 80°. It is preferable to control it. By etching the end so that it has a tapered shape, half This prevents the conductive film 1010 and the microcrystalline semiconductor film 1008 from coming into direct contact. Moreover, the distance between these layers at the edges can be sufficiently large, and the edges The current can be reduced.

[0410] Furthermore, by making the ends tapered, the layer formed on top of them in a later process will be covered Coverage can be improved.

[0411] Next, as shown in Figure 20(F), a conductive film 1011 is formed on the semiconductor film 1010.

[0412] The conductive film 1011 is formed using, for example, a sputtering method or a vacuum deposition method. This can be done. In addition, the conductive film 1011 can use a conductive nanopaste such as silver, gold, or copper. It can also be formed by extruding using screen printing or inkjet printing methods, and then firing. Cut.

[0413] Next, the conductive film 1011 is etched. Specifically, first, the conductive film 1011 is selectively etched. A resist is formed. Next, the conductive film 1011 is etched using the resist as a mask. As shown in Figure 21(G), a pair of electrodes 1006a and 1006b are formed.

[0414] Next, the semiconductor film 1010 and the amorphous semiconductor film 1009 are etched. As shown in Figure 21(H), the buffer layer 1004 and the pair of semiconductor layers 1005a and A semiconductor layer 1005b is formed.

[0415] At this time, a portion of the formed buffer layer 1004 is etched, creating depressions. However, it is preferable to form it with a thickness such that a portion of the amorphous semiconductor film 1009 superimposed on the depression remains. It seems so. The film thickness after etching in the remaining etched portion (the portion overlapping with the depression) is It is preferable that the film thickness be about half of the film thickness before etching. Note that the film thickness before etching is As described above, the wavelength is 100 nm to 500 nm, preferably 150 nm to 40 The wavelength is 0 nm, and more preferably 200 nm to 300 nm. Buffer layer 100 4 functions as an etching stopper for the microcrystalline semiconductor layer 1003.

[0416] Furthermore, in this embodiment, the ends of electrodes 1006a and 1006b and the semiconductor layer 10 The edges of 05a and semiconductor layer 1005b may be made to not coincide. As a result, the distance between the ends of electrodes 1006a and 1006b increases, and the source electrode or drain The distance between one of the inlet electrodes and the other of the source or drain electrodes becomes sufficiently large. This reduces leakage current and prevents short circuits. Also, electrode 1 The ends of 006a and electrode 1006b, and the ends of semiconductor layer 1005a and semiconductor layer 1005b Because the shape does not match that of the part, the ends of electrode 1006a and electrode 1006b and the semiconductor Electric field concentration is less likely to occur at the edges of layer 1005a and semiconductor layer 1005b. Therefore, the goal is to fabricate thin-film transistors that are highly reliable, have low off-current, and high dielectric strength. It is possible.

[0417] By following the above steps, the thin-film transistor shown in Figure 18 can be fabricated.

[0418] Furthermore, as shown in Figure 18 as an example, transistors containing a microcrystalline semiconductor layer are amorphous Because it has higher reliability compared to transistors using only a semiconductor layer, one aspect of the present invention is By applying this to the dynamic circuit, malfunctions can be suppressed.

[0419] This embodiment can be combined with other embodiments as appropriate.

[0420] (Embodiment 5) In this embodiment, regarding an electronic device that uses a display device, which is one aspect of the present invention, as its display unit: explain.

[0421] A display device according to one aspect of the present invention can be used in the display units of various electronic devices. As an example of an electronic device to which a display device, which is one aspect of the present invention, can be applied, a video camera, Cameras such as digital cameras, goggle-type displays (head-mounted displays) Navigation systems, sound playback devices (car audio, audio components, etc.), Notebook personal computers, game consoles, mobile phones, portable information terminals (mobile computers) Computers, portable music players, portable game consoles, ebooks, or computers (Including those that have multiple functions by being built-in and performing multiple data processing), or Image playback device equipped with recording medium (specifically, Digital Versatile Di A device equipped with a display capable of playing recording media such as SC (DVD) and displaying the images. Examples include (placement). Specific examples of these electronic devices will be explained using Figures 22 and 23. Figures 22 and 23 show an example of the configuration of the electronic device in this embodiment. .

[0422] Figure 22(A) shows a display device, consisting of a housing 1101, a support base 1102, and a display unit 11 03, including speaker section 1104, video input terminal 1105, etc. This is one aspect of the present invention. The display device can be used in the display unit 1103. This includes all display devices for computer systems, TV broadcast reception, advertising displays, etc. Born.

[0423] Figure 22(B) shows a digital still camera, consisting of a main unit 1111, a display unit 1112, and an image receiving unit. 1113, operation key 1114, external connection port 1115, shutter button 1116, etc. This includes. A display device according to one aspect of the present invention can be used in the display unit 1112.

[0424] Figure 22(C) shows a notebook personal computer, consisting of a main unit 1121 and a casing 1122. Display unit 1123, keyboard 1124, external connection port 1125, pointing device Includes chair 1126, etc. A display device according to one aspect of the present invention is used in the display unit 1123. It is possible.

[0425] Figure 22(D) shows a mobile computer, consisting of a main unit 1131, a display unit 1132, and a switch. This includes a 1133, an operation key 1134, an infrared port 1135, and the like. This is one aspect of the present invention. The display device can be used in the display unit 1132.

[0426] Figure 22(E) shows a portable image playback device (specifically, a DVD player) equipped with a recording medium. The main unit 1141, the housing 1142, the display unit A1143, the display unit B1144, and the recording medium. Includes a DVD reader 1145, operation keys 1146, speaker unit 1147, etc. Display unit A1143 primarily displays image information, while display unit B1144 primarily displays text information. The display device, according to one aspect of the present invention, includes these display units A1143 and B11 It can be used in 44. Note that the image playback device equipped with a recording medium includes a home game console. This also includes things like that.

[0427] Figure 22(F) shows a goggle-type display (head-mounted display), and the main unit The present invention includes 1151, a display unit 1152, and an arm unit 1153. It can be used in the display unit 1152.

[0428] Figure 22(G) shows a video camera, consisting of a main unit 1161, a display unit 1162, a housing 1163, External connection port 1164, remote control receiver 1165, image receiver 1166, battery 116 7. Includes an audio input unit 1168, an operation key 1169, an eyepiece unit 1170, etc. One embodiment of the present invention The display device can be used in the display unit 1162.

[0429] Figure 22(H) shows a mobile phone, consisting of the main unit 1171, the casing 1172, the display unit 1173, and the voice Input section 1174, audio output section 1175, operation key 1176, external connection port 1177, A Includes the antenna 1178, etc. A display device according to one aspect of the present invention uses the display unit 1173 This is possible. Furthermore, the display unit 1173 displays white characters on a black background. This can reduce the current consumption of the mobile phone.

[0430] Figure 23 shows an example of a portable information terminal with multiple functions, where Figure 23(A) is a portable information terminal. Figure 23(B) is a front view of the information terminal, Figure 23(C) is a rear view of the portable information terminal. This is an unfolded diagram. A portable information terminal, as shown in Figure 23, can have multiple functions. For example, in addition to telephone functionality, it incorporates a computer and various data processing functions. It can also be done this way.

[0431] The portable information terminal shown in Figure 23 consists of two housings, housing 1180 and housing 1181. The enclosure 1180 contains a display unit 1182, a speaker 1183, and a microphone 1 184, operation key 1185, pointing device 1186, camera lens 1187 It is equipped with an external connection terminal 1188, an earphone terminal 1189, etc., and the casing 1181 has a keyboard Code 1190, external memory slot 1191, camera lens 1192, light 1193 It is equipped with these features. The antenna is also built into the casing 1181.

[0432] In addition to the above configuration, a contactless IC chip, a small recording device, etc., may also be incorporated. .

[0433] A display device according to one aspect of the present invention can be used in the display unit 1182, and depending on the usage configuration The display direction changes as appropriate. Also, the camera lens 11 is on the same plane as the display unit 1182. Because it is equipped with 87, video calls are possible. Also, the display unit 1182 is a viewfinder. The camera lens 1192 and light 1193 allow for the capture of both still images and videos. The speaker 1183 and microphone 1184 are not limited to voice calls, but also video calls and recording. It allows for playback and other functions. Operation key 1185 allows for simple functions such as making and receiving phone calls and sending emails. It allows for information input, screen scrolling, cursor movement, and more. Enclosures 1180 and 1181 (Figure 23(A)) slide apart and unfold as shown in Figure 23(C). It can be used as a portable information terminal. In this case, the keyboard 1190, pointing desk Smooth operation is possible using the vice 1186. External connection terminal 1188 is for AC adapter It can also be connected to various cables such as USB cables, and is suitable for charging and personal computing. Data communication with devices such as data controllers is possible. Additionally, a recording medium can be inserted into the external memory slot 1191. It can be inserted to accommodate larger amounts of data storage and transfer.

[0434] Furthermore, in addition to the above functions, it is equipped with infrared communication functions, television reception functions, etc. That's good too.

[0435] As described above, a display device according to one aspect of the present invention is a display device for various electronic devices as described above. It can be applied as a part.

[0436] Furthermore, this embodiment can be appropriately combined with other embodiments. [Explanation of Symbols]

[0437] 11 transistors 12 transistors 13 transistors 14 transistors 15 transistors 100 terminals 101 terminals 102 terminals 102A terminal 102B terminal 103 terminals 103A terminal 103B terminal 103C terminal 103D terminal 104 terminals 104A terminal 104B terminal 104C terminal 104D terminal 104E terminal 104F terminal 104G terminal 104H terminal 104I terminal 104J terminal 104K terminal 104L terminal 104M terminal 105 terminals 106 transistors 107 transistors 10⁸ Capacitive elements 109 transistors 110 transistors 111 transistors 112 Capacitive elements 113 Transistors 114 transistors 115 transistors 116 transistors 117 Nodes 118 nodes 119 nodes 120 transistors 121 terminals 122 transistors 123 Transistors 124 transistors 125 terminals 126 transistors 127 transistors 128 transistors 129 transistors 201 Control signal 202 Clock signal 203 Clock signal 204 Potential 205 Potential 206 Potential 207 Output signal 208 Control signal 209 Output signal 500 terminals 501 terminal 502 terminal 502A terminal 502B terminal 503 terminal 503A terminal 503B terminal 503C terminal 503D terminal 504 terminal 504A terminal 504B terminal 504C terminal 504D terminal 504E terminal 504F terminal 504G terminal 504H terminal 504I terminal 504J terminal 504K terminal 505 terminal 506 Transistors 507 Transistors 508 transistors 509 Transistors 510 Capacitive element 511 transistors 512 transistors 513 Transistors 514 transistors 515 nodes 516 nodes 517 Transistors 518 terminals 519 Transistors 520 transistors 521 Transistors 522 terminals 523 Transistors 524 transistors 525 transistors 526 transistors 601 Control signal 602 Clock signal 603 Clock signal 604 Potential 605 Potential 606 output signal 607 Control signal 608 Output signal 700 pixel section 701 Signal Line Drive Circuit 702 Scan Line Drive Circuit 703 Control Circuit 704 Clock signal generation circuit 705 signal line 705A signal line 705B signal line 706 scan lines 706A scan line 706B scan lines 706C scan lines 706D scan lines 707 Clock signal line 708 Clock signal line 709 pixels 710 Flip-flop circuit 710A Flip-Flop Circuit 710B Flip-Flop Circuit 710C Flip-Flop Circuit 710D Flip-Flop Circuit 750 pixels 751 transistors 752 liquid crystal elements 753 Capacitive element 754 Wiring 755 Wiring 756 Wiring 757 Wiring 758 Electrode 801 start signal 802 Clock signal 803 Clock signal 804 Output signal 805 Output signal 806 Output signal 807 Output signal 900 circuit boards 901 Impurity region 902 Semiconductor layer 903 Gate Insulator 904 Gate Stop 905a electrode 905b electrode 906 Interlayer insulating film 907 circuit board 908 Guard Post 910 Gate Insulator 911 Semiconductor layer 912 Semiconductor layer 912a Semiconductor layer 912b semiconductor layer 913a electrode 913b electrode 1000 circuit boards 1001 Guard Station 1002 Gate Insulator 1003 Microcrystalline semiconductor layer 1004 Buffer Layer 1005a Semiconductor layer 1005b Semiconductor layer 1006a electrode 1006b electrode 1007 Conductive film 1008 Microcrystalline semiconductor film 1009 Amorphous semiconductor film 1010 Semiconductor film 1011 Conductive film 1101 enclosure 1102 Support stand 1103 Display section 1104 Speaker section 1105 Video input terminal 1111 Main Unit 1112 Display section 1113 Image receiving section 1114 Operation Keys 1115 External connection port 1116 Shutter button 1121 Main Unit 1122 cabinet 1123 Display section 1124 keyboard 1125 External connection port 1126 Pointing device 1131 Main Unit 1132 Display section 1133 Switch 1134 Operation Keys 1135 Infrared port 1141 Main Unit 1142 cabinet 1143 Display part A 1144 Display part B 1145 Reading Unit 1146 Operation Keys 1147 Speaker section 1151 Main Unit 1152 Display section 1153 Arm section 1161 Main Unit 1162 Display section 1163 cabinet 1164 External connection port 1165 Remote control receiver 1166 Image receiving section 1167 Battery 1168 Voice Input Section 1169 Operation Keys 1170 Eyepiece 1171 Main Unit 1172 cabinet 1173 Display section 1174 Voice input section 1175 Audio output section 1176 Operation Keys 1177 External connection port 1178 Antenna 1180 cabinets 1181 cabinet 1182 Display section 1183 Speakers 1184 Microphone 1185 Operation Keys 1186 Pointing device 1187 Camera Lenses 1188 External connection terminal 1189 Earphone jack 1190 keyboard 1191 External memory slots 1192 Camera Lenses 1193 Light

Claims

1. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor is always in contact with the output signal line. Either the source or the drain of the second transistor is always in contact with the output signal line. The gate of the second transistor is always in contact with the first signal line. Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The source or drain of the third transistor is always in contact with the second signal line. The gate of the third transistor is always in conductivity with the second signal line. Either the source or the drain of the fourth transistor is always in electrical contact with the power line. The source or drain of the fourth transistor is always in contact with the gate of the first transistor. Either the source or the drain of the fifth transistor is always in electrical contact with the power line. The source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or the drain of the sixth transistor is always in electrical contact with the power line. The source or drain of the sixth transistor is always in contact with the gate of the first transistor. The gate of the sixth transistor is always in contact with the third signal line. The source or drain of the seventh transistor is always in electrical contact with the power line. The source or drain of the seventh transistor is always in conductivity with the output signal line. Either the source or the drain of the eighth transistor is always in electrical contact with the power line. The source or drain of the eighth transistor is always in contact with the gate of the first transistor. The gate of the eighth transistor is always in electrical contact with the gate of the seventh transistor. Either the source or the drain of the ninth transistor is always in electrical contact with the power line. The source or drain of the ninth transistor is always in contact with the gate of the seventh transistor. The gate of the ninth transistor is always in contact with the second signal line. When the source or drain of the second transistor is in a conductive state with the output signal line through at least the channel forming region of the second transistor, the potential of the source or drain of the second transistor is input to the output signal line through at least the channel forming region of the second transistor. A semiconductor device in which the signal of the first signal line is not input to the gate of the fourth transistor and the other of the source or drain of the fifth transistor.

2. It has first to ninth transistors, Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor is always in contact with the output signal line. Either the source or the drain of the second transistor is always in contact with the output signal line. The gate of the second transistor is always in contact with the first signal line. Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The source or drain of the third transistor is always in contact with the second signal line. The gate of the third transistor is always in conductivity with the second signal line. Either the source or the drain of the fourth transistor is always in electrical contact with the power line. The source or drain of the fourth transistor is always in contact with the gate of the first transistor. Either the source or the drain of the fifth transistor is always in electrical contact with the power line. The source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The gate of the fifth transistor is always in conductivity with the second signal line. Either the source or the drain of the sixth transistor is always in electrical contact with the power line. The source or drain of the sixth transistor is always in contact with the gate of the first transistor. The gate of the sixth transistor is always in contact with the third signal line. The source or drain of the seventh transistor is always in electrical contact with the power line. The source or drain of the seventh transistor is always in conductivity with the output signal line. Either the source or the drain of the eighth transistor is always in electrical contact with the power line. The source or drain of the eighth transistor is always in contact with the gate of the first transistor. The gate of the eighth transistor is always in electrical contact with the gate of the seventh transistor. Either the source or the drain of the ninth transistor is always in electrical contact with the power line. The source or drain of the ninth transistor is always in contact with the gate of the seventh transistor. The gate of the ninth transistor is always in contact with the second signal line. When the source or drain of the second transistor is in a conductive state with the output signal line through at least the channel forming region of the second transistor, the potential of the source or drain of the second transistor is input to the output signal line through at least the channel forming region of the second transistor. The signal from the first signal line is not input to the gate of the fourth transistor or to the other of the source or drain of the fifth transistor. At least one of the transistors 1 to 9 is A first conductive layer having a region that functions as a gate electrode, A first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film, An oxide semiconductor layer having a region located above the first insulating layer and functioning as a channel-forming region, A second conductive layer having a region located above the oxide semiconductor layer and functioning as a source electrode, It has a third conductive layer having a region located above the oxide semiconductor layer and functioning as a drain electrode, The first conductive layer comprises titanium and copper. The first insulating layer comprises oxygen and silicon, The semiconductor device having the second conductive layer and the third conductive layer made of titanium and copper, respectively.

3. A semiconductor device according to either claim 1 or claim 2, and a pixel, The pixel has a tenth transistor, Either the source or the drain of the 10th transistor is always in electrical contact with the liquid crystal element. The source or drain of the 10th transistor is always in contact with the fourth signal line. The gate of the 10th transistor is always in conductivity with the output signal line. The display device is configured such that the driving mode of the liquid crystal element is FFS mode.

Images