Display panel and repair method

Abstract

A display panel and repair method that allows a faulty wiring to be repaired by using other wiring that is not the faulty wiring. [Solution] A display panel according to one embodiment of the present invention may comprise: a first drive voltage line and a second drive voltage line spaced apart on either side of a pixel; a plurality of drive voltage linking patterns connecting the first and second drive voltage lines; and a plurality of gate lines intersecting the first and second drive voltage lines. Here, the plurality of gate lines may include at least one gate line having an open portion, and the plurality of drive voltage linking patterns may include repair patterns connecting the open portions of at least one gate line.

Description

Technical Field

[0001] The present invention relates to a display panel and a repair method, and more specifically, to a display panel and a repair method capable of repairing wiring defects.

Background Art

[0002] Entering the full-fledged information age, the field of display devices that visually display electrical information signals is rapidly developing.

[0003] Specific examples of display devices include a liquid crystal display device (LCD), an organic light emitting display device (OLED), a quantum dot display device, and the like.

[0004] Generally, a display device includes a display panel; a gate driving circuit and a source driving circuit that are electrically connected to the display panel and output a gate signal and a data signal. The display panel may include a display area having a plurality of pixels and a peripheral area where the gate driving circuit and the source driving circuit are arranged around the display area. Here, in the display area, configurations of various transistors, light emitting elements, data lines, gate lines, drive voltage lines, reference voltage lines, and common voltage lines may be formed.

[0005] The configuration of the display area can be formed through a plurality of thin film deposition and etching processes on a substrate. When a defect occurs in the etching process of the display panel, a wiring defect such as an open circuit of a gate line, a data line, and a reference voltage line may occur.

Summary of the Invention

Problems to be Solved by the Invention

[0006] In one embodiment, the display panel and repair method allow for the repair of a wiring defect by utilizing other wiring that is not the target of the wiring defect.

[0007] The problems that this invention aims to solve are not limited to those mentioned above, and any other problems not mentioned will be clearly understood by a person with ordinary skill in the art to which the technical concept of this invention belongs from the following description. [Means for solving the problem]

[0008] A display panel according to one embodiment of the present invention may comprise: a first drive voltage line and a second drive voltage line spaced apart on either side of a pixel; a plurality of drive voltage coupling patterns connecting the first and second drive voltage lines; and a plurality of gate lines intersecting the first and second drive voltage lines. Here, the plurality of gate lines may include at least one gate line having an open portion, and the plurality of drive voltage coupling patterns may include repair patterns connecting the open portions of at least one gate line.

[0009] A display panel and repair method according to one embodiment of the present invention can be used to easily repair various wiring defects by utilizing a mesh-like drive voltage line.

[0010] The effects of the present invention are not limited to those mentioned above, and any further effects not mentioned will be clearly understood by a person with ordinary skill in the art to which the technical concept of the present invention pertains, based on the following description. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic plan view of a display panel of the present invention according to one embodiment. [Figure 2] This is a circuit diagram for a subpixel circuit according to one embodiment. [Figure 3] This is a plan view showing the normal wiring state of a display panel of the present invention according to one embodiment. [Figure 4] This is a schematic circuit diagram showing the normal wiring state of the display panel of the present invention according to one embodiment. [Figure 5A] This is an enlarged plan view of the circuit section shown in Figure 3. [Figure 5B] This is a plan view showing a drive voltage coupling pattern according to one embodiment. [Figure 6A] This is a plan view of a display panel of the present invention according to one embodiment. [Figure 6B] This is a plan view showing the signal path of a repaired gate line according to one embodiment. [Figure 7A] This figure shows a faulty wiring condition 1 of the gate line according to one embodiment. [Figure 7B] This figure shows a faulty wiring condition 2 of the gate line according to one embodiment. [Figure 8A] This is a plan view showing the repair process according to one embodiment. [Figure 8B] This is a plan view showing the repair process according to one embodiment. [Figure 8C] This is a plan view showing the repair process according to one embodiment. [Figure 8D] This is a plan view showing the repair process according to one embodiment. [Figure 9A] This is a schematic circuit diagram showing a repair process according to one embodiment. [Figure 9B] This is a schematic circuit diagram showing a repair process according to one embodiment. [Figure 9C] This is a schematic circuit diagram showing a repair process according to one embodiment. [Figure 9D] This is a schematic circuit diagram showing a repair process according to one embodiment. [Figure 10A] This is a cross-sectional view showing the repair process according to one embodiment. [Figure 10B] This is a cross-sectional view showing the repair process according to one embodiment. [Figure 10C] This is a cross-sectional view showing the repair process according to one embodiment. [Figure 11] This is a plan view showing a defective pixel according to one embodiment. [Figure 12]It is a circuit schematic diagram showing defective pixels according to an embodiment. [Figure 13] It is a diagram schematically showing a pixel repair method according to an embodiment. [Figure 14A] It is a plan view showing a pixel repair process according to an embodiment. [Figure 14B] It is a plan view showing a pixel repair process according to an embodiment. [Figure 14C] It is a plan view showing a pixel repair process according to an embodiment. [Figure 15A] It is a circuit schematic diagram showing a pixel repair process according to an embodiment. [Figure 15B] It is a circuit schematic diagram showing a pixel repair process according to an embodiment. [Figure 15C] It is a circuit schematic diagram showing a pixel repair process according to an embodiment. [Figure 16A] It is a cross-sectional view showing a pixel repair process according to an embodiment. [Figure 16B] It is a cross-sectional view showing a pixel repair process according to an embodiment. [Figure 16C] It is a cross-sectional view showing a pixel repair process according to an embodiment.

Embodiments for Carrying Out the Invention

[0012] The advantages, features, and methods for achieving them of the present invention will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in various different forms. These embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention. The present invention is only defined by the scope of the claims.

[0013] The shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings illustrating embodiments of the present invention are illustrative and are not limited to those described herein. Furthermore, in describing the present invention, if a specific explanation of related prior art is deemed to unnecessarily obscure the gist of the invention, such detailed explanation will be omitted.

[0014] Wherever words such as "include," "encompass," "have," "possess," "equip," or "consist of" are used as referred to herein, other parts may be added unless "only" or "solely" is used. When a component is expressed in the singular, it is considered to include multiple components unless otherwise explicitly stated.

[0015] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0016] When describing the positional relationship between two parts, for example, "on top," "on the top of," "on the bottom of," "on the side of," etc., one or more other components may be located between the two parts unless "immediately" or "directly" is used.

[0017] When an element or layer is described as being "on" another element or layer, this includes all cases where the other layer or element is directly above or between the other element and the other element.

[0018] Furthermore, while terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from others. Therefore, the first component mentioned below may also be the second component within the technical concept of the present invention.

[0019] Throughout the specification, the same reference numeral refers to the same component.

[0020] The dimensions and thicknesses of the components shown in the drawings are provided for illustrative purposes only and are not necessarily limited to the dimensions and thicknesses of the components shown herein.

[0021] The features of each of the various embodiments of the present invention can be combined or linked together, either partially or entirely, allowing for a variety of technically interconnected and driven configurations. Each embodiment can be implemented independently of the others, or they can be implemented together in a related manner.

[0022] In this specification, “apparatus” may include display devices such as liquid crystal modules (LCMs) and organic light-emitting display modules (OLED modules), which include a display panel and a drive unit for driving the display panel. It may also include set electronic apparatuses or set devices or set apparatuses, such as complete products or final products including LCMs, OLED modules, etc., such as notebook computers, televisions, personal computer monitors, automotive apparatuses, or other forms of vehicles, and mobile electronic apparatuses such as smartphones or electronic pads.

[0023] Therefore, the display device in the present invention may include the display device itself, such as LCMs and OLED modules, as well as application products including LCMs and OLED modules, or set devices that are intended for end consumers.

[0024] Furthermore, in some embodiments, an LCM or OLED module, consisting of a display panel and a drive unit, may be referred to as a "display device," while the finished electronic device including the LCM or OLED module may be referred to as a "set device." For example, a display device may include a liquid crystal (LCD) or organic light-emitting (OLED) display panel and a source PCB, which is a control unit for driving the display panel. A set device may further include a set PCB, which is a set control unit electrically connected to the source PCB and drives the entire set device.

[0025] The display panels used in the embodiments of the present invention may include, but are not limited to, any form of display panel, such as liquid crystal display panels, organic light-emitting diode (OLED) display panels, and electroluminescent display panels.

[0026] The features of each of the various embodiments of the present invention can be combined or linked together, either partially or entirely, and are technically capable of various interconnections and drives. Each embodiment can be implemented independently of the others, or they can be implemented together in a related manner.

[0027] Various embodiments of the present invention will be described in detail below with reference to the attached drawings. The scales of the components shown in the drawings are not limited to those shown in the drawings, as they differ from the actual scales for the sake of explanation.

[0028] Figure 1 is a schematic plan view of a display panel according to one embodiment of the present invention.

[0029] Referring to Figure 1, the horizontal direction X and vertical direction Y of the display panel 100 can be the length direction and width direction of the display panel 100, respectively. The horizontal direction X and vertical direction Y of the display panel 100 can also be expressed as the row direction and length direction. The thickness direction Z can mean the direction perpendicular to the plane having the horizontal direction X and vertical direction Y of the display panel 100. The display panel 100 may have a cross-section in the thickness direction Z.

[0030] Referring to Figure 1, the display panel 100 according to an embodiment of the present invention may include a display panel drive circuit for writing pixel data to pixels, and a power supply unit 140 for generating the power necessary to drive the pixels and the display panel drive circuit.

[0031] The display area AA of the display panel 100 may include a pixel array for displaying the input video. The pixel array may include a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. The display panel 100 may include power lines commonly connected to the pixels. The power lines are connected to constant voltage nodes of the pixel circuit and can supply the constant voltage necessary to drive the pixels PXL to the pixels PXL. The power lines may be represented by stripe or mesh wiring and commonly connected to the pixels of the display panel 100.

[0032] Each pixel PXL may contain a first, second, third, and fourth subpixel, each having a different color, for the purpose of embodying a color. The color arrangement of the subpixels can be changed. The first subpixel may be a blue (B) subpixel, the second a green (G) subpixel, the third a red (R) subpixel, and the fourth a white (W) subpixel, but is not limited to these.

[0033] Each subpixel may include a pixel circuit for driving a light-emitting element. Each pixel circuit may be connected to data lines, gate lines, and power lines. Each subpixel may be divided into a circuit region and an emission region. The pixel circuit may be located in the circuit region. The emission region may be the region from which light is emitted from a light-emitting element electrically connected to the pixel circuit.

[0034] A pixel array may contain multiple pixel lines L1 to LN. Each of the pixel lines L1 to LN may contain a line of pixels arranged along the X-axis in the pixel array of the display panel 100. Pixels arranged in a pixel line can share a gate line GL. Subpixels arranged in the column direction Y along the data line direction can share the same data line DL. One horizontal period is the time obtained by dividing one frame period by the total number of pixel lines L1 to LN.

[0035] The power supply unit 140 uses a DC-DC converter to output the voltage necessary to drive the pixels of the display panel 100 and the display panel drive circuit. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

[0036] The display panel drive circuit writes pixel data of the input video to the pixels of the display panel 100 under the control of the timing controller 130. The display panel drive circuit may include a data drive unit 110 and a gate drive unit 120.

[0037] The display panel driving circuit can drive pixels using DRD (Double Rate Driving). In a display panel driven by DRD, data lines DL are connected to adjacent subpixels on the left and right, reducing the number of channels in the data driving unit 110 and the number of data lines DL, which is advantageous for ensuring the aperture ratio of the pixels.

[0038] The display panel drive circuit may further include a touch sensor drive unit for driving the touch sensor. The touch sensor drive unit is omitted in Figure 1. The data drive unit 110 and the touch sensor drive unit may be integrated together in a single source drive IC (Integrated Circuit).

[0039] The data drive unit 110 receives pixel data of the input video, which is received as a digital signal from the timing controller 130, and can output a data voltage. The data drive unit 110 can use a DAC (Digital to Analog Converter) to convert the pixel data of the input video into a gamma-compensated voltage for each frame period and output the data voltage. The data voltage can be output from each channel of the data drive unit 110 through an output buffer.

[0040] The gate drive unit 120 may be formed in the display panel 100 together with the pixel array's TFT array and wiring. The gate drive unit 120 may be located on the non-display area NA of the display panel 100, or at least a portion of it may be located within the display area AA where the input video is reproduced.

[0041] The gate drive unit 120 is positioned in the non-display areas NA on either side of the display panel 100, flanking the display area AA, and can supply gate pulses to the gate line GL from both sides using a double-feeding method. In another embodiment, the gate drive unit 120 is positioned on either side of the non-display areas NA on the left or right of the display panel 100, and can supply gate signals to the gate line GL using a single-feeding method. The gate drive unit 120 sequentially outputs gate signal pulses (hereinafter referred to as "gate pulses") to the gate line under the control of the timing controller 130. The gate drive unit 120 can sequentially supply these signals to the gate line GL by shifting the gate pulses using a shift register. The gate drive unit 120 may include one or more shift registers that output gate signal pulses.

[0042] The timing controller 130 receives digital video data of the input video and timing signals synchronized with this data from the host system 200. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a clock, and a data enable signal. The vertical and horizontal synchronization signals can be omitted because the vertical and horizontal periods can be determined from the method of counting the data enable signal. The data enable signal has a period of 1 horizontal period (1H). Based on the timing signals received from the host system 200, the timing controller 130 generates a data timing control signal to control the operating timing of the data drive unit 110 and a gate timing control signal to control the operating timing of the gate drive unit 120.

[0043] The timing controller 130 can add white data to the three primary color pixel data (RGB) input from the host system, convert it into four sub-color data RGBW, and transmit it to the data drive unit 110. A known color conversion algorithm can be used to convert the three primary color pixel data RGB into four sub-color data RGBW, which includes white color data.

[0044] For example, the timing controller 130 can generate W data for the first pixel data based on the minimum grayscale value among the R data, G data, and B data of the first pixel data received as input video data, and convert the first pixel data into 4 subcolor data RGBW. Furthermore, the timing controller 130 can generate W data for the second pixel data based on the minimum grayscale value among the R data, G data, and B data of the second pixel data received as input video data, and convert the second pixel data into 4 subcolor data RGBW.

[0045] In each of the first and second pixel data, the gradation values ​​of the R, G, and B data may be lower by the amount of the W data. Here, R data is the data written to the red subpixel, G data is the data written to the green subpixel, B data is the data written to the blue subpixel, and W data is the data written to the white subpixel.

[0046] The level shifter 150 receives a gate timing control signal from the timing controller 130, generates a start pulse and a shift clock, and provides them to the gate drive unit 120. The start pulse and shift clock output from the level shifter 150 swing between the gate high voltage and the gate low voltage.

[0047] The host system 200 may include one mainboard from among a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, or a wearable terminal. The host system can scale the video signal from the video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with the timing signal.

[0048] Figure 2 is a circuit diagram for a subpixel circuit according to one embodiment.

[0049] Referring to Figure 2, each subpixel PXL circuit (hereinafter referred to as the subpixel circuit) can be connected to a data line DL to which the pixel data voltage Vdata is applied, a gate line GL to which the gate pulse SCAN is applied, a drive voltage line VDDL to which the pixel drive voltage EVDD is applied, a low-potential voltage line VSSL to which the low-potential voltage EVSS is applied, and a reference voltage line RL to which the reference voltage Vref is applied.

[0050] Each subpixel circuit may include a light-emitting element (EL), a plurality of transistors DT, T1, T2, and a capacitor C. However, the structure of the subpixel circuit in the display panel of the present invention is not limited thereto.

[0051] The light-emitting element (EL) may be an organic light-emitting diode (OLED) or an inorganic light-emitting element such as a micro-LED. The light-emitting element (EL) may include, but is not limited to, red, green, and blue light-emitting elements. The anode electrode of the light-emitting element (EL) may be electrically connected to a driving element (DT) and positioned in the corresponding light-emitting region for each pixel. The light-emitting element (EL) is driven to emit light when current is generated from the driving element (DT), and the light is emitted outside the display panel through the light-emitting region.

[0052] The driving element DT can drive the light-emitting element EL by generating a current in response to the gate-source voltage. The driving element DT comprises a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. A capacitor C is connected between the first node N1 and the third node N3. The second node N2 is connected to the driving voltage line VDDL. The third node N3 is connected to the anode electrode of the light-emitting element EL. The cathode electrode of the light-emitting element EL is connected to the low-voltage line VSSL to which the low-voltage EVSS is applied.

[0053] The first switch element T1 is connected between the data line DL and the first node N1. The first switch element T1 is turned on in response to the gate pulse SCAN. When the first switch element T1 is turned on, the data voltage Vdata of the pixel data is applied to the first node N1 to which the data is applied, and the pixel data is written to the subpixel. The first switch element T1 comprises a gate electrode connected to the gate line GL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0054] The second switch element T2 is connected between the third node N3 and the reference voltage line RL. The second switch element T2 is turned on in response to the gate pulse SCAN. When the second switch element T2 is turned on, the third node N3 is connected to the reference voltage line RL. The second switch element T2 comprises a gate electrode connected to the gate line GL, a first electrode connected to the third node N3, and a second electrode connected to the reference voltage line RL.

[0055] The driving element DT must have uniform electrical characteristics across all subpixels; however, variations in process and element characteristics can cause differences between subpixels, and these differences can increase over time as the subpixels are driven. To compensate for such variations in the electrical characteristics of the driving element DT, an external compensation circuit may be applied to the display panel driving circuit.

[0056] Figure 3 is a plan view showing the normal wiring state of a display panel according to one embodiment of the present invention. Figure 4 is a schematic circuit diagram showing the normal wiring state of a display panel according to one embodiment of the present invention. Figure 5A is an enlarged plan view of the circuit section of Figure 3, and Figure 5B is a plan view showing the drive voltage coupling pattern according to one embodiment.

[0057] Referring to Figures 3 and 4, a display panel according to one embodiment may comprise a plurality of pixels PXL1, PXL1', PXL2, PXL2', and may comprise a drive voltage line MVDDL, a reference voltage line RL, data lines DL1, DL2, DL3, DL4, and gate lines GL1, GL2 for driving the plurality of pixels PXL1, PXL1', PXL2, PXL2'. The horizontal X direction of the display panel 100 may be arranged alongside the gate lines GL1, GL2, and the vertical Y direction may be arranged alongside the drive voltage line VDDL, the reference voltage line RL, and the data lines DL1, DL2, DL3, DL4.

[0058] Multiple pixels PXL (PXL1, PXL1', PXL2, PXL2') may include the first pixel PXL1, the first' pixel PXL1', the second pixel PXL2, and the second' pixel PXL2'.

[0059] The first pixel PXL1 and the first' pixel PXL1' have the same structure and can be arranged in a repeating manner in the vertical direction Y. In this case, some circuit parts of the first and first' pixels PXL1 and PXL1' can be arranged side by side in the horizontal direction X. For example, the first and second circuit parts CA1 and CA2 of the first pixel PXL1 can be arranged side by side in the horizontal direction X with the third and fourth circuit parts CA3 and CA4 of the first' pixel PXL1'.

[0060] The second pixel PXL2 and the second' pixel PXL2' have the same structure and can be arranged in a repeating manner in the vertical direction Y. In this case, some circuit parts of the second pixel PXL2 and the second' pixel PXL2' can be arranged side by side in the horizontal direction X. For example, the first' and second' circuit parts CA1' and CA2' of the second pixel PXL2 can be arranged side by side in the horizontal direction X with the third' and fourth' circuit parts CA3' and CA4' of the second' pixel PXL2'.

[0061] The first pixel PXL1 and the second pixel PXL2 can be arranged in a repeating manner along the horizontal X direction. Similarly, the first' pixel PXL1' and the second' pixel PXL2' can be arranged in a repeating manner along the horizontal X direction. The first and second pixels PXL1 and PXL2 will be used as examples to illustrate the concept of two pixels repeating along the horizontal X direction.

[0062] The first pixel PXL1 and the second pixel PXL2 may have their respective first to fourth light-emitting parts EA (EA1, EA2, EA3, EA4, EA1', EA2', EA3', EA4') arranged sequentially in the lateral direction X. For example, with respect to the drive voltage line VDDL between the first and second pixels PXL1 and PXL2, the first to fourth light-emitting parts EA1, EA2, EA3, and EA4 of the first pixel PXL1 may be arranged sequentially from left to right on the left side, and the first to fourth light-emitting parts EA1', EA2', EA3', and EA4' of the second pixel PXL2 may be arranged sequentially from left to right on the right side.

[0063] On the other hand, the first pixel PXL1 and the second pixel PXL2 may have their respective first to fourth circuit sections CA (CA1, CA2, CA3, CA4, CA1', CA2', CA3', CA4') arranged in a symmetrical configuration with respect to the vertical direction Y. With respect to the drive voltage line VDDL located between the first and second pixels PXL1 and PXL2, the first to fourth circuit sections CA1, CA2, CA3, CA4 of the first pixel PXL1 located on the left and the first to fourth circuit sections CA1', CA2', CA3', CA4' of the second pixel PXL2 located on the right may have a symmetrical configuration with respect to each other.

[0064] For example, the first and second circuit parts CA1 and CA2 of the first pixel PXL1 may be arranged above the corresponding first and second light-emitting parts EA1 and EA2, respectively, and the third and fourth circuit parts CA3 and CA4 of the first pixel PXL1 may be arranged below the corresponding third and fourth light-emitting parts EA3 and EA4, respectively. For example, the first' and second' circuit parts CA1' and CA2' of the second pixel PXL2 may be arranged below the corresponding first' and second' light-emitting parts EA1' and EA2', respectively, and the third' and fourth' circuit parts CA3' and CA4' of the second pixel PXL2 may be arranged above the corresponding third' and fourth' light-emitting parts EA3' and EA4', respectively. However, the arrangement structure of the multiple pixels is illustrative, and embodiments of the present invention are not limited thereto.

[0065] Each of the multiple pixels PXL1, PXL2 may include at least one subpixel. For example, the first pixel PXL1 may include a first subpixel comprising a first light-emitting unit EA1 and a first circuit unit CA1, a second subpixel comprising a second light-emitting unit EA2 and a second circuit unit CA2, a third subpixel comprising a third light-emitting unit EA3 and a third circuit unit CA3, and a fourth subpixel comprising a fourth light-emitting unit EA4 and a fourth circuit unit CA4.

[0066] For example, the second pixel PXL2 may include a first subpixel having a first 'light-emitting part EA1' and a first 'circuit part CA1', a second subpixel having a second 'light-emitting part EA2' and a second 'circuit part CA2', a third subpixel having a third 'light-emitting part EA3' and a third 'circuit part CA3', and a fourth subpixel having a fourth 'light-emitting part EA4' and a fourth 'circuit part CA4'.

[0067] Each of the multiple pixels PXL1, PXL2 may contain subpixels that emit different colors from each other. For example, the multiple pixels PXL1, PXL2 may contain red subpixels, green subpixels, blue subpixels, and white subpixels. For example, the red subpixel may be the first subpixel, the green subpixel may be the second subpixel, the white subpixel may be the third subpixel, and the blue subpixel may be the fourth subpixel.

[0068] Referring to Figures 3 and 4, the first and first' light-emitting parts EA1, EA1' can emit red as the first subpixel, the second and second' light-emitting parts EA2, EA2' can emit green as the second subpixel, the third and third' light-emitting parts EA3, EA3' can emit white as the third subpixel, and the fourth and fourth' light-emitting parts EA4, EA4' can emit blue as the fourth subpixel. However, the types of subpixels are illustrative, and the embodiments of the present invention are not limited thereto.

[0069] Each subpixel can be connected to a data line DL, a gate line GL, a drive voltage line MVDDL, and a reference voltage line RL.

[0070] Data lines DL1, DL2, DL3, and DL4 are branches of their respective main data lines DL10, DL20, DL30, and DL40, which branch into two adjacent pixels PXL1 and PXL2, and can be driven by the DRD method.

[0071] For example, the first main data line DL10 may branch off to the first data line DL1 and be connected to the first subpixel of the first pixel PXL1 and the second pixel PXL2, respectively; the second main data line DL20 may branch off to the second data line DL2 and be connected to the second subpixel of the first pixel PXL1 and the second pixel PXL2, respectively; the third main data line DL30 may branch off to the third data line DL3 and be connected to the third subpixel of the first pixel PXL1 and the second pixel PXL2, respectively; and the fourth main data line DL40 may branch off to the fourth data line DL4 and be connected to the fourth subpixel of the first pixel PXL1 and the second pixel PXL2, respectively.

[0072] Here, each of the first to fourth data lines DL1, DL2, DL3, and DL4 can form branch lines extending from their respective data lines DL1, DL2, DL3, and DL4 to the corresponding subpixels. This allows the first to fourth data lines DL1, DL2, DL3, and DL4 to supply data signals to the corresponding subpixels through the branch lines.

[0073] Two data lines branching off from a main data line may have their branch lines routed in different directions to two different circuit sections located in the same column. For example, of two data lines branching off from a single main data line, one data line may have its branch line routed above one circuit section, while the other data line may have its branch line routed below the other circuit section.

[0074] Gate lines GL(GL1, GL2) may include a first gate line GL1 and a second gate line GL2. The first and second gate lines GL1 and GL2 may be arranged in a repeating manner in the vertical direction Y. Adjacent first and second gate lines GL1 and GL2 may be arranged on the upper and lower sides, respectively, in the vertical direction Y of the circuit section CA.

[0075] For example, the first gate line GL1 may be positioned above the circuit section CA with respect to the vertical direction Y, and the second gate line GL2 may be positioned below the circuit section CA with respect to the vertical direction Y. Each of the first and second gate lines GL1 and GL2 may correspond to two data lines branching off from the main data line. This allows the main data line to supply the same signal to the two data lines, while each of the two data lines can intersect with different first and second gate lines.

[0076] For example, the first gate line GL1 can supply signals to the third circuit section CA3 and the fourth circuit section CA4 of the first pixel PXL1, and can supply signals to the first circuit section CA1' and the second circuit section CA2' of the second pixel PXL2. For example, the second gate line GL2 can supply signals to the first circuit section CA1 and the second circuit section CA2 of the first pixel PXL1, and can supply signals to the third' circuit section CA3' and the fourth' circuit section CA4' of the second pixel PXL2.

[0077] In this case, for the first pixel PXL1, the first subpixel may be formed at the intersection of the second gate line GL2 and the first data line DL1, the second subpixel may be formed at the intersection of the second gate line GL2 and the second data line DL2, the third subpixel may be formed at the intersection of the first gate line GL1 and the third data line DL3, and the fourth subpixel may be formed at the intersection of the first gate line GL1 and the fourth data line DL4.

[0078] For the second pixel PXL2, the first subpixel may be formed at the intersection of the first gate line GL1 and the first data line DL1, the second subpixel may be formed at the intersection of the first gate line GL1 and the second data line DL2, the third subpixel may be formed at the intersection of the second gate line GL2 and the third data line DL3, and the fourth subpixel may be formed at the intersection of the second gate line GL2 and the fourth data line DL4.

[0079] In other words, in the DRD drive system, the first and second pixels PXL1 and PXL2 are supplied with the same main data lines DL10, DL20, DL30, and DL40 signals, but can be driven individually by different gate lines GL1 and GL2.

[0080] For example, the first subpixel of the first pixel PXL1 may be driven by the first data line DL1 and the second gate line GL2, which branch off to the left from the first main data line DL10, and the first subpixel of the second pixel PXL2 may be driven by the first data line DL1 and the first gate line GL1, which branch off to the right from the first main data line DL10. For example, the second subpixel of the first pixel PXL1 may be driven by the second data line DL2 and the second gate line GL2, which branch off to the left from the second main data line DL20, and the second subpixel of the second pixel PXL2 may be driven by the second data line DL2 and the first gate line GL1, which branch off to the right from the second main data line DL20.

[0081] For example, the third subpixel of the first pixel PXL1 may be driven by the third data line DL3 and the first gate line GL1, which branch off to the left from the third main data line DL30, and the third subpixel of the second pixel PXL2 may be driven by the third data line DL3 and the second gate line GL2, which branch off to the right from the third main data line DL30. For example, the fourth subpixel of the first pixel PXL1 may be driven by the fourth data line DL4 and the first gate line GL1, which branch off to the left from the fourth main data line DL40, and the fourth subpixel of the second pixel PXL2 may be driven by the fourth data line DL4 and the second gate line GL2, which branch off to the right from the fourth main data line DL40.

[0082] Referring to Figure 5B, one embodiment of the present invention's drive voltage line MVDDL may include a plurality of drive voltage lines VDDL arranged in the vertical direction Y, and a plurality of drive voltage linking patterns EVDD_1 connecting the plurality of drive voltage lines VDDL. The drive voltage lines VDDL and the drive voltage linking patterns EVDD_1 may intersect with each other and form a mesh. However, the display panel of the present invention is not limited to this. For example, the drive voltage lines VDDL and the drive voltage linking patterns EVDD_1 can be formed integrally in the same layer.

[0083] Each of the drive voltage lines VDDL may be positioned in the region between each pixel PXL1, PXL2. In other words, the drive voltage lines VDDL may be spaced apart from each other, with the first pixel PXL1 or the second pixel PXL2 in between.

[0084] A drive voltage coupling pattern EVDD_1 can couple drive voltage lines VDDL. Each drive voltage coupling pattern EVDD_1 can be placed between adjacent first and second gate lines GL1 and GL2. Each drive voltage coupling pattern EVDD_1 can have a symmetrical configuration with respect to a drive voltage line VDDL placed between first and second pixels PXL1 and PXL2.

[0085] Each drive voltage coupling pattern EVDD_1 may include a coupling line EVDD_a and an overlapping portion EVDD_b. Each drive voltage coupling pattern EVDD_1 may be arranged in a repeating manner of coupling line EVDD_a and overlapping portion EVDD_b. Such coupling line EVDD_a and overlapping portion EVDD_b can be formed integrally. The overlapping portion EVDD_b is a region that overlaps with the drive voltage line VDDL and may be in contact with the drive voltage line VDDL. For example, each overlapping portion EVDD_b and each drive voltage line VDDL may be in contact at a fifth contact portion CT5.

[0086] Each connecting line EVDD_a may extend from and be positioned between the superimposed sections EVDD_b. That is, a connecting line EVDD_a may be positioned between each of the drive voltage lines VDDL. A connecting line EVDD_a may include a first connecting line EVDD_1a, a second connecting line EVDD_2a, and a third connecting line EVDD_3a positioned between the first and second connecting lines EVDD_1a and EVDD_2a.

[0087] The first and second connecting lines EVDD_1a and EVDD_2a can be extended from each of the superimposed areas EVDD_b toward the reference voltage line RL. Depending on the shape of the light-shielding pattern (LS in Figure 5A), the first and second connecting lines EVDD_1a and EVDD_2a may be arranged generally in the lateral direction X, except for some curved areas.

[0088] The first and second connecting lines EVDD_1a and EVDD_2a may be arranged so as not to overlap with the branch wiring of the data lines DL1, DL2, DL3, DL4 and the reference voltage line RL, respectively. For this purpose, the first and second connecting lines EVDD_1a and EVDD_2a may be arranged on opposite sides of the circuit section with respect to the longitudinal direction Y.

[0089] For example, the first connection line EVDD_1a may be located above the first and second circuit sections CA1 and CA2 of the first pixel PXL1, and the second connection line EVDD_2a may be located below the third and fourth circuit sections CA3 and CA4 of the first' pixel PXL1' adjacent to the first pixel PXL1, with reference to the reference voltage line RL.

[0090] As another example, the first connection line EVDD_1a may be located above the third' and fourth' circuit sections CA3' and CA4' of the second pixel PXL2, and the second connection line EVDD_2a may be located below the first' and second' circuit sections CA1' and CA2' of the second' pixel PXL2' adjacent to the second pixel PXL2, with reference to the reference voltage line RL.

[0091] The third connection line EVDD_3a may be bent from the first and second connection lines EVDD_1a and EVDD_2a, respectively, and positioned in the vertical direction Y. Such a third connection line EVDD_3a may have a region that overlaps along the length direction of the reference voltage line RL, where the length direction of the reference voltage line RL is the direction in which the reference voltage line RL is positioned on the display panel.

[0092] The reference voltage line RL may be placed between each drive voltage line VDDL. For example, the reference voltage line RL may be placed between each second and third data lines DL2 and DL3.

[0093] The reference voltage line RL can supply a reference voltage to each of the subpixels located on either side in the lateral direction X. For example, the reference voltage line RL can be connected to each subpixel through branch wiring extending from the reference voltage line RL to the circuit sections of each subpixel on either side.

[0094] In Figure 5A, any two circuit sections CA1 and CA2 are shown in enlargement. On the other hand, the first to fourth circuit sections CA1, CA2, CA3, CA4 of the first pixel PXL1 in Figure 3, and the first' to fourth' circuit sections CA1', CA2', CA3', CA4' of the second pixel PXL2, may have the same structure as the circuit sections illustrated and described in Figure 5A.

[0095] Referring to Figure 5A, the first circuit section CA1 according to one embodiment is connected to the branch wiring DL1_1 of the first data line DL1, the branch wiring RL_1 of the reference voltage line RL, and the drive voltage coupling pattern EVDD_1, and may include a first switch element, a second switch element, a drive element, and a capacitor.

[0096] In one embodiment, the second circuit section CA2 is connected to the branch wiring DL2_1 of the second data line DL2, the branch wiring RL_2 of the reference voltage line RL, and the drive voltage coupling pattern EVDD_1, and may include a first switch element T1, a second switch element T2, a drive element DT, and a light-shielding layer LS. However, the structures of the circuit sections CA1, CA2, CA3, CA4, CA1', CA2', CA3', and CA4' are illustrative, and the embodiments of the present invention are not limited thereto. In the following, the first and second switch elements T1, T2, the drive element DT, and the capacitor will be described with reference to the second circuit section CA2.

[0097] The light-shielding layer LS is configured as one of the electrodes of the capacitor and may have a light-shielding function that blocks light directed toward the active layers ACT1, ACT2, and ACT3.

[0098] The capacitor may consist of a light-shielding layer LS, a first active layer ACT1 of the first switching element T1, and an insulator between the light-shielding layer LS and the first active layer ACT1.

[0099] The first switching element T1 can be turned on in response to a gate pulse of the second gate line GL2.

[0100] The first switch element T1 may include a first active layer ACT1, a first-first contact portion CT1_1 and a first-second contact portion CT1_2 on both sides of the first active layer ACT1. The first switch element T1 may be connected to the second data line DL2 through the first-first contact portion CT1_1 and to the gate electrode GT of the drive element DT through the first-second contact portion CT1_2. Here, the first-first and first-second contact portions CT1_1 and CT1_2 are provided with electrodes for connecting to the second data line DL2 and the gate electrode GT, respectively.

[0101] The second switching element T2 can be turned on in response to the gate pulse of the second gate line GL2.

[0102] The second switching element T2 may include a second active layer ACT2, a second-first contact portion CT2_1 and a second-second contact portion CT2_2 on both sides of the second active layer ACT2. The second switching element T2 may be connected to a reference voltage line RL through the second-first contact portion CT2_1 and to a light-shielding layer LS through the second-second contact portion CT2_2. Here, the second-first and second-second contact portions CT2_1 and CT2_2 are provided with electrodes for connecting to the reference voltage line RL and capacitor C, respectively.

[0103] The drive element DT can be turned on when a signal is applied to the gate electrode GT.

[0104] The driving element DT may include a third active layer ACT3, a third-first contact portion CT3_1 and a third-second contact portion CT3_2 on either side of the third active layer ACT3. The gate electrode GT of the driving element DT may be connected to the first active layer ACT1 of the first switch element T1, connected to the driving voltage coupling pattern EVDD_1 through the third-first contact portion CT3_1, and connected to the second active layer ACT2 of the second switch element T2 through the third-second contact portion CT3_2. Here, the third-first and third-second contact portions CT3_1 and CT3_2 are provided with electrodes for connecting to the driving voltage coupling pattern EVDD_1 and the second active layer ACT2 of the second switch element T2, respectively.

[0105] Furthermore, the driving element DT is connected to the anode electrode of the light-emitting element through the third-second contact portion CT3_2, thereby driving the light-emitting element. Here, the third-second contact portion CT3_2 is equipped with an electrode for connection to the anode electrode of the light-emitting element.

[0106] On the other hand, the first gate line GL1 may be composed of multiple layers GL1_1 and GL1_2 in some regions. The first gate line GL1 may branch at points where it intersects with the drive voltage line VDDL, the first and second data lines DL1 and DL2, and the reference voltage line RL. The second gate line GL2 may have the same structure as the first gate line GL1.

[0107] The first gate line GL1 may include a first layer GL1_1 and a second layer GL1_2. The first layer GL1_1 may be a gate line extending from a pad portion. The second layer GL1_2 is a different layer from the first layer GL1_1 and may be located in a region that does not intersect with the signal lines (e.g., DL1_1, DL2_1, RL1, RL2). However, the structures of the first and second gate lines GL1 and GL2 are illustrative, and embodiments of the present invention are not limited thereto.

[0108] Figure 6A shows a faulty wiring state 1 of the gate line according to one embodiment. Figure 6B shows a faulty wiring state 2 of the gate line according to one embodiment.

[0109] As mentioned above, the first gate line GL1 may include the first layer GL1_1 and the second layer GL1_2. The gate line GL can be formed through thin film deposition and etching processes. In this process, defects may occur in the gate line GL, such as etching in areas that should not be etched (state 1) or not etching in areas that should be etched (state 2).

[0110] Figure 6A shows state 1, in which a defect occurs in which a portion of the first gate line GL1 is open. In one embodiment of the present invention, the display panel may have state 1 while having an open portion OP on any one of the first gate lines GL1. For example, state 1 may occur in a single-wiring region where the wiring is not composed of a double layer or is not branched. Therefore, the first gate line GL1 in state 1 may have an open portion OP on the first layer GL1_1. Among these, the open portion OP may be located in a region of the first layer GL1_1 that does not overlap with the second layer GL1_2.

[0111] However, the above-described state 1 is illustrative, and the embodiments of the present invention are not limited thereto. For example, state 1 may occur at the second gate line GL2, and the open portion OP can occur at any position on the gate line.

[0112] Figure 6B shows State 2, in which a defect occurs where a portion of the second gate line GL2 is short-circuited with another adjacent signal line. In one embodiment, the display panel of the present invention may have State 2 while including a short-circuit portion ST in any one of the second gate lines GL2. For example, the second gate line GL2 in State 2 may include a short-circuit portion ST in the second layer GL2_2. For example, the short-circuit portion ST may be connected to a drive voltage line VDDL that is arranged adjacent to the second layer GL2_2 of the second gate line GL2. However, State 2 described above is illustrative, and embodiments of the present invention are not limited thereto.

[0113] Furthermore, the display panel of the present invention according to one embodiment can be repaired in the following manner for states 1 and 2.

[0114] In this case, when repairing state 2, an additional step can be added to cut the short section ST. By cutting the short section ST, an open section OP may be formed in the second gate line GL2. Therefore, the repair process described below will focus on repairing the open section OP of the second gate line GL2.

[0115] Figure 7A is a plan view of a display panel according to one embodiment of the present invention. Figure 7B is a plan view showing the signal path of a repaired gate line according to one embodiment.

[0116] Referring to Figure 7A, a display panel according to one embodiment may comprise: a first drive voltage line VDDL(1) and a second drive voltage line VDDL(2) separated on either side of a pixel PXL(PXL1, PXL1', PXL2, PXL2'); a plurality of drive voltage coupling patterns EVDD_1 connecting the first and second drive voltage lines VDDL(1) and VDDL(2); and a plurality of gate lines GL(GL1, GL2) intersecting the first and second drive voltage lines VDDL(1) and VDDL(2). Here, the plurality of gate lines GL include at least one gate line GL with an open portion OP, and the plurality of drive voltage coupling patterns EVDD_1 may include a repair pattern RPL separated from the first and second drive voltage lines VDDL(1) and VDDL(2) and connecting the open portion OP of at least one gate line.

[0117] In one embodiment of the present invention, the display panel includes an open section OP in the second gate line GL2 among a plurality of gate lines GL1 and GL2. For example, the open section OP may be superimposed on the branch wiring DL3_3 of the third data line DL3 and the branch wiring RL_3 of the reference voltage line RL.

[0118] The repair method according to one embodiment can be performed in units of the drive voltage coupling pattern EVDD_1. In the display panel of the present invention according to one embodiment, the repair pattern RPL, which is separated from the first and second drive voltage lines VDDL(1) and VDDL(2), connects the open portion OP of the second gate line GL2, thereby repairing the second gate line GL2 where a defect has occurred. As a result, the repaired second gate line GL2 can allow gate pulses to flow normally through the repair pattern RPL.

[0119] For this purpose, the display panel of the present invention may have a mesh-like arrangement of drive voltage lines MVDDL, which comprises multiple drive voltage lines VDDL and multiple drive voltage linking patterns EVDD_1. Even if the mesh-like drive voltage lines MVDDL are used as repair patterns RPL in some areas, the drive voltage can be supplied to the entire display area.

[0120] Multiple drive voltage lines VDDL may include a first drive voltage line VDDL(1) and a second drive voltage line VDDL(2) arranged adjacent to each other with a pixel PXL in between.

[0121] Each of the first and second drive voltage lines VDDL(1) and VDDL(2) may include a first dummy drive voltage line DVDDL(1) and a second dummy drive voltage line DVDDL(2), respectively, separated by cuts C3, C4, C5, and C6. That is, the first dummy drive voltage line DVDDL(1) and the second dummy drive voltage line DVDDL(2) can be fabricated by forming cuts C3, C4, C5, and C6 in the first and second drive voltage lines VDDL(1) and VDDL(2). The first dummy drive voltage line DVDDL(1) may be the region between the third cut C3 and the fourth cut C4. The second dummy drive voltage line DVDDL(2) may be the region between the fifth cut C5 and the sixth cut C6. The first and second dummy drive voltage lines DVDDL(1) and DVDDL(2), which are not supplied with drive voltage, can be used to electrically connect the repair pattern RPL and the repair gate lines GL2(1) and GL2(2).

[0122] The first and second drive voltage lines VDDL(1) and VDDL(2) may include a third cut section C3, a fourth cut section C4, a fifth cut section C5, and a sixth cut section C6. This allows the drive voltage to be interrupted for the circuit portion in the area where the repair is performed.

[0123] The third and fourth cut sections C3 and C4 may be formed on one first drive voltage line VDDL(1). The fifth and sixth cut sections C5 and C6 may be formed on another second drive voltage line VDDL(2). The third to sixth cut sections C3, C4, C5, and C6 may be located between the branched wiring of the first and second gate lines GL1 and GL2, respectively. This allows the display panel of the present invention according to one embodiment to be easily cut during the cutting process by using the branched wiring of the gate line as a reference.

[0124] The superimposed portion located on one side of the repair pattern RPL contacts the first dummy drive voltage line DVDDL(1) through the fifth contact portion, and the first repair gate line GL2(1) may contact it through the first connecting portion WD1. The superimposed portion located on the other side of the repair pattern RPL contacts the second dummy drive voltage line DVDDL(2) through the fifth contact portion, and the second repair gate line GL2(2) may contact it through the second connecting portion WD2.

[0125] Multiple drive voltage coupling patterns EVDD_1 may include a repair pattern RPL that connects the open portion OP of the second gate line GL2 where a failure has occurred. The repair pattern RPL can be disconnected by two adjacent coupling lines EVDD_a in the lateral direction X, a first disconnection C1, and a second disconnection C2. In other words, the repair pattern RPL can be determined by the first and second disconnections C1 and C2. Such a repair pattern RPL may include two adjacent overlapping portions EVDD_b, and a coupling line EVDD_a between the two adjacent overlapping portions EVDD_b.

[0126] Multiple gate lines GL1, GL2 may include at least one second gate line GL2 having an open section OP. The second gate line GL2 having an open section OP may include: a dummy gate line DGL having an open section OP and positioned between the cutting sections C7, C8, C9, C10; a first repair gate line GL2(1) connected to the repair pattern RPL through a first connecting section WD1; and a second repair gate line GL2(2) connected to the repair pattern RPL through a second connecting section WD2.

[0127] The dummy gate line DGL is separated from the first and second repair gate lines GL2(1) and GL2(2), respectively, and is provided with an open section OP. The dummy gate line DGL may be determined by seventh to tenth cutting sections C7, C8, C9, and C10.

[0128] The first and second repair gate lines GL2(1) and GL2(2) may have a first coupling section WD1 and a second coupling section WD2 in the region where they overlap with two adjacent dummy drive voltage lines DVDDL(1) and DVDDL(2), respectively. The second gate line GL2 may be electrically connected to the repair pattern RPL through the first and second coupling sections WD1 and WD2.

[0129] In the first connecting section WD1, the first repair gate line GL2(1) and the first dummy drive voltage line DVDDL(1), which are arranged in different layers, may come into contact. In the second connecting section WD2, the second repair gate line GL2(2) and the second dummy drive voltage line DVDDL(2), which are arranged in different layers, may come into contact. Each of the repair gate lines GL2(1), GL2(2), and the dummy drive voltage lines DVDDL(1), DVDDL(2) may come into contact by welding through a laser process. However, the method of contact between each of the repair gate lines GL2(1), GL2(2), and the dummy drive voltage lines DVDDL(1), DVDDL(2) is illustrative, and the display panel of the present invention according to one embodiment is not limited thereto.

[0130] The circuit section in the area where the repair is performed cannot operate normally because the drive voltage is not supplied. In this case, the circuit section in the area where the repair is performed may include cuts in the drive voltage line VDDL and the second gate line GL2 to prevent abnormal operation.

[0131] The second gate line GL2 may further include a seventh cut section C7, an eighth cut section C8, a ninth cut section C9, and a tenth cut section C10. This allows the gate pulse to be interrupted for the circuit portion in the region where the repair is performed.

[0132] The seventh to tenth cut sections C7, C8, C9, and C10 may be located outside the signal lines of the circuit sections supplied with the signal for the second gate line GL2, at least in the area where the repair is performed. For example, the seventh to tenth cut sections C7, C8, C9, and C10 may be located outside the third' and fourth' circuit sections CA3' and CA4' supplied with the signal for the second gate line GL2. For example, with respect to different drive voltage lines VDDL between which a repair pattern is placed, the seventh to tenth cut sections C7, C8, C9, and C10 may be formed in the region of the second gate line GL2 adjacent to one drive voltage line VDDL and in the region of the second gate line GL2 adjacent to the other drive voltage line VDDL, respectively.

[0133] However, the display panel of the present invention according to one embodiment is not limited to the number and location of the cut sections as shown and described. For example, the seventh and eighth cut sections C7, C8, or the ninth and tenth cut sections C9, C10 formed in the second gate line GL2 can also be formed as a single cut section.

[0134] Furthermore, it may further include a disconnection section that disconnects the branch wiring DL1_1, DL2_1, DL3_1, DL4_1 of the first to fourth data lines DL1, DL2, DL3, DL4, which are connected by the respective circuit sections CA1, CA2, CA3, CA4, and the branch wiring RL_1, RL_2, RL_3, L_4 of the reference voltage line RL, so as to prevent abnormal operation of the circuit section by supplying various signals to the area where the repair is performed.

[0135] Referring to Figure 7B, the repaired second gate line GL2 can be supplied with gate pulses along the first signal path SS. The first signal path SS can proceed sequentially along the first repaired gate line GL2(1), the first dummy drive voltage line DVDDL(1), the repair pattern RPL, the second dummy drive voltage line DVDDL(2), and the second repaired gate line GL2(2).

[0136] Figures 8A to 8D are plan views showing the repair process according to one embodiment. Figures 9A to 9D are schematic circuit diagrams showing the repair process according to one embodiment. Figures 10A to 10C are cross-sectional views showing the repair process according to one embodiment.

[0137] Figures 9A to 9D are schematic circuit diagrams corresponding to Figures 8A to 8D, respectively. Also, Figures 8A and 9A, 8B and 9B, 8C and 9C, and 8D and 9D represent the same process stage. Figures 10A to 10C are cross-sectional process views of the connecting portions WD1 and WD2 formed in Figures 8C and 9C.

[0138] Furthermore, the welding process shown in Figures 8C and 9C can be performed before the cutting process shown in Figures 8B and 9B.

[0139] Referring to Figures 8A and 9A, an open section OP can be provided on the second gate line GL2. The open section OP may be located on the second gate line GL2 adjacent to the third circuit section CA3'. For example, the open section OP may overlap with at least one of the branch wiring DL3_1 of the third data line DL3 and the branch wiring RL_3 of the reference voltage line RL.

[0140] Referring to Figures 8B and 9B, the first to tenth cut sections C1, C2, C3, C4, C5, C6, C7, C8, C9, and C10 can be formed through the cutting process. The first to tenth cut sections C1, C2, C3, C4, C5, C6, C7, C8, C9, and C10 may be located outside the area where the repair is performed. The first to tenth cut sections C1, C2, C3, C4, C5, C6, C7, C8, C9, and C10 can cut a portion of the signal wiring through the laser process. As a result, the first to tenth cut sections C1, C2, C3, C4, C5, C6, C7, C8, C9, and C10 can supply various signals to the area where the repair is performed, preventing abnormal operation of the circuit section.

[0141] The first and second disconnections C1 and C2 may be formed in the drive voltage coupling pattern EVDD_1. In this case, the drive voltage coupling pattern EVDD_1 between the first and second disconnections C1 and C2 may become a repair pattern RPL.

[0142] Third to sixth cuts C3, C4, C5, and C6 may be formed in the drive voltage line VDDL. A first dummy drive voltage line DVDDL(1) may be formed between the third and fourth cuts C3 and C4, and a second dummy drive voltage line DVDDL(2) may be formed between the fifth and sixth cuts C5 and C6. This allows the drive voltage to be interrupted in the area where the repair is performed.

[0143] The seventh to tenth cut sections C7, C8, C9, and C10 may be formed in the second gate line GL2. A dummy gate line DGL may be formed between the seventh and eighth cut sections C7 and C8 and the ninth and tenth cut sections C9 and C10, with an open section OP. A first repair gate line GL2(1) superimposed on the first dummy drive voltage line DVDDL(1) may be formed, and a second repair gate line GL2(2) superimposed on the second dummy drive voltage line DVDDL(2) may be formed. This allows the gate pulse to be interrupted in the region where repair is performed.

[0144] However, the display panel of the present invention according to one embodiment is not limited to the number and position of the cut sections as shown and described.

[0145] Referring to Figures 8C and 9C, through the welding process, connecting portions WD1 and WD2 can be formed in the region where the repair gate lines GL2(1) and GL2(2) and the dummy drive voltage lines DVDDL(1) and DVDDL(2) overlap. The first connecting portion WD1 can be formed in the overlapping region of the first repair gate line GL2(1) and the first dummy drive voltage line DVDDL(1), and the second connecting portion WD2 can be formed in the overlapping region of the second repair gate line GL2(2) and the second dummy drive voltage line DVDDL(2). The first and second connecting portions WD1 and WD2 can electrically connect the repair gate lines GL2(1) and GL2(2) to the repair pattern RPL through the dummy drive voltage lines DVDDL(1) and DVDDL(2).

[0146] In each of the first and second connecting sections WD1 and WD2, one of the repair gate lines GL2(1) and GL2(2) and the dummy drive voltage lines DVDDL(1) and DVDDL(2), which are arranged in different layers, is welded so that the two components can come into contact. The method for forming the first and second connecting sections WD1 and WD2 will be explained with reference to Figures 10A to 10C.

[0147] Referring to Figure 10A, one embodiment of the present invention may comprise: a substrate 10; a drive voltage line 11 disposed on the substrate 10; a first insulating layer 20 covering the drive voltage line 11; a second insulating layer 21 disposed on the first insulating layer 20; a second gate line 23 disposed on the second insulating layer 21; a third insulating layer 30 covering the second gate line 23; and a fourth insulating layer 40 disposed on the third insulating layer 30.

[0148] Referring to Figure 10B, a laser process can be performed while a laser is irradiated from below the substrate 10. Through the laser process, the drive voltage line 11 can be welded.

[0149] Referring to Figure 10C, the welded drive voltage line 11a may come into contact with the second gate line 23. The laser process can be terminated when the welded drive voltage line 11a and the second gate line 23 come into contact (CTa). At this point, a gap 11b may be formed between the welded drive voltage line 11a and the substrate 10.

[0150] Next, referring to Figures 8D and 9D, the first and second connecting parts WD1 and WD2 are formed, and the gate pulse of the second gate line GL2 can be supplied through the repair pattern RPL. Therefore, the first signal path SS to which the gate pulse of the second gate line GL2 is supplied can proceed sequentially along the first repair gate line GL2(1), the first dummy drive voltage line DVDDL(1), the repair pattern RPL, the second dummy drive voltage line DVDDL(2), and the second repair gate line GL2(2).

[0151] Figure 11 is a plan view showing a defective pixel according to one embodiment. Figure 12 is a schematic circuit diagram showing a defective pixel according to one embodiment. Figures 11 and 12 show the state after the repair process described above has been performed.

[0152] Referring to Figures 11 and 12, one embodiment of the present invention may include an open section OP on one of the multiple first and second gate lines GL1 and GL2, specifically on the second gate line GL2, and may include a repair pattern RPL for repairing the open section OP.

[0153] Performing a repair process on the second gate line GL2 may result in the supply of normal signals to the third and fourth circuit sections CA3' and CA4' of the second pixel PXL2, and to the first and second circuit sections CA1' and CA2' of the second' pixel PXL2'. For example, the third and fourth subpixels SP3 and SP4 of the second pixel PXL2, and the first and second subpixels SP1' and SP2' of the second' pixel PXL2' may be in a non-operating state D.

[0154] On the other hand, normal signals can be supplied to the first' and second' circuit sections CA1' and CA2' of the second pixel PXL2, and to the third' and fourth' circuit sections CA3' and CA4' of the second' pixel PXL2'. For example, the first and second subpixels SP1 and SP2 of the second pixel PXL2, and the third' and fourth' subpixels SP3' and SP4' of the second' pixel PXL2' can be in a normal state N.

[0155] Figure 13 is a schematic diagram illustrating a data copy repair method for defective pixels according to one embodiment.

[0156] Referring to Figure 13, one embodiment of the present invention may comprise an anode electrode AND corresponding to each subpixel, and a pixel repair section RP_P arranged in the circuit section of each subpixel.

[0157] An anode electrode AND according to one embodiment of the present invention may be arranged to correspond to each of a plurality of subpixels SP1, SP2, SP3, SP4, SP1', SP2', SP3', SP4'. For example, an anode electrode AND corresponding to a third' subpixel SP3' may include: a first anode electrode AND_1 superimposed on a third' light-emitting portion EA3'; a second anode electrode AND_2 superimposed on a third' circuit portion CA3'; and a third anode electrode AND_3 extending from the first anode electrode AND_1 to another third subpixel SP3. Here, the third anode electrode AND_3 of the third' subpixel SP3' may partially superimpose on a pixel repair portion RP_P located in the third circuit portion CA3' of another third subpixel SP3.

[0158] Figures 14A to 14C are plan views showing the pixel repair process according to one embodiment. Figures 15A to 15C are schematic circuit diagrams showing the pixel repair process according to one embodiment. Figures 16A to 16C are cross-sectional views showing the pixel repair process according to one embodiment. Each of Figures 14A to 14C represents the same process stage as each of Figures 15A to 15C.

[0159] Referring to Figures 14A and 15A, the third anode electrode portion AND_3 corresponding to the third' subpixel SP3' can be superimposed on the light-shielding layer LS located on the third' circuit portion CA3' of another third subpixel SP3. In this case, the light-shielding layer LS is provided with a pixel repair portion RP_P, and the pixel repair portion RP_P can be superimposed on the third anode electrode portion AND_3.

[0160] Referring to Figures 14B and 15B, a third connecting portion WD3 can be formed in the pixel repair portion RP_P. In the third connecting portion WD3, the third anode electrode portion AND_3 of the third' subpixel SP3' and the light-shielding layer LS of the third subpixel SP3 can come into contact. For example, through a laser process, the third anode electrode portion AND_3 of the third' subpixel SP3' or the light-shielding layer LS of the third subpixel SP3 can be welded, and at this time, the third anode electrode portion AND_3 and the light-shielding layer LS can come into contact. The method for forming the third connecting portion WD3 will be explained in relation to Figures 16A to 16C.

[0161] Referring to Figure 16A, a display panel of the present invention according to one embodiment may comprise: a substrate 10; a light-shielding layer 111 disposed on the substrate 10; a first insulating layer 20 covering the light-shielding layer 111; a third insulating layer 30 disposed on the first insulating layer 20; a fifth insulating layer 50 disposed on the third insulating layer 30; a third anode electrode portion 81 disposed between the first insulating layer 20 and the fifth insulating layer 50; an intermediate layer 83 disposed on the third anode electrode portion 81; and a cathode electrode 85 disposed on the fifth insulating layer 50.

[0162] Here, the third anode electrode portion 81 is the same as the third anode electrode portion AND_3 of the third' subpixel SP3' shown in Figures 14B and 15B, and the light-shielding layer 111 is the same as the light-shielding layer LS of the third subpixel SP3 shown in Figures 14B and 15B.

[0163] Referring to Figure 16B, the laser process can be carried out while a laser is irradiated from below the substrate 10. Through the laser process, the light-shielding layer 111 can be welded.

[0164] Referring to Figure 16C, the welded light-shielding layer 111a can come into contact with the third anode electrode AND_3. The laser process can be completed when the welded light-shielding layer 111a and the third anode electrode AND_3 come into contact (CTb). At this point, a gap 111b may be formed between the welded light-shielding layer 111a and the substrate 10.

[0165] Next, referring to Figures 14C and 15C, the pixel drive data of the third subpixel SP3' can be transmitted to the light-shielding layer LS of the third subpixel SP3 through the third coupling portion WD3. At this time, the light-shielding layer LS of the third subpixel SP3 may be electrically connected to a driving element that causes the third' light-emitting portion EA3' of the third subpixel SP3 to emit light, and the driving element may be electrically connected to the second anode electrode portion AND_2 of the third subpixel SP3.

[0166] This allows the drive data of the third' subpixel SP3', copied to the light-shielding layer LS of the third subpixel SP3, to be sequentially supplied to the second anode electrode AND_2 and the first anode electrode AND_1 of the third subpixel SP3. For example, the second signal path DS of the pixel drive data supplied in the repaired normal state Nr can sequentially proceed along the third anode electrode AND_3 of the third' subpixel SP3', the light-shielding layer LS of the third subpixel SP3, the drive element of the third subpixel SP3, the second anode electrode AND_2 and the first anode electrode AND_1 of the third subpixel SP3.

[0167] Such a pixel repair process can be performed on the first', second', third, and fourth subpixels SP1', SP2', SP3, and SP4 in the non-operating state D. For example, the first' subpixel SP1' can undergo the pixel repair process with the first subpixel SP1, the second' subpixel SP2' can undergo the pixel repair process with the second subpixel SP2, the third subpixel SP3 can undergo the pixel repair process with the third' subpixel SP3', and the fourth subpixel SP4 can undergo the repair process with the fourth' subpixel SP4'.

[0168] As a result, in one embodiment of the present invention, the display panel can normalize a defective pixel by copying data from an adjacent pixel through a gate repair process.

[0169] While embodiments of the present invention have been described in more detail above with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and can be implemented in various ways without departing from the technical concept of the present invention.

[0170] Therefore, the embodiments disclosed in this invention are intended to illustrate, not to limit, the technical concept of the invention, and the scope of the technical concept of the invention is not limited by such embodiments.

[0171] Therefore, the examples described above should be understood in all respects as illustrative and not limiting.

[0172] The scope of protection of this invention shall be interpreted as per the claims, and any technical ideas within an equivalent scope shall be interpreted as being included within the scope of the rights of this invention. [Explanation of Symbols]

[0173] VDDL: Drive voltage line EVDD_1: Drive voltage coupling pattern GL1: First Gate Line GL2: Second Gate Line RPL: Repair Pattern OP: Open Section DVDDL(1): 1st dummy drive voltage line DVDDL(2): Second dummy drive voltage line

Claims

1. A first drive voltage line and a second drive voltage line are spaced apart from each other with a pixel in between, A plurality of drive voltage coupling patterns that connect the first and second drive voltage lines, It comprises a plurality of gate lines that intersect the first and second drive voltage lines, The plurality of gate lines include at least one gate line having an open section, A display panel in which the plurality of drive voltage coupling patterns include a repair pattern that connects the open portion of at least one gate line.

2. Each of the aforementioned plurality of drive voltage coupling patterns is A superimposed portion that contacts each of the first and second drive voltage lines, Includes a connecting line that connects the overlapping portions, The display panel according to claim 1, wherein the repair pattern includes the overlapping portion and the connecting line.

3. The first drive voltage line is, First cutting section and The first cutting portion is separated from the first drive voltage line by a first dummy drive voltage line, and includes the first dummy drive voltage line, The second drive voltage line is The second cutting section and The second cutting portion is separated from the second drive voltage line by a second dummy drive voltage line, and the second dummy drive voltage line is also included. The display panel according to claim 2, wherein the superimposed portion of the repair pattern is in contact with the first and second dummy drive voltage lines, respectively.

4. The at least one gate line includes a first repair gate line and a second repair gate line that are spaced apart from each other with the open portion in between. The display panel according to claim 3, wherein the first and second repair gate lines are electrically connected to the respective overlapping portions of the repair pattern.

5. A first connecting portion located at the intersection of the first repair gate line and the first dummy drive voltage line, The present invention further includes a second connecting portion located at the intersection of the second repair gate line and the second dummy drive voltage line, The display panel according to claim 4, wherein each of the first and second repair gate lines and each of the first and second dummy drive voltage lines are in contact at the first and second connecting portions, respectively.

6. The system further includes a reference voltage line positioned between the first and second drive voltage lines, The display panel according to claim 2, wherein the connecting line partially overlaps the reference voltage line along the longitudinal direction of the reference voltage line.

7. The aforementioned pixel comprises a plurality of pixels, including a first pixel and a second pixel. Each of the plurality of pixels includes a circuit section, a light-emitting section, and at least one anode electrode. The anode electrode is A first anode electrode section superimposed on the light-emitting section, A second anode electrode portion extends from the first anode electrode portion and overlaps with the circuit portion, It includes a third anode electrode portion that extends from the first anode electrode portion and overlaps with the circuit portion of another adjacent pixel, The display panel according to claim 1, wherein the third anode electrode portion of the first pixel is in contact with the circuit portion of the second pixel via the third connecting portion.

8. The aforementioned pixel comprises a plurality of pixels, including a first pixel and a second pixel. Each of the aforementioned plurality of pixels comprises a plurality of sub-pixels that emit different colors from each other. The display panel according to claim 1, wherein each of the first pixel and the second pixel emits the same color subpixels, which are supplied with the same data signal and different gate pulses from each other.

9. A first step of forming a first drive voltage line and a second drive voltage line spaced apart from each other with a pixel in between, and a plurality of drive voltage connection patterns connecting the first and second drive voltage lines, The process includes a second step of forming a plurality of gate lines that intersect with the first and second drive voltage lines, The plurality of gate lines include at least one gate line having an open section, A method for repairing a display panel, comprising: a third step of separating at least one of the plurality of drive voltage coupling patterns from the first and second drive voltage lines and forming a repair pattern that connects the open portion of the at least one gate line.

10. The third step includes a third-first step of forming a first cut portion and a second cut portion in each of the first and second drive voltage lines, In the above-mentioned 3-1 stage, A first dummy drive voltage line is formed between the first cut portions, separated from the first drive voltage line. A method for repairing a display panel according to claim 9, wherein a second dummy drive voltage line is formed between the second cut portions, separated from the second drive voltage line.

11. The repair pattern contacts each of the first and second dummy drive voltage lines, The at least one gate line overlaps with the first and second dummy drive voltage lines on both sides of the open portion, The method for repairing a display panel according to claim 10, wherein the third step includes a third-second step of forming a connecting portion in the overlapping region of at least one gate line and each of the first and second dummy drive voltage lines.

12. In the above-mentioned 3-2 stage, The method for repairing a display panel according to claim 11, wherein at least one gate line and each of the first and second dummy drive voltage lines are in contact at each of the connecting portions.

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