Semiconductor devices and power converters

Abstract

To provide a semiconductor device that can suppress the snapback phenomenon in RC-IGBTs when the IGBTs turn on and the hole injection from the IGBT region to the diode region during diode conduction with a simple structure.SOLUTION: In a semiconductor device having an IGBT region 21 and a diode region 22 in the same chip, the gate resistance R of the IGBTs near the boundary between the IGBT region 21 and the diode region 22 is greater than the gate resistance of the IGBTs near the center of the IGBT region 21.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a power conversion device.

Background Art

[0002] An RC-IGBT (RC: Reverse-Conducting, reverse-conducting IGBT) incorporating an IGBT (Insulated Gate Bipolar Transistor) and a diode in the same chip has the advantage of reducing the chip size because the termination regions of the IGBT and the diode can be shared. Also, since the operating timings of the IGBT and the diode are different, heat generated by losses in either the IGBT region or the diode region is dispersed to the other, enabling heat dissipation across the entire chip, so there is also the advantage of reducing the thermal resistance.

[0003] On the other hand, in an RC-IGBT, when the IGBT is turned on, electrons injected from the surface side of the IGBT near the boundary with the diode, in particular, do not escape from the p layer, which is the collector layer on the back side of the IGBT, but escape to the n+ layer, which is the cathode layer of the diode. There is a problem that a snap-back phenomenon occurs when the IGBT is turned on, that is, hole injection from the p layer on the back side does not occur unless a voltage higher than the built-in voltage of the pn junction on the back side is applied.

[0004] Furthermore, in RC-IGBTs, when the IGBT is turned off and the potential of the surface electrode becomes higher than the potential of the back electrode, causing the diode to conduct, hole injection into the diode region occurs, particularly from the p-layer, which is the surface body layer of the IGBT near the boundary with the diode. This increases the concentration of holes in the drift layer near the boundary between the diode region and the IGBT region. Subsequently, when the potential of the surface electrode becomes lower than the potential of the back electrode and the diode recovers, a recovery current flows as the holes in the drift layer flow toward the surface electrode. However, because the concentration of holes is high near the boundary between the diode region and the IGBT region, a high density of recovery current flows near the boundary, placing a high load on the semiconductor substrate. This presents a problem of hole injection from the IGBT region to the diode region when the diode conducts.

[0005] Here, Patent Document 1 describes a semiconductor substrate having an IGBT region overlapping with the collector region, a diode region overlapping with the cathode region, a drift region distributed across the IGBT region and the diode region, a body region, a body contact region, and an emitter region located within the IGBT region, and an anode region and an anode contact region located within the diode region, wherein the body region has a first body region and a second body region having a lower p-type impurity concentration than the first body region and the anode region, and the second body region is located in the anode region A semiconductor device is described in which the first body region is adjacent to the second body region on the opposite side of the anode region (abstract, Figure 2).

[0006] According to the semiconductor device described in Patent Document 1, since the p-type impurity concentration in the second body region adjacent to the anode region is low, when the diode is turned on, there are fewer holes flowing from the second body region toward the cathode region. As a result, the concentration of holes in the drift region near the boundary between the diode region and the IGBT region is not very high, and a high recovery current is suppressed from flowing near the boundary between the diode region and the IGBT region during recovery operation, thereby reducing the load on the semiconductor substrate (paragraph 0007).

[0007] Thus, Patent Document 1 describes a structure that solves the problem of hole injection from the IGBT region to the diode region when the diode is conducting. Furthermore, although Patent Document 1 does not mention the problem of snapback when the IGBT is turned on, it is thought that this can also be solved by the structure described in Patent Document 1. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2019-106430 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] However, Patent Document 1 presents the problem that, in order to lower the p-type impurity concentration in the body region of the IGBT near the boundary (the second body region of the IGBT adjacent to the anode region) compared to the body region of the IGBT near the center (the first body region of the IGBT), new photolithography and implantation processes are required, which increases manufacturing costs.

[0010] Therefore, the problem that the invention aims to solve is to provide a semiconductor device and a power converter that can suppress the snapback phenomenon when the IGBT is turned on and the hole injection from the IGBT region to the diode region when the diode conducts, with a simple structure in an RC-IGBT. [Means for solving the problem]

[0011] To solve this problem, the semiconductor device of the present invention is characterized in that, for example, in a semiconductor device having an IGBT region and a diode region on the same chip, the gate resistance of the IGBT near the boundary between the IGBT region and the diode region is greater than the gate resistance of the IGBT near the center of the IGBT region.

[0012] Furthermore, the power conversion device of the present invention is characterized by having, for example, the semiconductor device as a switching element. [Effects of the Invention]

[0013] According to the present invention, by making the gate resistance of the IGBT near the boundary greater than that of the IGBT near the center, when the IGBT is turned on, the IGBT near the center, which is further away from the boundary, turns on before the IGBT near the boundary. As a result, the path of electrons from the IGBT near the center to the cathode layer of the diode is longer, and a voltage drop occurs as electrons flow along this length, resulting in a forward bias. When this exceeds the built-in voltage, hole injection from the collector layer on the back side begins, thus suppressing the snapback phenomenon when the IGBT is turned on.

[0014] Furthermore, by using a simple structure in which the gate resistance of the IGBTs near the boundary is greater than that of the IGBTs near the center, when the IGBTs turn off, the IGBTs near the center, which are further away from the boundary, turn off before the IGBTs near the boundary. Since the IGBTs near the center turn off first and are further away, the amount of hole injection from them is small, and the IGBTs near the boundary, which turn off later, have a shorter time for hole injection, thus reducing the amount of hole injection from them. In this way, compared to when they turn off simultaneously, hole injection from the IGBT region to the diode region during diode conduction can be suppressed. [Brief explanation of the drawing]

[0015] [Figure 1] A cross-sectional view illustrating the schematic configuration of the semiconductor device of Example 1. [Figure 2] A plan view illustrating the gate wiring shape of the semiconductor device in Example 1. [Figure 3] A plan view illustrating the gate wiring shape of the semiconductor device in Example 2. [Figure 4] Current-voltage characteristics illustrating the snapback phenomenon in RC-IGBTs.

Best Mode for Carrying Out the Invention

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant descriptions are omitted.

Embodiment

[0017] FIG. 1 is a cross-sectional view for explaining a schematic configuration of a semiconductor device according to Embodiment 1.

[0018] The semiconductor device 100 according to Embodiment 1 is an RC-IGBT and has an IGBT region 21 and a diode region 22 in the same chip (on the same semiconductor substrate).

[0019] An IGBT is formed in the IGBT region 21. The IGBT includes, for example, a drift layer 1 of a first conductivity type (n-type in FIG. 1), a trench 3, a gate electrode 5 provided in the trench 3, a body layer 2 of a second conductivity type (p-type in FIG. 1) provided adjacent to the trench 3 on the surface side of the drift layer 1, an emitter layer 7 of the first conductivity type provided on the surface side of the body layer 2, and a collector layer 11 of the second conductivity type provided on the back side of the drift layer 1.

[0020] In FIG. 1, an example in which the first conductivity type is n-type and the second conductivity type is p-type is used for explanation, but the present invention is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type. In that case, electrons and holes are reversed.

[0021] A diode is formed in the diode region 22. The diode includes, for example, a drift layer 1, a body layer 2 that functions as an anode layer of the second conductivity type provided on the surface side of the drift layer 1, and a cathode layer 12 of the first conductivity type provided on the back side of the drift layer 1.

[0022] Furthermore, the semiconductor device 100 has, in common to both the IGBT region 21 and the diode region 22, a first conductivity type buffer layer 10 formed between the collector layer 11 or cathode layer 12 and the drift layer 1, a surface electrode 13, an interlayer insulating film 9 provided between the emitter layer 7 or body layer 2 and the surface electrode 13, and a back electrode 14.

[0023] The surface electrode 13 is connected to the body layer 2 in the IGBT region 21 and the diode region 22 via contact holes and a second conductivity type body contact layer 8. Therefore, the surface electrode 13 has an emitter potential E and an anode potential A.

[0024] The gate electrode 5 is adjacent to the body layer 2 and the emitter layer 7 via an insulating film 4 formed in the trench 3. The gate electrode 5 is supplied with a gate potential G from a gate drive circuit (not shown) or the like.

[0025] The diode region 22 also has a trench 3, and an insulating film 4 and a dummy electrode 6 are provided within the trench 3 of the diode region 22. The dummy electrode 6 is supplied with, for example, the emitter potential E, but is not limited to this, and may be supplied with other potentials such as the gate potential.

[0026] The impurity concentrations in each layer are as follows: for example, the drift layer 1 has a low concentration of n- impurities, the emitter layer 7 has a high concentration of n+ impurities, and the cathode layer 12 has a high concentration of p+ impurities.

[0027] Here, the semiconductor device 100 of Example 1 is characterized in that the gate resistance R of the IGBT near the boundary between the IGBT region 21 and the diode region 22 is greater than the gate resistance of the IGBT near the center of the IGBT region 21.

[0028] This simple structure allows the IGBTs near the boundary to turn on later than the IGBTs near the center, thus suppressing the snapback phenomenon when the IGBTs turn on, as will be described later. Furthermore, the IGBTs near the boundary turn off later than the IGBTs near the center, thus suppressing hole injection from the IGBT region to the diode region when the diode conducts, as will be described later.

[0029] Figure 4 shows the current-voltage characteristics illustrating the snapback phenomenon in an RC-IGBT. In Figure 4, the horizontal axis represents voltage V and the vertical axis represents current I. In Figure 4, the characteristic without snapback 31 is shown by a dotted line, and the characteristic with snapback 32 is shown by a solid line.

[0030] In typical IGBTs, as shown in characteristic 31 without snapback, hole injection begins when the pn junction on the back side (the p-type collector layer 11 and the n-type buffer layer 10 in Figure 1) exceeds the built-in voltage, initiating IGBT operation, and the current I rises in a curve-like manner with respect to the voltage V.

[0031] However, in an RC-IGBT, when the IGBT is turned on, the voltage at the pn junction on the back side is initially lower than the built-in voltage. Therefore, near the boundary between the IGBT region 21 and the diode region 22, electrons 15 injected from the body layer 2 on the front side of the IGBT do not escape from the p layer, which is the collector layer 11 on the back side of the IGBT, but instead escape to the n+ layer, which is the cathode layer 12 of the diode. As shown in characteristic 32 with snapback, the MOS operation initially occurs where the current I increases linearly with respect to the voltage V. This is because the structure of the IGBT with the p layer on the back side replaced with an n+ layer is the same as the structure of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Subsequently, when the voltage across the pn junction on the back side rises and exceeds the built-in voltage, IGBT operation begins. At that time, the characteristics return to the same as characteristic 31 without snapback, so the voltage V temporarily decreases as shown in characteristic 32 with snapback. This phenomenon is called the snapback phenomenon. When the snapback phenomenon occurs, the voltage during MOS operation becomes higher compared to the waveform during normal IGBT operation, resulting in a greater loss.

[0032] In contrast, the semiconductor device 100 of Example 1 has a simple structure in which the gate resistance R of the IGBT near the boundary is larger than that of the IGBT near the center. As a result, when the IGBT is turned on, the IGBT near the center, which is further away from the boundary, turns on before the IGBT near the boundary. Therefore, as shown in Figure 1, the path of electrons 15 from the IGBT near the center to the cathode layer 12 of the diode is longer, as the electrons 15 flow along that length and near the surface of the pn junction on the back side. This causes a voltage drop and a forward bias, and when it exceeds the built-in voltage, hole injection from the collector layer 11 on the back side begins, thus suppressing the snapback phenomenon when the IGBT is turned on.

[0033] Furthermore, in the semiconductor device 100 of Example 1, a simple structure is used in which the gate resistance R of the IGBT near the boundary is larger than that of the IGBT near the center. As a result, when the IGBTs turn off, the IGBTs near the center, which are further away from the boundary, turn off before the IGBTs near the boundary. The IGBTs near the center, which turn off first, are further away, so the amount of hole injection from them is small. The IGBTs near the boundary, which turn off later, have a shorter time for hole injection, so the amount of hole injection from them can be reduced. Therefore, compared to when they turn off simultaneously, hole injection from the IGBT region 21 to the diode region 22 during diode conduction can be suppressed.

[0034] Next, we will describe a method for making the gate resistance R of the IGBT near the boundary larger than that near the center in Example 1.

[0035] Figure 2 is a plan view illustrating the gate wiring shape of the semiconductor device of Example 1.

[0036] As shown in Figure 2, the gate wiring of the semiconductor device 100 in Embodiment 1 includes a gate common wiring 16, also called a gate finger, and gate lead wiring 17 that connects the gate common wiring 16 to each gate electrode 5, supplying a gate potential G to the gate electrode 5 via the gate wiring. In addition, each dummy electrode 6 of the diode region 22 is connected by dummy wiring 18, and an emitter potential E is supplied to it.

[0037] Furthermore, the gate lead wires 17 of the IGBTs near the boundary are thinner than the gate lead wires 17 of the IGBTs near the center. This allows the gate resistance R of the IGBTs near the boundary to be greater than that of the IGBTs near the center.

[0038] Here, it is desirable that the gate extraction wiring 17 gradually becomes thicker as it goes from near the boundary portion to near the central portion. In FIG. 2, an example is shown in which the width of the gate extraction wiring 17 becomes thicker as Wc < Wb < Wa as it goes from near the boundary portion to near the central portion. Thereby, the effect of Example 1 can be obtained more effectively.

[0039] In addition, since it can be realized only by changing the shape of the gate wiring, when manufacturing, it is only necessary to change the mask shape for patterning the gate wiring, and no new photo process or implant process is required, so there is no increase in manufacturing cost.

Example

[0040] FIG. 3 is a plan view for explaining the shape of the gate wiring of the semiconductor device of Example 2.

[0041] Example 2 is a modification of Example 1. The difference from Example 1 is that the gate extraction wiring 17 is connected and integrated with each other for the gate extraction wirings 17 for the adjacent gate electrodes 5 in the vicinity of the central portion. In this case, the width of the gate extraction wiring 17 corresponding to each gate electrode 5 can be considered to be like Wa shown in FIG. 3 because the middle point up to the middle point between the adjacent gate electrodes 5 is considered as the virtual delimiter of the gate extraction wiring 17. Thereby, the gate resistance of the IGBT in the vicinity of the central portion can be made smaller than that in Example 1. Since the rest is the same as in Example 1, duplicate explanations are omitted.

Example

[0042] Example 3 is an example of a power conversion device using the semiconductor device of Example 1 or Example 2 as a switching element. Since the configuration of the power conversion device is the same as a general configuration, detailed explanation is omitted.

[0043] As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Also, a part or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0044] 1. Drift Layer 2 Body Layers 3 Trench 4. Insulating film 5 gates 6 Dummy electrodes 7. Emitter layer 8 Body Contact Layers 9 Interlayer insulating film 10 buffer layers 11 Collector layer 12 Cathode Layers 13 Surface electrode 14 Backside electrode 15 electron 16-gate common wiring 17 Gate Outlet Wiring 18 Dummy Wiring 21 IGBT area 22 Diode region 31 Characteristics without snapback 32 Characteristics of snapback 100 Semiconductor Equipment G gate potential E emitter potential Anode potential R resistance I current V Voltage

Claims

1. In a semiconductor device having an IGBT region and a diode region within the same chip, A semiconductor device characterized in that the gate resistance of the IGBT near the boundary between the IGBT region and the diode region is greater than the gate resistance of the IGBT near the center of the IGBT region.

2. In claim 1, A semiconductor device characterized in that the timing at which the IGBTs near the boundary are turned on is later than the timing at which the IGBTs near the central part are turned on.

3. In claim 1, A semiconductor device characterized in that the timing at which the IGBTs near the boundary turn off is later than the timing at which the IGBTs near the central part turn off.

4. In claim 1, A semiconductor device characterized in that the gate lead wiring of the IGBTs near the boundary is thinner than the gate lead wiring of the IGBTs near the central portion.

5. In claim 4, The semiconductor device is characterized in that the gate lead wiring gradually becomes thicker as it moves from the vicinity of the boundary to the vicinity of the central part.

6. In claim 1, The IGBT comprises a first-conductivity drift layer, a trench, a gate electrode provided within the trench, a second-conductivity body layer provided adjacent to the trench on a surface side of the drift layer, a first-conductivity emitter layer provided on the surface side of the body layer, and a second-conductivity collector layer provided on a back side of the drift layer. The semiconductor device is characterized in that the diode in the diode region comprises the drift layer, the body layer which functions as a second conductivity type anode layer provided on the surface side of the drift layer, and the first conductivity type cathode layer provided on the back side of the drift layer.

7. A power conversion device characterized by having a semiconductor device according to any one of claims 1 to 6 as a switching element.

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