Semiconductor equipment

Abstract

To provide a highly reliable semiconductor device in which a semiconductor chip is mounted on a substrate by sinter bonding, which can prevent a rising portion from falling off due to protrusion of a sinter bonding material without using a specific jig.SOLUTION: A semiconductor device includes a substrate, a semiconductor chip, a sintered metal layer that joins the substrate and the semiconductor chip, a first resin layer formed in contact with a side surface of the sintered metal layer, a second resin layer that contacts the first resin layer and covers the first resin layer, and a gel-like sealant that contacts the second resin layer and seals the substrate and the semiconductor chip.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present invention relates to the structure of a semiconductor device, and particularly to a technique effective when applied to a semiconductor device in which a semiconductor chip is mounted on a substrate by sintering bonding.

Background Art

[0002] In recent years, environmental and resource issues on a global scale have been in the spotlight. For the effective utilization of resources, the promotion of energy conservation, and the suppression of greenhouse gas emissions, high-efficiency power conversion devices represented by inverter devices using the switching of power semiconductor devices have attracted attention. Such power conversion devices are widely applied to home appliances such as refrigerators and air conditioners, industrial machinery, hybrid electric vehicles (HEVs), electric vehicles (EVs), railways, power, and social infrastructure-related equipment.

[0003] A power conversion device is composed of many components such as a power semiconductor device (power module) incorporating a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), a bus bar, a capacitor, an inductor, various sensors, and a control circuit. For the purpose of reducing the installation area and ensuring safety, a small and highly reliable power conversion device is required. For this, the miniaturization and high reliability of the power semiconductor device, which is a main component of the power conversion device, are important.

[0004] Currently, IGBTs, diodes, etc. mainly made of Si are used as the power semiconductor elements incorporated in the power semiconductor device. The power semiconductor device is progressing in miniaturization and large capacity as described above, and along with this, stable operation at high temperatures is required.

[0005] Furthermore, power semiconductor devices are required to have "high voltage resistance," "low on-resistance," and "high-speed switching" characteristics. SiC, which has a dielectric breakdown field strength 10 times that of Si and a band gap 3 times that of Si, is beginning to be applied as a next-generation power semiconductor device and is expected to become widespread. Because this next-generation power semiconductor device can be used at even higher temperatures than Si devices, high reliability at high temperatures is required for power semiconductor devices.

[0006] Various technologies are being researched and developed to address these technical challenges. One example is a bonding technology using metal nanoparticles. Because metal nanoparticles have high chemical activity due to their surface energy being greater than their volume energy, the sintering temperature is significantly reduced, while after sintering they exhibit the high heat resistance inherent to the metal. Therefore, they can be suitably used as bonding materials for semiconductor devices in high-temperature environments.

[0007] However, in the manufacturing method of semiconductor devices using metal nanoparticles, during pressure bonding, some of the paste containing excess metal nanoparticles may protrude outside the semiconductor device and adhere to wiring and other parts, causing a short circuit.

[0008] To solve such problems, there is a technology such as that described in Patent Document 1. In Patent Document 1, a bonding jig is used which has an opening into which a semiconductor element can be loosely inserted and a bonding material relief portion at the opening edge of the opening having an opening cross-sectional area larger than the opening cross-sectional area of ​​the opening. By pressurizing the bonding material between the semiconductor element and the substrate with a bonding material containing metal particles, the thickness of the bonding material protruding from the semiconductor element is made smaller than the thickness of the bonding material in the portion sandwiched between the semiconductor element and the substrate. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2011-216772 [Overview of the project] [Problems that the invention aims to solve]

[0010] While the technology described in Patent Document 1 above can suppress shrinkage cracks in the protruding bonding material, it requires additional jigs or a pressurizing process.

[0011] Furthermore, in the case of large-area bonding layers applied to large-area semiconductor elements mounted on high-heat-resistant power modules used in electric railways, electric vehicles, and industrial applications, the amount of paste used increases, often causing the paste that has squeezed out from the semiconductor element to creep up onto the side of the element. Therefore, a technology is needed to prevent the detachment of the creeping-up portion after sintering.

[0012] Therefore, the object of the present invention is to provide a highly reliable semiconductor device in which a semiconductor chip is mounted on a substrate by sintering bonding, which can prevent the detachment of the protruding portion due to the overflow of the sintering bonding material without the use of a specific jig. [Means for solving the problem]

[0013] To solve the above problems, the present invention comprises a substrate, a semiconductor chip, a sintered metal layer that joins the substrate and the semiconductor chip, a first resin layer formed in contact with the side surface of the sintered metal layer, a second resin layer that contacts and covers the first resin layer, and a gel-like sealing material that contacts the second resin layer and seals the substrate and the semiconductor chip. The first resin layer and the second resin layer are formed to cover the vicinity of the center of each side of the semiconductor chip, excluding the four corners, when the semiconductor chip is viewed from above. The present invention also comprises a substrate, a semiconductor chip, a sintered metal layer that joins the substrate and the semiconductor chip, a first resin layer formed in contact with the side surface of the sintered metal layer, a second resin layer that contacts and covers the first resin layer, and a gel-like sealing material that contacts the second resin layer and seals the substrate and the semiconductor chip, wherein the present invention further comprises a third resin layer formed to cover the entire upper surface of the semiconductor chip when the semiconductor chip is viewed from above. [Effects of the Invention]

[0014] According to the present invention, in a semiconductor device in which a semiconductor chip is mounted on a substrate by sintering bonding, it is possible to realize a highly reliable semiconductor device that can prevent the detachment of the protruding portion due to the overflow of the sintering bonding material without using a specific jig.

[0015] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0016] [Figure 1A] This is a diagram showing a cross-sectional structure of a semiconductor device according to Embodiment 1 of the present invention. [Figure 1B] It is an enlarged view of part A in FIG. 1A. [Figure 1C] It is a view taken in the direction of B-B' of FIG. 1B (plan view). [Figure 1D] It is a diagram showing a modified example of FIG. 1C. [Figure 2A] This is a diagram showing a cross-sectional structure of a semiconductor device according to Embodiment 2 of the present invention. [Figure 2B] It is an enlarged view of part C in FIG. 2A. [Figure 2C] It is a view taken in the direction of D-D' of FIG. 2B (plan view). [Figure 3A] This is a diagram showing a cross-sectional structure of a semiconductor device according to Embodiment 3 of the present invention. [Figure 3B] It is an enlarged view of part E in FIG. 3A. [Figure 3C] It is a view taken in the direction of F-F' of FIG. 3B (plan view).

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals, and detailed descriptions of overlapping parts are omitted. [[ID=--41]]

Embodiment

[0018] Referring to FIGS. 1A to 1D, a semiconductor device according to Embodiment 1 of the present invention will be described. FIG. 1A is a diagram showing a cross-sectional structure of a semiconductor device 100A of this embodiment. FIG. 1B is an enlarged view of part A in FIG. 1A. FIG. 1C is a view taken in the direction of B-B' of FIG. 1B (plan view). FIG. 1D is a diagram showing a modified example of FIG. 1C. <---

[0019] As shown in Figure 1A, the semiconductor device 100A of this embodiment mainly comprises an insulating circuit board 1, a power semiconductor chip such as an IGBT (hereinafter simply referred to as "semiconductor chip") 2, and a silicone gel 8, which is a gel-like sealing material that seals the insulating circuit board 1 and the semiconductor chip 2.

[0020] The insulating circuit board 1 and semiconductor chip 2 are housed in a resin case 7, and the resin case 7 is sealed by filling the inside with silicone gel 8 and sealing it with a resin case lid 9.

[0021] In this embodiment, semiconductor chip 2 is assumed to be a semiconductor chip using Si or SiC, but it is not limited to these.

[0022] The insulated circuit board 1 has an insulating substrate 1A, to which circuit electrodes 1B are joined to one side of the insulating substrate 1A and back surface electrodes 1C are joined to the other side via brazing material (not shown).

[0023] The back electrode 1C is bonded to the heat dissipation base 6 by a bonding material 3 such as solder or a sintered metal layer. The semiconductor chip 2 is bonded to the circuit electrode 1B by a sintered metal layer 10.

[0024] The heat dissipation base 6 and the insulating circuit board 1 need to efficiently dissipate the heat generated by the semiconductor chip 2. For this reason, aluminum (Al) or a composite material of aluminum and silicon carbide (Al-SiC) is used for the heat dissipation base 6. In addition, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc. are used for the insulating substrate 1A of the insulating circuit board 1, and aluminum (Al) copper (Cu), etc. are used for the circuit electrodes 1B.

[0025] The main terminal 5 is connected to the portion of the circuit electrode 1B where the semiconductor chip 2 is not mounted, and the semiconductor chip 2 and the main terminal 5 are electrically connected via the circuit electrode 1B or the circuit electrode 1B and the metal wire 4.

[0026] The main terminal 5 is a plate-shaped metal terminal for transmitting power to and from the semiconductor device 100A. The end not connected to the circuit electrode 1B is connected to an external device (not shown) on the outside of the resin case 7, and serves as the input / output terminal of the semiconductor device 100A. In addition, although not shown, the semiconductor device 100A also has control terminals and auxiliary terminals.

[0027] The semiconductor device 100A having the above-described configuration is manufactured by the following procedure.

[0028] The semiconductor chip 2 is, for example, a switching device such as an IGBT or a diode, and is bonded to the circuit electrode 1B of the insulating circuit board 1 via a sintered metal layer 10 such as sintered copper or sintered silver.

[0029] Then, a metal wire 4 is used to connect the electrode on the other side of the semiconductor chip 2 that is not joined to the circuit electrode 1B, and the circuit electrode 1B of the insulating circuit board 1 that is not joined to the semiconductor chip 2. Additionally, if necessary, the electrodes on the sides of multiple semiconductor chips 2 that are not joined to the respective circuit electrodes 1B are connected to each other with the metal wire 4.

[0030] Next, the insulating circuit board 1 on which the semiconductor chip 2 is mounted is joined to the heat dissipation base 6 via a bonding material 3 such as solder or sintered metal.

[0031] Subsequently, the resin case 7 is attached to the outer periphery of the heat dissipation base 6 using an adhesive or the like (not shown), and the main terminal 5 is joined to the surface of the circuit electrode 1B.

[0032] Finally, silicone gel 8 is injected into the resin case 7 and allowed to harden, and the resin case lid 9 is placed over the resin case 7 to complete the semiconductor device 100A.

[0033] In this embodiment, the semiconductor device 100A, as shown in Figure 1B, comprises a first resin layer 12 formed in contact with the side surface of the sintered metal layer 10, and a second resin layer 13 formed in contact with the first resin layer 12 and covering the first resin layer 12.

[0034] As described above, as the area of ​​the semiconductor chip 2 increases, the amount of paste used in the process of forming the sintered metal layer 10 that bonds the circuit electrodes 1B of the insulating circuit substrate 1 to the semiconductor chip 2 also increases. As a result, paste that spills out from between the semiconductor chip 2 and the circuit electrodes 1B tends to creep up onto the side of the chip, making it easier for sintered overflow portions 11 to form. In other words, the sintered metal layer 10 is formed between the circuit electrodes 1B of the insulating circuit substrate 1 and the semiconductor chip 2, and on the side of the semiconductor chip 2. If these sintered overflow portions 11 fall off, they may adhere to other wiring parts, etc., and cause a short circuit.

[0035] Therefore, in the semiconductor device 100A of this embodiment, a first resin layer 12 is formed on the side surface of the sintered metal layer 10 including the sintered overhang portion 11, and a second resin layer 13 is formed to cover the first resin layer 12, thereby preventing the sintered overhang portion 11 from falling off.

[0036] Examples of resin materials used for the first resin layer 12 include polyamide-imide resin and polyetheramide-imide resin.

[0037] Furthermore, examples of resin materials used for the second resin layer 13 include epoxy resin and the like.

[0038] The formation of the first resin layer 12 and the second resin layer 13 is performed after the semiconductor chip 2 is bonded to the circuit electrode 1B by the sintered metal layer 10.

[0039] A first resin layer 12 made of polyamide-imide resin or the like is formed on the side surface of the sintered metal layer 10 including the sintered overhang portion 11, and then a second resin layer 13 made of epoxy resin or the like is formed.

[0040] Subsequently, the insulating circuit board 1 is bonded to the heat dissipation base 6, the resin case 7 is bonded, then sealed with silicone gel 8, and the resin case lid 9 is bonded to the resin case 7.

[0041] Furthermore, as shown in Figure 1C, it is desirable that the first resin layer 12 and the second resin layer 13 be formed over the entire side surface of the semiconductor chip 2, i.e., the sintered metal layer 10, when the semiconductor chip 2 is viewed from above. By covering the entire side surface of the semiconductor chip 2 with the first resin layer 12 and the second resin layer 13, it is possible to reliably prevent the detachment of the sintered overhang portion 11 from the entire circumference of the semiconductor chip 2.

[0042] On the other hand, depending on the relationship between the area of ​​the semiconductor chip 2 and the amount of paste used to form the sintered metal layer 10, the sintered overflow portion 11 is not necessarily formed around the entire circumference of the semiconductor chip 2. For example, 3D measurement results after the formation of the sintered metal layer 10 may show that the sintered overflow portion 11 is concentrated near the center of each side (4 sides) of the semiconductor chip 2, excluding the four corners, when viewed from above.

[0043] In a semiconductor device 100A under these conditions, as shown in Figure 1D, the first resin layer 12 and the second resin layer 13 should be formed so as to cover the central area of ​​each side (4 sides) of the semiconductor chip 2, excluding the four corners.

[0044] As described above, the semiconductor device 100A of this embodiment is provided with a first resin layer 12 and a second resin layer 13 on the side surface of the sintered metal layer 10 including the sintered overhang portion 11.

[0045] This reduces the risk of short-circuit failures caused by sintered material creeping up the side of the semiconductor chip 2 detaching during post-sintering processes such as wire bonding or joining to an insulating circuit board, and adhering to unintended locations. [Examples]

[0046] Referring to Figures 2A to 2C, a semiconductor device according to Embodiment 2 of the present invention will be described. Figure 2A is a diagram showing the cross-sectional structure of the semiconductor device 100B of this embodiment. Figure 2B is an enlarged view of part C in Figure 2A. Figure 2C is a view (plan view) of the direction of the arrow D-D' in Figure 2B.

[0047] The semiconductor device 100B of this embodiment differs from Embodiment 1 (Figures 1A and 1B) in that, in addition to forming a first resin layer 12 and a second resin layer 13 on the side surface of the sintered metal layer 10 including the sintered overhang portion 11, a third resin layer 14 is formed on the upper surface of the semiconductor chip 2, excluding the outer periphery. The other configurations are the same as in Embodiment 1.

[0048] Furthermore, the first resin layer 12 and the third resin layer 14 are formed simultaneously in the same process, as will be described later. Therefore, the first resin layer 12 and the third resin layer 14 are made of the same resin material, such as polyamide-imide resin or polyetheramide-imide resin.

[0049] As can be seen from Figures 2B and 2C, the third resin layer 14 is formed to cover the upper surface of the semiconductor chip 2, excluding the outer periphery, when the semiconductor chip 2 is viewed from above.

[0050] This third resin layer 14 is formed to cover the connection between the semiconductor chip 2 and the metal wire 4, and reinforces the connection between the semiconductor chip 2 and the metal wire 4.

[0051] In the manufacturing process of the semiconductor device 100B of this embodiment, after connecting multiple semiconductor chips 2 and between semiconductor chips 2 and circuit electrodes 1B that are not joined to the semiconductor chips 2 with metal wires 4, polyamide-imide resin and polyetheramide-imide resin are applied to the upper surface of the semiconductor chips 2 excluding the outer periphery and to the side surface of the sintered metal layer 10 including the sintered overhang portion 11, respectively, thereby simultaneously forming the first resin layer 12 and the third resin layer 14.

[0052] Next, a second resin layer 13 made of epoxy resin or the like is formed.

[0053] Subsequently, the insulating circuit board 1 is bonded to the heat dissipation base 6, the resin case 7 is bonded, then sealed with silicone gel 8, and the resin case lid 9 is bonded to the resin case 7.

[0054] In this embodiment, the semiconductor device 100B can be manufactured without complicating the process by simultaneously forming the first resin layer 12 and the third resin layer 14. [Examples]

[0055] Referring to Figures 3A to 3C, a semiconductor device according to Embodiment 3 of the present invention will be described. Figure 3A is a diagram showing the cross-sectional structure of the semiconductor device 100C of this embodiment. Figure 3B is an enlarged view of part E in Figure 3A. Figure 3C is a view (plan view) of the arrows F-F' in Figure 3B.

[0056] The semiconductor device 100C of this embodiment differs from Embodiment 1 (Figures 1A and 1B) in that, in addition to forming a first resin layer 12 and a second resin layer 13 on the side surface of the sintered metal layer 10 including the sintered overhang portion 11, a third resin layer 14 is formed on the entire upper surface of the semiconductor chip 2. The other configurations are the same as in Embodiment 1.

[0057] Furthermore, the first resin layer 12 and the third resin layer 14 are formed simultaneously in the same process, as will be described later. Therefore, the first resin layer 12 and the third resin layer 14 are made of the same resin material, such as polyamide-imide resin or polyetheramide-imide resin.

[0058] This third resin layer 14 is formed to cover the connection between the semiconductor chip 2 and the metal wire 4, and reinforces the connection between the semiconductor chip 2 and the metal wire 4.

[0059] In the manufacturing process of the semiconductor device 100C of this embodiment, after connecting multiple semiconductor chips 2 and between semiconductor chips 2 and circuit electrodes 1B that are not joined to the semiconductor chips 2 with metal wires 4, polyamide-imide resin or polyetheramide-imide resin is applied to the entire upper surface of the semiconductor chip 2 and the side surface of the sintered metal layer 10 including the sintered overhang portion 11, thereby simultaneously forming the first resin layer 12 and the third resin layer 14 as a single unit.

[0060] Next, a second resin layer 13 made of epoxy resin or the like is formed.

[0061] Subsequently, the insulating circuit board 1 is bonded to the heat dissipation base 6, the resin case 7 is bonded, then sealed with silicone gel 8, and the resin case lid 9 is bonded to the resin case 7.

[0062] In this embodiment, by forming the first resin layer 12 and the third resin layer 14 simultaneously and integrally, a semiconductor device 100C can be manufactured that reliably covers the sintered overflow portion 11 without complicating the process.

[0063] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations. [Explanation of Symbols]

[0064] 1...Insulated circuit board, 1A...Insulated substrate, 1B...Circuit electrode, 1C...Back electrode, 2...Power semiconductor chip (semiconductor chip), 3...Bonding material, 4...Metal wire, 5...Main terminal, 6...Heat dissipation base, 7...Resin case, 8...Silicone gel, 9...Resin case lid, 10...Sintered metal layer, 11...Sintered overhang, 12...First resin layer, 13...Second resin layer, 14...Third resin layer, 100A, 100B, 100C...Semiconductor device.

Claims

1. circuit board and Semiconductor chips and A sintered metal layer that joins the substrate and the semiconductor chip, A first resin layer formed in contact with the side surface of the sintered metal layer, A second resin layer that contacts and covers the first resin layer, The device comprises a gel-like sealing material that contacts the second resin layer to seal the substrate and the semiconductor chip, The semiconductor device is characterized in that the first resin layer and the second resin layer are formed to cover the vicinity of the center of each side of the semiconductor chip, excluding the four corners, when the semiconductor chip is viewed in plan view.

2. A semiconductor device according to claim 1, The semiconductor device is characterized in that the first resin layer is a polyamide-imide resin or a polyetheramide-imide resin.

3. A semiconductor device according to claim 1, The semiconductor device is characterized in that the second resin layer is an epoxy resin.

4. A semiconductor device according to claim 1, The semiconductor device is characterized in that the sealing material is a silicone gel.

5. A semiconductor device according to claim 1, The semiconductor device is characterized in that the first resin layer and the second resin layer are formed on the entire side surface of the sintered metal layer when the semiconductor chip is viewed in plan view.

6. A semiconductor device according to claim 1, A semiconductor device characterized by comprising a third resin layer formed so as to cover the upper surface of the semiconductor chip, excluding the outer peripheral portion, when the semiconductor chip is viewed from above.

7. A semiconductor device according to claim 6, The semiconductor chip comprises a metal wire connected to the aforementioned semiconductor chip, The semiconductor device is characterized in that the third resin layer is formed to cover the connection portion between the semiconductor chip and the metal wire.

8. A substrate and Semiconductor chips and A sintered metal layer that joins the substrate and the semiconductor chip, A first resin layer formed in contact with the side surface of the sintered metal layer, A second resin layer that contacts and covers the first resin layer, The device comprises a gel-like sealing material that contacts the second resin layer to seal the substrate and the semiconductor chip, A semiconductor device characterized by comprising a third resin layer formed so as to cover the entire upper surface of the semiconductor chip when viewed from above.

9. A semiconductor device according to claim 1, The semiconductor device is characterized in that the sintered metal layer is formed between the substrate and the semiconductor chip, and on the side surface of the semiconductor chip.

Images