Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device capable of reducing input capacitance.SOLUTION: A silicon carbide semiconductor device comprises a silicon carbide substrate with a first principal surface. The silicon carbide substrate has a drift region having a first conductivity type, a body region having a second conductivity type, and a source region having the first conductivity type. A plurality of gate trenches 5 that are prescribed by a lateral face which reaches the drift region while penetrating through the source region and the body region and a bottom face continuous to the lateral face, and that extend along a virtual straight line L1 parallel to the first principal surface, are provided on the first principal surface. The lateral face extends along the virtual straight line and has a first lateral face and a second lateral face separated from each other. A gate electrode 82 has a first region 82A provided between an upper end part of the first lateral face and that of the second lateral face, a second region 82B provided between the gate trenches adjacent along the virtual straight line, and a third region 82C provided between the first region and the second region and electrically connected with the first region and the second region, in a plan view perpendicular to the first principal surface.SELECTED DRAWING: Figure 3

Description

Technical Field

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[0001] The present disclosure relates to a silicon carbide semiconductor device.

Background Art

[0002] As one of the silicon carbide semiconductor devices, a silicon carbide semiconductor device having a plurality of trenches for gate electrodes formed on the main surface has been disclosed (Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional silicon carbide semiconductor device, the input capacitance is large.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of reducing the input capacitance.

Means for Solving the Problems

[0006] The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, the first main surface is provided with a plurality of gate trenches defined by a side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface connected to the side surface, and extending along an imaginary straight line parallel to the first main surface, each of the gate trenches The device further comprises a gate insulating film in contact with the aforementioned side surfaces and bottom surfaces and the first main surface, and a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between itself and the silicon carbide substrate, wherein the side surfaces have a first side surface and a second side surface that extend along the virtual line and are separated from each other, and the gate electrode has, in a plan view perpendicular to the first main surface, a first region between the upper end of the first side surface and the upper end of the second side surface, a second region between adjacent gate trenches along the virtual line, and a third region between the first region and the second region that is electrically connected to the first region and the second region. Furthermore, the first, second, and third regions are made of the same material, and in plan view, the width of the second region is smaller than the width of the first region. . [Effects of the Invention]

[0007] According to this disclosure, the input capacity can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a perspective cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a perspective cross-sectional view (part 2) showing the configuration of a silicon carbide semiconductor device according to the first embodiment. [Figure 3] Figure 3 shows the configuration of the gate electrode and the first main surface in the silicon carbide semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 3) showing the configuration of the silicon carbide semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] Figure 11 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] Figure 12 is a cross-sectional view (part 6) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] Figure 13 is a cross-sectional view (part 7) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] Figure 14 is a cross-sectional view (part 8) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] Figure 15 is a cross-sectional view (part 9) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] Figure 16 is a cross-sectional view (part 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 17] Figure 17 is a cross-sectional view (part 11) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 18] Figure 18 is a cross-sectional view (part 12) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] Figure 19 is a cross-sectional view (part 13) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 20]FIG. 20 is a cross-sectional view (part 14) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 15) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 16) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 23] FIG. 23 is a cross-sectional view (part 17) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 24] FIG. 24 is a diagram showing the configuration of a gate electrode and a first main surface in a silicon carbide semiconductor device according to the second embodiment. [Figure 25] FIG. 25 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the second embodiment. [Figure 26] FIG. 26 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the third embodiment. [Figure 27] FIG. 27 is a cross-sectional view showing a method of manufacturing a silicon carbide semiconductor device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0009] Embodiments for carrying out the invention will be described below.

[0010] [Description of Embodiments of the Present Disclosure] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by () and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this disclosure a negative sign is placed before the number. Also, the following description uses the XYZ Cartesian coordinate system, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the semiconductor device. Furthermore, the XY plane view is also called the plan view, and from any point, the +Z direction may be called up, upper side, or up, and the -Z direction may be called down, lower side, or down.

[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, the first main surface is provided with a plurality of gate trenches defined by a side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface connected to the side surface, and extending along a virtual straight line parallel to the first main surface, the gate trenches The device further comprises a gate insulating film in contact with each of the aforementioned side surfaces and bottom surfaces and the first main surface, and a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between itself and the silicon carbide substrate, wherein the side surfaces have a first side surface and a second side surface that extend along the virtual straight line and are spaced apart from each other, and the gate electrode has, in a plan view perpendicular to the first main surface, a first region between the upper end of the first side surface and the upper end of the second side surface, a second region between adjacent gate trenches along the virtual straight line, and a third region between the first region and the second region that is electrically connected to the first region and the second region.

[0012] In a plan view, the first region of the gate electrode is located between the upper end of the first side surface and the upper end of the second side surface, resulting in a small parasitic capacitance between the gate electrode and the source region, thus reducing the input capacitance.

[0013] [2] In [1], the distance between the virtual plane including the bottom surface and the top surface of the first region may be smaller than the distance between the virtual plane and the first main surface. In this case, the parasitic capacitance between the gate electrode 82 and the source region 13 is easier to reduce.

[0014] [3] In [1], at least a portion of the second upper surface of the third region may be inclined from the first upper surface of the first region. In this case, the concentration of thermal stress acting from the gate electrode to the insulating film formed on the gate electrode can be alleviated.

[0015] [4] In [3], the maximum angle between the first main surface and the second upper surface in a cross-sectional view perpendicular to the first main surface and parallel to the virtual line may be smaller than the maximum angle between the first main surface and the side surface. In this case, thermal stress concentration is particularly easily mitigated.

[0016] [5] In any of [1] to [4], the width of the second region in the plan view may be less than or equal to the width of the first region. In this case, the parasitic capacitance between the second region and the source region can be further reduced, and the input capacitance can be further reduced.

[0017] [6] In any of [1] to [5], an insulating film is provided that covers the gate electrode, and the upper surface of the insulating film may be a curved surface with continuously changing curvature. This can alleviate the concentration of thermal stress acting on the insulating film from the source electrode formed on the insulating film.

[0018] [7] In any of [1] to [6], the first side and the second side may include a {0-33-8} plane. Including a {0-33-8} plane in the first and second side allows for good mobility on the side of the gate trench and reduces channel resistance.

[0019] [Embodiments of this Disclosure] (First Embodiment) A first embodiment will be described. The first embodiment relates to a so-called vertical MOS-type field-effect transistor (FET) using silicon carbide, and this MOS-type FET is an example of a silicon carbide semiconductor device. Figures 1 and 2 are perspective cross-sectional views showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Figure 2 shows a transparent view of a part of the internal structure of the silicon carbide semiconductor device. Figure 3 is a diagram showing the configuration of the gate electrode and the first main surface in the silicon carbide semiconductor device according to the first embodiment. Figures 4 to 6 are cross-sectional views showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Figure 4 corresponds to a cross-sectional view along the line IV-IV in Figure 3. Figure 5 corresponds to a cross-sectional view along the line VV in Figure 3. Figure 6 corresponds to a cross-sectional view along the line VI-VI in Figure 3.

[0020] As shown in Figures 1 to 6, the silicon carbide semiconductor device 100 according to the first embodiment mainly comprises a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85.

[0021] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type).

[0022] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.

[0023] The silicon carbide epitaxial layer 40 mainly comprises a drift region 11, a body region 12, a source region 13, an electric field relaxation region 16, a connection region 17, and a contact region 18.

[0024] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity.

[0025] The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. The body region 12 is located on top of the drift region 11.

[0026] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The source region 13 is located on top of the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0027] The contact region 18 contains p-type impurities such as aluminum and has a p-type conductivity. The contact region 18 penetrates the source region 13 and contacts the body region 12. The contact region 18 constitutes the first main surface 1.

[0028] Multiple gate trenches 5 are provided on the first main surface 1, defined by the side surface 3 and the bottom surface 4. The gate trenches 5 extend, for example, along the Y-axis. Multiple gate trenches 5 are arranged at regular intervals along the Y-axis. Also, multiple gate trenches 5 are arranged at regular intervals along the X-axis. Multiple gate trenches 5 may be arranged in an array. The side surface 3 penetrates the source region 13, the body region 12, and a part of the drift region 11, reaching the drift region 11. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the drift region 11. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y-axis, the angle θ1 of the side surface 3 with respect to a virtual plane P1 including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. In this disclosure, the positional relationship of each part may be explained using a virtual straight line L1 parallel to the Y-axis.

[0029] Side surface 3 has a first side surface 3A and a second side surface 3B extending along the Y-axis. The first side surface 3A and the second side surface 3B are parallel to the Y-axis. The first side surface 3A and the second side surface 3B are separated from each other along the X-axis. The first side surface 3A and the second side surface 3B preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The second side surface 3B is in the -X direction with respect to the first side surface 3A.

[0030] The field relaxation region 16 contains p-type impurities such as aluminum and has a p-type conductivity. The field relaxation region 16 is located between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the field relaxation region 16 is, for example, located between the bottom surface 4 of the gate trench 5 and the second main surface 2. A part of the upper end surface of the field relaxation region 16 faces a part of the lower end surface of the body region 12. The field relaxation region 16 extends along the Y-axis, similar to the gate trench 5. In a plan view perpendicular to the first main surface 1, the field relaxation region 16 overlaps with the gate trench 5. In a plan view perpendicular to the first main surface 1, the field relaxation region 16 may overlap with multiple gate trenches 5 along the Y-axis. Alternatively, multiple field relaxation regions 16 are arranged at regular intervals along the X-axis. Multiple field relaxation regions 16 may be arranged in a stripe pattern.

[0031] The connection region 17 contains p-type impurities such as aluminum and has a p-type conductivity. The connection region 17 electrically connects the contact region 18 and the field relaxation region 16. The connection region 17 is located between adjacent gate trenches 5 along the Y-axis in a plan view perpendicular to the first main surface 1. The connection region 17 is in contact with the field relaxation region 16. The connection region 17 is in contact with at least one of the body region 12 or the contact region 18. The connection region 17 may be in contact with both the body region 12 and the contact region 18. The connection region 17 is located between the field relaxation region 16 and the contact region 18.

[0032] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12 and the drift region 11 at the side surface 3. The gate insulating film 81 may also be in contact with the source region 13 at the first main surface 1.

[0033] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (polySi) containing conductive impurities. The gate electrode 82 is located inside the gate trench 5.

[0034] The gate electrode 82 extends along the Y-axis, similar to the gate trenches 5. In a plan view perpendicular to the first main surface 1, the gate electrode 82 overlaps with the multiple gate trenches 5. In a plan view perpendicular to the first main surface 1, the gate electrode 82 has a first region 82A, a second region 82B, and a third region 82C. In a plan view perpendicular to the first main surface 1, the first region 82A overlaps with the gate trenches 5 and lies between the upper end 6A of the first side surface 3A and the upper end 6B of the second side surface 3B. The second region 82B lies between adjacent gate trenches 5 along the Y-axis in a plan view perpendicular to the first main surface 1. The second region 82B is on the first main surface 1. The third region 82C lies between the first region 82A and the second region 82B in a plan view perpendicular to the first main surface 1 and is electrically connected to the first region 82A and the second region 82B. The second region 82B is also electrically connected to the first region 82A.

[0035] Furthermore, the distance D1 between the virtual plane P1 including the base 4 and the top surface 31 of the first region 82A is smaller than the distance D2 between the virtual plane P1 and the first main surface 1. The width W2 of the second region 82B may be larger than the width W1 of the first region 82A. The top surface 31 of the first region 82A is an example of a first top surface.

[0036] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface with continuously changing curvature. The upper surface of the interlayer insulating film 83 is a curved surface that is convex in the +Z direction above the gate trench 5.

[0037] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. The source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 90.

[0038] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with both the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0039] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 is ohmic-bonded to the source region 13 and the contact region 18. The source wiring 62 covers the upper and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61, respectively. The source wiring 62 is made of a material containing, for example, aluminum.

[0040] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material including, for example, polyimide. An opening 86 is formed in the passivation film 85, through which a portion of the source wiring 62 is exposed.

[0041] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, nickel silicide. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is ohmic bonded to the silicon carbide single crystal substrate 50.

[0042] A buffer layer containing n-type impurities such as nitrogen and having an n-type conductivity may be provided between the silicon carbide single crystal substrate 50 and the drift region 11.

[0043] Next, a method for manufacturing the silicon carbide semiconductor device 100 according to the first embodiment will be described. Figures 7 to 23 are cross-sectional views showing the method for manufacturing the silicon carbide semiconductor device 100 according to the first embodiment. Figures 7 to 15 show the changes in the cross-section shown in Figure 4. Figures 16 to 23 show the changes in the cross-section shown in Figure 6.

[0044] First, a silicon carbide single crystal substrate 50 is prepared as shown in Figure 7. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen. In this way, a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 is obtained.

[0045] Next, as shown in Figures 8 and 16, ion implantation is performed into the silicon carbide epitaxial layer 40 to form the body region 12, source region 13, field relaxation region 16, connection region 17, and contact region 18. The remainder of the silicon carbide epitaxial layer 40 becomes the drift region 11. In the ion implantation to form the body region 12, field relaxation region 16, connection region 17, or contact region 18, p-type impurities such as aluminum are implanted. In the ion implantation to form the source region 13, n-type impurities such as phosphorus are implanted.

[0046] Next, as shown in Figures 9 and 17, multiple gate trenches 5 are formed in the source region 13, the body region 12, and the drift region 11. The gate trenches 5 can be formed as follows.

[0047] First, a mask (not shown) having an opening is formed over the region where the gate trench 5 is to be formed. Next, using the mask, a portion of the source region 13, a portion of the body region 12, and a portion of the drift region 11 are removed by etching. The etching is, for example, reactive ion etching (RIE). By etching, a recess is formed in the region where the gate trench 5 is to be formed, having a side portion that is substantially perpendicular to the first main surface 1, and a bottom portion that is continuously provided with the side portion and substantially parallel to the first main surface 1.

[0048] Next, thermal etching is performed in the recesses. Thermal etching can be performed by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with a mask formed on the first main surface 1. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere may include, for example, chlorine (Cl2), boron trichloride (BCl3), sulfur hexafluoride (SF6), or carbon tetrafluoride (CF4). For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen (O2) gas as the reaction gas, with a heat treatment temperature of 800°C to 900°C. The reaction gas may also include a carrier gas in addition to the chlorine gas and oxygen gas mentioned above. Examples of carrier gases that can be used include nitrogen (N2) gas, argon (Ar) gas, or helium (He) gas.

[0049] The above thermal etching process forms a gate trench 5 on the first main surface 1. The gate trench 5 has a bottom surface 4 consisting of a drift region 11 and a side surface 3 that penetrates the source region 13 and the body region 12 and connects to the bottom surface 4. After thermal etching, the mask is removed from the first main surface 1.

[0050] Next, as shown in Figures 10 and 18, a gate insulating film 81 is formed. For example, by thermal oxidation of the silicon carbide substrate 10, a gate insulating film 81 is formed that is in contact with the source region 13, the body region 12, the drift region 11, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C to 1400°C. This forms a gate insulating film 81 that is in contact with the first main surface 1, the side surface 3, and the bottom surface 4. When the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the thermally oxidized gate insulating film 81 and the silicon carbide substrate 10.

[0051] Next, the silicon carbide substrate 10 may be subjected to heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In NO annealing, the silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100°C to 1400°C. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0052] Next, as shown in Figures 11 and 19, a polysilicon film 91 for the gate electrode containing conductive impurities is formed. The polysilicon film 91 is formed on the gate insulating film 81. The polysilicon film 91 is formed, for example, by a low-pressure chemical vapor deposition (LP-CVD) method.

[0053] Next, as shown in Figures 12 and 20, a mask 92 is formed over the area of ​​the polysilicon film 91 where the second region 82B is to be formed and a portion of the area where the third region 82C is to be formed. The material of the mask 92 is, for example, a photoresist. Next, a RIE of the polysilicon film 91 is performed using the mask 92 to form a gate electrode 82 having a first region 82A, a second region 82B, and a third region 82C from the polysilicon film 91.

[0054] Next, as shown in Figures 13 and 21, the mask 92 is removed and the interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by the CVD method. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. A portion of the interlayer insulating film 83 may be formed inside the gate trench 5. Next, contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 by etching the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0055] Next, as shown in Figures 14 and 22, the sharp edges of the surface of the interlayer insulating film 83 are softened by heat treatment (reflow), making the upper surface of the interlayer insulating film 83 a curved surface with continuously changing curvature. If the material of the interlayer insulating film 83 is BPSG (boronic phosphoric silicate glass), the heat treatment temperature is, for example, 800°C or higher. Next, a barrier metal film 84 is formed to cover the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is formed, for example, by sputtering and RIE. The barrier metal film 84 is composed of, for example, a material containing titanium nitride.

[0056] Next, a metal film (not shown) for the contact electrode 61, which is in contact with the source region 13 and the contact region 18, is formed on the first main surface 1. The metal film for the contact electrode 61 is formed, for example, by sputtering. The metal film for the contact electrode 61 is made of a material containing nickel, for example. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900°C to 1100°C for about 5 minutes. As a result, at least a portion of the metal film for the contact electrode 61 reacts with the silicon contained in the silicon carbide substrate 10 and becomes silicided. As a result, a contact electrode 61 that ohmic-bonds with the source region 13 and the contact region 18 is formed. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon.

[0057] Next, as shown in Figures 15 and 23, the source wiring 62 is formed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed, for example, by sputtering. The source wiring 62 is made of a material containing, for example, aluminum or copper. The source wiring 62 may be made of a material containing aluminum and copper. For example, the source wiring 62 is an aluminum film or an aluminum alloy film. In this way, a source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0058] Next, a passivation film 85 is formed to cover the source wiring 62 (see Figure 1). The passivation film 85 is made of a material including, for example, polyimide. The passivation film 85 is formed, for example, by a coating method. The passivation film 85 may also be formed by a plasma CVD method. Next, an opening 86 is formed in the passivation film 85, through which a portion of the source wiring 62 is exposed. If the polyimide is photosensitive, the opening 86 can be formed by exposure and development. In addition, a drain electrode 70 is formed on the second main surface 2, which is ohmic bonded to the silicon carbide single crystal substrate 50.

[0059] In this way, the silicon carbide semiconductor device 100 can be manufactured.

[0060] In the silicon carbide semiconductor device 100 according to the first embodiment, in a plan view, the first region 82A of the gate electrode 82 is located between the upper end 6A of the first side surface 3A and the upper end 6B of the second side surface 3B. Therefore, the parasitic capacitance between the gate electrode 82 and the source region 13 is small, and the input capacitance can be reduced. In addition, the first regions 82A in adjacent gate trenches 5 along the Y-axis are electrically connected to each other via the second region 82B and the third region 82C. Therefore, the potential of the first regions 82A in adjacent gate trenches 5 along the Y-axis can be controlled in common.

[0061] The distance D1 between the virtual plane P1 and the upper surface 31 of the first region 82A is smaller than the distance D2 between the virtual plane P1 and the first main surface 1, which makes it easier to reduce the parasitic capacitance between the gate electrode 82 and the source region 13.

[0062] Because the upper surface of the interlayer insulating film 83 is a curved surface with continuously changing curvature, the concentration of thermal stress acting from the source electrode 60 to the interlayer insulating film 83 can be mitigated. Therefore, for example, the thermal cycle resistance during operation can be improved.

[0063] (Second Embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the form of the second region 82B of the gate electrode 82. Figure 24 is a diagram showing the configuration of the gate electrode and the first main surface in the silicon carbide semiconductor device according to the second embodiment. Figure 25 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second embodiment. Figure 25 corresponds to a cross-sectional view along the line XXV-XXV in Figure 24.

[0064] As shown in Figures 24 and 25, in the silicon carbide semiconductor device 200 according to the second embodiment, in a plan view perpendicular to the first main surface 1, the width W2 of the second region 82B is less than or equal to the width W1 of the first region 82A.

[0065] Other configurations of the second embodiment are the same as those of the first embodiment.

[0066] When manufacturing the silicon carbide semiconductor device 200 according to the second embodiment, for example, the planar shape of the mask 92 can be changed from the shape in the first embodiment.

[0067] The same effects as the first embodiment can be obtained in the second embodiment. Furthermore, in the second embodiment, since the width W2 of the second region 82B is less than or equal to the width W1 of the first region 82A, the parasitic capacitance between the second region 82B and the source region 13 and contact region 18 can be reduced. Therefore, the input capacitance can be further reduced.

[0068] Furthermore, in the first embodiment, the shortest distance between adjacent gate electrodes 82 along the X-axis depends on the distance between adjacent second regions 82B, whereas in the second embodiment, it depends on the distance between adjacent first regions 82A. Therefore, according to the second embodiment, it is possible to increase the number density of gate electrodes 82 and allow a larger current to flow.

[0069] Furthermore, if the distance between adjacent first regions 82A is the same between the first and second embodiments, in the second embodiment, it is easier to suppress the preferential growth of the interlayer insulating film 83 around the second region 82B, which is convex relative to the first region 82A, during the formation of the interlayer insulating film 83. This makes it easier to form contact holes 90 more stably. For example, it is possible to reduce residual film and etching deficiencies when forming contact holes 90. Also, since it is easier to form wider contact holes 90 than in the first embodiment, the flatness of the surface of the source wiring 62 can be improved.

[0070] (Third embodiment) A third embodiment will now be described. The third embodiment differs from the first embodiment mainly in the form of the first region 82A of the gate electrode 82. Figure 26 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the third embodiment. Figure 26, like Figure 6, corresponds to a cross-sectional view along the line VI-VI in Figure 3.

[0071] As shown in Figure 26, in the silicon carbide semiconductor device 300 according to the third embodiment, the upper surface 33 of the third region 82C is connected to the upper surface 31 of the first region 82A and the upper surface 32 of the second region 82B. The upper surface 33 may include multiple planes, or it may include a curved surface. The side surface 3 may include a curved surface, or it may include a curved surface. Also, at least a part of the upper surface 33 is inclined from the upper surface 31. In a cross-sectional view perpendicular to the X-axis, i.e., a cross-sectional view perpendicular to the first main surface 1 and parallel to the Y-axis, the maximum value of the angle θ2 between the first main surface 1 and the upper surface 33 is smaller than the maximum value of the angle θ3 between the first main surface 1 and the side surface 3. The upper surfaces 31 and 32 may be parallel to the bottom surface 4. The upper surface 33 of the third region 82C is an example of a second upper surface.

[0072] The other configurations of the third embodiment are the same as those of the first embodiment.

[0073] Next, a method for manufacturing the silicon carbide semiconductor device 300 according to the third embodiment will be described. Figure 27 is a cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device 300 according to the third embodiment.

[0074] When manufacturing the silicon carbide semiconductor device 300 according to the third embodiment, first, the same process as in the first embodiment is carried out up to the formation of the polysilicon film 91 (see Figures 11 and 19). Next, as shown in Figure 27, the same as in the first embodiment, a mask 92 is formed on the area where the second region 82B of the polysilicon film 91 is to be formed and a part of the area where the third region 82C is to be formed. Next, the polysilicon film 91 is subjected to chemical dry etching using the mask 92 to form a gate electrode 82 having a first region 82A, a second region 82B, and a third region 82C from the polysilicon film 91. Since the anisotropy of chemical dry etching is lower than that of RIE, at least a part of the upper surface 33 of the third region 82C is inclined from the upper surface of the first region 82A.

[0075] Subsequently, the mask 92 is removed, and the same processing as in the first embodiment is carried out after the formation of the interlayer insulating film 83.

[0076] In this way, the silicon carbide semiconductor device 300 can be manufactured.

[0077] The same effects as the first embodiment can be obtained with the third embodiment. Furthermore, since at least a portion of the upper surface 33 of the third region 82C is inclined from the upper surface 31 of the first region 82A, the concentration of thermal stress acting from the gate electrode 82 to the interlayer insulating film 83 can be mitigated. In particular, the maximum value of angle θ2 in a cross-sectional view perpendicular to the X axis is smaller than the maximum value of angle θ3, which makes it easier to mitigate the concentration of thermal stress. For this reason, for example, damage to the interlayer insulating film 83 during the manufacturing process can be suppressed, and thermal cycle resistance during operation can be improved.

[0078] In the second embodiment, as in the third embodiment, the maximum value of angle θ2 in a cross-sectional view perpendicular to the X-axis may be smaller than the maximum value of angle θ3.

[0079] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of symbols]

[0080] 1. First main surface 2. Second main surface 3 Sides 3A 1st side 3B 2nd side 4. Bottom 5 Gate Trench 6A, 6B Upper end 10 Silicon carbide substrate 11. Drift Region 12 Body Region 13 Source Area 16. Electric field relaxation region 17 Connection Area 18 Contact Area 31 Top surface (first top surface) 32 Top side 33 Top surface (second top surface) 40 Silicon Carbide Epitaxial Layer 50 Silicon carbide single crystal substrate 60 source electrodes 61 Contact electrodes 62 Source Wiring 70 Drain electrode 81 Gate Insulator 82 Grid gate 82A 1st area 82B 2nd area 82C 3rd area 83 Interlayer insulating film 84 Barrier metal film 85 Passivation membrane 86 Opening 90 Contact Holes 91 Polysilicon film 92 masks 100, 200, 300 silicon carbide semiconductor devices D1, D2 distance L1 Virtual Line P1 Virtual Plane W1, W2 width θ1, θ2, θ3 angles

Claims

1. A silicon carbide substrate having a first main surface is provided, The silicon carbide substrate is A drift region having a first conductivity type, A body region provided on the drift region and having a second conductivity type different from the first conductivity type, A source region having the first conductivity type is provided on the body region so as to be separated from the drift region, It has, The first main surface is provided with a plurality of gate trenches that extend along a virtual straight line parallel to the first main surface, defined by a side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface that is connected to the side surface. A gate insulating film is provided that is in contact with each of the side surfaces and bottom surfaces of the gate trench and the first main surface, A gate electrode is provided on the gate insulating film so as to sandwich the gate insulating film between itself and the silicon carbide substrate, It further possesses, The aforementioned side surface has a first side surface and a second side surface that extend along the virtual straight line and are separated from each other. The gate electrode, in a plan view perpendicular to the first main surface, A first region located between the upper end of the first side surface and the upper end of the second side surface, A second region located between adjacent gate trenches along the aforementioned virtual line, A third region located between the first region and the second region and electrically connected to the first region and the second region, It has, The first region, the second region, and the third region are composed of a common material. A silicon carbide semiconductor device wherein, in the plan view, the width of the second region is smaller than the width of the first region.

2. The silicon carbide semiconductor device according to claim 1, wherein the distance between the virtual plane including the bottom surface and the first upper surface of the first region is smaller than the distance between the virtual plane and the first main surface.

3. The silicon carbide semiconductor device according to claim 1, wherein at least a portion of the second upper surface of the third region is inclined from the first upper surface of the first region.

4. In a cross-sectional view perpendicular to the first main surface and parallel to the virtual line, The silicon carbide semiconductor device according to claim 3, wherein the maximum value of the angle between the first main surface and the second upper surface is smaller than the maximum value of the angle between the first main surface and the side surface.

5. The gate electrode has an insulating film covering it, The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the upper surface of the insulating film is a curved surface with continuously changing curvature.

6. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the first side surface and the second side surface include a {0-33-8} plane.

Images