Power semiconductor modules and power converters

Abstract

To provide a power semiconductor module which can suppress cracks of an insulation substrate.SOLUTION: A resin sealing type power semiconductor module 200 having no support member of an insulation substrate has an insulation substrate 50, a conductor layer pattern 11, a conductor layer pattern 12 and a conductor layer pattern 13, first semiconductor chip groups 31 and 32 bonded onto the conductor layer pattern 11, second semiconductor chip groups 33 and 34 bonded onto the conductor layer pattern 12, a lead frame 21 for electrically connecting an opposite side of the conductor layer pattern 11 and the conductor layer pattern 12, and a lead frame 22 for electrically connecting the opposite side of the conductor layer pattern 12 and the conductor layer pattern 13. The respective lead frames are arranged across slits 71 and 72 between the conductor layer pattern 11 and the conductor layer pattern 12, and the lead frames are arranged in single layers in a direction vertical to the arrangement surfaces of the respective conductor layer patterns of the insulation substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the structure of a power semiconductor module, and particularly relates to a technology effective for application to a resin-sealed power semiconductor module manufactured without including a base plate or a radiator serving as a support member of an insulating substrate.

Background Art

[0002] Power semiconductor modules using switching elements such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), and semiconductor elements such as freewheel diodes are used for power control and motor control of industrial equipment, electric railway vehicles, automobiles, home appliances, etc. In recent years, particularly due to the spread of electric vehicles, the need for power semiconductor modules for in-vehicle inverters has been increasing. In order to provide a low price while increasing the power utilization efficiency of an in-vehicle inverter, the power semiconductor module is required to achieve low cost while realizing low loss.

[0003] To achieve low-loss characteristics, there are multiple options such as applying new materials such as GaN (gallium nitride) and SiC (silicon carbide) to power semiconductor chips, and applying a new type of Si (silicon)-made IGBT having reverse conductivity. On the other hand, there are also various technical directions for reducing the cost of power semiconductor modules. Cost reduction is also possible by changing manufacturing processes such as replacing the members constituting the module with inexpensive ones, or changing the method of molding the outer shape of the module from the conventional case method to a mold resin sealing method with a low manufacturing cost. However, in reality, bottlenecks in manufacturing occur.

[0004] Insulating substrates, one of the module components, primarily use ceramic substrates to ensure their insulating properties. Silicon nitride (SiN) substrates, with their high toughness, and aluminum nitride (AlN) substrates, with their high thermal conductivity, have excellent characteristics but are expensive, creating a dilemma. In particular, for power semiconductor modules used in automotive inverters, which are produced in large quantities, the use of inexpensive alumina (Al2O3) substrates is desirable, but they have the problem of low bending strength.

[0005] Furthermore, in order to further reduce costs by introducing resin encapsulation using transfer molding or potting methods in the process of molding the outer shape of the module, a module structure that can withstand the shrinkage stress generated during the resin cooling and curing process is necessary. In other words, even when using inexpensive ceramic substrates with low bending strength, technology to suppress defects such as cracks in the ceramic substrate caused by stress generated during the resin encapsulation process is crucial.

[0006] Even with resin-encapsulated power semiconductor modules, if the module is equipped with a mechanically rigid base plate and support members such as heat sinks, problems such as cracks in the ceramic substrate due to stress, as described above, do not become apparent. However, in automotive inverters that combine multiple small power semiconductor modules to satisfy the required rated current, a simple configuration of mounting semiconductor switching elements on an insulating substrate and encapsulating them in resin is frequently used. Therefore, in the manufacturing process of power semiconductor modules, if a base plate or heat sink that serves as a support member for the insulating substrate is not provided, it is necessary to overcome problems caused by stress, such as cracks in the ceramic substrate, and improve the manufacturing yield.

[0007] As background technology for this field, for example, there is technology such as that described in Patent Document 1. Patent Document 1 shows a configuration that can reduce surge voltage compared to conventional methods. A ceramic substrate is used, and multiple electrode bars are used to connect circuit patterns on the substrate. By arranging the electrode bars in a laminate structure, the inductance is reduced and the surge voltage is suppressed. There is no description of the sealing resin, but Figure 1 of Patent Document 1 discloses that a laminate electrode bar structure capable of improving rigidity is arranged in the center of the plane of the ceramic substrate.

[0008] Furthermore, Patent Document 2 describes forming the terminal case 88 that determines the outer shape of the semiconductor module 100 with a thermosetting resin, and discloses a structure in which a bridging member spans the slits created between the wiring patterns on the substrate in order to improve the thermal equilibrium of multiple semiconductor chips arranged on a ceramic substrate. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2004-214452 [Patent Document 2] International Publication No. 2020 / 071102 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] Referring to Figure 1 of the above-mentioned Patent Document 1, the chip arrangement of the IGBTs and diodes constituting the half-bridge circuit and the shapes of the electrode bars 32, 33, and 34 that electrically connect them are shown. It is stated that the multiple electrode bars are arranged close to each other with an insulator in between.

[0011] Furthermore, referring to Figure 2 of the above-mentioned Patent Document 2, a structure is described in which wiring patterns on a ceramic substrate are connected by a lead frame consisting of a chip joint portion 180, a wiring joint portion 182, leg portions 185 and 186, and a bridging portion 184.

[0012] However, the above-mentioned conventional technologies have several drawbacks in terms of preventing cracks in ceramic substrates.

[0013] In the configuration described in Patent Document 1, assuming that the module's outer shape is molded by resin encapsulation, the structure involves overlapping electrode bars on the plane of the ceramic substrate. Therefore, it is easy to surmise that the resin thickness must be increased to encapsulate the entire module. This leads to increased shrinkage stress and higher costs due to the increased total resin volume. Consequently, as mentioned above, its application to automotive inverters, which aim for small and inexpensive power semiconductor modules, is difficult.

[0014] Furthermore, Patent Document 2 shows that a lead frame including a cross-linked portion spans the slits that occur between wiring patterns 164-1 to 164-3, which can be said to be a structure that reinforces the rigidity of the ceramic substrate. However, the arrangement of the lead frame is limited, and for example, the lead frame is not placed over the longest slit in the center of the ceramic substrate. In order to reinforce the rigidity of the ceramic substrate, it is necessary to identify the areas where the greatest stress occurs during cooling and curing after resin encapsulation and where cracks are likely to occur, and then take countermeasures. Therefore, it is considered difficult to prevent cracks from occurring in the ceramic substrate with the configuration of Patent Document 2, which does not address the long slit in the center of the substrate.

[0015] Therefore, the object of the present invention is to provide a power semiconductor module and a power conversion device using the same, which can effectively suppress cracks in the insulating substrate that tend to occur during the cooling and curing of the sealing resin, in a resin-encapsulated power semiconductor module that does not use a base plate or heat sink that serve as support members for the insulating substrate. [Means for solving the problem]

[0016] To solve the above problems, the present invention provides a resin-encapsulated power semiconductor module without a support member for an insulating substrate, comprising: an insulating substrate; a first conductor layer pattern disposed on the insulating substrate; a second conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern; a third conductor layer pattern disposed on the insulating substrate and electrically insulated from the first and second conductor layer patterns; a first group of semiconductor chips having one or more semiconductor chips bonded to the first conductor layer pattern; and a second group of semiconductor chips having one or more semiconductor chips bonded to the second conductor layer pattern. The device comprises a first lead frame that electrically connects the opposite side of the bonding surface between the first semiconductor chip group and the first conductor layer pattern to the second conductor layer pattern, and a second lead frame that electrically connects the opposite side of the bonding surface between the second semiconductor chip group and the second conductor layer pattern to the third conductor layer pattern, wherein each of the first lead frame and the second lead frame is arranged across the slit between the first conductor layer pattern and the second conductor layer pattern, and the lead frames are arranged in a single layer in a direction perpendicular to the arrangement surface of each conductor layer pattern on the insulating substrate. [Effects of the Invention]

[0017] According to the present invention, in a resin-encapsulated power semiconductor module that does not use a base plate or heat sink as a support member for the insulating substrate, it is possible to realize a power semiconductor module that can effectively suppress cracks in the insulating substrate that tend to occur during the cooling and curing of the encapsulating resin, and a power conversion device using the same.

[0018] This allows the use of alumina (Al2O3) substrates as insulating substrates for power semiconductor modules, thereby improving the manufacturing yield and reducing the cost of power semiconductor modules, as well as the cost of power conversion devices.

[0019] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0020] [Figure 1] It is a plan view of a power semiconductor module according to Embodiment 1 of the present invention. [Figure 2] It is a cross-sectional view taken along the line A-A' of FIG. 1. [Figure 3] It is a cross-sectional view taken along the line B-B' of FIG. 1. [Figure 4] It is a plan view of a conventional power semiconductor module. [Figure 5] It is a cross-sectional view taken along the line C-C' of FIG. 4. [Figure 6] It is a diagram showing an example of an analysis result of stress in a ceramic substrate. [Figure 7A] It is a diagram showing an overview of an analysis model of FIG. 6. (Conventional example) [Figure 7B] It is a diagram showing an overview of an analysis model of FIG. 6. (The present invention) [Figure 8] It is a plan view of a power semiconductor module according to Embodiment 2 of the present invention. [Figure 9] It is a diagram conceptually showing mutual inductance in the D-D' cross section of FIG. 8. [Figure 10] It is an external view of a power semiconductor module according to Embodiment 1 and Embodiment 2 of the present invention. [Figure 11] It is a block diagram showing a circuit configuration of a power conversion device according to Embodiment 3 of the present invention. [Figure 12] It is a diagram conceptually showing mutual inductance in the A-A' cross section of FIG. 1. [Figure 13] It is an equivalent circuit diagram showing a main circuit inductance path in FIG. 1. [Figure 14] It is an equivalent circuit diagram showing a main circuit inductance path in FIG. 8.

Mode for Carrying Out the Invention

[0021] [[ID=5Embodiments of the present invention will be described below with reference to the drawings. In each drawing, components with the same configuration or similar functions are denoted by the same reference numerals, and detailed descriptions of overlapping parts are omitted. [Examples]

[0022] Referring to Figures 1 to 7B and Figure 10, a power semiconductor module of Embodiment 1 of the present invention will be described. In this embodiment, a module structure is shown that suppresses the occurrence of cracks in the ceramic insulating substrate when the sealing resin cools and hardens, and the effect of reducing stress applied to the ceramic insulating substrate is also described.

[0023] ≪Schematic configuration≫ Figure 1 shows the schematic configuration of the power semiconductor module 200 of this embodiment. It should be noted that, for convenience, the arrangement of components in the lower layer, which are normally invisible due to the sealing resin 60, is shown in the plan view of Figure 1 under the assumption of transparency. Figure 1 shows a plan view of the power semiconductor module 200 as seen from above, while Figures 2 and 3 show cross-sectional structural diagrams along the cross-sectional lines A-A' and B-B' indicated in the plan view, respectively.

[0024] ≪Plane configuration≫ The power semiconductor module 200 of this embodiment, shown in Figure 1, has a half-bridge circuit configured on a single insulating substrate (ceramic substrate) 50. The area of ​​the resin encapsulation 60, indicated by the dotted line, shows the outer shape of the power semiconductor module.

[0025] As shown in Figure 1, the power semiconductor module 200 of this embodiment is a so-called 2-in-1 type power semiconductor module that has two sets of IGBT chips and diode chips (reference numerals 31 and 32, 33 and 34), and has three external main terminals 1, 2, and 3.

[0026] External main terminal 1 functions as a high-voltage power supply terminal, and external main terminal 3 functions as a low-voltage power supply terminal, supplying DC voltage to the half-bridge circuit on the insulating substrate 50. External main terminal 2 functions as an AC voltage terminal, supplying load current to the outside.

[0027] The three external main terminals 1, 2, and 3 are each connected to three conductor layer patterns 11, 12, and 13 arranged on an insulating substrate 50 and electrically insulated from one another.

[0028] The conductor layer pattern 11 is arranged in one region of the insulating substrate 50 (the right-hand region of the insulating substrate 50 in Figure 1) so as to extend along one side of the insulating substrate 50 in the Y direction. The conductor layer pattern 12 is arranged in the other region of the insulating substrate 50 (the left-hand region of the insulating substrate 50 in Figure 1) so as to extend along the other side of the insulating substrate 50 in the Y direction. A slit 71 is formed between the conductor layer pattern 11 and the conductor layer pattern 12, separating them and providing electrical insulation.

[0029] The conductor layer pattern 13 extends along one side of the insulating substrate 50 in the X direction, with a portion of it located in one region of the insulating substrate 50 (the right-hand region in Figure 1) and another portion located in the other region (the left-hand region in Figure 1). A slit 72 is formed between the conductor layer patterns 11 and 12 and the conductor layer pattern 13, separating the conductor layer patterns 11 and 12 from the conductor layer pattern 13 and providing electrical insulation.

[0030] The external main terminal 1 is electrically connected to a conductor layer pattern 11 bonded to an insulating substrate 50. In Figure 1, an upper arm circuit is constructed by connecting one IGBT chip 31 as a semiconductor switching element and one diode chip 32 as a semiconductor diode element in antiparallel to the conductor layer pattern 11. The collector electrode of the IGBT chip 31 and the cathode electrode of the diode chip 32 are electrically and mechanically connected to the conductor layer pattern 11 via solder and sintering material. Signal terminals 5 and 6 are the gate control terminal and emitter sense terminal, respectively, which control the switching of the IGBT chip 31. Each terminal connected to the conductor layer patterns 15 and 16 is connected to the gate electrode 303 and emitter electrode 302 on the IGBT chip 31 via bonding wires 25 and 26.

[0031] The emitter electrode 302 of the IGBT chip 31 and the anode electrode 304 of the diode chip 32 are both electrically and mechanically connected via the lead frame 21 to the conductor layer pattern 12 to which the potential of the AC voltage terminal is applied. The connection method is the same as that for the collector electrode of the IGBT chip 31 and the cathode electrode of the diode chip 32, using solder and sintered material.

[0032] The conductor layer pattern 12 is connected to the collector electrode of the IGBT chip 33 and the cathode electrode of the diode chip 34, which constitute the lower arm circuit, as well as the external main terminal 2, which is an AC voltage terminal. The lead frame 22 connects the emitter electrode 302 of the IGBT chip 33 and the anode electrode 304 of the diode chip 34, and is also connected to the conductor layer pattern 13. Similar to the upper arm circuit, the signal terminal (gate control terminal) 7 and the signal terminal (emitter sense terminal) 8 control the switching of the IGBT chip 33.

[0033] Here, the sintered material described above is a sintered copper bonding material that includes copper nanoparticles, which are composed of multiple single crystals having a particle size of 0.1 nm to 10 nm, and have a copper oxide layer formed on their surface containing copper oxide. The sintered copper bonding technology uses the above copper nanoparticles as a bonding material for semiconductor chips, and forms a sintered copper bonding layer by sintering the copper nanoparticles together. Compared to conventional solder and silver, copper has higher fracture resistance, and can extend the fracture life of the bond even when used at high temperatures of 175°C or higher. In addition, the sintered copper bonding material has high bonding properties to non-precious metals such as copper and nickel, and does not require expensive gold or silver plating films on the electrode material to be bonded, thus reducing the cost required for bonding.

[0034] The key feature of this invention lies in the arrangement of lead frames 21 and 22 with respect to a slit 71 that occurs between the conductive layer pattern 11 and the conductive layer pattern 12. Lead frames 21 and 22 each extend in the direction of arrangement of multiple semiconductor chips (the Y direction in Figure 1), then become L-shaped, and straddle the slit 71 at a right angle. Note that the angle is not necessarily limited to a right angle (90°), and may be approximately a right angle or straddle at an angle.

[0035] Since the two sets of chips, IGBT chip 31 and diode chip 32, and IGBT chip 33 and diode chip 34, are roughly point-symmetric with respect to the center position of the substrate in the slit 71, the two L-shaped lead frames 21 and 22 are also arranged point-symmetrically with respect to the center position of the substrate in the slit 71, as shown in Figure 1. The lead frames 21 and 22 add a so-called bridge-like reinforcing structure, and by adopting this arrangement, the length of the slit 71 can be shortened from the distance Y1 to Y2 shown in Figure 1.

[0036] ≪Cross-sectional configuration≫ Figures 2 and 3 show the module structure along the cross-sectional lines A-A' and B-B' shown in Figure 1, respectively. To facilitate understanding of the internal structure of the power semiconductor module 200, some components in the depth direction as seen from the A-A' and B-B' cross-sectional lines are also shown. The A-A' cross-sectional view in Figure 2 shows the arrangement of lead frames 21 and 22 and slits 71 and 72. The conductor layer pattern 14 is a conductor layer pattern bonded to the lower plane of the insulating substrate 50.

[0037] The cross-sectional view A-A' in Figure 2 shows the view from lead frame 22 toward lead frame 21, and it can be seen that the bridge structure formed by the conductors consisting of semiconductor chips (diode chip 32, IGBT chip 33) and lead frames 21 and 22 spans the slit 71. Of the outer shape of the power semiconductor module 200 formed by the sealing resin 60, the length Z1 shown in the figure is defined as the height of the power semiconductor module 200.

[0038] The cross-sectional view B-B' in Figure 3 shows the cross-sectional configuration of the region where the lead frames 21 and 22 are not positioned on the slit 71. The cross-sectional shapes of lead frames 21 and 22 are in two stages, upper and lower. The lower half, which connects to the electrodes of the semiconductor chips (IGBT chip 31, diode chip 34), is shaped to match the width of the electrodes of the semiconductor chips.

[0039] In the power semiconductor module 200 of this embodiment, as shown in Figure 3, the external shape of the sealing resin 60 is characterized to suppress shrinkage stress that imparts mechanical stress to the slit 71. Since the lead frames 21 and 22 surround the center of the insulating substrate 50, the shape of the sealing resin 60 is partially deformed in the central portion where there are no lead frames to provide a recessed shape 61 (width X4) as shown in Figure 3. The height of the power semiconductor module 200 in the recessed shape 61 is defined as Z1a.

[0040] Thus, the structure of this embodiment makes it possible to simultaneously achieve the arrangement of a lead frame for rigidity reinforcement that spans the slit 71 generated on the insulating substrate 50, and to reduce the thickness of the sealing resin 60 in the central part of the substrate where the rigidity reinforcement by the lead frame does not reach.

[0041] Figure 10 shows the external view of the power semiconductor module 200 after molding. In the center of the figure is a recessed shape 61, whose planar shape is rectangular. The recessed shape 61 is formed in a roughly rectangular area enclosed by the lead frames 21 and 22. The length of its short side X4 is a value determined by the spacing between the lead frames, but it is desirable to set it to 4 mm or more in order to obtain the effect of thinning. Furthermore, as an example of the heights Z1 and Z1a of the power semiconductor module 200 described above, Z1 can be set to 5 mm and Z1a to 3 mm, and as a result the recessed height of the recessed shape 61 becomes the difference of 2 mm. It is desirable that the recessed height (depth) of this recessed shape 61 be 2 mm or more.

[0042] The external shape of the power semiconductor module 200 shown in Figure 10 is the same as that of the power semiconductor module 202 in Example 2 (Figure 8), which will be described later.

[0043] An example of a quantitative evaluation of stiffness is shown below.

[0044] Assuming that an alumina (Al2O3) substrate is used for the insulating substrate 50, its thickness is set to 0.3 mm and its Young's modulus to 300 GPa. The lead frame is made of copper, with a thickness of 1.5 mm and a Young's modulus of 130 GPa. Since rigidity can be roughly calculated by the product of thickness and Young's modulus, if the alumina substrate and the lead frame were the same width, the rigidity of the copper lead frame would be slightly more than 200% of that of the alumina substrate. However, assuming that the sum of the widths of the lead frames is 40% of the width of the slits 71 which dominate the rigidity of the alumina substrate, the increase in rigidity due to the introduction of the lead frame can be roughly estimated to be 80% higher than before the introduction.

[0045] Furthermore, since the lead frame exerts its rigidity through the power semiconductor chips (IGBT chips and diode chips) and their bonding materials, the selection of chip type and die bond bonding material is crucial. Needless to say, the effects of the present invention will be even more pronounced by selecting a SiC chip with higher hardness instead of a Si chip, and a bonding method using sintered copper or sintered silver that can ensure more than twice the bonding strength instead of solder.

[0046] ≪Example of a conventional lead frame configuration≫ To make the configuration and effects of this embodiment easier to understand, Figures 4 and 5 will be used to describe an example of a conventional power semiconductor module configuration.

[0047] Figure 4 is a plan view of a conventional power semiconductor module 201, and Figure 5 is a cross-sectional view taken along line C-C' in Figure 4. Similar to Figures 2 and 3, some of the components in the depth direction as seen from the C-C' cross-section are also shown to facilitate understanding of the internal structure of the power semiconductor module 201.

[0048] The conventional power semiconductor module 201 shown in Figure 4 illustrates a module configuration that realizes a half-bridge circuit similar to that in Figure 1 on an insulating substrate 50. Although lead frames 21 and 22 are used, the configuration shown is that of a conventional example.

[0049] Unlike the configuration of this embodiment (Figure 1), there is no rigid reinforcing structure, and a slit 71 with length Y3 is generated in the center of the insulating substrate 50. As the sealing resin 60 cools and hardens, stress is generated around the slit 71, and there is a high risk of cracks occurring in the central part of the insulating substrate 50.

[0050] Qualitative Trends Based on Analysis Results The stress in the central part of the insulating substrate 50 will be explained using Figures 6 to 7B.

[0051] Figure 6 shows the results of analyzing the stress N in the central part of the ceramic substrate using a simulator. Figures 7A and 7B are diagrams illustrating the overview of the analysis model in Figure 6, showing a cross-sectional structure that mimics a conventional example and the structure of the present invention, respectively.

[0052] A copper conductive layer pattern 11, 12, and 14 with a thickness of 0.4 mm was placed on an insulating substrate (ceramic substrate) 50, which was assumed to be made of alumina (Al2O3). The stress N was observed in the central part of the insulating substrate (ceramic substrate) 50, which was 0.3 mm thick, and directly below the slit 71.

[0053] Figure 7B, which simulates the structure of the present invention, shows a configuration in which a copper plate LF equivalent to a lead frame is additionally placed to block the slit 71. In Figures 7A and 7B, it is assumed that epoxy resin is used as the encapsulating resin 60, with a thickness T, and that it is placed on the conductor layer patterns 11 and 12. Figure 6 shows the dependence of stress N when the value of T is changed. Here, T values ​​of 4 mm to 7 mm are used. A realistic T value is about 4 mm, and considering the thickness of the insulating substrate 50 and the conductor layer patterns 11 and 12, the total thickness of the resin-encapsulated power semiconductor module is about 5 mm.

[0054] In Figure 6, the horizontal axis shows the change in resin thickness T. In the case of the cross-sectional structure mimicking the conventional example shown in Figure 7A (plots marked with ▲ in the figure), it can be seen that even when the resin thickness T decreases, the stress N does not decrease and remains high. On the other hand, in the cross-sectional structure mimicking the structure of the present invention shown in Figure 7B (plots marked with 〇 in the figure), it can be seen that, compared to the conventional example, the stress N itself decreases, and the stress N decreases as the resin thickness T decreases.

[0055] This trend qualitatively demonstrates the effectiveness of the combined measures described in this embodiment: the addition of a lead frame to reinforce rigidity and the partial thinning of the resin thickness. Furthermore, as shown in the data for the conventional example in Figure 6, it was found that simply thinning the resin thickness T does not result in a stress reduction effect. Although these trends in the analysis results fluctuate depending on the thermal expansion coefficients of the resin and copper conductive layer patterns and their respective thicknesses, and are not constant trends, they demonstrate the effectiveness of the present invention.

[0056] As described above, the power semiconductor module of this embodiment is a resin-encapsulated power semiconductor module that does not have a base plate or heat sink that serves as a support member for the insulating substrate 50, and comprises an insulating substrate 50, a first conductor layer pattern 11 disposed on the insulating substrate 50, a second conductor layer pattern 12 disposed on the insulating substrate 50 and electrically insulated from the first conductor layer pattern 11, a third conductor layer pattern 13 disposed on the insulating substrate 50 and electrically insulated from the first conductor layer pattern 11 and the second conductor layer pattern 12, a first semiconductor chip group (IGBT chip 31, diode chip 32) having one or more semiconductor chips bonded on the first conductor layer pattern 11, and a second semiconductor having one or more semiconductor chips bonded on the second conductor layer pattern 12. The semiconductor chip group (IGBT chip 33, diode chip 34) is electrically connected to the second conductor layer pattern 12 on the opposite side of the junction surface between the first conductor layer pattern 11 of the first semiconductor chip group and the second conductor layer pattern 12, and the semiconductor chip group is electrically connected to the third conductor layer pattern 13 on the opposite side of the junction surface between the second conductor layer pattern 12 of the second semiconductor chip group and the third conductor layer pattern 13. Each of the first lead frame 21 and the second lead frame 22 is positioned across the slit 71 between the first conductor layer pattern 11 and the second conductor layer pattern 12, and is positioned so as not to overlap each other in a direction perpendicular to the arrangement surface of each conductor layer pattern 11, 12, 13 of the insulating substrate 50, i.e., so that the lead frames 21 and 22 are in a single layer.

[0057] Furthermore, slit 71 is located in the center of the insulating substrate 50 and is the longest of the multiple slits between the conductor layer patterns 11, 12, and 13 formed on the insulating substrate 50.

[0058] Furthermore, the thickness of the sealing resin 60 in the region including at least a part of the slit 71 is thinner than the thickness of the sealing resin 60 in the other regions.

[0059] Furthermore, in a direction perpendicular to the arrangement surface of each conductor layer pattern 11, 12, and 13 of the insulating substrate 50, only the sealing resin 60 is arranged on the first lead frame 21 and the second lead frame 22.

[0060] This effectively suppresses cracks in the insulating substrate 50 that tend to occur during the cooling and curing of the sealing resin 60. [Examples]

[0061] The power semiconductor module of Embodiment 2 of the present invention will be described with reference to Figures 8 and 9, and Figures 12 to 14. Figures 12 and 13 are diagrams relating to Embodiment 1 and are shown for comparison with this embodiment.

[0062] Figure 8 is a plan view of the power semiconductor module 202 of this embodiment. Compared to the configuration of Embodiment 1 (Figure 1), the terminal shapes of the external main terminals 1 and 3 and the shape of the conductor layer pattern around them have been changed. The shapes of the lead frame 21 and lead frame 22A with respect to the slit 71 are the same as in Embodiment 1 (Figure 1).

[0063] The lead frame 22A has an L-shaped frame design while also serving as the external main terminal 3 shown in Example 1 (Figure 1). This design allows the path from the IGBT chip 33 to the external main terminal 3A to be constructed with a uniform and thick conductor. For example, the conductor layer patterns 11-13 are copper circuit patterns with a thickness of 0.4 mm. On the other hand, since thick copper lead frames can be used for lead frames 21 and 22A regardless of the thickness of the conductor layer patterns 11-13, their thickness can be set to 1.0 mm to 1.5 mm.

[0064] Compared to the external main terminal 1 in Example 1 (Figure 1), the external main terminal 1A has a length on the insulating substrate 50 that extends to the vicinity of the diode chip 32, and its shape is such that it passes over the upper part of the conductor layer pattern 13.

[0065] Figure 9 shows a cross-sectional view along the cross-sectional line D-D' in Figure 8. By adopting the configuration of this embodiment as described above, the external main terminal 3A (which is also the lead frame 22A), which is a low-voltage power supply terminal, can have two features in relation to the external main terminal 1A, which is a high-voltage power supply terminal: (1) the thick conductor cross-sectional shapes can be arranged in parallel with each other, and (2) a region is created in which it is arranged in parallel with the conductor layer pattern 13 in a planar manner. In other words, the external main terminal 1A can be arranged in parallel with the lead frame 22A in terms of their thick conductor cross-sectional shapes, and can also be arranged in parallel with the conductor layer pattern 13 over a wide width.

[0066] External main terminals 1A and 3A are wiring paths that constitute the main circuit inductance Ls, which affects the switching characteristics of the power semiconductor module 202. Figure 14 shows the equivalent circuit of the main circuit inductance path of the power semiconductor module 202 in this embodiment shown in Figure 8. External main terminal 1A corresponds to Term1A in the figure, and external main terminal 3A corresponds to Term3A.

[0067] Term 1A is connected to the IGBT chip 31 and diode chip 32 via L1A and L1B, which correspond to the inductance generated at the external main terminal 1A. These semiconductor chips are connected to the IGBT chip 33 and diode chip 34 via inductance L21, which corresponds to the lead frame 21, and further connected to Term 3A via inductances L22A, L22B, and L13, which correspond to the lead frame 22A and conductor layer pattern 13, and L3, which indicates the inductance of the external main terminal 3A.

[0068] The total inductance of the path from Term1A to Term3A is the main circuit inductance Ls. The smaller this value, the more the surge voltage during switching can be reduced, thereby reducing switching losses.

[0069] From the equivalent circuits shown in Figures 9 and 14, in this embodiment, mutual inductances M1-13, M1-22, and M1-3 are generated between the conductor layer pattern 13 and the lead frame 22A (which also serves as the external main terminal 3A) with respect to inductances L1A and L1B. As shown in Figure 9, since the currents flowing through external main terminals 1A and 3A are in opposite directions, mutual inductance M is generated, which has the effect of reducing the value of the main circuit inductance Ls. The reason why the value of the main circuit inductance Ls decreases is that the sign of the mutual inductance M is negative, which is the opposite of the self-inductance of the conductor layer pattern and the lead frame that constitute Ls.

[0070] Here, we will compare the configuration of Example 1 (Figure 1) with that of Example 1 using Figures 12 and 13.

[0071] In the cross-sectional structure of Embodiment 1 shown in Figure 12 (cross-section A-A' in Figure 1), mutual inductance M11-13 is generated between the conductor layer pattern 13 and the laminated structure of the lead frame 22 with respect to the conductor layer pattern 11.

[0072] Figure 13 shows the equivalent circuit of the main circuit inductance path of the power semiconductor module 200 of Example 1 (Figure 1). Focusing on the main circuit inductance path, in addition to the inductances L1 and L11 generated between the external main terminal 1 and the conductor layer pattern 11, mutual inductances M1-3 are generated between the conductor layer pattern 13 and the external main terminal 3, in addition to the above M11-13.

[0073] Comparing Example 1 (Figure 1) and Example 2 (Figure 8), the external main terminals, conductor layer patterns, and lead frame lengths are the same, but as can be seen from the comparison between Figure 13 and Figure 14, the mutual inductances are different. Comparing the magnitude of the difference in mutual inductance between Example 1 and Example 2, the relationship given by equation (1) holds.

[0074] |M1-13 + M1-22| > |M11-13| (Formula 1) In other words, by arranging the external main terminals 1 and 3, and the surrounding conductor layer pattern and lead frame as shown in Example 1 (Figure 1), as in this embodiment (Figure 8), the value of the mutual inductance that affects the main circuit inductance Ls can be increased. Therefore, in this embodiment, the main circuit inductance Ls can be kept smaller than in Example 1.

[0075] As described above, the power semiconductor module of this embodiment has an external main terminal 1A electrically connected to the first conductor layer pattern 11, and a portion of the external main terminal 1A is configured to face the second lead frame 22A across the sealing resin 60 and the third conductor layer pattern 13 across the sealing resin 60 on the arrangement surface of each conductor layer pattern 11, 12, and 13 of the insulating substrate 50.

[0076] Furthermore, the external main terminal 3A is molded integrally with the second lead frame 22A.

[0077] In this embodiment, the main circuit inductance Ls can be reduced by changing the shape of the external main terminal while easing the stress on the insulating substrate (ceramic substrate) 50.

[0078] Therefore, by introducing inexpensive but weakly bending insulating substrates such as alumina (Al2O3) substrates into resin-encapsulated power semiconductor modules, the risk of substrate cracking can be reduced, enabling high-yield manufacturing and thus lowering the cost of power semiconductor modules.

[0079] Furthermore, since the main circuit inductance can be reduced, switching losses can be reduced. [Examples]

[0080] The power converter of Embodiment 3 of the present invention will be described with reference to Figure 11. Figure 11 is a block diagram showing the circuit configuration of the power converter of this embodiment.

[0081] Figure 11 shows an example of a three-phase AC motor that drives the axle of an electric vehicle, which consists of a battery 250, a power converter 260, and a motor 270 that acts as the load.

[0082] The power converter 260 in this embodiment includes three single-phase leg circuits, each composed of a 2-in-1 power semiconductor module 200 or power semiconductor module 202, a capacitor 240, and a control circuit 230. The power converter 260 also includes gate drive circuits 210 (210a to 210c) equal to the number of AC phases.

[0083] The power converter 260 maintains the main voltage (Vcc) with the capacitor 240, and the gate drive signals for the semiconductor switching elements in each power semiconductor module 200 (202) generated by the control circuit 230 are input to each power semiconductor module 200 (202) via gate drive circuits 210a, 210b, and 210c.

[0084] The leg circuits 220a, 220b, and 220c constitute the first-phase inverter leg, the second-phase inverter leg, and the third-phase inverter leg, respectively. The output of each inverter leg is connected to the motor 270.

[0085] In this embodiment, the leg circuits 220a, 220b, and 220c have the same circuit configuration. Therefore, the circuit configuration will be explained using leg circuit 220a as an example.

[0086] The leg circuit 220a comprises a pair of upper and lower arms composed of power semiconductor modules 200a (202a), and a gate drive circuit 210a that controls the on / off state of the power semiconductor modules 200a (202a).

[0087] According to this embodiment, the power semiconductor module 200 or power semiconductor module 202 mounted on the power converter 260 is the same as the power semiconductor module described in either Embodiment 1 or Embodiment 2, which makes it possible to reduce the cost of the power converter 260 and the electric vehicle motor drive system that includes it.

[0088] Furthermore, by using the power semiconductor module 202 described in Example 2, the main circuit inductance can be reduced, thereby reducing switching losses compared to conventional module configurations.

[0089] Therefore, the power converter 260 and the electric vehicle motor drive system comprising it can be made less expensive and have lower losses.

[0090] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations.

[0091] For example, the dimensions and insulation distances of the components constituting the power semiconductor module 200 and the power semiconductor module 202 can be arbitrary depending on their application.

[0092] Furthermore, the chip arrangement of the semiconductor switching elements constituting the power semiconductor module 200 and the power semiconductor module 202 is not limited to the illustrated configuration.

[0093] The power semiconductor module 200 or power semiconductor module 202 may be any of the following: a parallel connection of IGBTs and diodes as described in each embodiment; a parallel connection of multiple MOSFET chips; a unipolar device such as a JFET (Junction Field Effect Transistor); or a bipolar device such as a BJT (Bipolar Junction Transistor). Depending on the device, the main terminal and sense terminal may be referred to as "drain" and "source" in addition to the "collector" and "emitter" mentioned above.

[0094] Furthermore, the power converter 260 to which the power semiconductor module 200 or power semiconductor module 202 is applied can be used not only in motor drive systems for electric vehicles, but also in PCS (Power Conditioning System) in solar power generation equipment and railway vehicle electrical systems, etc. [Explanation of symbols]

[0095] 1.1A…External main terminal (high voltage power terminal) 2…External main terminal (AC voltage terminal) 3.3A…External main terminal (low voltage power terminal) 5, 7… Signal terminals (gate control terminals) 6, 8… Signal terminals (emitter sense terminals) 11…Conductor layer pattern (potential of high-voltage power supply terminals) 12…Conductor layer pattern (potential of AC voltage terminals) 13…Conductor layer pattern (potential of low-voltage power supply terminals) 14...Conductor layer pattern 15, 18… Conductor layer pattern (potential of gate voltage terminal) 16,19…Conductor layer pattern (potential of emitter sense voltage terminal) 21, 22, 22A… Lead frame 25, 27… (Bonding wire for gate wiring) 26, 28… (Bonding wires for emitter sense wiring) 31, 33… IGBT chips 32, 34… Diode chips 50…Insulating substrate (ceramic substrate) 60…Sealing resin 61…(Recess shape of the sealing resin) 71, 72… (slits between conductor layer patterns) 200, 201, 202… Power semiconductor modules 210, 210a~210c... Gate drive circuit 220, 220a~220c...Reg circuits 230...Control circuit 240... Capacitor 250... Battery 260... Power converter 270...Electric motor 301...Collector electrode 302...Emitter electrode 303… Gate 304... Anode electrode 305... Cathode electrode X1,X4,Y1,Y2,Y3,Y4…distance T...Thickness of the sealing resin

Claims

1. A resin-encapsulated power semiconductor module that does not have a support member for the insulating substrate, Insulating substrate and A first conductor layer pattern disposed on the insulating substrate, A second conductor layer pattern is disposed on the insulating substrate and electrically insulated from the first conductor layer pattern, A third conductor layer pattern is disposed on the insulating substrate and is electrically insulated from the first conductor layer pattern and the second conductor layer pattern, A first group of semiconductor chips having one or more semiconductor chips bonded on the first conductor layer pattern, A second group of semiconductor chips having one or more semiconductor chips bonded to the second conductor layer pattern, A first lead frame electrically connects the opposite side of the junction surface between the first semiconductor chip group and the first conductor layer pattern to the second conductor layer pattern, The second lead frame electrically connects the opposite side of the junction surface between the second semiconductor chip group and the second conductor layer pattern to the third conductor layer pattern, A power semiconductor module characterized in that each of the first lead frame and the second lead frame is arranged across a slit between the first conductor layer pattern and the second conductor layer pattern, and the lead frame is arranged in a single layer in a direction perpendicular to the arrangement surface of each conductor layer pattern on the insulating substrate.

2. A power semiconductor module according to claim 1, A power semiconductor module characterized in that each of the first lead frame and the second lead frame does not overlap with each other in a direction perpendicular to the arrangement plane of each conductor layer pattern on the insulating substrate.

3. A power semiconductor module according to claim 1, The slit is located in the center of the insulating substrate. A power semiconductor module characterized by having the longest length among a plurality of slits between each of the conductor layer patterns formed on the insulating substrate.

4. A power semiconductor module according to claim 3, The insulating substrate, the first group of semiconductor chips, the second group of semiconductor chips, the first lead frame, and the sealing resin for sealing the second lead frame are provided. A power semiconductor module characterized in that the thickness of the sealing resin in the region including at least a portion of the slit is thinner than the thickness of the sealing resin in other regions.

5. A power semiconductor module according to claim 1, A power semiconductor module characterized in that, in a direction perpendicular to the arrangement surface of each conductor layer pattern of the insulating substrate, only sealing resin is arranged on the first lead frame and the second lead frame.

6. A power semiconductor module according to claim 4, The sealing resin has a recess on its surface, The power semiconductor module is characterized in that the recess is a region where the thickness of the sealing resin is thin, and its depth is 2 mm or more.

7. A power semiconductor module according to claim 4, The sealing resin has a recess on its surface, The power semiconductor module is characterized in that the recess is a region where the thickness of the sealing resin is thin, and when the power semiconductor module is viewed from above, it has a rectangular shape with a short side of 4 mm or more.

8. A power semiconductor module according to claim 1, Having an external terminal electrically connected to the first conductor layer pattern, A power semiconductor module characterized in that a portion of the external terminals faces the second lead frame across the sealing resin and the third conductor layer pattern across the sealing resin on the arrangement surface of the insulating substrate for each conductor layer pattern.

9. A power semiconductor module according to claim 1, The aforementioned insulating substrate is made of alumina (Al 2 O 3 A power semiconductor module characterized by having a ceramic substrate whose main component is ).

10. A power semiconductor module according to claim 1, A power semiconductor module characterized in that at least one of the following is a bonding or connection using sintered copper: bonding the first semiconductor chip group to the first conductor layer pattern, connecting the first semiconductor chip group to the first lead frame, bonding the second semiconductor chip group to the second conductor layer pattern, and connecting the second semiconductor chip group to the second lead frame.

11. A power semiconductor module according to claim 1, A first external terminal electrically connected to the first conductor layer pattern, The third conductor layer pattern is electrically connected to a second external terminal, A power semiconductor module characterized in that the second external terminal is molded integrally with the second lead frame.

12. A main circuit having one or more pairs of upper and lower arms, The system includes a drive circuit for driving the upper and lower arms, A power conversion device characterized in that the upper and lower arms use the power semiconductor module described in any one of claims 1 to 11.

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