Silicon carbide semiconductor equipment
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MITSUMI ELECTRIC CO LTD
- Filing Date
- 2022-06-21
- Publication Date
- 2026-07-30
Smart Images
Figure 0007897506000001 
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a silicon carbide semiconductor device.
[0002] This application claims priority based on Japanese Application No. 2021-150122 filed on September 15, 2021, and incorporates all the descriptions described in the Japanese application.
Background Art
[0003] A silicon carbide semiconductor device aimed at suppressing dielectric breakdown of an insulating film under a gate pad is disclosed (for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
[0005] The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface, an interlayer insulating film covering the first main surface, and a gate pad and a source pad provided on the interlayer insulating film, wherein the silicon carbide substrate, in a plan view from a direction perpendicular to the first main surface, has a first region including a plurality of unit cells, a second region overlapping the gate pad, and a third region adjacent to the second region, and each of the plurality of unit cells has a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type, a source region provided on the first main surface and separated from the drift region by the body region and having the first conductivity type, and a portion provided on the first main surface and electrically connected to the body region The interlayer insulating film comprises a contact region having the second conductivity type, a gate electrode electrically connected to the gate pad, and a gate insulating film provided between the drift region, the body region, the source region and the gate electrode, wherein the second region has a first semiconductor region having the second conductivity type, and the third region has a second semiconductor region having the second conductivity type, and the first and second semiconductor regions are connected to each other on the first main surface, and the interlayer insulating film has a first contact hole reaching the source region and the contact region, and a second contact hole reaching the second semiconductor region, and the source pad is connected to the source region and through the first contact hole The aforementioned Electrically connected to the contact region, electrically connected to the second semiconductor region via the second contact hole, and in a cross-sectional view from a direction parallel to the first main surface, the second dimension of the second contact hole in the short-side direction is greater than the first dimension of the first contact hole in the short-side direction. The semiconductor has an active region containing the plurality of unit cells and a terminal region provided around the active region, the terminal region having a third semiconductor region having the second conductivity type, the second semiconductor region being provided between the gate pad and the terminal region in a plan view from a direction perpendicular to the first main surface and including a fourth semiconductor region connected to the first semiconductor region and the third semiconductor region on the first main surface, the concentration of impurities of the second conductivity type in the third semiconductor region being lower than the concentration of impurities of the second conductivity type in the fourth semiconductor region, and the second contact hole including a third contact hole reaching the fourth semiconductor region . [Brief explanation of the drawing]
[0006] [Figure 1] Figure 1 is a top view showing a silicon carbide semiconductor device according to the first embodiment. [Figure 2] Figure 2 shows the various regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment. [Figure 3]Figure 3 is a top view showing region 221 in Figures 1 and 2 through the passivation film, gate pad, and source pad. [Figure 4] Figure 4 is a top view showing the configuration of the first main surface of the silicon carbide substrate in region 221 in Figures 1 and 2. [Figure 5] Figure 5 is a top view showing region 222 in Figures 1 and 2 through the passivation film, gate pad, and source pad. [Figure 6] Figure 6 is a top view showing region 222 in Figures 1 and 2 through the passivation film, gate pad, and source pad. [Figure 7] Figure 7 is a cross-sectional view showing a silicon carbide semiconductor device according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view showing the structure of a unit cell. [Figure 9] Figure 9 is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment. [Figure 10] Figure 10 is a top view showing a silicon carbide semiconductor device according to the third embodiment. [Figure 11] Figure 11 shows the various regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the third embodiment. [Figure 12] Figure 12 is a cross-sectional view (part 1) showing a silicon carbide semiconductor device according to the third embodiment. [Figure 13] Figure 13 is a cross-sectional view (part 2) showing a silicon carbide semiconductor device according to the third embodiment. [Figure 14] Figure 14 is a top view showing a silicon carbide semiconductor device according to the fourth embodiment. [Figure 15] Figure 15 shows the various regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the fourth embodiment. [Figure 16] Figure 16 is a cross-sectional view showing a silicon carbide semiconductor device according to the fourth embodiment. [Figure 17] Figure 17 is a top view showing a silicon carbide semiconductor device according to the fifth embodiment. [Figure 18]FIG. 18 is a diagram showing each region in a silicon carbide substrate in a silicon carbide semiconductor device according to the fifth embodiment. [Figure 19] FIG. 19 is a top view showing a silicon carbide semiconductor device according to the sixth embodiment. [Figure 20] FIG. 20 is a diagram showing each region in a silicon carbide substrate in a silicon carbide semiconductor device according to the sixth embodiment. [Figure 21] FIG. 21 is a top view showing a silicon carbide semiconductor device according to the seventh embodiment. [Figure 22] FIG. 22 is a diagram showing each region in a silicon carbide substrate in a silicon carbide semiconductor device according to the seventh embodiment. [Figure 23] FIG. 23 is a top view showing a silicon carbide semiconductor device according to the eighth embodiment. [Figure 24] FIG. 24 is a top view showing the configuration of the first main surface of the silicon carbide substrate in region 223 in FIG. 23. [Figure 25] FIG. 25 is a cross-sectional view (part 1) showing a silicon carbide semiconductor device according to the eighth embodiment. [Figure 26] FIG. 26 is a cross-sectional view (part 2) showing a silicon carbide semiconductor device according to the eighth embodiment. [Figure 27] FIG. 27 is a cross-sectional view (part 3) showing a silicon carbide semiconductor device according to the eighth embodiment. [Figure 28] FIG. 28 is a top view showing a modification example of the first region. [Embodiments for Carrying Out the Invention]
[0007] [Problems to be Solved by the Present Disclosure] In the silicon carbide semiconductor device described in Patent Document 1, when a surge occurs, electric field concentration is likely to occur in the interlayer insulating film. Such electric field concentration can lead to breakdown.
[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of alleviating electric field concentration in an interlayer insulating film.
[0009] [Effects of the Present Disclosure] According to this disclosure, electric field concentration in the interlayer insulating film can be mitigated.
[0010] The implementation methods are described below.
[0011] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described first. In the crystallographic descriptions in this specification and drawings, individual orientations are indicated by [], collective orientations by <>, individual planes by () and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this specification a negative sign is placed before the number.
[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface, an interlayer insulating film covering the first main surface, and a gate pad and a source pad provided on the interlayer insulating film, wherein the silicon carbide substrate, in a plan view from a direction perpendicular to the first main surface, has a first region including a plurality of unit cells, a second region overlapping the gate pad, and a third region adjacent to the second region, each of the plurality of unit cells having a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type, a source region provided on the first main surface and separated from the drift region by the body region and having the first conductivity type, a contact region provided on the first main surface and electrically connected to the body region and having the second conductivity type, a gate electrode electrically connected to the gate pad, and the drift region, the body The interlayer insulating film comprises a region and a gate insulating film provided between the source region and the gate electrode, wherein the second region has a first semiconductor region having the second conductivity type, and the third region has a second semiconductor region having the second conductivity type, the first semiconductor region and the second semiconductor region are connected to each other on the first main surface, and the interlayer insulating film has a first contact hole reaching the source region and the contact region, and a second contact hole reaching the second semiconductor region, the source pad is electrically connected to the source region and the contact region via the first contact hole, and is electrically connected to the second semiconductor region via the second contact hole, and in a cross-sectional view from a direction parallel to the first main surface, the second dimension of the second contact hole in the short side direction is larger than the first dimension of the first contact hole in the short side direction.
[0013] A third region is provided adjacent to the second region, and the first and second semiconductor regions are connected on the first main surface. Furthermore, in a cross-sectional view from a direction parallel to the first main surface, the second dimension in the short-side direction of the second contact hole is larger than the first dimension in the short-side direction of the first contact hole. Therefore, the contact resistance between the source pad and the second semiconductor region is reduced, and even if a surge occurs, the electric field concentration on the interlayer insulating film in the second region can be mitigated.
[0014] [2] In [1], the contact region and the second semiconductor region may be connected to each other on the first main surface. In this case, it is easier to control the contact region and the second semiconductor region to the same potential.
[0015] [3] In [1] or [2], there is an active region including the plurality of unit cells and a termination region provided around the active region, wherein the termination region has a third semiconductor region having the second conductivity type, and the second semiconductor region includes a fourth semiconductor region provided between the gate pad and the termination region in a plan view from a direction perpendicular to the first main surface, which is connected to the first semiconductor region and the third semiconductor region in the first main surface, the concentration of impurities of the second conductivity type in the third semiconductor region is lower than the concentration of impurities of the second conductivity type in the fourth semiconductor region, and the second contact hole may include a third contact hole that reaches the fourth semiconductor region. In this case, electric field concentration on the interlayer insulating film near the termination region can be mitigated.
[0016] [4] In [3], a field insulating film is provided between the first semiconductor region, the fourth semiconductor region, and the third semiconductor region and the interlayer insulating film, wherein a fourth contact hole reaching the fourth semiconductor region is formed in the field insulating film, the interlayer insulating film is in contact with the fourth semiconductor region inside the fourth contact hole, and the third contact hole is located inside the fourth contact hole. In this case, electric field concentration in the interlayer insulating film can be further reduced.
[0017] [5] In [3] or [4], there is a source runner that is electrically connected to the source pad and electrically connected to the fourth semiconductor region via the third contact hole, and in a cross-sectional view from a direction parallel to the first main surface, the side of the source runner away from the gate pad may be on the boundary line between the third semiconductor region and the fourth semiconductor region, or closer to the gate pad than the boundary line. In this case, electric field concentration in the interlayer insulating film below the source runner is easily mitigated.
[0018] [6] In any of [3] to [5], the fourth semiconductor region includes a first gate runner electrically connected to the gate pad, extending in a first direction parallel to the first main surface and positioned closer to the termination region than the gate pad, and a second gate runner electrically connected to the gate pad, extending in the first direction, away from the first gate runner and positioned closer to the termination region than the gate pad, wherein the fourth semiconductor region includes a fifth semiconductor region provided between the first gate runner and the second gate runner in a plan view from a direction perpendicular to the first main surface and connected to the first semiconductor region on the first main surface, and the second contact hole may include a fifth contact hole reaching the fifth semiconductor region. In this case, the contact resistance between the source pad and the fourth semiconductor region can be further reduced in the vicinity of the gate pad.
[0019] [7] In any of [3] to [5], there is a third gate runner electrically connected to the gate pad, extending in a first direction parallel to the first main surface and positioned closer to the termination region than the gate pad, the fourth semiconductor region includes a sixth semiconductor region provided between the gate pad and the third gate runner in a plan view from a direction perpendicular to the first main surface and connected to the first semiconductor region on the first main surface, and the second contact hole may include a sixth contact hole reaching the sixth semiconductor region. In this case, the degree of freedom in the arrangement of the gate pad can be increased.
[0020] [8] In any of [3] to [7], the plurality of unit cells extend in a first direction parallel to the first main plane and are arranged in a second direction perpendicular to the first direction, the gate pad has a rectangular planar shape with the first direction as its longitudinal direction when viewed from a plane perpendicular to the first main plane, the second semiconductor region includes a seventh semiconductor region provided in the second direction with the gate pad sandwiched between it and the fourth semiconductor region, and the second contact hole may include a seventh contact hole that reaches the seventh semiconductor region. In this case, the contact resistance between the source pad and the second semiconductor region can be further reduced.
[0021] [9] In [8], in a cross-sectional view from a direction parallel to the first main surface, the third dimension of the third contact hole in the short-side direction may be equal to the fourth dimension of the seventh contact hole in the short-side direction. In this case, the current generated in the first semiconductor region is likely to flow evenly toward the third and seventh contact holes.
[0022]
[10] In [8] or [9], the fifth dimension of the third contact hole in the first direction may be greater than the sixth dimension of the gate pad in the first direction. In this case, contact resistance is more easily reduced.
[0023]
[11] In any of [8] to
[10] , in plan view, the silicon carbide substrate has a rectangular shape with a first and second side parallel to each other, and a third and fourth side perpendicular to the first and second sides, and includes a fourth gate runner extending along the first side, a fifth gate runner extending along the second side, and a sixth gate runner extending from the gate pad toward the fourth side between the fourth and fifth gate runners, wherein the fourth, fifth and sixth gate runners are electrically connected to the gate pad. In this case, it is easy to apply the gate voltage evenly to each unit cell from the fourth, fifth and sixth gate runners.
[0024]
[12] In
[11] , the seventh dimension in the first direction of the portion of the seventh contact hole between the fourth gate runner and the sixth gate runner in a plan view may be 1 / 2 or more of the distance between the fourth gate runner and the sixth gate runner. In this case, the dimension in the first direction of a unit cell located on the extension of the seventh contact hole in the portion between the fourth gate runner and the sixth gate runner will be 1 / 2 or less of the distance between the fourth gate runner and the sixth gate runner. Therefore, it is easy to apply a gate voltage to this unit cell in the same way as to other unit cells.
[0025]
[13] In
[11] or
[12] , the eighth dimension in the first direction of the portion of the seventh contact hole between the fifth gate runner and the sixth gate runner in a plan view may be 1 / 2 or more of the distance between the fifth gate runner and the sixth gate runner. In this case, the dimension in the first direction of a unit cell located on the extension of the seventh contact hole in the portion between the fifth gate runner and the sixth gate runner will be 1 / 2 or less of the distance between the fifth gate runner and the sixth gate runner. Therefore, it is easy to apply a gate voltage to this unit cell in the same way as to other unit cells.
[0026]
[14] In any of
[11] to
[13] , among the plurality of unit cells located closer to the fourth edge than the seventh semiconductor region, some unit cells located closer to the third edge may be further away from the sixth gate runner in the second direction than the remaining unit cells. In this case, electric field concentration in the vicinity of the sixth gate runner can be mitigated.
[0027] [Embodiments of this Disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In this specification and drawings, the X1-X2 direction, Y1-Y2 direction, and Z1-Z2 direction are mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as the ZX plane. For convenience, the Z1-Z2 direction is considered the up and down direction, with the Z1 side being the upper side and the Z2 side being the lower side. Furthermore, a plan view means viewing the object from the Z1 side, and a planar shape means the shape of the object as viewed from the Z1 side.
[0028] (First Embodiment) A first embodiment will be described. The first embodiment relates to a so-called vertical MOSFET (silicon carbide semiconductor device). Figure 1 is a top view showing a silicon carbide semiconductor device according to the first embodiment. Figure 2 is a diagram showing each region within the silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment. Figure 3 is a top view showing region 221 in Figures 1 and 2, with the passivation film, gate pad, and source pad visible through it. Figure 4 is a top view showing the configuration of the first main surface of the silicon carbide substrate in region 221 in Figure 2. Figure 5 is a top view showing region 222 in Figure 2, with the passivation film, gate pad, and source pad visible through it. Figure 6 is a top view showing region 222 in Figure 2, with the passivation film, gate pad, and source pad visible through it. Figure 7 is a cross-sectional view showing a silicon carbide semiconductor device according to the first embodiment. Figure 7 corresponds to a cross-sectional view along line VII-VII in Figures 1 and 2. Figure 8 is a cross-sectional view showing the configuration of a unit cell. In Figures 7 and 8, the passivation membrane is omitted.
[0029] As shown in Figures 1 to 8, the MOSFET 201 according to the first embodiment comprises a silicon carbide substrate 10 and a gate insulating film. 4The MOSFET 201 further includes a gate pad 61, a source pad 62, a gate runner (gate wiring) 61A, a gate runner 61B, a gate runner 61C, a gate runner 61D, a gate runner 61E, and a source runner (source wiring) 62C. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 20 and a silicon carbide epitaxial layer 30 on the silicon carbide single crystal substrate 20. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 30 constitutes the first main surface 1, and the silicon carbide single crystal substrate 20 constitutes the second main surface 2. The silicon carbide single crystal substrate 20 and the silicon carbide epitaxial layer 30 are composed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 20 contains n-type impurities such as nitrogen (N) and has n-type (first conductivity type).
[0030] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.
[0031] In plan view, the silicon carbide substrate 10 has a rectangular shape with a first side 91 and a second side 92 that are parallel to each other, and a third side 93 and a fourth side 94 that are perpendicular to the first side 91 and the second side 92. The first side 91 and the second side 92 are parallel in the Y1-Y2 direction, and the third side 93 and the fourth side 94 are parallel in the X1-X2 direction. The first side 91 is on the X2 side of the second side 92, and the second side 92 is on the X1 side of the first side 91. The third side 93 is on the Y1 side of the fourth side 94, and the fourth side 94 is on the Y2 side of the third side 93.
[0032] The silicon carbide substrate 10 has an active region 41 and an end region 42 provided around the active region 41 in a plan view.
[0033] The active region 41 has a first region 101, a second region 102, and a third region 103. The first region 101 is a region in which multiple unit cells 40 are arranged. The second region 102 is a region that overlaps with the gate pad 61 in a plan view. The unit cells 40 are aligned in the Y1-Y2 direction, with the X1-X2 direction being the longitudinal direction. The dimensions of each unit cell 40 in the Y1-Y2 direction are common. Each unit cell 40 has one set of gate trench and gate electrode. The unit cells 40 are aligned in the Y1-Y2 direction at a constant pitch P1. The X1-X2 direction is an example of the first direction, and the Y1-Y2 direction is an example of the second direction.
[0034] The silicon carbide epitaxial layer 30 mainly comprises a drift region 31, a body region 32, a source region 33, a contact region 34, an embedded region 35, an embedded junction termination extension (JTE) region 36, and a surface JTE region 37. The drift region 31 is provided across the active region 41 and the termination region 42. The body region 32, source region 33, contact region 34, and embedded region 35 are provided within the active region 41. The embedded JTE region 36 and the surface JTE region 37 are provided in the termination region 42. Parts of the contact region 34 and the embedded region 35 may also be provided in the termination region 42.
[0035] The drift region 31 is provided on the silicon carbide single crystal substrate 20. The drift region 31 is located closer to the first main surface 1 than to the silicon carbide single crystal substrate 20. The drift region 31 may be connected to the silicon carbide single crystal substrate 20. The drift region 31 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity.
[0036] The body region 32 is located on the drift region 31. The body region 32 contains p-type impurities such as aluminum (Al) and has a p-type conductivity (second conductivity). The body region 32 is located closer to the first main surface 1 than the drift region 31. The drift region 31 is located closer to the second main surface 2 than the body region 32. The body region 32 is in contact with the drift region 31.
[0037] The source region 33 is located on the body region 32. The source region 33 is separated from the drift region 31 by the body region 32. The source region 33 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The source region 33 is located closer to the first main surface 1 than the body region 32. The body region 32 is located closer to the second main surface 2 than the source region 33. The source region 33 is in contact with the body region 32. The source region 33 constitutes the first main surface 1. The source region 33 is covered by the gate insulating film 43. The source region 33 is in direct contact with the gate insulating film 43.
[0038] The contact region 34 contains p-type impurities, such as aluminum, and has a p-type conductivity. The concentration of p-type impurities in the contact region 34 is higher than, for example, the concentration of p-type impurities in the body region 32. The contact region 34 penetrates the source region 33 and the body region 32. The contact region 34 is in contact with the body region 32. The contact region 34 constitutes the first main surface 1.
[0039] As shown in Figure 8, within the first region 101, a gate trench 5 is provided on the first principal surface 1, defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 33 and the body region 32 to the drift region 31. The bottom surface 4 is continuous with the side surface 3. The source region 33, the body region 32, and the drift region 31 are in contact with the side surface 3. The bottom surface 4 is located in the drift region 31. The bottom surface 4 is, for example, a plane parallel to the second principal surface 2. The angle θ1 of the side surface 3 with respect to the plane containing the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.
[0040] In a plan view, the gate trench 5 extends in the X1-X2 direction parallel to the first main surface 1. Also in a plan view, multiple gate trenches 5 are provided at regular intervals in the Y1-Y2 direction. Gate trenches 5 are not provided in the second region 102 and the third region 103.
[0041] The embedded region 35 contains p-type impurities such as aluminum and has a p-type conductivity. The embedded region 35 is located closer to the second main surface 2 than the contact region 34. The contact region 34 is located closer to the first main surface 1 than the embedded region 35. The embedded region 35 is in contact with the contact region 34. The embedded region 35 is formed at a depth greater than the gate trench 5. The upper end surface of the embedded region 35 is located closer to the second main surface 2 than the bottom surface 4 of the gate trench 5.
[0042] The embedded JTE region 36 is in contact with the embedded region 35 in a direction parallel to the first main surface 1. The embedded JTE region 36 is formed in an annular shape in plan view. The embedded JTE region 36 contains p-type impurities such as aluminum and has a p-type conductivity. The embedded JTE region 36 is separated from the first main surface 1 and the second main surface 2. The upper end surface of the embedded JTE region 36 is in contact with the lower end surface of the contact region 34.
[0043] The surface JTE region 37 is in contact with the contact region 34 in a direction parallel to the first main surface 1. The surface JTE region 37 is formed in an annular shape in plan view. The surface JTE region 37 contains p-type impurities such as aluminum and has a p-type conductivity. The surface JTE region 37 is located above the embedded JTE region 36. The surface JTE region 37 is separated from the embedded JTE region 36. The surface JTE region 37 is located closer to the first main surface 1 than the embedded JTE region 36. The embedded JTE region 36 is located closer to the second main surface 2 than the surface JTE region 37. The surface JTE region 37 constitutes the first main surface 1. A part of the drift region 31 is located between the surface JTE region 37 and the embedded JTE region 36. For example, the concentration of p-type impurities in the surface JTE region 37 is lower than the concentration of p-type impurities in the contact region 34. The surface JTE region 37 is an example of a third semiconductor region 113.
[0044] The gate insulating film 43 is, for example, an oxide film. The gate insulating film 43 is composed of a material containing, for example, silicon dioxide. The gate insulating film 43 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 43 is in contact with the drift region 31 at the bottom surface 4. The gate insulating film 43 is in contact with the source region 33, the body region 32, and the drift region 31 at the side surface 3. The gate insulating film 43 may also be in contact with the source region 33, the contact region 34, and the surface JTE region 37 at the first main surface 1.
[0045] The gate electrode 51 is provided on the gate insulating film 43. The gate electrode 51 is made of, for example, polysilicon (polySi) containing conductive impurities. A portion of the gate electrode 51 is located inside the gate trench 5. A portion of the gate electrode 51 is located above the first main surface 1.
[0046] The interlayer insulating film 44 is provided in contact with the gate electrode 51 and the gate insulating film 43. The interlayer insulating film 44 is, for example, an oxide film. The interlayer insulating film 44 is composed of a material containing, for example, silicon dioxide. The interlayer insulating film 44 electrically insulates the gate electrode 51 from the contact electrode 52 and the source pad 62.
[0047] A gate contact hole 70 is formed in the interlayer insulating film 44. The gate electrode 51 is exposed from the interlayer insulating film 44 through the contact hole 70.
[0048] The gate pad 61 is provided on the interlayer insulating film 44 and is in contact with the gate electrode 51 within the contact hole 70. The gate pad 61 is made of a material including, for example, aluminum.
[0049] A source contact hole 71 is formed in the interlayer insulating film 44 and the gate insulating film 43. The source region 33 and the contact region 34 within the first region 101 are exposed from the interlayer insulating film 44 and the gate insulating film 43 through the contact hole 71. The contact hole 71 is an example of a first contact hole.
[0050] Contact holes 72 are formed in the interlayer insulating film 44 and the gate insulating film 43. Through the contact holes 72, the contact region 34 within the third region 103 is exposed from the interlayer insulating film 44 and the gate insulating film 43. A portion of the source region 33 may also be exposed through the contact holes 72. In a cross-sectional view from a direction parallel to the first main surface 1, the dimension W2 in the short-side direction of the contact hole 72 is greater than the dimension W1 in the short-side direction of the contact hole 71. Dimension W1 is the dimension of the contact hole 71 in the Y1-Y2 direction, and dimension W2 is the dimension of the contact hole 72 in the Y1-Y2 direction. Contact hole 72 is an example of a second contact hole. Dimension W1 is an example of a first dimension, and dimension W2 is an example of a second dimension.
[0051] The contact electrode 52 is in contact with the source region 33 and the contact region 34 within the contact hole 71. The contact electrode 52 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 52 may also be made of a material containing titanium, aluminum, and silicon. The contact electrode 52 is ohmic-bonded to the source region 33 and the contact region 34.
[0052] The source pad 62 is provided on the interlayer insulating film 44 and is in contact with the contact electrode 52 within the contact hole 71. The source pad 62 is made of a material including, for example, aluminum. The source pad 62 may include a barrier metal film (not shown) covering the surface of the interlayer insulating film 44. As shown in Figure 1, the source pad 62 may include source pads 62A and 62B. For example, source pad 62A is located on the X2 side of the center of the silicon carbide substrate 10 in the X1-X2 direction, and source pad 62B is located on the X1 side of the center of the silicon carbide substrate 10 in the X1-X2 direction.
[0053] The gate pad 61 is located on the Y1 side of the source pad 62, and the planar shape of the gate pad 61 is rectangular. For example, the dimension of the gate pad 61 in the X1-X2 direction is larger than the dimension in the Y1-Y2 direction. The source pad 62 is located on the Y2 side of the gate pad 61, and the planar shape of the source pad 62 is rectangular. The distance from the first side 91 of the gate pad 61 and the distance from the second side 92 are approximately the same. The distance from the third side 93 of the gate pad 61 is smaller than the distance from the fourth side 94. The distance from the first side 91 of the source pad 62 and the distance from the second side 92 are approximately the same. The distance from the third side 93 of the source pad 62 is larger than the distance from the fourth side 94. The dimension of the gate pad 61 in the X1-X2 direction may be smaller than the dimension of the source pad 62 in the X1-X2 direction, and the dimension of the gate pad 61 in the Y1-Y2 direction may be smaller than the dimension of the source pad 62 in the Y1-Y2 direction. The source pad 62 is positioned so as to include a center line that divides the silicon carbide substrate 10 into two parts in the Y1-Y2 direction when viewed from above.
[0054] Gate runner 61A extends along the first side 91 in the Y1-Y2 direction. Gate runner 61B extends along the second side 92 in the Y1-Y2 direction. Gate runners 61C and 61D are connected to gate pad 61. Gate runners 61C and 61D extend along the third side 93 in the X1-X2 direction. Gate runner 61C is on the X2 side of gate pad 61, and gate runner 61D is on the X1 side of gate pad 61. The Y1 end of gate runner 61A is connected to the X2 end of gate runner 61C. The Y1 end of gate runner 61B is connected to the X1 end of gate runner 61D. Gate runner 61A is on the X2 side of source pad 62A, and gate runner 61B is on the X1 side of source pad 62B. Thus, the gate pad 61 is continuous with gate runners 61C and 61D, gate runner 61A is continuous with gate runner 61C, and gate runner 61B is continuous with gate runner 61D. Gate runners 61A and 61B are separated from the gate pad 61 in the X1-X2 direction. Gate runner 61E is connected to the gate pad 61 and extends in the Y1-Y2 direction between source pads 62A and 62B. Gate runners 61A, 61B, 61C, 61D, and 61E are made of the same material as the gate pad 61. Gate runner 61C is an example of a first gate runner, and gate runner 61D is an example of a second gate runner. Gate runner 61A is an example of a fourth gate runner, gate runner 61B is an example of a fifth gate runner, and gate runner 61E is an example of a sixth gate runner.
[0055] The source runner 62C is provided in a ring shape on the outside of the source pad 62 and gate runners 61A, 61B, 61C, and 61D in a plan view. The source runner 62C is connected to and continuous with the source pad 62. The source runner 62C is made of the same material as the source pad 62. Contact holes for the source runner 62C are formed in a ring shape in the interlayer insulating film 44 and the gate insulating film 43, and the source runner 62C is electrically connected to the contact region 34 through the ring contact holes. In a cross-sectional view from a direction parallel to the first main surface 1, the side surface 64 of the source runner 62C away from the gate pad 61 is preferably on the boundary line between the contact region 34 and the surface JTE region 37, or closer to the gate pad 61 than this boundary line. This is because it is easier to mitigate electric field concentration in the interlayer insulating film 44 below the source runner 62C.
[0056] The passivation film 80 covers the gate pad 61, the source pad 62, and the interlayer insulating film 44. The passivation film 80 is in contact with the gate pad 61, the source pad 62, and the interlayer insulating film 44. The passivation film 80 also covers the gate runners 61A, 61B, 61C, 61D, and 61E, and the source runner 62C. The passivation film 80 is also in contact with the gate runners 61A, 61B, 61C, 61D, and 61E, and the source runner 62C. The passivation film 80 is made of a material including, for example, silicon nitride or polyimide. The passivation film 80 has an opening 81 that exposes a part of the upper surface of the gate pad 61, and an opening 82 that exposes a part of the upper surface of the source pad 62.
[0057] The drain electrode 53 is in contact with the second main surface 2. The drain electrode 53 is in contact with the silicon carbide single crystal substrate 20 on the second main surface 2. The drain electrode 53 is electrically connected to the drift region 31. The drain electrode 53 is made of a material containing, for example, nickel silicide. The drain electrode 53 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 53 is ohmic bonded to the silicon carbide single crystal substrate 20. A buffer layer containing, for example, n-type impurities such as nitrogen and having an n-type conductivity may be provided between the silicon carbide single crystal substrate 20 and the drift region 31.
[0058] The second region 102 is located on the Z2 side of the gate pad 61. The third region 103 is connected to the second region 102. The third region 103 has a fourth region 104 and a seventh region 107. The fourth region 104 is located on the Z2 side of the gate runner 61C, the Z2 side of the gate runner 61D, and, in plan view, on the Y1 side of the gate pad 61, gate runner 61C, and gate runner 61D. The seventh region 107 is located on the Y2 side of the gate pad 61 in plan view. The first region 101 is located on the Y2 side of the seventh region 107 and, in plan view, on the Y2 side of the gate runners 61C and 61D. The first region 101 is provided in the X1-X2 direction, from the vicinity of gate runner 61A to the vicinity of gate runner 61B.
[0059] As described above, the gate trench 5 is provided in the first region 101, but not in the second region 102 and the third region 103. Similarly, the source region 33 is provided in the first region 101, but not in the second region 102 and the third region 103. Therefore, in the second region 102 and the third region 103, the first main surface 1 is composed of contact regions 34. The contact regions 34 in the first region 101, the contact regions 34 in the second region 102, and the contact regions 34 in the third region 103 are connected to each other on the first main surface 1. In this embodiment, the source region 33 is provided between adjacent gate trenches 5 in the Y1-Y2 direction. Each unit cell 40 includes a pair of gate trenches 5 and gate electrodes 51, and multiple unit cells 40 are arranged in the first region 101 at a constant pitch P1 in the Y1-Y2 direction. A contact region 34 within the second region 102 is an example of the first semiconductor region 111, and a contact region 34 within the third region 103 is an example of the second semiconductor region 112. A contact region 34 within the fourth region 104 is an example of the fourth semiconductor region 114, and a contact region 34 within the seventh region 107 is an example of the seventh semiconductor region 117.
[0060] On the Z1 side of the first region 101, the source contact holes 71 formed in the interlayer insulating film 44 are arranged in the Y1-Y2 direction at a constant pitch P2 equal to the pitch P1.
[0061] On the Z1 side of the second region 102, a gate contact hole 70 is formed in the interlayer insulating film 44, but contact holes 71 and 72 are not formed. The gate contact hole 70 is also formed in the portion of the interlayer insulating film 44 between the gate runners 61A, 61B, 61C, 61D, and 61E and the gate electrode 51.
[0062] On the Z1 side of the third region 103, the contact hole 72 includes a contact hole 73 that reaches the contact region 34 in the fourth region 104, and a contact hole 77 that reaches the contact region 34 in the seventh region 107. In a cross-sectional view from a direction parallel to the first main surface 1, the dimension W3 in the short direction of the contact hole 73 and the dimension W7 in the short direction of the contact hole 77 are greater than the dimension W1 in the short direction of the contact hole 71. Dimension W3 is the dimension of the contact hole 73 in the Y1-Y2 direction, and dimension W7 is the dimension of the contact hole 77 in the Y1-Y2 direction. Dimensions W3 and W7 may be equal. Contact hole 73 is an example of a third contact hole, and contact hole 77 is an example of a seventh contact hole. Dimension W3 is an example of a third dimension, and dimension W7 is an example of a fourth dimension. Contact hole 73 is part of the contact hole for the source runner 62C.
[0063] Within contact holes 73 and 77, the contact electrode 52 is in contact with the contact region 34. The contact electrode 52 is in ohmic contact with the contact region 34. The source pad 62 is also in contact with the contact electrode 52 within contact hole 77. The source runner 62C is in contact with the contact electrode 52 within contact hole 73.
[0064] In the first embodiment, a third region 103 is provided that is connected to the second region 102, and the contact region 34 is connected in both the second region 102 and the third region 103. Furthermore, in a cross-sectional view from a direction parallel to the first main surface 1, the dimension W2 in the short direction of the contact hole 72 is larger than the dimension W1 in the short direction of the contact hole 71. This reduces the contact resistance between the source pad 62 and the contact region 34, and even if a surge occurs, it is possible to mitigate the electric field concentration on the interlayer insulating film 44 in the second region 102.
[0065] Furthermore, because the contact region 34 is in contact with the surface JTE region 37, even when a large voltage is applied between the drain electrode 53 and the source runner 62C, the electric field concentration on the interlayer insulating film 44 below the source runner 62C can be mitigated.
[0066] Furthermore, in this embodiment, the third region 103 includes the fourth region 104 and the seventh region 107. The third region 103 may include only one of the fourth region 104 or the seventh region 107, but including both the fourth region 104 and the seventh region 107 further reduces the contact resistance between the source pad 62 and the contact region 34. Also, when the short-side dimension W3 of the contact hole 73 and the short-side dimension W7 of the contact hole 77 are equal, the current generated in the contact region 34 within the second region 102 tends to flow evenly towards the contact holes 73 and 77.
[0067] Furthermore, since gate runners 61A, 61B, and 61E extending in the Y1-Y2 direction are provided, it is easy to apply the gate voltage evenly to each unit cell 40 from the gate runners 61A, 61B, and 61E.
[0068] Furthermore, since the contact region 34 in the first region 101 and the contact region 34 in the third region 103 are connected to each other, it is easy to control them to the same potential.
[0069] Furthermore, it is preferable that the dimension L1 of the contact hole 73 in the X1-X2 direction is larger than the dimension L2 of the gate pad 61 in the X1-X2 direction. This is because it is easier to reduce the contact resistance in the fourth region 104. Dimension L1 is an example of a fifth dimension, and dimension L2 is an example of a sixth dimension.
[0070] Furthermore, it is preferable that the dimension L3 of the contact hole 77 in the X1-X2 direction in the portion between gate runner 61A and gate runner 61E in a plan view is at least half the distance between gate runner 61A and gate runner 61E. In this case, the dimension of the unit cell 40 positioned on the extension of the contact hole 77 in the portion between gate runner 61A and gate runner 61E in the X1-X2 direction will be less than or equal to half the distance between gate runner 61A and gate runner 61E. Therefore, it is easier to apply a gate voltage to this unit cell 40 in the same way as to other unit cells 40. Dimension L3 is an example of the seventh dimension.
[0071] Similarly, the dimension L4 in the X1-X2 direction of the portion of the contact hole 77 between gate runner 61B and gate runner 61E in a plan view is preferably at least half the distance between gate runner 61B and gate runner 61E. In this case, the dimension in the X1-X2 direction of the unit cell 40 positioned on the extension of the contact hole 77 in the portion between gate runner 61B and gate runner 61E is less than or equal to half the distance between gate runner 61B and gate runner 61E. Therefore, it is easier to apply a gate voltage to this unit cell 40 in the same way as to other unit cells 40. Dimension L4 is an example of the eighth dimension.
[0072] (Second Embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in that it has a field insulating film. Figure 9 is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment. Figure 9, like Figure 7, corresponds to a cross-sectional view along line VII-VII in Figures 1 and 2. In Figure 9, the passivation film is omitted.
[0073] As shown in Figure 9, the MOSFET 202 according to the second embodiment has a field insulating film 45. The field insulating film 45 is provided on the second region 102, the fourth region 104, and the termination region 42. In a plan view, the field insulating film 45 has a contact hole 74 that reaches the contact region 34 in the fourth region 104, on the Y1 side of the gate pad 61, gate runners 61C and 61D. The interlayer insulating film 44 is provided on the field insulating film 45 above the second region 102, the fourth region 104, and the termination region 42. The interlayer insulating film 44 is also provided inside the contact hole 74. Inside the contact hole 74, there is a gate insulating film 43 between the interlayer insulating film 44 and the contact region 34. The contact hole 73 is smaller than the contact hole 74 and is located inside the contact hole 74. Above the second region 102, a gate electrode 51 is provided on the field insulating film 45. The contact hole 74 is an example of a fourth contact hole.
[0074] The other configurations are the same as in the first embodiment.
[0075] According to the second embodiment, since a field insulating film 45 is provided, electric field concentration in the interlayer insulating film 44 can be further mitigated.
[0076] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the arrangement of the gate pads 61. Figure 10 is a top view showing the silicon carbide semiconductor device according to the third embodiment. Figure 11 is a diagram showing each region within the silicon carbide substrate in the silicon carbide semiconductor device according to the third embodiment. Figures 12 and 13 are cross-sectional views showing the silicon carbide semiconductor device according to the third embodiment. Figure 12 corresponds to a cross-sectional view along line XII-XII in Figures 10 and 11. Figure 13 corresponds to a cross-sectional view along line XIII-XIII in Figures 10 and 11. In Figures 12 and 13, the passivation film is omitted.
[0077] As shown in Figures 10 to 13, in the MOSFET 203 of the third embodiment, the gate pad 61 is in contact with the gate runners 61C and 61D, but the gate pad 61 is positioned on the Y2 side of the gate runners 61C and 61D. Therefore, there is no gate pad 61 between the gate runner 61C and the gate runner 61D. The gate runners 61C and 61D are separated from each other.
[0078] The fourth region 104 includes a fifth region 105 located between gate runner 61C and gate runner 61D in a plan view. The fifth region 105 is connected to the second region 102 on the first main surface 1. In other words, the contact region 34 within the fourth region 104 includes the contact region 34 between gate runner 61C and gate runner 61D in a plan view. The contact region 34 between gate runner 61C and gate runner 61D in a plan view is connected to the contact region 34 within the second region 102 on the first main surface 1. The contact region 34 within the fifth region 105 is an example of the fifth semiconductor region 115.
[0079] The contact hole 72 includes a contact hole 75 that reaches the contact area 34 between gate runners 61C and 61D in a plan view. In a plan view, the contact hole 75 is located on the Y1 side of the gate pad 61 and between gate runners 61C and 61D. In a cross-sectional view from a direction parallel to the first main surface 1, the dimension W5 in the short direction of the contact hole 75 is greater than the dimension W1 in the short direction of the contact hole 71. The contact hole 75 may be a part of the contact hole 73. Dimension W5 may be greater than the dimension W3 of the other part of the contact hole 73. The contact hole 75 is an example of a fifth contact hole.
[0080] Within the contact hole 75, the contact electrode 52 is in contact with the contact region 34. The contact electrode 52 is in ohmic contact with the contact region 34. The source pad 62 is also in contact with the contact electrode 52 within the contact hole 75.
[0081] The other configurations are the same as in the first embodiment.
[0082] The same effects as the first embodiment can be obtained with the third embodiment. Furthermore, the contact resistance between the source runner 62C connected to the source pad 62 and the contact region 34 in the fourth region 104 can be further reduced in the vicinity of the gate pad 61.
[0083] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in the arrangement of the gate pads 61. Figure 14 is a top view showing the silicon carbide semiconductor device according to the fourth embodiment. Figure 15 is a diagram showing the various regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the fourth embodiment. Figure 16 is a cross-sectional view showing the silicon carbide semiconductor device according to the fourth embodiment. Figure 16 corresponds to a cross-sectional view along the line XVI-XVI in Figures 14 and 15. In Figure 16, the passivation film is omitted.
[0084] As shown in Figures 14 to 16, the MOSFET 204 according to the fourth embodiment has a gate runner 61F instead of gate runners 61C and 61D. The gate runner 61F extends in the X1-X2 direction along the third side 93. The Y1 side end of gate runner 61A is connected to the X2 side end of gate runner 61F. The Y1 side end of gate runner 61B is connected to the X1 side end of gate runner 61F. The gate pad 61 is separated from the gate runner 61F in the Y1-Y2 direction. The MOSFET 204 further has a gate runner 61G. The gate runner 61G extends in the Y1-Y2 direction and connects the gate runner 61F and the gate pad 61. The gate runners 61F and 61G are made of the same material as the gate pad 61. The gate runner 61F is an example of a third gate runner.
[0085] The fourth region 104 includes a sixth region 106 located between the gate pad 61 and the gate runner 61F in a plan view. The sixth region 106 is connected to the second region 102 on the first main surface 1. In other words, the contact region 34 within the fourth region 104 includes the portion between the gate pad 61 and the gate runner 61F in a plan view. The contact region 34 between the gate pad 61 and the gate runner 61F in a plan view is connected to the contact region 34 within the second region 102 on the first main surface 1. The contact region 34 within the sixth region 106 is an example of the sixth semiconductor region 116.
[0086] The contact hole 72 includes a contact hole 76 that reaches the contact area 34 between the gate pad 61 and the gate runner 61F in a plan view. In a plan view, the contact hole 76 is located on the Y1 side of the gate pad 61 and on the Y2 side of the gate runner 61F. In a cross-sectional view from a direction parallel to the first main surface 1, the dimension W6 in the short direction of the contact hole 76 is greater than the dimension W1 in the short direction of the contact hole 71. The contact hole 76 is an example of a sixth contact hole.
[0087] Within the contact hole 76, the contact electrode 52 is in contact with the contact region 34. The contact electrode 52 is in ohmic contact with the contact region 34. The source pad 62 is also in contact with the contact electrode 52 within the contact hole 76.
[0088] The other configurations are the same as in the first embodiment.
[0089] The same effects as the first embodiment can be obtained with the fourth embodiment. Furthermore, the fourth embodiment allows for greater flexibility in the placement of the gate pads 61.
[0090] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment differs from the fourth embodiment mainly in the arrangement of the gate pads 61. Figure 17 is a top view showing the silicon carbide semiconductor device according to the fifth embodiment. Figure 18 is a diagram showing each region within the silicon carbide substrate in the silicon carbide semiconductor device according to the fifth embodiment.
[0091] As shown in Figures 17 and 18, the MOSFET 205 according to the fifth embodiment does not have a gate runner 61G, and the gate runner 61E is connected to the gate runner 61F. Also, the gate pad 61 is provided on the X2 side of the gate runner 61E, but not on the X1 side. Similar to the fourth embodiment, the contact hole 72 includes a contact hole 76 that reaches the contact region 34 between the gate pad 61 and the gate runner 61F in a plan view (see Figure 16).
[0092] The other configurations are the same as in the fourth embodiment.
[0093] The same effects as those of the fourth embodiment can be obtained with the fifth embodiment.
[0094] (Sixth Embodiment) Next, a sixth embodiment will be described. The sixth embodiment differs from the fifth embodiment mainly in the arrangement of the gate pads 61. Figure 19 is a top view showing the silicon carbide semiconductor device according to the sixth embodiment. Figure 20 is a diagram showing the various regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the sixth embodiment.
[0095] As shown in Figures 19 and 20, in the MOSFET 206 according to the sixth embodiment, the gate pad 61 is in contact with the gate runner 61A, not the gate runner 61E. Similar to the fourth embodiment, the contact hole 72 includes a contact hole 76 that reaches the contact region 34 between the gate pad 61 and the gate runner 61F in a plan view (see Figure 16).
[0096] The other configurations are the same as in the fifth embodiment.
[0097] The same effects as those of the fifth embodiment can be obtained with the sixth embodiment.
[0098] (Seventh Embodiment) Next, the seventh embodiment will be described. The seventh embodiment differs from the sixth embodiment mainly in the arrangement of the gate pads 61. Figure 21 is a top view showing the silicon carbide semiconductor device according to the seventh embodiment. Figure 22 is a diagram showing each region within the silicon carbide substrate in the silicon carbide semiconductor device according to the seventh embodiment.
[0099] As shown in Figures 21 and 22, in the MOSFET 207 according to the seventh embodiment, the gate pad 61 is in contact with the gate runners 61E and 61A. The gate pad 61 is located on the Y2 side of the gate runner 61F. Therefore, the gate pad 61 is not present on the X2 side of the gate runner 61F. On the X2 side of the gate runner 61F, the dimension of the contact hole 73 in the short direction is larger than the dimension of the short direction in other parts. Note that the contact hole 72 does not necessarily include the contact hole 76.
[0100] The other configurations are the same as in the sixth embodiment.
[0101] The same effects as those of the sixth embodiment can be obtained with the seventh embodiment.
[0102] (Eighth embodiment) Next, the eighth embodiment will be described. The eighth embodiment differs from the first embodiment mainly in the configuration of the contact region 34 on the Y2 side of the second region 102. Figure 23 is a top view showing the silicon carbide semiconductor device according to the eighth embodiment. Figure 24 is a top view showing the configuration of the first main surface of the silicon carbide substrate in region 223 in Figure 23. Figures 25 to 27 are cross-sectional views showing the silicon carbide semiconductor device according to the eighth embodiment. Figure 25 corresponds to a cross-sectional view along the line XXV-XXV in Figure 24. Figure 26 corresponds to a cross-sectional view along the line XXVI-XXVI in Figure 24. Figure 27 corresponds to a cross-sectional view along the line XXVII-XXVII in Figure 24. In Figures 25 to 27, the passivation film is omitted.
[0103] As shown in Figures 23 to 27, in the MOSFET 208 according to the eighth embodiment, among the multiple unit cells 40 located closer to the fourth side 94 than the seventh region 107, some unit cells 40 located closer to the third side 93 are further from the gate runner 61E in the X1-X2 direction than the remaining unit cells 40. For example, at a position closer to the fourth side 94 than the seventh region 107 (Y2 side), among the multiple gate trenches 5 arranged in the Y1-Y2 direction, the first trench group 5A of some gate trenches 5 located on the Y1 side is further from the gate runner 61E in a plan view than the second trench group 5B of other gate trenches 5 located on the Y2 side than the first trench group 5A. In a plan view, the dimension of the contact region 34 between the first trench group 5A and the gate runner 61E in the X1-X2 direction is larger than the dimension of the contact region 34 between the second trench group 5B and the gate runner 61E in the X1-X2 direction.
[0104] The other configurations are the same as in the first embodiment.
[0105] The same effects as the first embodiment can be obtained with the eighth embodiment. Furthermore, according to the eighth embodiment, electric field concentration in the interlayer insulating film 44 near the gate runner 61E of the first trench group 5A can be mitigated.
[0106] (Variation of the first domain) Here, a modified example of the first region will be described. In this modified example, the configuration of the unit cell differs from that of the first embodiment. Figure 28 is a top view showing the modified example of the first region. Figure 28 shows the configuration of the first main surface of the silicon carbide substrate, similar to Figure 4.
[0107] In this modified example, in the first region 101, multiple gate trenches 5 are formed between two adjacent gate runners in the X1-X2 direction. In addition, in the first region 101, the contact region 34 is provided between adjacent gate trenches 5 in the X1-X2 direction and extends in the Y1-Y2 direction.
[0108] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of symbols]
[0109] 1. First main surface 2. Second main surface 3 Sides 4. Bottom 5 Gate Trench 5A Trench Group 1 5B Second Trench Group 10 Silicon carbide substrate 20 Silicon carbide single crystal substrate 30 Silicon carbide epitaxial layer 31 Drift Region 32 Body Region 33 Source Area 34 Contact area 35. Recessed area 36 Embedded JTE area 37. Surface JTE region (third semiconductor region) 40 unit cells 41 Active area 42 Termination area 43 Gate insulating film 44 Interlayer insulating film 45 Field Insulating Film 51 Guard Station 52 Contact electrodes 53 Drain electrode 61 Gate Pad 61A, 61B, 61C, 61D, 61E, 61F, 61G Gate Runner 62, 62A, 62B Source Pad 62C Source Runner - 6 4 Sides 70, 71, 72, 73, 74, 75, 76, 77 Contact holes 80 Passivation membrane 81, 82 Opening 91 First side 92 Second side 93 Third side 94 Fourth side 101 First area 102 Second area 103 Third area 104 4th area 105 5th area 106 Area 6 107 Area 7 111 First Semiconductor Area 112 Semiconductor Area 2 113 Third Semiconductor Area 114 Fourth Semiconductor Area 115. Semiconductor Domain #5 116. Semiconductor Area 6 117. Semiconductor Area 7 201, 202, 203, 204, 205, 206, 207, 208 MOSFET 221, 222, 223 areas
Claims
1. A silicon carbide substrate having a first main surface, An interlayer insulating film covering the first main surface, A gate pad and a source pad are provided on the interlayer insulating film, It has, The silicon carbide substrate, when viewed in a plan view from a direction perpendicular to the first main surface, A first region containing multiple unit cells, A second region overlapping with the aforementioned gate pad, A third region adjacent to the second region, It has, Each of the aforementioned plurality of unit cells is A drift region having a first conductivity type, A body region having a second conductivity type different from the first conductivity type, A source region having a first conductivity type is provided on the first main surface, separated from the drift region by the body region, A contact region provided on the first main surface, electrically connected to the body region, and having the second conductivity type, A gate electrode electrically connected to the gate pad, A gate insulating film is provided between the drift region, the body region, the source region and the gate electrode, It has, The second region has a first semiconductor region having the second conductivity type, The third region has a second semiconductor region having the second conductivity type, The first semiconductor region and the second semiconductor region are connected to each other in the first main surface. The interlayer insulating film, A first contact hole reaching the source region and the contact region, A second contact hole reaching the second semiconductor region, Formed, The aforementioned source pad is The source region and the contact region are electrically connected via the first contact hole, The second semiconductor region is electrically connected via the second contact hole, In a cross-sectional view taken from a direction parallel to the first main surface, the second dimension of the second contact hole in the short-side direction is greater than the first dimension of the first contact hole in the short-side direction. The active region comprising the plurality of unit cells, A terminal region provided around the active region, It has, The termination region has a third semiconductor region having the second conductivity type, The second semiconductor region is provided between the gate pad and the termination region in a plan view from a direction perpendicular to the first main surface, and includes a fourth semiconductor region that is continuous with the first semiconductor region and the third semiconductor region on the first main surface. The concentration of the second conductivity type impurity in the third semiconductor region is lower than the concentration of the second conductivity type impurity in the fourth semiconductor region. The silicon carbide semiconductor device includes a third contact hole that reaches the fourth semiconductor region, wherein the second contact hole includes the third contact hole.
2. The silicon carbide semiconductor device according to claim 1, wherein the contact region and the second semiconductor region are connected to each other on the first main surface.
3. The field insulating film is provided between the first semiconductor region, the fourth semiconductor region, and the third semiconductor region and the interlayer insulating film, A fourth contact hole reaching the fourth semiconductor region is formed in the field insulating film. Inside the fourth contact hole, the interlayer insulating film is in contact with the fourth semiconductor region. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the third contact hole is located inside the fourth contact hole.
4. The source runner is electrically connected to the source pad and electrically connected to the fourth semiconductor region via the third contact hole, The silicon carbide semiconductor device according to claim 1 or 2, wherein, in a cross-sectional view from a direction parallel to the first main surface, the side of the source runner away from the gate pad is located on the boundary line between the third semiconductor region and the fourth semiconductor region, or closer to the gate pad than the boundary line.
5. A first gate runner is electrically connected to the gate pad, extends in a first direction parallel to the first main surface, and is positioned closer to the end region than the gate pad, A second gate runner is electrically connected to the gate pad, extends in the first direction, is separated from the first gate runner, and is positioned closer to the end region than the gate pad, It has, The fourth semiconductor region is provided between the first gate runner and the second gate runner in a plan view from a direction perpendicular to the first main surface, and includes a fifth semiconductor region that is connected to the first semiconductor region on the first main surface. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the second contact hole includes a fifth contact hole that reaches the fifth semiconductor region.
6. It has a third gate runner that is electrically connected to the gate pad, extends in a first direction parallel to the first main surface, and is positioned closer to the end region than the gate pad, The fourth semiconductor region is provided between the gate pad and the third gate runner in a plan view from a direction perpendicular to the first main surface, and includes a sixth semiconductor region that is connected to the first semiconductor region on the first main surface. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the second contact hole includes a sixth contact hole that reaches the sixth semiconductor region.
7. The plurality of unit cells extend in a first direction parallel to the first main surface and are arranged in a second direction perpendicular to the first direction. The gate pad has a rectangular planar shape with the first direction as its longitudinal direction when viewed from a direction perpendicular to the first main surface. The second semiconductor region includes a seventh semiconductor region located in the second direction, with the gate pad sandwiched between it and the fourth semiconductor region. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the second contact hole includes a seventh contact hole that reaches a seventh semiconductor region.
8. The silicon carbide semiconductor device according to claim 7, wherein, in a cross-sectional view from a direction parallel to the first main surface, the third dimension of the third contact hole in the short-side direction is equal to the fourth dimension of the seventh contact hole in the short-side direction.
9. The silicon carbide semiconductor device according to claim 7, wherein the fifth dimension of the third contact hole in the first direction is greater than the sixth dimension of the gate pad in the first direction.
10. In the plan view, the silicon carbide substrate has a rectangular shape with a first and second side that are parallel to each other, and a third and fourth side that are perpendicular to the first and second sides. A fourth gate runner extending along the first side, A fifth gate runner extending along the second side, Between the fourth gate runner and the fifth gate runner, a sixth gate runner extends from the gate pad toward the fourth side, It has, The silicon carbide semiconductor device according to claim 7, wherein the fourth gate runner, the fifth gate runner, and the sixth gate runner are electrically connected to the gate pad.
11. The seventh dimension of the seventh contact hole in the first direction in a plan view between the fourth gate runner and the sixth gate runner is: The silicon carbide semiconductor device according to claim 10, wherein the distance between the fourth gate runner and the sixth gate runner is 1 / 2 or more.
12. The eighth dimension in the first direction of the portion of the seventh contact hole between the fifth gate runner and the sixth gate runner in a plan view is: The silicon carbide semiconductor device according to claim 10, wherein the distance between the fifth gate runner and the sixth gate runner is 1 / 2 or more.
13. The silicon carbide semiconductor device according to claim 10, wherein, among a plurality of unit cells located closer to the fourth edge than the seventh semiconductor region, some unit cells located closer to the third edge are further away from the sixth gate runner in the second direction than the remaining unit cells.