Semiconductor integrated circuit equipment
By providing power supply terminals on the top of the first semiconductor chip through vias and embedded wiring, the design complexity and cost issues of semiconductor integrated circuits are addressed, achieving stable power supply and improved manufacturing efficiency.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SOCIONEXT INC
- Filing Date
- 2022-03-03
- Publication Date
- 2026-07-30
AI Technical Summary
The design of semiconductor integrated circuit devices is complicated and costly when external terminals for hard macros are required on both the top and bottom of semiconductor chips, due to the need for power supply voltage distribution.
A semiconductor integrated circuit device with a first semiconductor chip and a second semiconductor chip, where the back surfaces face each other, and includes terminals on the upper part of the first chip connected via vias and embedded power supply wiring to supply power voltages, allowing external terminals to be provided only on the top.
This configuration simplifies the design, reduces costs, and stabilizes power supply by suppressing voltage drops and noise, enhancing manufacturing flexibility and yield.
Smart Images
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Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor integrated circuit device including stacked semiconductor chips.
Background Art
[0002] Due to the higher integration and lower voltage resulting from the miniaturization of semiconductor integrated circuits, more attention needs to be paid to the design against power supply voltage drop (IR-Drop) and power supply noise. Therefore, the design of a power delivery network (PDN) that supplies a power supply voltage to a semiconductor integrated circuit becomes important.
[0003] In addition, semiconductor integrated circuits widely provide an internal power switch to reduce power consumption by turning on / off the power switch according to the operation of the system in order to reduce power consumption.
[0004] In Patent Document 1, a semiconductor device is disclosed in which a power switch is provided in a first semiconductor chip among stacked semiconductor chips, and a power supply potential (power supply voltage) is supplied from a second semiconductor chip bonded to the back surface of the first semiconductor chip and configured with power supply wiring to the power switch.
Prior Art Documents
Patent Documents
[0005]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0006] In Patent Document 1, a power supply voltage is supplied from a pad as an external terminal provided at the lower part of the second semiconductor chip. This power supply voltage is supplied to the power switch of the first semiconductor chip via the power supply wiring of the second semiconductor chip.
[0007] Generally, when designing large-scale semiconductor integrated circuit devices, many circuits grouped together as specific functional units, called IP cores (Intellectual Property cores), are used. Among these, IP cores called hard macros include their layout structure in the provided data, and these cannot be modified. In this case, if it is specified that the pads serving as external terminals for the hard macro are provided on the top of the first semiconductor chip, then in a structure like that shown in Patent Document 1, in order to supply power voltage, external terminals must be provided not only on the bottom of the second semiconductor chip but also on the top of the first semiconductor chip. This makes the design of the semiconductor integrated circuit device difficult and also increases costs.
[0008] This disclosure aims to provide a semiconductor integrated circuit device that can accommodate cases where external terminals are provided on the upper part of the first semiconductor chip. [Means for solving the problem]
[0009] In a first aspect of this disclosure, a semiconductor integrated circuit device is provided, comprising a first semiconductor chip and a second semiconductor chip, wherein the back surface of the first semiconductor chip and the main surface of the second semiconductor chip are arranged opposite each other. The first semiconductor chip includes a first terminal formed on the upper part of its main surface and connected to a first power supply that supplies a first power supply voltage, a second terminal formed on the upper part of its main surface and connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a power switch circuit provided between the first power supply and a third power supply that supplies a third power supply voltage different from the first and second power supply voltages, for controlling the connection and disconnection between the first and third power supplies, a first embedded power supply wiring formed in an embedded power supply wiring layer and connected to the first power supply, a second embedded power supply wiring formed in the embedded power supply wiring layer and connected to the second power supply, and a first via connected to the first terminal and provided to penetrate from the main surface to the back surface. The second semiconductor chip includes a first wiring connected to the first embedded power supply wiring and the first via.
[0010] According to this disclosure, a first terminal is formed on the upper part of the main surface of the first semiconductor chip, which is connected to a first power supply that supplies a first power supply voltage. The first terminal is connected to a power switch circuit via a first via that penetrates the first semiconductor chip from the main surface to the back surface, a first wiring of the second semiconductor chip, and a first embedded power supply wiring of the first semiconductor chip. As a result, the first power supply voltage can be supplied to the power switch circuit from the first terminal formed on the upper part of the main surface of the first semiconductor chip, and this can accommodate even if it is specified that an external terminal is provided on the upper part of the first semiconductor chip.
[0011] A second aspect of this disclosure relates to a semiconductor integrated circuit device including a first semiconductor chip and a second semiconductor chip, wherein the back surface of the first semiconductor chip and the main surface of the second semiconductor chip are arranged facing each other. The first semiconductor chip includes a first terminal provided on the upper part of its main surface and connected to a first power supply that supplies a first power supply voltage, a second terminal provided on the upper part of its main surface and connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a power switch circuit provided between the first power supply and a third power supply that supplies a third voltage different from the first and second voltages, for controlling the connection and disconnection between the first and third power supplies, a first embedded power supply wiring formed in an embedded power supply wiring layer and connected to the first power supply, a second embedded power supply wiring formed in the embedded power supply wiring layer and connected to the second power supply, and a first wiring formed in a first wiring layer above the embedded power supply wiring layer and connected to the first terminal and the first embedded power supply wiring. The second semiconductor chip includes a second wiring connected to the first embedded power supply wiring.
[0012] According to this disclosure, a first terminal is formed on the upper part of the main surface of the first semiconductor chip, and is connected to a first power supply that supplies a first power supply voltage. The first terminal is connected to a power switch circuit via the first wiring of the first wiring layer and the first embedded power supply wiring of the embedded power supply wiring layer in the first semiconductor chip. As a result, the first power supply voltage can be supplied to the power switch circuit from the first terminal formed on the upper part of the main surface of the first semiconductor chip, and this can accommodate even if it is specified that an external terminal is provided on the upper part of the first semiconductor chip.
[0013] A third aspect of this disclosure provides a semiconductor integrated circuit device including a first semiconductor chip and a second semiconductor chip, wherein the back surface of the first semiconductor chip and the main surface of the second semiconductor chip are arranged facing each other. The first semiconductor chip includes a first terminal located on the upper part of its main surface and connected to a first power supply that supplies a first power supply voltage, a second terminal located on the upper part of its main surface and connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a power switch circuit located between the first power supply and a third power supply that supplies a third voltage different from the first and second voltages, which controls the connection and disconnection between the first and third power supplies, a first embedded power supply wiring formed in an embedded power supply wiring layer and connected to the first power supply, a second embedded power supply wiring formed in the embedded power supply wiring layer and connected to the second power supply, a third embedded power supply wiring formed in the embedded power supply wiring layer and connected to the third power supply, a first wiring formed in a first wiring layer above the embedded power supply wiring layer and connected to the first terminal and the first embedded power supply wiring, and a first via exposed on the back surface and connected to the third embedded power supply wiring. The second semiconductor chip includes a second wiring connected to the first via.
[0014] According to this disclosure, a first terminal is formed on the upper part of the main surface of the first semiconductor chip, and is connected to a first power supply that supplies a first power supply voltage. The first terminal is connected to a power switch circuit via the first wiring of the first wiring layer and the first embedded power supply wiring of the embedded power supply wiring layer in the first semiconductor chip. As a result, the first power supply voltage can be supplied to the power switch circuit from the first terminal formed on the upper part of the main surface of the first semiconductor chip, and this can accommodate even if it is specified that an external terminal is provided on the upper part of the first semiconductor chip. [Effects of the Invention]
[0015] According to this disclosure, it is also possible to address cases where external terminals are provided on the top of the first semiconductor chip. [Brief explanation of the drawing]
[0016] [Figure 1] A cross-sectional view showing an overview of a semiconductor integrated circuit device according to the first embodiment. [Figure 2] A plan view showing an example of the layout structure of the first semiconductor chip according to the first embodiment. [Figure 3] A circuit diagram showing the configuration of a power switch circuit included in the first semiconductor chip according to the first embodiment. [Figure 4] A circuit diagram showing the configuration of the buffer in the power switch control circuit according to the first embodiment. [Figure 5] A plan view showing an example of the layout structure of a standard cell area according to the first embodiment. [Figure 6A] A cross-sectional view showing an example of the layout structure of a standard cell area according to the first embodiment. [Figure 6B] A cross-sectional view showing an example of the layout structure of a standard cell area according to the first embodiment. [Figure 7] A plan view showing another example of the layout structure of a standard cell area according to the first embodiment. [Figure 8] A cross-sectional view showing another example of the layout structure of a standard cell area according to the first embodiment. [Figure 9] A plan view showing another example of the layout structure of the standard cell region according to the first embodiment. [Figure 10] A cross-sectional view showing another example of the layout structure of the standard cell region according to the first embodiment. [Figure 11] A plan view showing an example of the layout structure of the standard cell region of the first semiconductor chip according to the second embodiment. [Figure 12] A plan view showing an example of the layout structure of the standard cell region of the second semiconductor chip according to the second embodiment. [Figure 13A] A cross-sectional view showing an example of the layout structure of the standard cell region according to the second embodiment. [Figure 13B] A cross-sectional view showing an example of the layout structure of the standard cell region according to the second embodiment. [Figure 14] A plan view showing another example of the layout structure of the standard cell region according to the second embodiment. [Figure 15] A plan view showing another example of the layout structure of the standard cell region according to the second embodiment.
BEST MODE FOR CARRYING OUT THE INVENTION
[0017] Hereinafter, embodiments will be described with reference to the drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant descriptions may be omitted. In the following description, two directions parallel to the surface of the substrate and perpendicular to each other are defined as the X direction (first direction) and the Y direction (second direction), and the direction perpendicular to the surface of the substrate is defined as the Z direction. Also, the coincidence of the arrangements in the present disclosure does not strictly exclude those that become inconsistent due to manufacturing variations, and even when there is a deviation in the arrangement due to manufacturing variations, the arrangements can be regarded as coincident.
[0018] (First Embodiment) FIG. 1 shows a cross-sectional view of a semiconductor integrated circuit device according to the first embodiment.
[0019] As shown in Figure 1, the semiconductor integrated circuit device according to the first embodiment includes a first semiconductor chip 10 and a second semiconductor chip 20.
[0020] The first semiconductor chip 10 includes a substrate 11 and a wiring layer 12.
[0021] The substrate 11 is, for example, a silicon substrate, and semiconductor elements such as transistors are formed on the surface side of the substrate 11. The transistor is, for example, a FinFET that includes fins 13 on the source, drain, and channel.
[0022] The wiring layer 12 includes wiring 14 and an insulating layer 15 formed on the surface of the substrate 11. A portion of the wiring 14 is connected to the fins 13. In addition, embedded power wiring 16 connected to the wiring 14 is formed on the surface side of the substrate 11. The embedded power wiring 16 is an embedded power rail (BPR) of the embedded power wiring layer, which is formed by embedding at least a portion of it in the substrate 11.
[0023] The substrate 11 is provided with vias 17 connecting from embedded power wiring 16 to the back surface of the substrate 11. The substrate 11 is also provided with vias 18 connecting from pads 19 to wiring 23 formed on the upper surface of wiring layer 22. Pads 19 are external terminals that connect to, for example, a wiring board or other board. Vias 17 and 18 are, for example, through-silicon vias (TSVs).
[0024] The second semiconductor chip 20 is positioned opposite the back surface of the substrate 11 of the first semiconductor chip 10. The second semiconductor chip 20 includes a substrate 21 and a wiring layer 22.
[0025] The substrate 21 is, for example, a silicon substrate.
[0026] The wiring layer 22 is formed on the surface of the substrate 21. The upper surface of the wiring layer 22 faces the back surface of the substrate 11 of the first semiconductor chip 10. In other words, the wiring layer 22 is located between the substrate 11 and the substrate 21.
[0027] The wiring layer 22 includes multiple wires 23. Some of the wires 23 formed on the upper surface of the wiring layer 22 are connected to the embedded power wiring 16 via via 17. Also, some of the wires 23 formed on the upper surface of the wiring layer 22 are connected to the pad 19 via via 18. Furthermore, some of the multiple wires 23 are connected to each other via via 24.
[0028] Figure 2 is a plan view showing an example of the layout structure of the first semiconductor chip according to the first embodiment. Figure 3 is a circuit diagram showing the configuration of the power switch circuit included in the first semiconductor chip according to the first embodiment.
[0029] As shown in Figure 2, the first semiconductor chip 10 includes multiple standard cell regions 31 and input / output (I / O) cell regions 32 arranged around them. The number of standard cell regions 31 may be one or three or more.
[0030] As shown in Figure 3, the standard cell area 31 includes a standard cell 41 and a power switch circuit 42. The standard cell 41 includes various logic circuits, such as NAND gates and inverter circuits. The standard cell area 31 is equipped with VSS wiring to supply ground voltage to the standard cell 41 and VDDV wiring to supply power voltage. The standard cell area 31 is also equipped with VDD wiring to supply power voltage to the power switch circuit 42 from an external source.
[0031] As shown in Figure 3, the power switch circuit 42 includes a switch transistor 51 and a power switch control circuit 52. The switch transistor 51 is a P-channel MOS transistor and is connected between the VDD and VDDV wiring. The power switch control circuit 52 is connected to the gate of the switch transistor 51 and controls the operation of the switch transistor 51. The power switch control circuit 52 switches the switch transistor 51 on and off, controlling the conduction between the VDD and VDDV wiring. The power switch control circuit 52 is, for example, a buffer.
[0032] Figure 4 is a circuit diagram showing the configuration of the buffer in the power switch control circuit according to the first embodiment.
[0033] As shown in Figure 4, the buffer 60 used in the power switch control circuit 52 has inverters 61 and 62. An input signal IN is input to inverter 61, the output of inverter 61 is input to the gate of switch transistor 51 and inverter 62, and an output signal OUT is output from inverter 62. Both inverters 61 and 62 include a pair of P-channel MOS transistors and N-channel MOS transistors.
[0034] Figure 5 is a plan view showing an example of the layout structure of a standard cell area according to the first embodiment. Figures 6A and 6B are cross-sectional views showing an example of the layout structure of a standard cell area according to the first embodiment. Specifically, Figure 6A(a) shows a cross-section of line X1-X1', Figure 6A(b) shows a cross-section of line X2-X2', and Figure 6B shows a cross-section of line Y1-Y1'.
[0035] As shown in Figures 5, 6A, and 6B, the standard cell area 31 contains multiple standard cells 41 and multiple power switch circuits 42.
[0036] Furthermore, as shown in Figure 5, the standard cell area 31 has multiple embedded power supply wires 101 and 102 extending in the X direction, which are arranged alternately in the Y direction. The power switch circuit 42 also includes an embedded power supply wire 103 extending in the X direction. The embedded power supply wire 103 is positioned between adjacent embedded power supply wires 101 in the Y direction, and is positioned so that its position in the Y direction coincides with that of the embedded power supply 102. The embedded power supply wire 101 corresponds to the VDDV wire, the embedded power supply wire 102 corresponds to the VSS wire, and the embedded power supply wire 103 corresponds to the VDD wire. Also, the embedded power supply wires 101 to 103 are part of the embedded power supply wire 16.
[0037] As shown in Figure 6B, the standard cell 41 and the power switch circuit 42 include a FinFET composed of fins 13.
[0038] As shown in Figures 6A and 6B, an element isolation film 11a is formed on the surface of the substrate 11. The element isolation film 11a is formed, for example, by the STI (Shallow Trench Isolation) method. Multiple grooves extending in the X direction are formed in the substrate 11 and the element isolation film 11a. The embedded power wiring 101 to 103 is formed within these grooves. The surfaces of the embedded power wiring 101 to 103 are covered with an insulating film 104. In this way, the embedded power wiring 101 to 103 is formed in the embedded power wiring layer of the first semiconductor chip 10. Note that the surface of the element isolation film 11a and the surface of the insulating film 104 may or may not be flush with the surface of the substrate 11.
[0039] Local wiring 111 is formed above the embedded power wiring 101-103. A portion of local wiring 111 is connected to the embedded power wiring 101-103. Although not shown in the diagram, a portion of local wiring 111 is also connected to fin 13. Local wiring 111 is part of wiring 14.
[0040] Vias 121 to 123 are formed on the substrate 11, penetrating the substrate 11 in the Z direction. Via 121 is formed below the embedded power wiring 101, via 122 is formed below the embedded power wiring 102, and via 123 is formed below the embedded power wiring 103. Vias 121 to 123 are part of via 17.
[0041] As shown in Figures 5, 6A, and 6B, in the wiring layer 22 of the second semiconductor chip 20, wirings 131 to 133 extending in the Y direction are arranged in the X direction on the upper wiring layer 22a. The upper surfaces of wirings 131 to 133 are exposed from the wiring layer 22. Wires 131 to 133 are connected to vias 121 to 123, respectively, via bumps 141 to 143.
[0042] In the wiring layer 22 of the second semiconductor chip 20, the lower wiring layer 22b has wirings 151-153 extending in the X direction, arranged in the Y direction. Wires 131-133 and 151-153 are part of wiring 23.
[0043] Vias 162 and 163 are formed between the upper wiring layer 22a and the lower wiring layer 22b. Wires 132 and 133 are connected to wires 152 and 153, respectively, via vias 162 and 163. Vias 162 and 163 are part of via 24. Although not shown in the diagram, vias connecting wires 131 and 151 are formed between the upper wiring layer 22a and the lower wiring layer 22b.
[0044] Here, vias 172 and 173 are formed on the first semiconductor chip 10, penetrating from the top surface of the wiring layer 12 to the back surface of the substrate 11. Vias 172 and 173 are part of via 18. Vias 172 and 173 are connected to wiring 132 and 133, respectively, via bumps 145 and 146. Bumps 141 to 145 are, for example, microbumps made of solder.
[0045] Vias 172 and 173 are connected to pads 19 via bumps 182 and 183. Although not shown in the diagram, each pad 19 is connected to a power supply located outside the semiconductor integrated circuit device that supplies power voltages VDD and VSS, respectively. In Figures 5 and 6, the pad 19 to which via 173 is connected is connected to the power supply that supplies power voltage VDD, and the pad 19 to which via 172 is connected is connected to the power supply that supplies power voltage VSS.
[0046] Specifically, the power supply voltage VDD is supplied to the power switch circuit 42 via bump 183, via 173, bump 146, wiring 133, bump 143, via 123, and embedded power supply wiring 103. In addition, the power supply voltage VSS is supplied to the standard cell 41 and the power switch circuit 42 via bump 182, via 172, bump 145, wiring 132, bump 142, via 122, and embedded power supply wiring 102.
[0047] As shown in Figure 5, vias 172 and 173 are positioned in locations where the standard cell 41 and power switch circuit 42 are not located in a plan view.
[0048] With the above configuration, the first semiconductor chip 10 includes a pad 19 formed on top of the wiring layer 12 and connected to a power supply that supplies a power voltage VDD, a pad 19 formed on top of the wiring layer 12 and connected to a power supply that supplies a power voltage VSS, a power switch circuit 42 provided between the VDD wiring and the VDDV wiring to control the connection and disconnection between the VDD wiring and the VDDV wiring, an embedded power wiring 103 formed in the embedded power wiring layer and connected to a power supply that supplies a power voltage VDD, an embedded power wiring 102 formed in the embedded power wiring layer and connected to a power supply that supplies a power voltage VSS, and a via 172 connected to the pad 19 connected to the power supply that supplies a power voltage VSS, and provided to penetrate the substrate 11 and the wiring layer 12. The second semiconductor chip 20 includes wiring 132 connected to the embedded power wiring 102 and the via 172.
[0049] Specifically, a pad 19 connected to a power supply that provides the power supply voltage VSS is formed on the upper part of the wiring layer 12 of the first semiconductor chip 10. This pad 19 is connected to the power switch circuit 42 via vias 172 that penetrate the substrate 11 and the wiring layer 12, wiring 132 of the second semiconductor chip 20, and embedded power supply wiring 102 of the first semiconductor chip 10. As a result, the power supply voltage VSS can be supplied from the pad 19 formed on the upper part of the wiring layer 12 of the first semiconductor chip 10 to the power switch circuit 42, thus accommodating the requirement that an external terminal be provided on the upper part of the first semiconductor chip 10.
[0050] Furthermore, the power supply voltages VDD and VSS supplied to the standard cell 41 and the power switch circuit 42 via vias 173 and 172 are supplied to the second semiconductor chip 20 before being supplied to the first semiconductor chip 10. This ensures a stable power supply voltage to the second semiconductor chip 20, thereby suppressing power supply voltage drops supplied to the standard cell 41 and the power switch circuit 42, and also suppressing power supply noise.
[0051] Furthermore, in the first semiconductor chip 10, embedded power wiring 101 to 103 extending in the X direction is connected to wiring 131 to 133 extending in the Y direction in the second semiconductor chip 20. Also, in the second semiconductor chip 20, wiring 131 to 133 is connected to wiring 151 to 153 extending in the X direction. As a result, a mesh-like power supply network is configured to supply power voltages VDDV, VSS, and VDD, thereby suppressing power voltage drop supplied to the standard cell 41 and the power switch circuit 42, and suppressing power noise.
[0052] Furthermore, wirings 131-133 and 151-153 are provided on the second semiconductor chip 20. This eliminates the need to configure a power supply network within the first semiconductor chip 10, thereby improving the flexibility of wiring arrangement within the first semiconductor chip 10.
[0053] Furthermore, the embedded power wiring 101 to 103 is formed in the embedded power wiring layer. As a result, there is no need to provide power wiring in the wiring layer 12, which improves the flexibility of the arrangement of wiring provided in the wiring layer 12 of the first semiconductor chip 10.
[0054] Furthermore, while bumps 141-145 are described as, for example, microbumps made of solder, they are not limited to this. For example, wiring 131-133 and vias 121-123 may be connected by a metal film such as tin (Sn). In other words, any configuration is acceptable as long as wiring 131-133 and vias 121-123 are connected.
[0055] (Variation 1) Figure 7 is a plan view showing another example of the layout structure of the standard cell area according to the first embodiment. Figure 8 is a cross-sectional view showing another example of the layout structure of the standard cell area according to the first embodiment. Specifically, Figure 8 shows a cross-section along the line X3-X3'.
[0056] In Figure 7, compared to Figure 5, connection portions 192 and 193 are formed below vias 172 and 173, respectively.
[0057] As shown in Figures 7 and 8, connection portions 192 and 193 are formed in the upper wiring layer 22a of the wiring layer 22. In a plan view, the connection portions 192 and 193 are each formed in a flat plate shape.
[0058] The connector 192 connects multiple (three in Figure 7) adjacent wires 132. In a plan view, the width of the connector 192 in the X and Y directions is wider than the width of the via 172 (bump 182) in the X and Y directions, respectively. Also, in a plan view, the bumps 145 and 182 are formed in the same shape (circles in Figure 7). Note that the connector 192 is not connected to the wires 131 and 133.
[0059] The connector 193 is connected to the wiring 133. In a plan view, the width of the connector 193 in the X and Y directions is wider than the width of the via 173 (bump 183) in the X and Y directions, respectively. Also, in a plan view, the bumps 146 and 183 are formed with the same shape (circles in Figure 7). Note that the connector 193 is not connected to the wiring 131 and 132.
[0060] In this modified example, since bump 145 and via 172 have the same shape in a plan view, and bump 146 and via 173 have the same shape in a plan view, the resistance between bump 182 of the first semiconductor chip 10 and wiring 132 of the second semiconductor chip 20, and the resistance between bump 183 of the first semiconductor chip 10 and wiring 133 of the second semiconductor chip 20 can be reduced. As a result, a stable power supply voltage can be supplied to wirings 132 and 133 of the second semiconductor chip 20.
[0061] In addition, the same effects as shown in Figure 5 can be obtained.
[0062] Although the connecting portions 192 and 193 are described as being formed in a flat plate shape, this is not the only option. For example, the connecting portions 192 and 193 may each be composed of multiple strip-shaped wires, or they may be formed in a grid pattern. That is, the connecting portions 192 and 193 may have slits in part and may include areas where no wires are formed.
[0063] (Modification 2) Figure 9 is a plan view showing another example of the layout structure of the standard cell region according to the first embodiment. Figure 10 is a cross-sectional view showing another example of the layout structure of the standard cell region according to the first embodiment. Specifically, Figure 10 shows a cross-section of line X4-X4'. Compared to Figure 5, Figure 9 shows that multiple wirings and multiple vias are arranged on the wiring layer 12 of the first semiconductor chip 10 instead of vias 172 and 173.
[0064] As shown in Figures 9 and 10, the upper wiring layer 12a of the wiring layer 12 of the first semiconductor chip 10 has multiple wirings 202 and 203 extending in the X direction. The upper surfaces of wirings 202 and 203 are exposed from the wiring layer 12 and are connected to bumps 182 and 183, respectively. The lower wiring layer 12b of the wiring layer 12 of the first semiconductor chip 10 has multiple wirings 212 and 213 extending in the Y direction. Wires 202 and 212 are formed below bump 182, and wirings 203 and 213 are formed below bump 183. In a plan view, parts of wirings 202, 203, 212, and 213 overlap with embedded power wirings 101 and 102.
[0065] Below wiring 202 and 203, multiple vias 222 and 223 are formed. Wiring 202 and 203 are connected to wiring 212 and 213, respectively, via vias 222 and 223. Also, below wiring 212 and 213, multiple vias 232 and 233 are formed. Wiring 212 and 213 are connected to embedded power wiring 102 and 103, respectively, via vias 232 and 233.
[0066] Furthermore, below wiring 213, multiple (in this case, five) embedded power wirings 103 are formed. These multiple embedded power wirings 103 are positioned between embedded power wirings 101 (or embedded power wirings 102) that are arranged in a line in the X direction.
[0067] Specifically, the power supply voltage VDD is supplied to the power switch circuit 42 via bump 183, wiring 203, via 223, wiring 213, via 233, and embedded power supply wiring 103. In addition, the power supply voltage VSS is supplied to the standard cell 41 and the power switch circuit 42 via bump 182, wiring 202, via 222, wiring 212, via 232, and embedded power supply wiring 102.
[0068] In this modified example, unlike in Figure 5, embedded power wiring 101 and 102 extending in the X direction are formed continuously below bumps 182 and 183, thereby strengthening the power supply voltage supplied to the first semiconductor chip 10.
[0069] Furthermore, since it is no longer necessary to form vias 172 and 173 that penetrate the wiring layer 12 and the substrate 11 on the first semiconductor chip 10, it is not necessary to form two types of TSVs (vias 121-123 and vias 172 and 173) with different lengths in the Z direction. This improves the ease of manufacturing the semiconductor integrated circuit device, thereby improving the yield and reliability of the semiconductor integrated circuit device.
[0070] In addition, the same effects as shown in Figure 5 can be obtained.
[0071] In this modified example, two wiring layers (upper wiring layer 12a and lower wiring layer 12b) are formed on the wiring layer 12 of the first semiconductor chip 10, and the power supply voltage is supplied to the standard cell 41 and the power switch circuit 42 via these wiring layers, but this is not limited to this. The number of wiring layers used to supply the power supply voltage to the standard cell 41 and the power switch circuit 42 may be one or three or more.
[0072] (Second Embodiment) Figure 11 is a plan view showing an example of the layout structure of the standard cell area of the first semiconductor chip according to the second embodiment, Figure 12 is a plan view showing an example of the layout structure of the standard cell area of the second semiconductor chip according to the second embodiment, and Figures 13A and 13B are cross-sectional views showing an example of the standard cell area in the semiconductor circuit device according to the second embodiment. Specifically, Figure 13A(a) shows a cross-section along line X5-X5', Figure 13A(b) shows a cross-section along line X6-X6', and Figure 13B shows a cross-section along line Y2-Y2'.
[0073] As shown in Figures 11, 12, 13A, and 13B, the upper wiring layer 12a of the wiring layer 12 of the first semiconductor chip 10 has multiple wirings 302 and 303 extending in the X direction. Multiple (in this case, three) wirings 302 are connected by connectors 305. Multiple (in this case, two) wirings 303 are connected by connectors 306. The upper parts of the connectors 305 and 306 are exposed from the wiring layer 12 and are connected to bumps 182 and 183, respectively. The lower wiring layer 12b of the wiring layer 12 of the first semiconductor chip 10 has multiple wirings 312 and 313 extending in the Y direction, which are arranged alternately in the X direction. In a plan view, some of the wirings 302, 303, 312, and 313 partially overlap with the embedded power wirings 101 and 102. Furthermore, in a plan view, wiring 302, 303, 312, and 313 partially overlap with the standard cell 41 and the power switch circuit 42.
[0074] Multiple vias 322 are formed below wiring 302 and connection 305, and multiple vias 323 are formed below wiring 303 and connection 306. Wiring 302 and connection 305 are connected to wiring 312 via vias 322. Wiring 303 and connection 306 are connected to wiring 313 via vias 323.
[0075] Below wiring 312 and 313, multiple vias 332 and 333 are formed. Wiring 312 and 313 are connected to embedded power wiring 102 and 103, respectively, via vias 332 and 333.
[0076] Specifically, the power supply voltage VDD is supplied to the power switch circuit 42 via bump 183, wiring 303 (connection part 306), via 323, wiring 313, via 333, and embedded power supply wiring 103. In addition, the power supply voltage VSS is supplied to the standard cell 41 and the power switch circuit 42 via bump 182, wiring 302 (connection part 305), via 322, wiring 312, via 332, and embedded power supply wiring 102.
[0077] With the above configuration, the first semiconductor chip 10 includes a pad 19 formed on the upper part of the wiring layer 12 and connected to a power supply that supplies the power supply voltage VDD, a pad 19 formed on the upper part of the wiring layer 12 and connected to a power supply that supplies the power supply voltage VSS, a power switch circuit 42 provided between the VDD wiring and the VDDV wiring to control the connection and disconnection between the VDD wiring and the VDDV wiring, an embedded power wiring 103 formed in the embedded power wiring layer and connected to a power supply that supplies the power supply voltage VDD, an embedded power wiring 102 formed in the embedded power wiring layer and connected to a power supply that supplies the power supply voltage VSS, an embedded power wiring 101 formed in the embedded power wiring layer and connected to a power supply that supplies the power supply voltage VDDV, wirings 302 and 312 formed in the upper wiring layer 12a and lower wiring layer 12b above the embedded power wiring layer, respectively, and connected to the pad 19 and the embedded power wiring 102 that supply the power supply voltage VSS, and vias 121 with exposed backs that are connected to the embedded power wiring 101. The second semiconductor chip 20 includes wiring 131 connected to via 121.
[0078] Specifically, a pad 19 connected to a power supply that provides the power supply voltage VSS is formed on the upper part of the wiring layer 12 of the first semiconductor chip 10. This pad 19 is connected to the power switch circuit 42 via the wiring 302 of the upper wiring layer 12a, the wiring 312 of the lower wiring layer 12b, and the embedded power supply wiring 102 of the first semiconductor chip 10. As a result, the power supply voltage VSS can be supplied from the pad 19 formed on the upper part of the wiring layer 12 of the first semiconductor chip 10 to the power switch circuit 42, thus accommodating the requirement that an external terminal be provided on the upper part of the first semiconductor chip 10.
[0079] Furthermore, in this embodiment, unlike in Figure 5, embedded power wiring 101 and 102 extending in the X direction are continuously formed below the bumps 182 and 183, thereby strengthening the power supply of the first semiconductor chip 10.
[0080] Furthermore, since standard cells 41 and power switch circuits 42 can also be placed below bumps 182 and 183, the area of the semiconductor integrated circuit device can be reduced.
[0081] Furthermore, since it is no longer necessary to form vias 172 and 173 that penetrate the wiring layer 12 and the substrate 11 on the first semiconductor chip 10, it is not necessary to form two types of TSVs (vias 121-123 and vias 172 and 173) with different lengths in the Z direction. This improves the ease of manufacturing the semiconductor integrated circuit device, thereby improving the yield and reliability of the semiconductor integrated circuit device.
[0082] (Variation 1) Figure 14 is a plan view showing another example of the layout structure of the standard cell area according to the second embodiment. Specifically, Figure 14 shows a plan view of the standard cell area 31 from the embedded power wiring layer of the first semiconductor chip 10 to the second semiconductor chip 20. Compared with Figures 11 and 12, in Figure 14, wirings 133 and 153 in the wiring layer 22 of the second semiconductor chip 20 are omitted. Figure 14 also shows the VDD wiring 310 formed on the wiring layer 12 of the first semiconductor chip 10. The power supply voltage VDD is supplied to the power switch circuit 42 via the VDD wiring 310.
[0083] As shown in Figure 14, the second semiconductor chip 20 has a power supply network (wirings 131, 151, 132, 152) that supplies power supply voltages VDDV and VSS to the standard cell 41 and the power switch circuit 42. This allows for strengthening of the power supply voltages VDDV and VSS supplied to the standard cell 41 and the power switch circuit 42. Note that the power supply network that supplies power supply voltage VDD to the standard cell 41 and the power switch circuit 42 is formed only on the first semiconductor chip 10 (see Figure 11, etc.).
[0084] Furthermore, since embedded power wiring 101 and 102 extending in the X direction are continuously formed below bumps 182 and 183, the power supply voltage supplied to the first semiconductor chip 10 is strengthened.
[0085] In addition, the same effects as those shown in Figures 11 and 12 can be obtained.
[0086] (Modification 2) Figure 15 is a plan view showing another example of the layout structure of the standard cell region according to the second embodiment. Specifically, Figure 15 shows a plan view of the standard cell region 31 from the embedded power wiring layer of the first semiconductor chip 10 to the second semiconductor chip 20. In Figure 15, compared to Figure 14, only the wiring 131 is formed on the wiring layer 22 of the second semiconductor chip 20.
[0087] Specifically, the wiring layer 22 of the second semiconductor chip 20 has flat wiring 131 extending in the X and Y directions. The embedded power wiring 101 is connected to the wiring 131 via vias 121 (and bumps 141). This allows the power supply voltage VDDV supplied to the power switch circuit 42 to be enhanced.
[0088] In addition, the same effects as shown in Figure 14 can be obtained.
[0089] Although the wiring 131 is described as being formed in a flat shape, it is not limited to this. For example, each of the wirings 131 may be composed of multiple strip-shaped wires, or it may be formed in a grid pattern. In other words, the wiring 131 may have slits in some parts, and it may not even have wiring formed therein.
[0090] In addition, the planar shape of the via is not particularly limited in each of the above embodiments and modifications, and can be, for example, circular, elliptical, square, or rectangular.
[0091] Furthermore, in each of the above embodiments and variations, the second semiconductor chip 20 does not necessarily have to include the substrate 21. [Industrial applicability]
[0092] This disclosure can also address cases where external terminals are provided on the upper part of the first semiconductor chip. [Explanation of Symbols]
[0093] 10. First semiconductor chip 20 Second Semiconductor Chip 11,21 circuit boards 12,22 wiring layer 13 fins 14,23,121~123,202,203,212,213,302,303,312,313 Wiring 16,101~103 Embedded power wiring 17, 18, 121~123, 172, 173 Beer 19 pads 41 Standard Cells 42 Power switch circuit
Claims
1. A semiconductor integrated circuit device including a first semiconductor chip and a second semiconductor chip, The back surface of the first semiconductor chip and the main surface of the second semiconductor chip are arranged facing each other. The first semiconductor chip is A first terminal is formed on the upper part of the main surface and is connected to a first power supply that supplies a first power supply voltage, A second terminal is formed on the upper part of the main surface and is connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, A power switch circuit is provided between the first power supply and the third power supply to control the connection and disconnection between the first and third power supplies, A first embedded power wiring is formed in the embedded power wiring layer and connected to the first power supply, A second embedded power wiring is formed in the embedded power wiring layer and connected to the second power supply, It includes a first via connected to the first terminal and provided to penetrate from the main surface to the back surface, A semiconductor integrated circuit device characterized in that the second semiconductor chip includes the first embedded power supply wiring and the first wiring connected to the first via.
2. In the semiconductor integrated circuit apparatus according to claim 1, The first semiconductor chip further includes a second via connected to the second terminal and provided to penetrate from the main surface to the back surface, The semiconductor integrated circuit device is characterized in that the second semiconductor chip further includes the second embedded power supply wiring and the second wiring connected to the second via.
3. In the semiconductor integrated circuit apparatus according to claim 1, The semiconductor integrated circuit device is characterized in that the first semiconductor chip is exposed on the back surface and further includes a third via connected to the first embedded power wiring and the first wiring.
4. In the semiconductor integrated circuit apparatus according to claim 1, The second semiconductor chip includes a plurality of the first wirings, The plurality of first wirings are connected via flat connecting portions, The semiconductor integrated circuit device is characterized in that the connection portion is connected to the first via.
5. In the semiconductor integrated circuit apparatus according to claim 4, The first and second embedded power supply wirings extend in the first direction, A semiconductor integrated circuit apparatus characterized in that the width of the connection portion in the first direction is wider than the width of the first via in the first direction.
6. A semiconductor integrated circuit device including a first semiconductor chip and a second semiconductor chip, The back surface of the first semiconductor chip and the main surface of the second semiconductor chip are arranged facing each other. The first semiconductor chip is A first terminal is formed on the upper part of the main surface and is connected to a first power supply that supplies a first power supply voltage, A second terminal is formed on the upper part of the main surface and is connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, A power switch circuit is provided between the first power supply and the third power supply to control the connection and disconnection between the first and third power supplies, A first embedded power wiring is formed in the embedded power wiring layer and connected to the first power supply, A second embedded power wiring is formed in the embedded power wiring layer and connected to the second power supply, It is formed in a first wiring layer above the embedded power wiring layer, and includes the first terminal and the first wiring connected to the first embedded power wiring, A semiconductor integrated circuit device characterized in that the second semiconductor chip includes a second wiring connected to the first embedded power wiring.
7. In the semiconductor integrated circuit apparatus according to claim 6, The first semiconductor chip is formed on the first wiring layer and further includes a third wiring connected to the second terminal and the second embedded power wiring, The semiconductor integrated circuit device is characterized in that the second semiconductor chip further includes a fourth wiring connected to the second embedded power wiring and the third wiring.
8. In the semiconductor integrated circuit apparatus according to claim 6, The semiconductor integrated circuit device is characterized in that the first wiring overlaps with at least one of the first and second embedded power wirings in a plan view.
9. In the semiconductor integrated circuit apparatus according to claim 6, The semiconductor integrated circuit device is characterized in that the first semiconductor chip is exposed on the back surface and further includes a second via connected to the first embedded power wiring and the first wiring.
10. A semiconductor integrated circuit device including a first semiconductor chip and a second semiconductor chip, The back surface of the first semiconductor chip and the main surface of the second semiconductor chip are arranged facing each other. The first semiconductor chip is A first terminal is formed on the upper part of the main surface and is connected to a first power supply that supplies a first power supply voltage, A second terminal is formed on the upper part of the main surface and is connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, A power switch circuit is provided between the first power supply and the third power supply to control the connection and disconnection between the first and third power supplies, A second embedded power wiring is formed in the embedded power wiring layer and is connected to the second power supply, A third embedded power wiring is formed in the embedded power wiring layer and connected to the third power supply, It is formed in the first wiring layer above the embedded power wiring layer, and the first wiring connected to the first terminal, It includes a first via that is exposed on the rear surface and connected to the third embedded power wiring, A semiconductor integrated circuit device characterized in that the second semiconductor chip includes a second wiring connected to the first via.
11. In the semiconductor integrated circuit apparatus according to claim 10, The semiconductor integrated circuit device is characterized in that the first semiconductor chip is formed on the first wiring layer and further includes a third wiring connected to the second terminal and the second embedded power wiring.
12. In the semiconductor integrated circuit apparatus according to claim 10, The semiconductor integrated circuit device is characterized in that the first wiring overlaps with the power switch circuit in a plan view.
13. In the semiconductor integrated circuit apparatus according to claim 10, The semiconductor integrated circuit device is characterized in that the first wiring overlaps with at least one of the second and third embedded power wirings in a plan view.
14. In the semiconductor integrated circuit apparatus according to claim 10, The second semiconductor chip is formed in a wiring layer below the second wiring and further includes a fourth wiring extending in the first direction. The semiconductor integrated circuit device is characterized in that the second wiring extends in a second direction different from the first direction and is connected to the fourth wiring.
15. In the semiconductor integrated circuit apparatus according to claim 10, The semiconductor integrated circuit device is characterized in that the second wiring is formed in a flat plate shape.