Lookup tables for nonlinear systems

Abstract

In the illustrated example, the circuit (100) includes a multiplexer (112). The multiplexer (112) receives an input voltage (110) and a calibration signal. An analog-to-digital converter (ADC) (106) is coupled to the multiplexer (112) and generates an output code in response to the calibration signal. A storage circuit (108) is coupled to the ADC (106) and stores an input code representing the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

Description

[Technical Field]

[0001] This specification generally relates to analog-to-digital converters, and more specifically to the use of lookup tables (LUTs) in ADCs. [Background technology]

[0002] In many electronic devices, an analog-to-digital converter (ADC) is used to convert an analog input voltage into a digital output signal. ADCs used to digitize signals in radio frequency (RF) sampling receivers are sometimes required to operate at high speeds, sometimes as high as gigasamples per second. However, in the case of such high-speed ADCs, it is necessary to compensate for the nonlinearity of the high-speed ADC. [Overview of the project]

[0003] In the example described, the circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A memory circuit is coupled to the ADC and stores the input code representing the calibration signal at the address corresponding to the output code. The stored input code includes an index value and a coarse value.

[0004] The disclosure also relates to a method that includes receiving an input voltage and a calibration signal, generating an output code by an analog-to-digital converter (ADC) in response to the calibration signal, and storing an input code representing the calibration signal at an address corresponding to the output code, wherein the stored input code includes an index value and a coarse value.

[0005] This disclosure also relates to a device including a processor, memory coupled to the processor, and circuitry coupled to the processor and memory. The circuitry includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A memory circuit is coupled to the ADC and stores an input code representing the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing a circuit according to the example embodiment.

[0007] [Figure 2] This is a block diagram illustrating a method for converting raw data to the final output using a lookup table within a memory circuit, according to one embodiment.

[0008] [Figure 3] This is a block diagram of a part of the circuit shown in Figure 1, according to one embodiment.

[0009] [Figure 4] This is a flowchart illustrating the operation method of a circuit according to one embodiment.

[0010] [Figure 5] This is a block diagram showing an exemplary device in which several embodiments of the exemplary embodiment can be implemented.

[0011] [Figure 6] This is a block diagram of a backend analog-to-digital converter according to the example embodiment.

[0012] [Figure 7] This is a block diagram of a combiner for connecting the multi-bit stage shown in Figure 6 to the first stage of a single-bit stage, according to the exemplary embodiment.

[0013] [Figure 8] A graph showing the AND gate delay and the comparator delay respectively generated by the AND gate and the delay comparator of the backend ADC in FIG. 6 according to an exemplary embodiment, where the AND gate delay and the comparator delay are functions of the input signal delay.

[0014] [Figure 9] A graph showing the output signal delay as a function of the input signal delay in FIG. 8 according to an exemplary embodiment.

[0015] [Figure 10] A circuit diagram of an example of a comparator circuit merged with a sign out and a delay out circuit for the backend ADC in FIG. 6 according to an exemplary embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0016] (Functionally and / or structurally) the same or similar features are designated by the same reference numbers or other reference indicators in the drawings.

[0017] U.S. Application No. 17 / 568,972, filed on January 5, 2022, by the same applicant, with the invention title "Calibration Method for Nonlinear ADC" (TI-100164), is hereby incorporated by reference in its entirety.

Patent Document 1

[0018] Figure 1 is a block diagram of circuit 100 according to an exemplary embodiment. Circuit 100 includes a calibration engine 102, a digital-to-analog converter (DAC) 104, an analog-to-digital converter (ADC) 106, and a memory circuit 108. The DAC 104 is coupled to the calibration engine 102. The ADC 106 is coupled to the calibration engine 102, the memory circuit 108, and the DAC 104 (via a multiplexer M112). The memory circuit 108 is also coupled to the calibration engine 102. In the exemplary embodiment, the memory circuit 108 may implement a LUT (lookup table).

[0019] Multiplexer M112 is coupled between DAC 104 and ADC 106. Multiplexer M112 is also coupled to calibration engine 102. Multiplexer M112 receives input voltage Vin110 and selectively outputs either input voltage Vin110 or the output of DAC 104. ADC 106 includes a preamplifier array 116, a delay multiplexer DM120, and a backend ADC 124. The preamplifier array 116 is coupled to multiplexer M112 and includes multiple preamplifiers. The delay multiplexer DM120 is coupled to the preamplifier array 116. The backend ADC 124 is coupled to the delay multiplexer DM120. Memory circuit 108 is coupled to backend ADC 124. Memory circuit 108 can be constructed of digital memory circuits (e.g., RAM, ROM), registers, and / or flip-flops. The memory circuit 108 may be part of a conventional memory circuit or part of a digital processor system. The calibration engine 102 may, in one example, be a processing unit, a digital signal processor (DSP), a processor, and / or a programmable logic device, or part thereof. The calibration engine 102 may include memory and logic. In some exemplary embodiments, the ADC 106 may be implemented as a voltage delay converter ("V2D"). Examples of such V2D converters are described in U.S. Patents 10,284,188, 10,673,456, 10,673,452, and 10,673,453 by the same applicant, each of which is incorporated herein by reference in whole. [Patent Document 2] U.S. Patent No. 10,284,188 [Patent Document 3] No. 10,673,456 [Patent Document 4] No. 10,673,452 [Patent Document 5] No. 10,673,453

[0020] In some exemplary embodiments, each component of the ADC 106 can independently communicate with the calibration engine 102 and with other components of the circuit 100. However, for the sake of brevity, these connections are not discussed herein. Each block or component of the circuit 100 can also be coupled to other blocks in Figure 1, but for the sake of brevity, these connections are not described herein. The circuit 100 may include one or more conventional components, which are not described herein for the sake of brevity.

[0021] In one example, circuit 100 is an analog-to-digital converter. Circuit 100 operates in calibration mode and mission mode (also called the "normal" mode of operation). In calibration mode, calibration engine 102 generates multiple input codes, each corresponding to a known analog voltage. DAC 104 generates a calibration signal (e.g., an analog voltage) in response to the multiple input codes. For example, DAC 104 generates a first calibration signal in response to a first input code among the multiple input codes. Multiplexer M112 provides the first calibration signal to ADC 106 in calibration mode. Preamplifier array 116 and delay multiplexer DM120 generate a delay signal in response to the first calibration signal. In one example, the delay signal represents the value of the analog input signal based on the amount of delay in the generated signal. Backend ADC 124 generates a first output code in response to the delay signal. Memory circuit 108 stores the first output code corresponding to the first input code. The memory circuit 108 stores the output code corresponding to each of the multiple input codes. In one exemplary embodiment, the memory circuit 108 maintains a lookup table (LUT) for storing the output code corresponding to each input code. In the exemplary embodiment, the output of the ADC 106 ("ADC Raw Code") may be M bits, and the output of the memory circuit 108 ("Corrected Output") may be N bits.

[0022] Similarly, DAC104 generates a second calibration signal in response to a second input code (of which multiple input codes) generated by calibration engine 102. Preamplifier array 116 and delay multiplexer DM120 generate a delay signal in response to the second calibration signal. Backend ADC124 generates a second output code in response to the delay signal. Memory circuit 108 stores the second output code corresponding to the second input code. The first output code is stored in a first location within memory circuit 108, and the second output code is stored in a second location within memory circuit 108. Thus, for each input code generated by calibration engine 102, the output code is stored in the lookup table within memory circuit 108. The lookup table within memory circuit 108 is populated in calibration mode with input codes and corresponding output codes. This lookup table is used in mission mode by circuit 100, as will be discussed in the detailed description below.

[0023] Table 1 below is an example illustrating the operation of circuit 100 while it is operating in calibration mode. Table 1 shows the input codes generated by the calibration engine 102 and the corresponding output codes generated by the ADC 106 and stored in the lookup table in the memory circuit 108. [Table 1]

[0024] As shown in Table 1, for input code 0 generated by the calibration engine 102, output code 0 is stored in the memory circuit 108. Similarly, for input code 2, the output code is 10 and is stored in the memory circuit 108. The memory circuit 108 stores the output code for each input code generated by the calibration engine 102. It is understood that both input and output codes are stored and processed in binary form within the circuit 100, and decimal values ​​are considered for ease of understanding. In one example, each input code is N bits and each output code is N+n bits, where N and n are both integers greater than zero. This reduces the nonlinearity of the ADC 106. As shown in Table 1, when N is 13, the lookup table in the memory circuit 108 is (2 N ) Corresponding to the input code (2 N )Stores the output code (8191). In Table 1, N is 13 and n is 2, and therefore the range of output codes stored in the memory circuit 108 is from 0 to 32767 (for example, 32768 (2 13+2 It changes up to ). In Table 1, the input code is the address and the output code is the data. The advantage of having a lookup table as shown in Table 1 is that the memory requirements are reduced. The memory requirement for the lookup table is approximately 120k(2 13 × 15 = 2 N ×(N+n) = number of memory locations × number of data bits). However, a lookup table like the one shown in Table 1 is more suitable for the low-speed operation of circuit 100.

[0025] A solution to overcome this problem is to populate the lookup table shown in Table 1 in reverse form (where the address for each value to be stored is provided by the output code). This is shown in Table 2, another example to illustrate the operation of circuit 100 while operating in calibration mode. Table 2 shows the input codes generated by the calibration engine 102 and the output codes generated by the backend ADC 124 corresponding to the input codes. [Table 2]

[0026] As shown in Table 2, when the input code is 0, output code 0 is generated, and input code 0 is stored in the memory circuit 108 at the address of the output code 0. Similarly, when the input code is 1, the generated output code is 8. Input code 1 is stored in the memory circuit 108 at the corresponding address of the output code 8. Therefore, in Table 2, the input code is data and the output code is an address. Compared to the lookup table shown in Table 1, the lookup table shown in Table 2 enables faster operation of the circuit 100. However, as shown in Table 2, the lookup table requires an increase in the memory area in the memory circuit 108. The memory requirement for the lookup table is approximately 420k(2 15 × 13 = 2 N+n ×(N), where N is 13 and n is 2).

[0027] To reduce the memory requirements in the memory circuit 108 and to enable high-speed operation of the circuit 100, the following methods are used in some exemplary embodiments. Table 3 below is an example illustrating the operation of the circuit 100 while operating in calibration mode. Table 3 shows the input codes generated by the calibration engine 102 and the output codes generated by the backend ADC 124 corresponding to the input codes. In the exemplary embodiments shown in Table 3, a value of "0" (e.g., logical low or logical 0) or "1" (e.g., logical high or logical "1") is stored at each position for the input code. A value of "1" specifies that the input code is incremented by 1 (relative to the previously stored value for the input code), while a value of "0" specifies that the input code is the same as the previous value for the input code. [Table 3]

[0028] As shown in Table 3, output code 0 is generated for input code 0, and input code 0 is stored in the memory circuit 108 at the address of output code 0 which is 0. Similarly, the input codes corresponding to output codes 1 to 7 remain 0. Therefore, the input codes corresponding to memory positions 1 to 7 remain "0". However, when the input code is 1, the output code is 8. Since the input code is 1 greater than the input codes corresponding to output codes 0 to 7, the input code corresponding to address 8 (the value of the output code) is "1". Since the output code is 9 when the input code is 1, and the input code is the same as the previous input code (for example, the input code corresponding to output code 8), the value "0" is stored at address 9. When the input code is 2, the output code is 10. Since the input code increases (compared to the input code corresponding to the input code for output code 9), the value stored at address 10 is "1". In Table 3, as in Table 2, the input code is data and the output code is an address. To calculate the output code for a specific input code, it is necessary to sum the input codes at all memory positions before the input code corresponding to the specific output code. For example, when the output code is 10, the sum of all input codes up to the current address (or output code 10) is 2. Therefore, the look-up table enables the high-speed operation of the circuit 100. However, this solution requires a large computational capacity because it is necessary to perform a summation operation for each memory position. The memory requirement for the look-up table in Table 3 is approximately 32k (2 15 =2 N+n where N is 13 and n is 2).

[0029] To enable the high-speed operation of the circuit 100, the following method is used. Table 4 below is an example for showing the operation of the circuit 100 while operating in the calibration mode. Table 4 shows the input codes generated by the calibration engine 102 and the output codes generated by the back-end ADC 124 corresponding to the input codes. As discussed with reference to Tables 2 and 3, the output code is the address for the corresponding input code (data). [Table 4]

[0030] Similar to Tables 1-3, in Table 4, output code 0 is generated for input code 0, and output code 8 is generated for input code 1. Input codes are stored as data, and output codes are stored as addresses; for example, an input code is stored at the address corresponding to the output code. Stored input codes include an index value and a gross value (e.g., the cumulative sum of index values). Index values ​​are represented in Table 4 (in the column for input codes) as "0", "1", "0", etc., and gross values ​​are represented as "0000X", "0001X", etc. Similar to the values ​​for input codes in Table 3, the index value is 1 when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code. The index value is 0 when the input code corresponding to the current output code is equal to the input code corresponding to the previous output code. For example, as shown in Table 2, the input code is 0 for all output codes 1 through 7. When the output code is 8, the input code is 1. Therefore, the index value remains 0 for output codes 1 through 7, and when the output code is 8, the index value is 1. The index value is always 1 when the input code corresponding to the current output code (e.g., output code 8) is not equal to the input code corresponding to the previous output code (e.g., output code 7).

[0031] The gross value for the current output code is the sum of the index values ​​generated for all previous output codes, plus the index value corresponding to the current output code. The gross value represents the cumulative total of the input codes. For example, the gross value for the current output code (e.g., output code 10) is the sum of all the index values ​​generated for all previous output codes (e.g., the index values ​​generated for output codes 1 through 9) and the index value corresponding to the current output code (e.g., output code 10). The sum of all index values ​​up to output code 10 is 0002. The memory requirement for the lookup table in Table 4 is approximately 450k (2 15 ×14=2 N+n (×This is the number of bits stored for each input code; in this formula, N is 13 and n is 2.)

[0032] To further refine the lookup tables shown in Table 4, the following exemplary implementations shown in Table 5 may be used. The output code includes the sum of M (e.g., most significant) bits and L (e.g., least significant) bits, where both M and L are integers greater than or equal to 1. The output code is reduced to M bits, and L bits are added to the index value. The reduced output code is called the block index (BI). The rough value is 2^L (e.g., 2 L ) is stored bit by bit. For example, when the output code is 15 bits (N+n) (see Tables 1-4 and explained above), M is 10 bits and L is 5 bits. The output code is reduced to 10 bits, and the index value is supplemented with 5 bits. This is shown in Table 5 below. Therefore, the reduced output code is from 0 to 1023(2 10 It is a block index (BI) that extends up to ), and the index value is 32 bits (2 5 The gross value is stored in 32-bit increments, for example, per block index. The gross value represents the cumulative sum of the input codes. [Table 5]

[0033] The input code is generated by the calibration engine 102, and the output code (corresponding to the input code) is generated by the backend ADC 124. Similar to Table 4, in Table 5, output code 0 is generated for input code 0, and output code 8 is generated for input code 1. The input code is stored as data, and the output code is stored as an address. The stored input code includes an index value and a gross value. Similar to the embodiments described with reference to Tables 2 to 4, the index value is 1 when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code. The index value is 0 when the input code corresponding to the current output code is equal to the input code corresponding to the previous output code. As shown in Table 5 (and with reference to Table 4), the index value is 0 when the output code is 0 and the index value remains 0 for output codes 1 through 7. When the output code is 8, the index value is 1. Similarly, when the output code is 10, the index value is 1, and when the output code is 11, the index value is 1.

[0034] The gross value is stored for every 32 bits of the index value. Therefore, a gross value is stored for each block index. The gross value is the sum of all index values ​​generated for all previous block indexes. For example, when BI is 0, the gross value is 0, and when BI is 1, the gross value is 5, which is the sum of all index values ​​generated for BI 0. Similarly, when BI is 2, the gross value is 16, which is the sum of all index values ​​generated for BI 0 and 1. The memory requirement for the lookup table in Table 5 is approximately 45k(2 10 ×(32+13)=2 M × (2 L It is +N)).

[0035] Therefore, the lookup table shown in Table 5 requires less memory than conventional solutions and also supports high-speed operation of circuit 100. In one exemplary embodiment, circuit 100 is an ADC, and the lookup table shown in Table 5 enables the ADC to operate at GSPS speed. Thus, the lookup table in memory circuit 108 is populated in calibration mode with input codes and corresponding output codes, as shown in Table 5. This lookup table is used by circuit 100 in mission mode, as will be discussed in the following paragraph.

[0036] In mission mode, the multiplexer M112 provides the input voltage Vin110 to the multiplexer M112. In one exemplary embodiment, the multiplexer M112 is controlled by the calibration engine 102. The combination of the preamplifier array 116 and the delay multiplexer DM120 generates a delay signal in response to the input voltage Vin110. The backend ADC 124 generates a low code (ADC low code) in response to the delay signal. The input code stored at the address corresponding to the low code in the lookup table in the memory circuit 108 (similar to the lookup table shown in Table 5) is generated by the circuit 100 as the final output 130 (corrected output). For each value of the input voltage Vin110, the low code is matched with the address of the output code, and the input code stored at the address is provided as the final output 130. Therefore, in one version, the mission mode represents the normal operation of circuit 100, where an analog signal (such as a radio frequency analog signal) is received as Vin 110 and converted to a digital representation (e.g., binary) via ADC 106 and memory circuit 108. Thus, the final output 130 is the digital representation of the analog signal Vin 110.

[0037] The multiplexer M112, ADC 106, and memory circuit 108 form one channel within circuit 100. Circuit 100 can be implemented with two or more channels. In one exemplary embodiment, each channel may be implemented in parallel with other channels. The second channel will include a second multiplexer (e.g., similar to multiplexer 112), a second ADC (e.g., similar to ADC 106), and a second memory circuit (e.g., similar to memory circuit 108). The second backend ADC in the second channel may be similar to the backend ADC 124 in the first channel, but both may have different transfer functions due to manufacturing variations, and therefore both are calibrated separately. Multiple channels can provide flexibility such as operating one channel in calibration mode and others in mission mode. Thus, when one channel is calibrated, the other channels are used in mission mode for analog-to-digital conversion. In one example, all channels are calibrated using DAC104, and all channels are controlled by calibration engine 102. In some exemplary embodiments, the backend ADCs in each channel are calibrated independently, eliminating the need for any channel matching. This also reduces the requirements for backend estimation and calibration algorithms.

[0038] In one example, the combination of preamplifier array 116, delay multiplexer DM120, and backend ADC 124 acts as a nonlinear ADC or delay-based ADC. While this combination is highly nonlinear, circuit 100 is highly linear and operates at high speed with relaxation area and power requirements. Circuit 100 is well-suited to the technology node. Circuit 100 pushes the high linearity requirement on DAC 104. This is advantageous because designing and implementing analog circuits for low-speed operation with linearity and accuracy is relatively less difficult. According to this disclosure, the backend ADC 124 may be designed to operate at high speed by compromising linearity. However, the backend ADC 124 operates in association with a lookup table within memory circuit 108, and circuit 100 behaves like a linear analog-to-digital converter (ADC). Similarly, memory circuit 108 may be implemented within a digital circuit and configured for high speed.

[0039] Interfaces of external analog signals to high-speed digital processing cores generally require an ADC. Faster data transmission speeds may require ADCs to operate at considerable speeds and with good signal-to-noise ratios. Without the benefits of some exemplary embodiments, these constraints result in significant power losses and large area requirements for supporting integrated circuits. These problems can be particularly pronounced at high sampling rates (e.g., around gigasamples per second (GSPS)) due to analog non-idealisms that can limit performance. While the exemplary embodiment of circuit 100 allows for the use of a wide range of architectures with one or more nonlinear ADCs, it provides a lookup table technique to the backend ADC 124 that can be calibrated to provide the superior performance of a highly linear ADC.

[0040] In calibration mode, the lookup table in memory circuit 108 is populated as shown in Table 5, and in mission mode, circuit 100 uses the high-speed ADC 106 and memory circuit 108 to generate an output code corresponding to the input voltage Vin 110. Therefore, circuit 100 does not use any complex algorithms or hardware for the digital conversion of the input voltage Vin 110. This reduces the area and power requirements of circuit 100. Thus, circuit 100 can be used in an RF sampling receiver operating at GSPS speed. Circuit 100 is well-suited to the technology node and can support high GSPS transfer rates in future technology nodes.

[0041] Figure 2 is a block diagram 200 illustrating a method for converting raw data to a final output using a lookup table in a memory circuit according to one embodiment. Block diagram 200 is described in relation to the circuit 100 shown in Figure 1 and represents the digital conversion of the input voltage Vin 110 to the final output 130. The memory circuit 108 stores the data as shown in Table 5. In one example, the total memory 204, the secondary adder 206, and the primary adder 210 are part of the memory circuit 108. A 15-bit raw code is received from the backend ADC 124. Five LSBs (least significant bits) are provided to the secondary adder 206, and 10 MSBs (most significant bits) are provided to the total memory 204.

[0042] The total memory 204 determines the block index (BI) based on the MSB and provides the corresponding gross value (for example, in 13-bit form) to the primary adder 210. The 32-bit index value corresponding to the BI is provided from the total memory 204 to the secondary adder 206. The secondary adder 206 performs an AND operation on the 32-bit index value and the bit mask. The bit mask is obtained from the 5-bit LSB. The secondary adder 206 sums the bits obtained after the AND operation, and the summed value (in 5-bit form) is provided to the primary adder 210. The primary adder sums the 13 bits received from the total memory 204 and the 5 bits received from the secondary adder 206 to produce the final output 230. This method will now be explained with the help of an example using Table 5, which is shown in relation to Figure 1.

[0043] For example, when the received input voltage Vin110 is equivalent to a decimal value of 34 (which represents the analog voltage level), the low code will be represented as 000000000100010. The first 10 bits (0000000001) are the most significant bits (MSB), and the last 5 bits (00010) are the least significant bits (LSB). In total memory 204, the block index (BI) is determined from the MSB. MSB0000000001 represents BI 1, whose gross value is 5 (from Table 5). The gross value is provided to the primary adder 210 in 13-bit form. Based on the block index (BI), total memory provides the 32 bits of the index value to the secondary adder 206. The 32 bits provided when BI is 1 are 1000 0001 1100 0011 0111 0000 0100 0010. The secondary adder 206 performs an AND operation on the 32 bits received from total memory 204 and a bitmask that in this example is 1110 0000 0000 0000 0000 0000 0000 0000. The bitmask is obtained from the LSB (for example, the five LSBs in this example). The binary value of the five LSBs is 2. Therefore, the number of 1s in the bitmask is the binary value of the LSB plus 1 (so, for example, the value is 3 in this example). Thus, the first 3 bits of the bitmask are 1 and the remaining bits are zero. The bits obtained after the AND operation are summed. In this example, the sum of the ANDed bits is a sum of 1s. The sum of these 1s is provided to the primary adder 210 in the form of 5 bits.

[0044] The primary adder 210 adds the gross value received from the total memory 204 and the total value from the secondary adder 206 to produce the final output 230. In this example, the primary adder 210 receives 5 from the total memory 204 and 1 from the secondary adder 206, and since the sum is 6, the primary adder 210 produces the binary representation of 6 as the final output 230. The sum of the index values ​​up to 34 bits (from Table 5) results in a sum of 6, which verifies that the resulting final output 230 is correct. Thus, the lookup table storage shown in Table 5 requires less memory compared to conventional solutions and also supports the high-speed operation of circuit 100. In one exemplary embodiment, circuit 100 is an ADC, and the lookup table shown in Table 5 allows the ADC to operate at GSPS speed.

[0045] Figure 3 is a block diagram of a portion of the circuit 100 shown in Figure 1, according to an exemplary embodiment. The preamplifier array 116 includes a plurality of preamplifiers numbered 1 through n, where n is an integer. Each preamplifier has one input coupled to the input voltage Vin 110 and another input coupled to a reference voltage (Vt1, Vt2, ...Vtn, etc.). These preamplifiers are labeled preamplifier 316a, preamplifier 316b through preamplifier 316n. The delay multiplexer DM 120 is coupled to the plurality of preamplifiers in the preamplifier array 116 (via the differential outputs of each preamplifier, such as OUT_P1 and OUT_M1 in the case of preamplifier 316a). The backend ADC 124 is coupled to the delay multiplexer DM 120 by differential signal lines, OUT_P and OUT_M. The calibration engine 102 is coupled to each preamplifier in the preamplifier array 116 via the input line 340, the delay multiplexer DM 120, and the backend ADC 124. The calibration engine 102 provides timing signals to each preamplifier via the input line 340, which are used to reset the preamplifiers in one exemplary embodiment.

[0046] In operation, the preamplifier 116 receives the input voltage Vin110 from the multiplexer M112. Similar to amplifiers 54-60 of U.S. Patent No. 10,673,456 (which is incorporated herein by reference in its entirety), each preamplifier receives a different threshold voltage. For example, preamplifier 316a receives the threshold voltage Vt1, preamplifier 316b receives the threshold voltage Vt2, and preamplifier 316n receives the threshold voltage Vtn. In one example, Vt1 < Vt2 < Vtn. The threshold voltages Vt1, Vt2 - Vtn are generated using a voltage divider 330 in one exemplary embodiment. Each preamplifier generates first and second output signals based on the difference between the input voltage Vin110 and the threshold voltage. For example, preamplifier 316a generates a differential signal, i.e., a first output signal OUT_M1 and a second output signal OUT_P1. Similarly, preamplifier 316n generates a differential signal, i.e., a first output signal OUT_Mn and a second output signal OUT_Pn.

[0047] Similar to the operation of multiplexer 211 in U.S. Patent No. 10,673,452 (which is incorporated herein by reference in its entirety), delay multiplexer DM120 receives first and second output signals from each of the multiple preamplifiers. Delay multiplexer DM1220 generates delayed signals (e.g., OUT_M and OUT_P) based on the output of one of the preamplifiers. The delayed signals include a first delayed signal OUT_M and a second delayed signal OUT_P, corresponding to the output signals of the preamplifier whose threshold voltage is closest to the input voltage Vin110. For example, if the input voltage Vin110 is closest to the threshold voltage Vt1 of preamplifier 316a, then the first delayed signal OUT_M and the second delayed signal OUT_P correspond to the first and second output signals OUT_M1 and OUT_P1 of preamplifier 316a. On the other hand, when the input voltage Vin110 is closest to the threshold voltage Vt2 of the preamplifier 316b, the first delay signal OUT_M and the second delay signal OUT_P correspond to the first and second output signals OUT_M2 and OUT_P2 of the preamplifier 316b. In one example, the calibration engine 102 allows the delay multiplexer DM120 to select the output signal of the preamplifier whose threshold voltage is closest to the input voltage Vin110. The backend ADC 124 generates a first raw code in response to the delay signal.

[0048] The preamplifiers 316a, 316b-316n within the preamplifier array 116 have variable gains as a result of various factors, including design, process, input voltage VIN, and / or temperature (for example, as used herein, “gain” may mean voltage gain, current gain, or delay, and as will be discussed in more detail below, the amplifiers / comparators have different delays based on the input signal). In one example, the gains and ranges of the preamplifiers 316a, 316b-316n are adjustable and preferably matched across the entire preamplifier array 116. The preamplifier array 116 and the backend ADC 124 enable the circuit 100 to operate as a high-speed, high-performance analog-to-digital converter (ADC).

[0049] Figure 4 is a flowchart 400 of how the circuit operates according to an exemplary embodiment. Flowchart 400 is described in relation to the circuit 100 in Figure 1. In step 402, the input voltage and calibration signal are received. In circuit 100, the multiplexer M112 receives the input voltage Vin110 and the calibration signal from the DAC 104. The circuit 100 shown in Figure 1 contains only a single channel. This signal channel operates in either calibration mode or mission mode. In alternative embodiments, as described above, the circuit 100 may contain multiple channels (each channel may contain a multiplexer 112 and an ADC 106, share a calibration engine or have its own dedicated calibration engine, share a memory circuit or have its own dedicated memory circuit), and each channel may operate in mission mode and / or calibration mode. In calibration mode, the calibration engine 102 generates multiple input codes. DAC104 generates a first calibration signal in response to a first input code among multiple input codes. In step 404, an output code is generated by an analog-to-digital converter (ADC) in response to the calibration signal. In circuit 100, the multiplexer M112 provides the first calibration signal to the ADC106 in calibration mode. The preamplifier array 116 and the delay multiplexer DM120 generate a delay signal in response to the first calibration signal. The backend ADC124 generates a first output code in response to the delay signal.

[0050] In step 406, the input code is stored at the address corresponding to the output code. The stored input code includes an index value and a gross value. The storage circuit 108 stores the first output code corresponding to the first input code in circuit 100. The storage circuit 108 stores the output code corresponding to each of the multiple input codes. In one exemplary embodiment, the storage circuit 108 maintains a lookup table to store the output code corresponding to each input code. As discussed in relation to Tables 4 and 5, the input code is stored as data and the output code is stored as an address. The input code is stored at the address corresponding to the output code. The stored input code includes an index value and a gross value.

[0051] The index value is binary "0" when the input code corresponding to the current output code is equal to the input code corresponding to a previous output code. The gross value for the current output code is the sum of the index values ​​generated for all previous output codes and the index value corresponding to the current output code. The gross value represents the cumulative total of the input codes. Table 5 shows the lookup table in memory circuit 108, which requires less memory than conventional solutions and also supports the high-speed operation of circuit 100. The output code includes the sum of M and L bits, both of which are integers greater than or equal to 1.

[0052] The output code is reduced to M bits, and the index value is supplemented with L bits. The coarse value is stored every 2^L bits. For example, when the output code is 15 bits, M is 10 bits and L is 5 bits. The output code is reduced to 10 bits, while the index value is supplemented with 5 bits. The memory requirements for the lookup table in Table 5 are approximately 45k(2 10 It is ×(32+13)).

[0053] Thus, the lookup table in the memory circuit 108 is populated in calibration mode with input codes and corresponding output codes, as shown in Table 5. This lookup table is used by circuit 100 in mission mode. In mission mode, an analog signal (such as a radio frequency analog signal) is received as Vin 110 and converted to a digital (e.g., binary) representation via ADC 106 and memory circuit 108. Circuit 100 uses a high-speed ADC and the lookup table in the memory circuit to convert the input voltage Vin, thereby reducing the area and power requirements of circuit 100. In one example, circuit 100 can be used in an RF sampling receiver operating at GSPS speed.

[0054] Figure 5 is a block diagram of the exemplary device 500, in which several embodiments of the exemplary embodiment can be implemented. Device 500 is a server farm, a vehicle, a communication device, a transceiver, a personal computer, a gaming platform, a computing device, or any other type of electronic system, or is incorporated into or part of such a system. Device 500 may include one or more conventional components that are not described herein for the sake of brevity of the description.

[0055] In one example, device 500 includes a microcontroller unit 502 and a memory 506. The microcontroller unit 502 can be a CISC (Compound Instruction Set Computer) CPU, a RISC (Reduced Instruction Set Computer) CPU, a digital signal processor (DSP), a processor, a CPLD (Programmable Compound Logic Device), or an FPGA (Field Programmable Gate Array).

[0056] Memory 506 (which can be RAM, flash memory, or disk storage) stores one or more software applications (e.g., embedded applications) that, when executed by the microcontroller unit 502, perform any appropriate function associated with device 500.

[0057] The microcontroller unit 502 may include memory and logic for storing information frequently accessed from memory 506. Device 500 includes circuitry 510. In one example, the microcontroller unit 502 may be located on the same PCB or module as circuitry 510. In another example, the microcontroller unit 502 is located outside of device 500. Circuitry 510 may function as an analog-to-digital converter. Circuitry 510 may include additional analog circuit elements, digital circuit elements, memory, and / or software.

[0058] Circuit 510 may include circuit elements similar to those of circuit 100 in Figure 1 in terms of connection and operation. Circuit 510 includes a calibration engine, a DAC (digital-to-analog converter), an ADC (analog-to-digital converter), a multiplexer, and a memory circuit. The multiplexer receives an input voltage Vin. The ADC includes a preamplifier array, a delay multiplexer, and a backend ADC. The preamplifier array includes multiple preamplifiers.

[0059] Circuit 510 operates in calibration mode and mission mode. In calibration mode, the calibration engine generates multiple inputs. The DAC generates a first calibration signal in response to a first input code among the multiple input codes. The multiplexer provides the first calibration signal to the ADC in calibration mode. The preamplifier array and delay multiplexer generate a delay signal in response to the first calibration signal. The backend ADC generates a first output code in response to the delay signal. The memory circuit stores the first output code corresponding to the first input code. The memory circuit stores the output code corresponding to each of the multiple input codes.

[0060] Input codes are stored as data, and output codes are stored as addresses. Input codes are stored at the corresponding addresses of output codes. Stored input codes include index values ​​and gross values. When the input code corresponding to the current output code is equal to the input code corresponding to a previous output code, the index value is 0. The gross value for the current output code is the sum of the index values ​​generated for all previous output codes and the index value for the current output code. The gross value represents the cumulative total of input codes.

[0061] The output code contains the sum of M and L bits, where both M and L are integers greater than or equal to 1. The output code is reduced to M bits, and the index value is supplemented with L bits. The coarse value is stored every 2^L bits. For example, when the output code is 15 bits, M is 10 bits and L is 5 bits. The output code is reduced to 10 bits, while the index value is supplemented with 5 bits. The memory requirement for the lookup table is approximately 45k(2 10 The result is ×(32+13)). Therefore, the lookup table requires less memory than conventional solutions and also supports the high-speed operation of circuit 510. In one exemplary embodiment, circuit 510 is an ADC, and the lookup table enables the ADC to operate at GSPS speed.

[0062] Therefore, the lookup table in the memory circuit is populated in calibration mode with input codes and corresponding output codes. This lookup table is used by circuit 510 in mission mode. In mission mode, an input voltage Vin (such as a radio frequency analog signal) is received and converted to a digital (e.g., binary) representation via the ADC and memory circuit. Circuit 510 uses the lookup table in the high-speed ADC and memory circuit to convert the input voltage Vin, thereby reducing the area and power requirements of circuit 510. In one example, device 500 is an RF sampling receiver, and circuit 510 enables device 500 to operate at GSPS speed.

[0063] Figure 6 is a block diagram of a backend analog-to-digital converter 600 according to an exemplary embodiment. The backend ADC 600 is similar in connection and operation to the backend ADC 124 shown in Figure 1. The ADC 106 shown in Figure 1 has a front end and a back end. The front end may implement a voltage delay function. In one example, the front end includes a preamplifier array and a delay multiplexer as shown in Figure 1. The back end may implement a delay digital function. According to one aspect of this disclosure, the front end of the ADC 106 converts the analog signal Vin received from the multiplexer M112 into a delayed signal similar to the signals OUT_P and OUT_M generated in Figure 3. In Figure 6, these delayed signals are represented as A0 and B0 on ​​lines 788 and 790, and the timing of the delayed signals A0 and B0 represents the input voltage Vin. A front-end that can be used to generate delayed signals A0 and B0 based on an input voltage Vin may be constructed and operated as described, for example, in U.S. Patent No. 10,673,456 (based on U.S. Patent No. 16 / 410,698). The front-end may include, for example, the conversion and folding circuit described in U.S. Patent No. 10,673,456, which includes a voltage delay converter block including a preamplifier for converting a voltage signal to a delayed signal, and a folding block including logic gates coupled to the preamplifier for selecting which of the delayed signals arrive first and which arrive later.

[0064] An example of a voltage delay device that may be incorporated within the front end of ADC106 and used to generate delayed signals A0 and B0 based on an input voltage Vin is shown in U.S. Patent Application No. 17 / 131,981, filed December 23, 2020. A voltage delay device constructed in accordance with U.S. Patent Application No. 17 / 131,981 may have, for example, first and second comparators connected to first and second lines carrying a complementary voltage representing the input voltage Vin to generate first and second output signals during the active phase when the complementary voltage reaches a suitable threshold voltage, so that the delay between the output signals represents the input voltage Vin. However, this disclosure is not limited to the devices and processes described in detail herein. Other suitable devices may implement a suitable voltage delay function within the front end of ADC106. As stated above, the entire disclosure of U.S. Patent No. 10,673,456 and U.S. Patent Application No. 17 / 131,981 is incorporated herein by reference. [Patent Document 6] U.S. Patent Application No. 17 / 131,981

[0065] The backend ADC 106 may have, for example, a multibit stage 798 and the first to i-th single-bit stages 7102 and 7104 connected in series with the multibit stage 798. If desired, the backend may have three, four, or more such single-bit stages (i=3, 4, or more). The single-bit stages 7102 and 7104 shown in Figure 6 are examples of continuous nonlinear stages. The backend ADC 600 receives delayed signals A0 and B0 from the frontend voltage delay circuit. The timing of the delayed signals A0 and B0 has a delay representing the input voltage Vin. The backend ADC 600 works with a calibration engine 602 (similar to the calibration engine 102 shown in Figure 1) and a memory circuit (similar to the memory circuit 108 shown in Figure 1) to generate the corresponding multibit digital code, which is produced as the final output 130 (Figure 1). Therefore, the final output 130 corresponds to a value that closely approximates the input voltage Vin.

[0066] The multi-bit stage 798 may have delay circuits and delay converters operating in parallel on lines 630, 632, 634, and 636 to generate M bits of digital information. In the illustrated example, M = 2. However, M may be greater than 2. This disclosure is not limited to the illustrated example. The delay residue from the multi-bit stage 798 may be combined by a combiner 604 and applied to a first single-bit stage 7102. If desired, the first to i-th single-bit stages 7102 and 7104 may be constructed and operated as a continuous stage to provide each bit of the digital information to a calibration engine 602.

[0067] The first stage 798 may have, for example, four delay comparators 606, 608, 610, and 612, and is connected to the combiner 604. Some exemplary embodiments may be implemented using a first stage having fewer or more delay comparators than four. In the exemplary embodiment shown in the figure, the first stage 798 generates two bits of digital information for the calibration engine 602. In the exemplary embodiment, each of the consecutive stages 7102 and 7104 generates a single bit of digital information for the calibration engine 602.

[0068] In the example shown, the rising edge of signal B0 on ​​line 790 precedes the rising edge of signal A0 on line 788. The first signal A0 is applied to the threshold input 794 of delay comparators 606, 608, 610, and 612. In the configuration shown, for example, delay comparators 606, 608, 610, and 612 are essentially identical to one another. The second signal B0 is applied to four different delay circuits 614, 616, 618, and 620, which generate four corresponding signals B04, B03, B02, and B01 on their respective lines 622, 624, 626, and 628.

[0069] The timing of the corresponding signals B04, B03, B02, and B01 is delayed relative to the timing of signal B0 on ​​line 790 by a different known amount, which is either less than or equal to the maximum gain of the front end. The delayed signals B04, B03, B02, and B01 are applied to the first input 792 of the respective delay comparators 606, 608, 610, and 612. The first delay comparator 606 emits a code signal on line 630 indicating which signal (B04 or A0) arrives at the first delay comparator 606 first. Similarly, the second delay comparator 608 emits a code signal on line 632 indicating which signal (B03 or A0) arrives at the second delay comparator 608 first. Similarly, the third and fourth delay comparators 610 and 612 issue code signals on lines 634 and 612 indicating which signal arrives at the third and fourth delay comparators 610 and 612 first.

[0070] Because the delay circuits 614, 616, 618, and 620 are different from each other, the timing of the rising edges of the delayed signals B04, B03, B02, and B01 are different from each other. Each of the delay comparators 606, 608, 610, and 612 issues a coded signal to the calibration engine 602 on their respective lines 630, 632, 634, and 636. The coded signals on lines 630, 632, 634, and 636 are functionally related to the timing difference between the rising edges of the input signals A0 and B0, and therefore functionally related to the input voltage Vin.

[0071] Because the amounts of delay provided by the four delay comparators 606, 608, 610, and 612 are different, the code signals 630, 632, 634, and 636 provide four binary data points to determine a 2-bit output. For example, if B0 precedes A0 and B01 precedes A0, the calibration engine 602 determines that the delay between the timings of signals A0 and B0 is greater than the delay contributed by the fourth delay circuit 620. Similarly, if B0 precedes A0 and A0 precedes B02, B03, and B04, the calibration engine 602 determines that the delay between the timings of signals A0 and B0 is less than each of the delays contributed by the third, second, and first delay circuits 618, 616, and 614.

[0072] If desired, the structure and operation of delay comparators 606, 608, 610, and 612 may be similar to those of delay comparator 782, which is described below. In operation, delay comparators 606, 608, 610, and 612 generate their respective delay signals IN4, IN3, IN2, and IN1 on their respective output lines 638, 640, 642, and 644. The delay signals IN4, IN3, IN2, and IN1 are applied to combiner 604 by output lines 638, 640, 642, and 644. In the configuration shown, the delay circuits 614, 616, 618, and 620 are different from each other and contribute to different delay amounts, while delay comparators 606, 608, 610, and 612 are essentially the same. Therefore, the timing of the rising edges of the delay signals IN4, IN3, IN2, and IN1 are different from each other.

[0073] Figure 7 is a block diagram of a combiner 604 for connecting the multi-bit stage shown in Figure 6 to the first single-bit stage of the single-bit stage, according to an exemplary embodiment. Combiner 604 is similar in connection and operation to combiner 604 shown in Figure 6. Combiner 604 has two fifth delay circuits 650 and 652, two AND gates 654 and 656, and a sixth delay circuit 658. In the shown configuration, the fifth delay circuits 650 and 652 are essentially identical to each other. However, this disclosure is not limited to the details of the configurations illustrated and described herein. Third and fourth delay signals IN2 and IN1 are applied to the fifth delay circuits 650 and 652 on output lines 642 and 644, and first and second delay signals IN4 and IN3 are applied to the AND gates 654 and 656 on output lines 638 and 640. The output signals from the fifth delay circuits 650 and 652 are also applied to AND gates 654 and 656 on conductive lines 662 and 664, respectively. The output signal from one AND gate 656 is applied to the sixth delay circuit 658 on conductive line 660, and the other AND gate 654 generates signal A1 on conductive line 788A1. The sixth delay circuit 658 generates signal B1 on conductive line 790B1.

[0074] In operation, the timing of the rising edges of the signals output from the fifth and sixth delay circuits 650, 652, and 658 on conductive lines 662, 664, and 790B1 is delayed relative to the timing of the rising edges of the signals input to the delay circuits 650, 652, and 658, respectively. The timing of the rising edges of the signals output from AND gates 654 and 656 on lines 788A1 and 660 corresponds to the timing of the later-arriving signals input to AND gates 654 and 656, respectively. The relative timing of the rising edges of signals A1 and B1 on lines 788A1 and 790B1 is functionally (i.e., predictably) related to the input voltage Vin (Figure 1). In other words, the delay circuits 650, 652, and 658 and the logic gates 654 and 656 establish a transfer function between the delays of the incoming signals IN4, IN3, IN2, and IN1 and the delays of the first and second signals A1 and B1.

[0075] For the configuration shown, the transfer function is as follows: [A] If the timing of the signal on line 638 precedes the timing of the signal on line 662 (the timing of the signal on line 662 corresponds to the timing of the signal on line 642 delayed by the fifth delay circuit 650), then the timing of the signal on line 788A1 corresponds to the timing of the signal on line 662. However, if the timing of the signal on line 662 precedes the timing of the signal on line 638, then the timing of the signal on line 788A1 corresponds to the timing of the signal on line 638. [B] If the timing of the signal on line 640 precedes the timing of the signal on line 664 (the timing of the signal on line 664 corresponds to the timing of the signal on line 644 delayed by the fifth delay circuit 652), then the timing of the signal on line 660 corresponds to the timing of the signal on line 664. However, if the timing of the signal on line 664 precedes the timing of the signal on line 640, then the timing of the signal on line 660 corresponds to the timing of the signal on line 640. [C] The timing of the signal on line 790B1 corresponds to the timing of the signal on line 660, which is delayed by the sixth delay circuit 658.

[0076] The amount by which delay circuits 650, 652, and 658 delay the signals passing through them can be selected to maximize or improve the gain of the first and second signals A1 and B1 as much as possible. The combiner 604 operates in delay mode, and the gain is related to the delay (not voltage). If the gain of the first and second signals A1 and B1 is too low, it means that the timing of the first and second signals A1 and B1 is too close to each other, and the information represented by the relative timing of those signals may be difficult to resolve.

[0077] One aspect of the present disclosure is such that the timing of signals on lines 788A1 and 790B1 is functionally (i.e., predictably) related to the timing of signals on lines 638, 640, 642, and 644. If a certain set of signal timings on lines 638, 640, 642, and 644 results in a first set of signal timings on lines 788A1 and 790B1, then it can be predicted that whenever the same set of signal timings occurs on lines 638, 640, 642, and 644, the same first set of signal timings will occur on lines 788A1 and 790B1. Similarly, if another set of signal timings on lines 638, 640, 642, and 644 results in a second set of signal timings on lines 788A1 and 790B1, then whenever the other set of signal timings occurs on lines 638, 640, 642, and 644, it can be predicted that the second set of signal timings will occur on lines 788A1 and 790B1. Furthermore, since the signal timings on lines 638, 640, 642, and 644 are functionally (i.e., predictably) related to the input voltage Vin, the signal timings on lines 788A1 and 790B1 are also functionally related to the input voltage Vin.

[0078] Referring again to Figure 6, signals A1 and B1 generated by combiner 604 (similar to combiner 604 in Figure 7) are applied to the second stage 7102 on output lines 788A1 and 790B1, respectively, similar to lines 788A1 and 790B1 (in Figure 7). The second stage (first remainder stage) 7102 is coupled to the first stage 798 (via combiner 604), and the i-th stage 7104 (which is the second remainder stage in the illustrated example) is coupled to the second stage 7102.

[0079] In the illustrated example, the second to i-th stages 7102 and 7104 each include AND gates (e.g., AND gate 776 in stage 7102 and AND gate 778 in stage 7104) and delayed comparators (e.g., delayed comparator 782 in stage 7102 and delayed comparator 784 in stage 7104). However, the illustrated AND gates are merely examples of logic gates that may be used in accordance with this disclosure. If desired, this disclosure may be implemented with or without AND gates, and / or with or without gates other than AND gates.

[0080] Furthermore, in the illustrated configuration, AND gates 776 and 778 may be essentially identical to each other, and delay comparators 782 and 784 may be essentially identical to each other. Conductive output lines 788A1 and 790B1 from combiner 604 are coupled to the inputs of the first AND gate 776 and delay comparator 782. Specifically, conductive line 788A1 is coupled to the first input 792 of delay comparator 782, and conductive line 790B1 is coupled to the threshold input 794 of delay comparator 782.

[0081] The output line 788A2 from the AND gate 776 is electrically coupled to one of the inputs of the AND gate 778 and to the input 792 of the delay comparator 784. The conductive line 790B2 from the first delay comparator 782 is electrically coupled to one of the other inputs of the AND gate 778 and to the threshold input 794 of the delay comparator 784. The pattern created by the second and third stages 7102 and 7104 can be continued for any number of additional stages as desired. Each successive stage has an AND gate and a delay comparator that is essentially identical to the AND gate and delay comparator of the second and third stages 7102 and 7104, and is similarly electrically coupled to the AND gate and delay comparator of the preceding stage.

[0082] In operation, signals AN and BN (for stages 7102 and 7104, respectively, N=1, 2, 3...) are applied to one of the AND gates 776 and 778, causing the AND gates 776 and 778 to generate the corresponding signal AN+1. For each of the AND gates 776 and 778, the timing of the rising edge of signal AN+1 tracks the timing of the rising edge of the later-arriving signal AN and BN. In particular, for each of the AND gates 776 and 778, the timing of the rising edge of signal AN+1 is equal to the timing of the rising edge of the earlier-arriving signal AN and BN plus a time amount related to the degree to which the rising edge of the later-arriving signal AN and BN lags behind the rising edge of the earlier-arriving signal AN and BN.

[0083] Figure 8 is a graph showing the AND gate delay and comparator delay generated by the AND gate and delay comparator, respectively, of the backend ADC of Figure 6 according to the exemplary embodiment, where the AND gate delay and comparator delay are functions of the input signal delay. The graph includes the X axis (T_IN) and the Y axis (output delay). The AND gate (e.g., AND gates 776, 778) delay and comparator (e.g., delay comparators 782, 784) delay are functions of the input signal delay according to the exemplary embodiment. The input signal delay is the delay between signals received by the AND gate or the delay converter. As shown, the AND gate delay 7100 contributed by each AND gate is linearly related to the absolute value of the input signal delay T_IN, where the input signal delay T_IN is the timing difference between signals AN and BN input to each AND gate, where N is an integer, N is equal to 1 in stage 7102, and N is equal to 2 in stage 7104. In the illustrated configuration, the relationship between the AND gate delay 7100 and the input T_IN is linear, regardless of whether AN or BN comes first or second.

[0084] Signals AN and BN are also applied to inputs 792 and 794, respectively, of delay comparators 782 and 784, causing the delay comparators 782 and 784 to generate the corresponding signal BN+1. For each of the delay comparators 782 and 784, the timing of the rising edge of signal BN+1 tracks the timing of the rising edge of the first of signals AN and BN to arrive. In particular, for each of the delay comparators 782 and 784, the timing of the rising edge of signal BN+1 is equal to (1) the timing of the rising edge of the first of signals AN and BN to arrive plus (2) a comparator delay of 7200, which is logarithmically inversely related to the absolute value of the input signal delay T_IN (in other words, the comparator delay is larger for more similar input values, and smaller when the difference between the two inputs to the comparator is larger).

[0085] Figure 9 is a graph showing the output signal delay as a function of the input signal delay in Figure 8, according to the exemplary embodiment. Subtracting the AND gate delay 7100 from the comparator delay 7200 results in the output signal delay T_OUT for any given single-bit stages 7102 and 7104. When the absolute value of the input signal delay T_IN is less than the threshold delay T_THRES, the output signal delay T_OUT is a positive value (meaning that the rising edge of signal BN+1 generated by the respective delay comparators 782 and 784 precedes the rising edge of signal AN+1 generated by the respective AND gates 776 and 778). On the other hand, when the absolute value of the input signal delay T_IN is greater than the threshold delay T_THRES, the output signal delay T_OUT is a negative value (meaning that the rising edge of signal BN+1 lags behind the rising edge of the corresponding signal AN+1). The positive or negative sign of the output signal delay T_OUT is reported to the calibration engine 602 on the signal line of the continuous delay comparator.

[0086] In operation, the first delay comparator 782 issues a first coded signal ("1" or "0") on a digital line 708 (an example of a digital output) to the calibration engine 602. The first coded signal (an example of a digital signal as described herein) reflects the order of the rising edges of signals A1 and B1 applied to the first input 792 and threshold input 794 of the delay comparator 782, based on which of the rising edges of signals A1 and B1 is received first by the first delay comparator 782. The AND gate 776 and the delay comparator 782 generate signals A2 and B2, which are applied to the AND gate 778 and the delay comparator 784 of the third stage 7104. The delay comparator 784 outputs a second coded signal ("1" or "0") on a second digital line 712 to the calibration engine 602. The second coded signal reflects the order in which the rising edges of signals A2 and B2 are applied to inputs 792 and 794 of the second delayed comparator 784, based on which of the rising edges of signals A2 and B2 is received first by the second delayed comparator 784.

[0087] Since the delay between signals A1 and B1 is predictable as a function of the input voltage Vin, and vice versa, and the delay between signals AN+1 and BN+1 output by a successive stage is predictable as a function of signals AN and BN received from the preceding stage, the code signal output by the stage cascade delay comparator is predictable as a function of the input voltage Vin, and vice versa. Therefore, the code composed of the code signals can be reliably compared with a given correlation to determine an approximation of the input voltage Vin. In operation, the timing of signals on lines 788A1 and 790B1 is functionally (i.e., predictably) related to the timing of signals on lines 788 and 790, as described above. The timing of signals on lines 788A2 and 790B2 is functionally (i.e., predictably) related to the timing of signals on lines 788A1 and 790B1. For example, the timing of signals on lines 788A3 and 790B3 is functionally (i.e., predictably) related to the timing of signals on lines 788A2 and 790B2.

[0088] Furthermore, if a certain set of signal timings on lines 788 and 790 results in a first set of signal timings on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc., then it can be predicted that whenever the same set of signal timings occurs on lines 788 and 790, the same first set of signal timings will always occur on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc. Similarly, if another set of signal timings on lines 788 and 790 results in a second set of signal timings on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc., then it can be predicted that whenever the other set of signal timings occurs on lines 788 and 790, the same second set of signal timings will occur on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc. Also, since the timing of the signals on lines 788 and 790 is functionally (i.e., predictably) related to the input voltage Vin, the timing of the signals on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc., which determine the code signals used to construct the output code, is also functionally related to the input voltage Vin.

[0089] Figure 10 is a schematic diagram showing an example of a comparator circuit merged with the sign-out and delay-out circuits for the backend ADC of Figure 6, according to an exemplary embodiment. The delay comparator 782 has a comparator circuit 2083 having first, second, third, fourth, fifth, sixth, seventh, and eighth transistors 2400, 2402, 2404, 2406, 2408, 2410, 2412, and 2414. In the illustrated example, the timing of the delay comparator 782 is controlled by a signal from the clock (CLK) applied to the gates of the first and fourth transistors 2400 and 2406 on conductive line 2122. The first and second signals A1 and B1 on lines 788A1 and 790B1 are applied to the gates of the sixth and fifth transistors 2410 and 2408, respectively. The drains of the first, second, and fifth transistors 2400, 2402, and 2408 are electrically connected to each other and to the gates of the third and eighth transistors 2404 and 2414 via the first conductive line 2416. The drains of the third, fourth, and sixth transistors 2404, 2406, and 2410 are similarly electrically connected to each other and to the gates of the second and seventh transistors 2402 and 2412 via the second conductive line 2418.

[0090] The first and second conductive lines 2416 and 2418 of the comparator circuit 2083 are electrically connected to the sign-out circuit 2420 via the third and fourth conductive lines 2422 and 2424, respectively. As shown in the figure, the sign-out circuit 2420 is merged with the comparator circuit 2083. The sign-out circuit 2420 has first, second, third, and fourth transistors 2426, 2428, 2430, and 2432. The third conductive line 2422 is electrically connected to the gates and sources of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively, while the fourth conductive line 2424 is electrically connected to the sources and gates of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively.

[0091] During operation, when the delay comparator 782 is enabled by the clock signal on line 2122, a code signal is generated in the code-out circuit 2420 on line 708. The code signal is transferred on line 708 to the zero calibration engine 602, which represents the order in which output signals A1 and B1 arrive at the first and threshold inputs 792 and 794 of the delay comparator 782. The operation of the code-out circuit 2420 is controlled by the inverted clock signal CLKZ applied to the gates of the third and fourth transistors 2430 and 2432 of the code-out circuit 2420. The inverted clock signal CLKZ is an inverted version of the clock signal applied to the comparator circuit 2083 on line 2122.

[0092] Third and fourth conductive lines 2422 and 2444 are also electrically connected to the delay-out circuit 2450. As shown in the figure, the delay-out circuit 2450 is merged with the comparator circuit 2083. The delay-out circuit 2450 has first, second, and third transistors 2442, 2444, and 2446. The third conductive line 2422 is electrically connected to the gate and source of the first and second transistors 2442 and 2444 of the delay-out circuit 2450, respectively, while the fourth conductive line 2424 is electrically connected to the source and gate of the first and second transistors 2442 and 2444 of the delay-out circuit 2450, respectively.

[0093] During operation, a delayed signal B2 is generated on line 790B2, which is electrically connected to the drains of both the first and second transistors 2442 and 2444 of the delay-out circuit 2450. The timing of the rising edge of the delayed signal B2 on line 790B2 relative to the timing of the rising edges of signals A1 and B2 on inputs 792 and 794 is a comparator delay 7102. The operation of the delay-out circuit 2450 is controlled by the same inverting clock signal CLKZ, which is applied to the third and fourth transistors 2430 and 2432 of the sign-out circuit 2420. The inverting clock signal CLKZ is applied to the gate of the third transistor 2446 of the delay-out circuit 2450. The drain of the third transistor 2446 of the delay-out circuit 2450 is electrically connected to the drains of the first and second transistors 2442 and 2444 of the delay-out circuit 2450.

[0094] The term “coupled” is used throughout this specification. This term may encompass connections, communications, or signaling paths that enable a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform a certain action, in the first example, device A is coupled to device B, or in the second example, device A is coupled to device B via intervening component C, such that device B is controlled by device A via a control signal provided by device A, provided that intervening component C does not substantially alter the functional relationship between device A and device B.

[0095] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that function at the time of manufacture by the manufacturer, and / or may be configured (or reconfigurable) after manufacture by the user to perform that function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the structure and / or layout of the hardware components and the interconnection of the devices, or a combination thereof.

[0096] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are used in general to mean an interconnection or end between device elements, circuit elements, integrated circuits, devices, or other electronic circuit or semiconductor components.

[0097] Circuits or devices described herein as including specific components may instead be adapted to be coupled to those elements to form the circuit elements or devices described. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage sources and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., semiconductor dies and / or integrated circuit (IC) packages), and may also be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either at the time of manufacture or after manufacture, for example, by the end user and / or a third party.

[0098] While this specification describes the use of specific transistors, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon FET ("MOSFET") may be used instead of an n-type MOSFET with little to no modification to the circuit. Other types of transistors (such as bipolar junction transistors (BJTs)) may also be used.

[0099] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead, with little to no modification to the remaining circuit elements. For example, metal-oxide-silicon FETs ("MOSFETs" (n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs - e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used instead of or in connection with the devices disclosed herein. Transistors may be depletion-mode devices, drain-extension devices, strengthening-mode devices, natural transistors, or other types of device structure transistors. Devices may also be mounted in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs). While some exemplary embodiments suggest that certain elements are included in the integrated circuit and others are outside the integrated circuit, in other exemplary embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being external to an integrated circuit may be included in the integrated circuit, and / or some features described as being internal to an integrated circuit may be incorporated externally. As used herein, the term “integrated circuit” means one or more circuits that are (i) incorporated in / on a semiconductor substrate, (ii) incorporated in a single semiconductor package, (iii) incorporated in the same module, and / or (iv) incorporated in / on the same printed circuit board.

[0100] The circuits described herein are reconfigurable to include replacement components to provide functionality available prior to the replacement of components and at least partially similar functionality. Components shown as registers generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the indicated register, unless otherwise specified. For example, a register or capacitor illustrated and described herein as a single component may instead be multiple registers or capacitors coupled in parallel between the same nodes, each. For example, a register or capacitor illustrated and described herein as a single component may instead be multiple registers or capacitors coupled in series between the same two nodes as a single register or capacitor, each.

[0101] The use of the term "grounding" in the preceding description includes chassis grounding, grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings in this description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the indicated value.

[0102] Modifications are possible in the embodiments described, and other embodiments within the scope of the claims are possible.

Claims

1. It is a circuit, A multiplexer configured to receive an input voltage and a calibration signal, An analog-to-digital converter (ADC) coupled to the multiplexer, configured to generate an output code in response to the calibration signal, A memory circuit coupled to the ADC, configured to store an input code representing the calibration signal at an address corresponding to the output code, wherein the stored input code includes an index value and a coarse value. Includes, The aforementioned index value is 1 when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code, and 0 when the input code corresponding to the current output code is equal to the input code corresponding to the previous output code. A circuit in which the aforementioned crude value is the cumulative sum of the aforementioned index values.

2. The circuit according to claim 1, A calibration engine coupled to the memory circuit and the ADC, the calibration engine being configured to generate a plurality of input codes, A digital-to-analog converter (DAC) coupled to the calibration engine, configured to generate the calibration signal in response to a certain input code of the plurality of input codes, A circuit that further includes the following.

3. The circuit according to claim 1, A circuit in which the output code is stored as an address and the input code is stored as data.

4. The circuit according to claim 1, A circuit in which the index value is 1 when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code, and the index value is 0 when the input code corresponding to the current output code is equal to the input code corresponding to the previous output code.

5. The circuit according to claim 1, A circuit in which the gross value for the current output code is the sum of the index values ​​generated for all previous output codes and the index value generated for the current output code.

6. The circuit according to claim 1, A circuit in which the output code includes M bits and L bits.

7. The circuit according to claim 6, The output code is reduced to M bits, L bits are added to the index value, and the rough value is 2 Ｌ A circuit that stores information bit by bit.

8. The circuit according to claim 1, The ADC, A plurality of preamplifiers, each preamplifier configured to compare one of the input voltage and the calibration signal with a threshold voltage, A delay multiplexer coupled to the plurality of preamplifiers, configured to generate a delay signal based on one of the outputs of the plurality of preamplifiers, A backend ADC configured to generate the output code in response to the delay signal, A circuit that includes this.

9. The circuit according to claim 8, A circuit in which each preamplifier has a different threshold voltage.

10. The circuit according to claim 8, The circuit is configured to operate in mission mode, and in mission mode, The multiplexer is further configured to provide the input voltage to the ADC, The ADC is further configured to generate a low code in response to the input voltage, and the input code stored at the address corresponding to the low code is generated as the final output.

11. It is a method, The multiplexer receives the input voltage and calibration signal, The analog-to-digital converter (ADC) generates an output code in response to the calibration signal, A memory circuit stores an input code representing the calibration signal at an address corresponding to the output code, wherein the stored input code includes an index value and a coarse value. Includes, The aforementioned index value is 1 when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code, and 0 when the input code corresponding to the current output code is equal to the input code corresponding to the previous output code. A method wherein the aforementioned gross value is the cumulative sum of the aforementioned index values.

12. The method according to claim 11, The calibration circuit generates multiple input codes, A digital-to-analog converter (DAC) generates a calibration signal in response to a certain input code of the plurality of input codes, Methods that further include the above.

13. The method according to claim 11, A method further comprising storing the output code as an address and the input code as data using the memory circuit.

14. The method according to claim 11, A method further comprising the summing of all index values ​​generated for all previous output codes in order to obtain a rough value for the current output code by a calibration circuit.

15. The method according to claim 11, A method wherein the output code includes M bits and L bits.

16. The method according to claim 15, The calibration circuit reduces the output code to M bits, The calibration circuit adds an L bit to the index value, The memory circuit determines the rough value by 2 Ｌ Storing bit by bit, Methods that further include the above.

17. The method according to claim 11, The input voltage is provided to the ADC by a multiplexer, The ADC generates low code in response to the input voltage, The memory circuit generates the input code stored at the address corresponding to the low code as the final output, Methods that further include the above.

18. It is a device, Processor and A memory coupled to the aforementioned processor, A circuit is formed which the processor and the memory are coupled, A multiplexer configured to receive an input voltage and a calibration signal, An analog-to-digital converter (ADC) coupled to the multiplexer, configured to generate an output code in response to the calibration signal, A memory circuit coupled to the ADC, configured to store an input code representing the calibration signal at an address corresponding to the output code, wherein the stored input code includes an index value and a coarse value. The circuit includes, Includes, The aforementioned index value is 1 when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code, and 0 when the input code corresponding to the current output code is equal to the input code corresponding to the previous output code. A device in which the aforementioned gross value is the cumulative sum of the aforementioned index values.

19. The device according to claim 18, The aforementioned circuit, A calibration engine coupled to the memory circuit and the ADC, the calibration engine being configured to generate a plurality of input codes, A digital-to-analog converter (DAC) coupled to the calibration engine, configured to generate the calibration signal in response to a certain input code of the plurality of input codes, Devices that further include the following.

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