Semiconductor equipment

Abstract

A highly reliable semiconductor device. The semiconductor device has: an oxide semiconductor layer that has a first surface and a second surface that is on the reverse side from the first surface; a gate electrode that is opposite the oxide semiconductor layer; a gate insulation layer that is between the oxide semiconductor layer and the gate electrode; and a pair of first electrodes that each contact the first surface of the oxide semiconductor layer. In a region that is near an end part of at least one of the first electrodes of the pair of first electrodes, the oxide semiconductor layer has a region in which the composition ratio of nitrogen is at least 2% to a depth of 2 nm from the first surface.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device in which an oxide semiconductor is used as a channel. [Background technology]

[0002] Recently, the development of semiconductor devices using oxide semiconductors as channels has been progressing as an alternative to amorphous silicon, low-temperature polysilicon, and single-crystal silicon (for example, Patent Document 1). Semiconductor devices using oxide semiconductors as channels can be formed with a simple structure and low-temperature process, similar to semiconductor devices using amorphous silicon as channels. Semiconductor devices using oxide semiconductors as channels are known to have higher mobility than semiconductor devices using amorphous silicon as channels. Semiconductor devices using oxide semiconductors as channels are known to have very low off-current.

[0003] For semiconductor devices using oxide semiconductors as channels to operate stably, it is important to supply more oxygen to the oxide semiconductor during the manufacturing process and reduce the oxygen vacancies formed in the oxide semiconductor. As one method of supplying oxygen to an oxide semiconductor, Patent Document 1 discloses a technique in which an insulating layer covering the oxide semiconductor is formed under conditions in which the insulating layer contains more oxygen. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2018-78339 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, an insulating layer formed under conditions containing more oxygen contains many defects. Due to this, characteristic abnormalities of a semiconductor device or characteristic fluctuations in a reliability test, which are considered to be caused by electrons being trapped in these defects, occur. On the other hand, when using an insulating layer with few defects, the amount of oxygen contained in the insulating layer cannot be increased. Therefore, oxygen cannot be sufficiently supplied from the insulating layer to the oxide semiconductor. Thus, even when an insulating layer containing a large amount of oxygen is used as the insulating layer covering the oxide semiconductor, it is required to realize a semiconductor device structure and a manufacturing method thereof for improving the reliability of the semiconductor device.

[0006] One of the problems of an embodiment of the present invention is to realize a highly reliable semiconductor device.

Means for Solving the Problems

[0007] A semiconductor device according to an embodiment of the present invention includes an oxide semiconductor layer having a first surface and a second surface opposite to the first surface, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, and a pair of first electrodes respectively contacting the first surface of the oxide semiconductor layer, and in a region near an end of at least one of the pair of first electrodes in the oxide semiconductor layer, the oxide semiconductor layer has a region with a nitrogen composition ratio of 2% or more within a depth range of 2 nanometers or less from the first surface.

Brief Description of the Drawings

[0008] [Figure 1] It is a cross-sectional view showing an outline of a semiconductor device according to an embodiment of the present invention. [Figure 2] It is a plan view showing an outline of a semiconductor device according to an embodiment of the present invention. [Figure 3] It is an enlarged cross-sectional view of a part of a semiconductor device according to an embodiment of the present invention. [Figure 4] It is a cross-sectional STEM image of a semiconductor device according to an embodiment of the present invention. [Figure 5]It is a diagram showing the result of composition analysis of the semiconductor device of the comparative example. [Figure 6] It is a diagram showing the result of composition analysis of the semiconductor device of the comparative example. [Figure 7] It is a diagram showing the result of composition analysis of the semiconductor device according to an embodiment of the present invention. [[ID=,7]] [Figure 8] It is a diagram showing the result of composition analysis of the semiconductor device according to an embodiment of the present invention. [Figure 9] It is a diagram showing the result of composition analysis of the semiconductor device according to an embodiment of the present invention. <, [Figure 10] It is a diagram showing the result of composition analysis of the semiconductor device according to an embodiment of the present invention. [Figure 11] It is a diagram showing the result of the reliability test performed on the semiconductor device of the comparative example. [Figure 12] It is a diagram showing the result of the reliability test performed on the semiconductor device according to an embodiment of the present invention. [Figure 13] It is a diagram showing the result of the reliability test performed on the semiconductor device according to an embodiment of the present invention. [Figure 14] It is a diagram showing the model of the simulation performed on the semiconductor device according to an embodiment of the present invention. [Figure 15] It is a diagram showing the result of the simulation performed on the semiconductor device according to an embodiment of the present invention. [Figure 16] It is a diagram showing the model of the simulation performed on the semiconductor device according to an embodiment of the present invention. <o [Figure 17] It is a diagram showing the result of the simulation performed on the semiconductor device according to an embodiment of the present invention. [Figure 18] It is an enlarged cross-sectional view of a part of the semiconductor device according to an embodiment of the present invention. [Figure 19] It is a cross-sectional view showing the manufacturing method of the semiconductor device according to an embodiment of the present invention. [Figure 20] It is a cross-sectional view showing the manufacturing method of the semiconductor device according to an embodiment of the present invention. [Figure 21] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] This is a cross-sectional TEM image of a semiconductor device according to one embodiment of the present invention. [Figure 24] This is a cross-sectional HAADF-STEM image of a semiconductor device according to one embodiment of the present invention. [Figure 25] This is the EDX mapping measurement result of a semiconductor device according to one embodiment of the present invention. [Figure 26] This is the EDX mapping measurement result of a semiconductor device according to one embodiment of the present invention. [Figure 27] This is the EDX mapping measurement result of a semiconductor device according to one embodiment of the present invention. [Figure 28] This is the EDX mapping measurement result of a semiconductor device according to one embodiment of the present invention. [Figure 29] This is a plan view showing an overview of a display device according to one embodiment of the present invention. [Figure 30] A block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. [Figure 31] This is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. [Figure 32] This is a cross-sectional view of a display device according to one embodiment of the present invention. [Figure 33] This is a plan view of the pixel electrodes and common electrodes of a display device according to one embodiment of the present invention. [Figure 34] This is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. [Figure 35] This is a cross-sectional view of a display device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] The embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with respect to previously shown drawings will be denoted by the same reference numeral followed by an alphabet, and detailed explanations may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upwards." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downwards." Thus, for the sake of explanation, the terms "up" or "downwards" are used, but for example, the substrate and the oxide semiconductor layer may be arranged in a way that is the opposite of what is shown in the figures. In the following explanation, for example, the expression "oxide semiconductor layer on the substrate" merely describes the upward and downward relationship between the substrate and the oxide semiconductor layer as described above, and other components may be arranged between the substrate and the oxide semiconductor layer. "Up" or "downwards" refers to the stacking order in a structure in which multiple layers are stacked. When referring to the pixel electrode above a transistor, the positional relationship between the transistor and the pixel electrode may not overlap in a plan view. On the other hand, when referring to the pixel electrode vertically above a transistor, it means a positional relationship where the transistor and the pixel electrode overlap in a plan view.

[0011] A "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, in the embodiments described later, liquid crystal display devices including a liquid crystal layer and organic EL display devices including an organic EL layer will be used as examples, but the structure in these embodiments can be applied to other display devices including the electro-optical layers described above.

[0012] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] The following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0014] <First Embodiment> A semiconductor device according to one embodiment of the present invention will be described with reference to Figures 1 to 17. The semiconductor device of the embodiment shown below may be used not only as a transistor used in a display device, but also as an integrated circuit (IC) such as a microprocessing unit (MPU), or as a memory circuit.

[0015] [Configuration of semiconductor device 10] The configuration of the semiconductor device 10 according to one embodiment of the present invention will be described using Figures 1 to 3. Figure 1 is a cross-sectional view showing an overview of the semiconductor device according to one embodiment of the present invention. Figure 2 is a plan view showing an overview of the semiconductor device according to one embodiment of the present invention. Figure 3 is an enlarged cross-sectional view of a part of the semiconductor device according to one embodiment of the present invention.

[0016] As shown in Figure 1, the semiconductor device 10 is provided above the substrate 100. The semiconductor device 10 includes a first gate electrode 110, a first gate insulating layer 120, a first oxide semiconductor layer 130, a first source electrode 141, a first drain electrode 143, a first insulating layer 150, an oxide layer 160, a first source wiring 171, and a first drain wiring 173. When the first source electrode 141 and the first drain electrode 143 are not particularly distinguished, these electrodes may be referred to as a pair of first electrodes 140 or simply as first electrodes 140. In the following description, when the first electrodes 140 are referred to, unless otherwise specified, it refers to a pair of first electrodes 140. When the first source wiring 171 and the first drain wiring 173 are not particularly distinguished, these wirings may be referred to as the first conductive layer 170.

[0017] The first gate electrode 110 is provided on the substrate 100. The first gate electrode 110 faces the first oxide semiconductor layer 130. The first gate insulating layer 120 is provided between the first gate electrode 110 and the first oxide semiconductor layer 130. In the example of Figure 1, the first gate electrode 110 and the first gate insulating layer 120 are provided below the first oxide semiconductor layer 130. The first electrode 140 is provided on the first gate insulating layer 120 and on the first oxide semiconductor layer 130. The first electrode 140 extends from the upper surface of the first gate insulating layer 120 up to the pattern edge of the first oxide semiconductor layer 130 and continues to the upper surface of the first oxide semiconductor layer 130. In other words, the first electrode 140 is in contact with the first oxide semiconductor layer 130 from above. The upper surface of the first oxide semiconductor layer 130 can be called the first surface 137, and the lower surface can be called the second surface 138. In this case, the first electrode 140 can be said to be in contact with the first surface 137 of the first oxide semiconductor layer 130.

[0018] The first oxide semiconductor layer 130 includes a channel region 131 between the first source electrode 141 and the first drain electrode 143. The first oxide semiconductor layer 130 in the channel region 131 is exposed from the first source electrode 141 and the first drain electrode 143. In other words, each of the first source electrode 141 and the first drain electrode 143 is in contact with the first oxide semiconductor layer 130 at the edge of the channel region 131.

[0019] The first insulating layer 150 covers the first oxide semiconductor layer 130 and the first electrode 140. Specifically, the first insulating layer 150 covers the first surface 137 of the first oxide semiconductor layer 130 sandwiched between the pair of first electrodes 140. The first insulating layer 150 is provided with first openings 151 and 153. The first opening 151 is an opening that reaches the first source electrode 141. The first opening 153 is an opening that reaches the first drain electrode 143. The oxide layer 160 is provided on top of the first insulating layer 150. The oxide layer 160 is provided with second openings 161 and 163. The second opening 161 is an opening continuous with the first opening 151. The second opening 163 is an opening continuous with the first opening 153.

[0020] The first conductive layer 170 is provided on top of the oxide layer 160 and inside the first openings 151 and 153. In a plan view, the first conductive layer 170 is provided in the same region as the oxide layer 160, except for the region where the first openings 151 and 153 are located. In other words, in a plan view, the oxide layer 160 is not provided in the region where the first conductive layer 170 is not provided, and the first insulating layer 150 is exposed from the oxide layer 160. The first conductive layer 170 is in contact with the first electrode 140 at the bottom of the first openings 151 and 153. The first conductive layer 170 is electrically connected to the first oxide semiconductor layer 130 via the first electrode 140.

[0021] In this embodiment, a configuration in which a bottom-gate transistor with a gate electrode located below the oxide semiconductor layer is used as the semiconductor device 10 is illustrated, but the configuration is not limited to this. For example, a top-gate transistor with a gate electrode located above the oxide semiconductor layer, or a dual-gate transistor with gate electrodes located both above and below the oxide semiconductor layer, may be used as the semiconductor device 10.

[0022] As shown in Figure 2, in a plan view, the first oxide semiconductor layer 130 is located inside the first gate electrode 110. In particular, in the region where the channel of the semiconductor device 10 is formed, the first oxide semiconductor layer 130 is located inside the first gate electrode 110. In other words, in a plan view, the outer edge of the pattern of the first oxide semiconductor layer 130 is surrounded by the outer edge of the pattern of the first gate electrode 110. In a plan view, the first electrode 140 crosses the first oxide semiconductor layer 130. In other words, the first electrode 140 intersects with the first oxide semiconductor layer 130. The second aperture 161 overlaps with the first aperture 151 in a plan view. The second aperture 163 overlaps with the first aperture 153 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0023] Figure 3 is an enlarged view of the region enclosed by the dotted line in Figure 1. As shown in Figure 3, a nitrogen-containing region 139 exists near the upper surface of the first oxide semiconductor layer 130 in the channel region 131 (the surface of the first oxide semiconductor layer 130 on the first insulating layer 150 side). The nitrogen-containing region 139 is located within a depth range of 2 nanometers, 3 nanometers, or 5 nanometers from the upper surface of the first oxide semiconductor layer 130. The nitrogen-containing region 139 contains nitrogen in addition to the main constituent elements of the first oxide semiconductor layer 130. The nitrogen composition ratio in the nitrogen-containing region 139 is 2 percent or more, 4 percent or more, or 6 percent or more.

[0024] As will be described in detail later, the first oxide semiconductor layer 130 has a region in the area near the edge of at least one of the pair of first electrodes 140 (particularly the first source electrode 141 side) where the nitrogen composition ratio is 2 percent or more, within a range of 2 nanometers in the depth direction from the upper surface (first surface 137) of the first oxide semiconductor layer 130. This configuration can improve the reliability of the semiconductor device 10. In this embodiment, the end of the channel region 131 on the first electrode 140 side and the end of the first electrode 140 on the channel region 131 side are in approximately the same position, but the configuration is not limited to this. For example, the channel region 131 and the first electrode 140 may be separated.

[0025] [Method for introducing nitrogen into nitrogen-containing region 139] One method for introducing nitrogen into the nitrogen-containing region 139 is to perform plasma treatment with the upper surface of the first oxide semiconductor layer 130 exposed. A first gate electrode 110, a first gate insulating layer 120, a first oxide semiconductor layer 130, and a first electrode 140 are formed on the substrate 100, and the first electrode 140 is etched to expose the first oxide semiconductor layer 130 of the channel region 131. Plasma treatment using a nitrogen-containing gas is performed on the surface of the first oxide semiconductor layer 130 exposed from the first electrode 140, thereby introducing nitrogen near the surface of the first oxide semiconductor layer 130. For example, by performing plasma treatment using N2O gas (hereinafter referred to as "N2O plasma treatment") as the plasma treatment, the nitrogen-containing region 139 is formed. The composition ratio of nitrogen in the nitrogen-containing region 139 is determined by controlling the processing time of the N2O plasma treatment.

[0026] [Regarding nitrogen content region 139] The effects of the nitrogen-containing region 139 and the nitrogen contained in that region on the semiconductor device 10 will be explained using Figures 4 to 17. Figure 4 is a cross-sectional STEM (Scanning Transmission Electron Microscope) image of a semiconductor device according to one embodiment of the present invention. In the STEM image of Figure 4, the first gate insulating layer 120 and the first insulating layer 150 are shown in black, the first oxide semiconductor layer 130 is shown in white, and the first electrode 140 is shown in gray.

[0027] [Analytical method for nitrogen-containing region 139] The compositional analysis of nitrogen-containing region 139 is performed using EDX (Energy Dispersive X-ray Spectrometer) installed in the STEM. For example, EDX analysis is performed at 256 points each in the vertical and horizontal directions for the STEM image shown in Figure 4. Based on the EDX spectral data obtained from the EDX analysis, the compositional ratio of the region specified by the designated line 201 and line extraction width 202 shown below is calculated.

[0028] In this embodiment, the apparatus and measurement conditions used for STEM observation and EDX analysis of nitrogen-containing region 139 are as follows. The apparatus and conditions shown below are examples, and the present invention is not limited to observations and analyses performed using the apparatus and conditions described below.

[0029] [STEM Observation] Equipment: JEOL JEM-ARM200F Condition: Acceleration voltage 200kV Magnification accuracy 10%

[0030] [EDX analysis] Equipment: JEOL JEM-ARM200F Condition: Acceleration voltage 200kV Beam diameter: approximately 0.2 nm Elemental analyzer JED-2300T X-ray detector Si drift detector Energy resolution: approximately 140 eV X-ray extraction angle 21.9° Solid angle 0.98sr Capture resolution: 256 x 256

[0031] The composition ratio is calculated for each point on the designated line 201 in Figure 4. In the calculation performed at each point on the designated line 201, EDX spectral data within the range specified by the line extraction width 202 are integrated. The following analysis results are the result of measurements taken to include the first insulating layer 150, the first oxide semiconductor layer 130, and the first gate insulating layer 120, as shown in Figure 4.

[0032] [Analysis results of region 139Z in the comparative example] Using Figures 5 and 6, the results of compositional analysis of the oxide semiconductor layer in the comparative example semiconductor device will be explained. The configuration of semiconductor device 10Z in the comparative example is almost the same as the configuration of semiconductor device 10 in this embodiment. Therefore, when explaining the configuration of semiconductor device 10Z, Figure 1 will be used for reference. However, in order to distinguish between the two, the reference numerals for each component in the comparative example are denoted by adding "Z" after the reference numerals for each component in this embodiment. As will be described in detail later, in the comparative example, a nitrogen-containing region is not formed on the upper surface of the first oxide semiconductor layer 130Z. Therefore, in the comparative example, the same region as the nitrogen-containing region 139 in this embodiment is called region 139Z.

[0033] Figure 5 shows the results of a compositional analysis of a comparative example semiconductor device. Figure 6 is a magnified view of the area near the boundary between the first insulating layer 150Z and the first oxide semiconductor layer 130Z in Figure 5. The horizontal axis ("Thk.") in Figures 5 and 6 indicates the position in the thickness direction of the designated line 201. The vertical axis in Figures 5 and 6 shows the composition ratio of silicon (left vertical axis) or the composition ratio of nitrogen (right vertical axis). Figures 5 and 6 show two types of spectra: the spectrum at 219Z, shown by a relatively thick line, shows the composition ratio of nitrogen, and the spectrum at 229Z, shown by a relatively thin line, shows the composition ratio of silicon.

[0034] Figures 5 and 6 show an example of a semiconductor device 10Z in which silicon oxide is used as the first gate insulating layer 120Z and the first insulating layer 150Z, and IGZO is used as the first oxide semiconductor layer 130Z. The silicon composition ratio (spectrum 229Z) changes abruptly at the boundary between the first gate insulating layer 120Z and the first oxide semiconductor layer 130Z, and at the boundary between the first insulating layer 150Z and the first oxide semiconductor layer 130Z. Nitrogen (spectrum 219Z) is detected in the first oxide semiconductor layer 130Z. In the comparative example in Figure 5, nitrogen is detected near the center of the first oxide semiconductor layer 130Z. On the other hand, as shown in Figure 6, nitrogen is hardly detected near the boundary between the first insulating layer 150Z and the first oxide semiconductor layer 130Z. In Figure 6, the boundary between the first insulating layer 150Z and the first oxide semiconductor layer 130Z can be defined as the position where the silicon spectrum detected in the first insulating layer 150Z drops to the background level. In Figure 6, the region within 2 nanometers of the boundary is defined as region 139Z.

[0035] [Analysis results of the nitrogen-containing region 139 according to this embodiment] The results of a compositional analysis of the first oxide semiconductor layer 130 of the semiconductor device 10 of this embodiment will be explained using Figures 7 and 8. Figure 7 is a diagram showing the results of a compositional analysis of a semiconductor device according to one embodiment of the present invention. Figure 8 is a magnified view of the area near the boundary between the first insulating layer 150 and the first oxide semiconductor layer 130 in Figure 7. In the following explanation, points that overlap with Figures 5 and 6 will be omitted from the explanation.

[0036] As shown in Figure 7, nitrogen is detected near the boundary between the first insulating layer 150 and the first oxide semiconductor layer 130 in the semiconductor device 10. As shown in Figure 8, in the depth direction from the boundary between the first insulating layer 150 and the first oxide semiconductor layer 130, there is a region within 2 nanometers (nitrogen-containing region 139) where the nitrogen composition ratio is approximately 2 percent (the exact value in the graph of Figure 8 is 1.88 percent) or more.

[0037] [Analysis results of nitrogen-containing region 139A according to this embodiment] Figures 9 to 10 illustrate the results of a compositional analysis of the first oxide semiconductor layer 130A in the semiconductor device 10A of this embodiment. Since the configuration of the semiconductor device 10A in this embodiment is almost the same as that of the semiconductor device 10 described above, Figure 1 will be used as a reference when explaining the configuration of the semiconductor device 10A. However, in order to distinguish between the two, the reference numerals for each component in Figures 9 to 10 are denoted by adding "A" after the reference numerals for each component in Figures 7 to 8. Figure 9 shows the results of a compositional analysis of a semiconductor device according to one embodiment of the present invention. Figure 10 shows magnified views of the area near the boundary between the first insulating layer 150A and the first oxide semiconductor layer 130A in Figure 9. The semiconductor device 10A has almost the same configuration as the semiconductor device 10 shown in Figures 7 and 8, but the conditions for introducing nitrogen into the first oxide semiconductor layer 130A are different. As a result, the nitrogen composition ratio in the nitrogen-containing region 139A of the semiconductor device 10A is higher than the nitrogen composition ratio in the nitrogen-containing region 139 of the semiconductor device 10.

[0038] As shown in Figure 9, in semiconductor device 10A, the nitrogen composition ratio near the boundary between the first insulating layer 150A and the first oxide semiconductor layer 130A is greater than the nitrogen composition ratio near the boundary between the first insulating layer 150 and the first oxide semiconductor layer 130 of semiconductor device 10. As shown in Figure 10, in the depth direction from the boundary between the first insulating layer 150A and the first oxide semiconductor layer 130A, there is a region within 2 nanometers (nitrogen-containing region 139A) where the nitrogen composition ratio is 6 percent or more (the exact value in the graph of Figure 10 is 6.09 percent).

[0039] [Reliability test results for semiconductor devices 10, 10A, and 10Z] Figures 11 to 13 show the results of reliability tests performed on the semiconductor devices of the comparative example and this embodiment. The reliability tests shown in Figures 11 to 13 are tests that evaluate NBTS (Negative Bias Thermal Stress) reliability. The conditions for the NBTS reliability test are as follows. • Light irradiation conditions: No irradiation (darkroom) Gate voltage: -40V Source and drain voltage: 0V • Stage temperature under stress: 125℃

[0040] As shown in Figures 11 to 13, the results of evaluating the electrical characteristics of each semiconductor device before stress application (0 sec) and after each stress application time (100 sec to 1000 sec) are displayed overlaid. The measurement conditions for the electrical characteristics of the semiconductor devices before and after stress application are as follows. Source-drain voltage: 0.1V, 10V Gate scanning voltage: -15V to 15V • Measurement environment: Darkroom • Stage temperature during measurement: 125°C (or "RT (room temperature)")

[0041] As shown in Figure 11, in the comparative example semiconductor device 10Z, as the stress application time increases, the threshold shifts positively, and the rise time of the ON current gradually slows down (hereinafter, these phenomena are referred to as "reliability degradation"). This reliability degradation is improved in Figures 12 and 13. In particular, in Figure 13, the positive shift in the threshold is almost nonexistent.

[0042] Referring to the nitrogen-containing regions 139, 139A, and 139Z shown in Figures 5 to 10, it is thought that the reason for the improved reliability of the semiconductor devices in Figures 11 to 13 is correlated with the nitrogen contained in nitrogen-containing regions 139 and 139A. In other words, it is thought that the greater the nitrogen composition ratio in nitrogen-containing regions 139 and 139A, the greater the improvement in reliability. No correlation was found between the amount of nitrogen in the region on the side of the first gate insulating layer 120, 120A, and 120Z from a position 10 nm from the top surface of the first oxide semiconductor layer 130, 130A, and 130Z, and the reliability of the semiconductor device. Therefore, it is thought that nitrogen near the top surface of the first oxide semiconductor layer (particularly in the range within a depth of 2 nanometers from the top surface) is involved in the improvement of semiconductor device reliability.

[0043] Defects may occur on the upper surface of the first oxide semiconductor layer 130 due to processes such as film deposition and etching of the first electrode 140. As will be described in detail later, the deterioration in reliability observed in the above reliability test is thought to be due to acceptor levels in the defects formed on the upper surface of the first oxide semiconductor layer 130. It is believed that the introduction of nitrogen into the first oxide semiconductor layer 130, which has acceptor level defects, reduces the number of acceptor levels and improves the aforementioned deterioration in reliability.

[0044] [Simulation to reproduce reliability degradation in semiconductor device 10] The simulation results that reproduced the deterioration of reliability in the semiconductor device 10 will be explained using Figures 14 to 17. Figures 14 and 16 show the simulation model performed on a semiconductor device according to one embodiment of the present invention. Figures 15 and 17 show the simulation results performed on a semiconductor device according to one embodiment of the present invention. In Figures 14 and 16, "SiO" corresponds to the first gate insulating layer 120 in Figure 1, "OS" corresponds to the first oxide semiconductor layer 130 in Figure 1, "S / D" corresponds to the first electrode 140, and "PASS" corresponds to the first insulating layer 150.

[0045] As shown in Figures 14 and 16, acceptor level defect regions (Defect Doping) are set on the surface of the OS. In Figure 14, Defect Doping is set across the entire channel region 131 and in the OS region corresponding to the upper surface of the first oxide semiconductor layer 130. In Figure 16, Defect Doping is set only in the OS region of the channel region 131 corresponding to the edge of the first electrode 140 (S / D).

[0046] The electrical characteristics (Id-Vg characteristics) of the semiconductor device shown in FIG. 15 are simulation results calculated by the simulation model of FIG. 14. The electrical characteristics (Id-Vg characteristics) of the semiconductor device shown in FIG. 17 are simulation results calculated by the simulation model of FIG. 16. The simulation results are the results calculated by changing the conditions for each defect density in "Defect Doping". In FIG. 15, the simulation results for the conditions where "Defect Doping" is zero (STD), 5×10 18 cm -2 、5×10 19 cm -2 、5×10 20 cm -2 are shown. In FIG. 17, the simulation results for the conditions where "Defect Doping" is zero (STD), 5×10 18 cm -2 、5×10 19 cm -2 、5×10 20 cm -2 、5×10 21 cm -2 、5×10 22 cm -2 are shown.

[0047] In the simulation results of both FIG. 15 and FIG. 17, as "Defect Doping" increases, the threshold value in the electrical characteristics of the semiconductor device 10 shifts positively, and the rise of the ON current becomes gentle. That is, in the above simulation results, the reliability degradation due to "Defect Doping" was reproduced. The reliability degradation is also reproduced in the simulation results of FIG. 17. Therefore, the defects of acceptor levels contained near the end of the first electrode 140 and near the upper surface of the first oxide semiconductor layer 130 in the channel region 131 of the semiconductor device 10 are considered to be the cause of the reliability degradation.

[0048] Considering the experimental results shown in Figures 4 to 13 and the simulation results shown in Figures 14 to 17, it is possible to improve the reliability degradation in the semiconductor device 10 by ensuring that, in the first oxide semiconductor layer 130 near the edge of the first electrode 140 within the channel region 131 (particularly near the edge of the first electrode 140 that functions as a source electrode), there is a region within 2 nanometers in the depth direction from the top surface of the first oxide semiconductor layer 130 where the nitrogen composition ratio is 2 percent or more.

[0049] [Materials of each component of the semiconductor device 10] As the substrate 100, a flexible substrate containing a resin and having flexibility can be used, such as a polyimide substrate, acrylic substrate, siloxane substrate, or fluororesin substrate. To improve the heat resistance of the substrate 100, impurities may be introduced into the above resins. In particular, if the semiconductor device 10 is a top-emission type display, the substrate 100 does not need to be transparent, so impurities that worsen the transparency of the substrate 100 can be used. On the other hand, if the substrate 100 does not need to be flexible, a rigid substrate that is translucent and not flexible, such as a glass substrate, quartz substrate, or sapphire substrate, can be used as the substrate 100. If the semiconductor device 10 is used in an integrated circuit that is not a display device, a non-translucent substrate such as a semiconductor substrate such as a silicon substrate, silicon carbide substrate, or compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate can be used as the substrate 100.

[0050] Common metallic materials can be used for the first gate electrode 110, the first electrode 140, and the first conductive layer 170. For example, these materials may include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloys or compounds thereof. The above materials may be used as a single layer or in a laminated configuration for the first gate electrode 110, the first electrode 140, and the first conductive layer 170.

[0051] For example, the metal element constituting the first electrode 140 that is in contact with the first oxide semiconductor layer 130 is more stable than the oxide of the metal element constituting the first oxide semiconductor layer 130. In other words, if there are multiple metal elements constituting the first oxide semiconductor layer 130, the Gibbs free energy (ΔG) of each of the metal oxides of the multiple metal elements is greater. f Therefore, it is preferable that the Gibbs free energy of the metal oxide of the metal element constituting the first electrode 140 in contact with the first oxide semiconductor layer 130 is smaller.

[0052] For example, when IGZO is used as the first oxide semiconductor layer 130, Ti can be used as the metal in contact with the IGZO. The Gibbs free energy of indium oxide is greater than the Gibbs free energies of Ga oxide and Zn oxide, respectively. In other words, indium oxide is chemically unstable and easily reduced. On the other hand, the Gibbs free energy of Ti oxide is sufficiently smaller than the Gibbs free energies of Ga oxide and Zn oxide, respectively. Therefore, when Ti is formed on IGZO, it combines with oxygen in the IGZO to form Ti oxide. As indium oxide is easily reduced as described above, if high energy is supplied while IGZO and Ti are in contact, the indium oxide is reduced and the Ti is oxidized. In the case of semiconductor device 10, when Ti is deposited on IGZO, oxygen in the IGZO is taken over by Ti in the upper part of the IGZO (first region 133), and the IGZO in the first region 133 becomes n-type, so the resistance of the IGZO decreases. This phenomenon reduces the contact resistance between IGZO and Ti.

[0053] As the first gate insulating layer 120 and the first insulating layer 150, general insulating layer materials can be used. For example, silicon oxide (SiO2) can be used as these insulating layers. x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y), aluminum nitride (AlN x O y ), aluminum nitride (AlN x Inorganic insulating layers such as ) can be used. As these insulating layers, insulating layers with few defects can be used. For example, when comparing the oxygen composition ratio in the first insulating layer 150 with the oxygen composition ratio in an insulating layer with the same composition as the first insulating layer 150 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the first insulating layer 150 is closer to the stoichiometric ratio for an insulating layer with the same composition as the first insulating layer 150 than the oxygen composition ratio in the other insulating layer.

[0054] The above SiO x N y and AlO x N y These are silicon compounds and aluminum compounds that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds that contain oxygen in a smaller proportion (x > y) than nitrogen.

[0055] As the first oxide semiconductor layer 130, a metal oxide having semiconductor properties can be used. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor with a different composition can also be used. For example, the ratio of In may be increased to improve mobility. Also, the ratio of Ga may be increased to increase the band gap and reduce the effect of light irradiation.

[0056] Other elements may be added to the oxide semiconductor containing In, Ga, Zn, and O, for example, metallic elements such as Al and Sn may be added. In addition to the oxide semiconductors mentioned above, oxide semiconductors containing In and Ga (IGO), oxide semiconductors containing In and Zn (IZO), oxide semiconductors containing In, Sn, and Zn (ITZO), and oxide semiconductors containing In and W can be used as the first oxide semiconductor layer 130. The first oxide semiconductor layer 130 may be amorphous or crystalline. Furthermore, the first oxide semiconductor layer 130 may be a mixed phase of amorphous and crystalline material.

[0057] The oxide layer 160 can be an oxide semiconductor layer with the same composition as the first oxide semiconductor layer 130, an oxide conductive layer such as ITO, or SiO x SiO x N y AlO x AlO x N y Such oxide insulating layers can be used. It is preferable that the oxide layer 160 be formed by sputtering. When the oxide layer 160 is formed by sputtering, the process gas used in sputtering remains in the oxide layer 160 film. For example, if Ar is used as the sputtering process gas, Ar may remain in the oxide layer 160 film. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the oxide layer 160. When an oxide insulating layer with the same composition as the material used for the first insulating layer 150 is used as the oxide layer 160, the oxygen composition ratio of the oxide layer 160 is greater than that of the first insulating layer 150.

[0058] <Second Embodiment> A semiconductor device according to one embodiment of the present invention will be described using Figures 18 to 33. The semiconductor device of the embodiment shown below may be used not only as a transistor used in a display device, but also as an integrated circuit (IC) such as a microprocessing unit (MPU), or as a memory circuit.

[0059] [Configuration of semiconductor device 10B] The overall configuration of the semiconductor device 10B according to the second embodiment is the same as the overall configuration of the semiconductor device 10 according to the first embodiment (Figure 1), so its description will be omitted. When describing the semiconductor device 10B, it may be explained with reference to Figure 1. In that case, "B" will be added after the reference numeral of the component shown in Figure 1. Figure 18 is an enlarged cross-sectional view of a part of the semiconductor device according to one embodiment of the present invention. Figure 18 corresponds to an enlarged view of the area enclosed by the dotted line frame in Figure 1.

[0060] As shown in Figure 18, in this embodiment, the first electrode 140B has a first conductive layer 145B, a second conductive layer 147B, and a third conductive layer 149B. An oxide portion 180B is provided at the pattern end of the first electrode 140B. The oxide portion 180B is provided above the first oxide semiconductor layer 130B. The oxide portion 180B is the oxide of the first electrode 140B. Specifically, the oxide portion 180B includes a first oxide portion 185B and a third oxide portion 189B. The first oxide portion 185B is provided at the end of the first conductive layer 145B and is the oxide of the first conductive layer 145B. The third oxide portion 189B is provided at the end of the third conductive layer 149B and is the oxide of the third conductive layer 149B. The first oxide portion 185B is conductive. The first oxidation region 185B is located on the channel region 131B side of the pattern edge of the second conductive layer 147B.

[0061] In this embodiment, a configuration in which the oxide of the second conductive layer 147B is not provided is illustrated, but a second oxide portion, which is the oxide of the second conductive layer 147B, may be provided between the first oxide portion 185B and the third oxide portion 189B. In other words, the second oxide portion may be provided at the edge of the second conductive layer 147B. As will be described in detail later, in this embodiment, the second oxide portion is formed in the manufacturing process of the semiconductor device 10B, but is removed in a subsequent process, so a structure like that shown in Figure 18 is formed. The first oxide portion 185B does not have to be conductive.

[0062] The first oxide semiconductor layer 130B includes a channel region 131B, a first region 133B, and a second region 135B.

[0063] Most of the channel region 131B is the region above the first oxide semiconductor layer 130B where the first electrode 140B is not provided. The oxide region 180B is provided above the first oxide semiconductor layer 130B of the channel region 131B. In other words, the oxide region 180B overlaps with the channel region 131B in a plan view. The edge of the first electrode 140B on the oxide region 180B side overlaps with a part of the channel region 131B in a plan view. However, the first electrode 140B does not necessarily have to overlap with the channel region 131B in a plan view.

[0064] The first region 133B and the second region 135B are regions in which the first electrode 140B is provided above the first oxide semiconductor layer 130B. In other words, the channel region 131B is the region in which the first oxide semiconductor layer 130B is exposed from the first electrode 140B in a plan view. The first region 133B and the second region 135B are regions in which the first oxide semiconductor layer 130B overlaps with the first electrode 140B in a plan view. No oxide portion 180B is provided above the first oxide semiconductor layer 130B in the first region 133B and the second region 135B. The first region 133B is provided over almost the entire region in which the first oxide semiconductor layer 130B overlaps with the first electrode 140B. On the other hand, the second region 135B is provided at a position further from the oxide portion 180B in a plan view compared to the first region 133B. In other words, there is a region below the first electrode 140B where the second region 135B is not provided.

[0065] The channel region 131B, the first region 133B, and the second region 135B are each formed from a single oxide semiconductor layer. Immediately after film formation, these regions all have the same composition and crystal state. However, due to the influence of the manufacturing process of the semiconductor device 10B, the composition and crystal state of the first oxide semiconductor layer 130B in each of the above regions differ.

[0066] In the first oxide semiconductor layer 130B in the first region 133B and the second region 135B, the indium contained in the first oxide semiconductor layer 130B is unevenly distributed. On the other hand, in the first oxide semiconductor layer 130B in the channel region 131B, the indium is not unevenly distributed. Whether or not indium is unevenly distributed in the first oxide semiconductor layer 130B may differ depending on the evaluation method and evaluation accuracy. If it is determined that indium is unevenly distributed in the first oxide semiconductor layer 130B in the channel region 131B, then the degree of indium uneven distribution in the first oxide semiconductor layer 130B in the first region 133B and the second region 135B is greater than the degree of indium uneven distribution in the first oxide semiconductor layer 130B in the channel region 131B. The degree of indium uneven distribution in the first oxide semiconductor layer 130B in the second region 135B is greater than the degree of indium uneven distribution in the first oxide semiconductor layer 130B in the first region 133B.

[0067] Here, a large degree of indium segregation means that the area with a high concentration of indium (high-concentration area) is larger than other areas, or that the size (or grain size) of crystallized indium is larger than other areas.

[0068] The degree of indium segregation can be determined, for example, by cross-sectional TEM (Transmission Electron Microscope) images, cross-sectional STEM (Scanning Transmission Electron Microscope) images, or cross-sectional SEM (Scanning Electron Microscope) images. For example, if the contrast is greater in the first oxide semiconductor layer 130B in the first region 133B and the second region 135B compared to the first oxide semiconductor layer 130B in the channel region 131B, it can be determined that the degree of indium segregation is greater in the first oxide semiconductor layer 130B in the first region 133B and the second region 135B compared to the first oxide semiconductor layer 130B in the channel region 131B.

[0069] Alternatively, in the contrast of the cross-sectional image described above, if the size of the "light" or "dark" areas is relatively large, it can be determined that the degree of indium segregation is high. Or, for example, in mapping analysis (surface analysis) using EDX (Energy Dispersive X-ray spectrometry) with SEM or STEM, if the signal intensity due to indium is greater in a region than in other regions, i.e., if the region where indium is densely concentrated is relatively large, it can be determined that the degree of indium segregation is high.

[0070] [Manufacturing method for semiconductor device 10B] A method for manufacturing a semiconductor device 10B according to one embodiment of the present invention will be described using Figures 19 to 22. Figures 19 to 22 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. In the following description of the manufacturing method, an example will be given in which Ti is used as the first conductive layer 145B and the third conductive layer 149B, and Al is used as the second conductive layer 147B.

[0071] As shown in Figure 19, a pattern for the first oxide semiconductor layer 130B is formed on the first gate insulating layer 120B, which is provided on the first gate electrode 110B (see Figure 1), and a pattern for the first electrode 140B is formed. The pattern end of the first electrode 140B is located on the first oxide semiconductor layer 130B. Since the manufacturing method up to the structure shown in Figure 19 can be a general semiconductor process, a detailed explanation is omitted.

[0072] Next, as shown in Figure 20, the first oxide semiconductor layer 130B and the first electrode 140B are subjected to plasma treatment using a gas containing oxygen and nitrogen. In this embodiment, N2O plasma treatment is performed as the plasma treatment. To rephrase the above steps, N2O plasma treatment is performed on at least the pattern edge of the first electrode 140B.

[0073] As shown in Figure 21, the N2O plasma treatment forms an oxidized portion 180B at the end of the first electrode 140B. Specifically, a first oxidized portion 185B is formed at the end of the first conductive layer 145B, a second oxidized portion 187B is formed at the end of the second conductive layer 147B, and a third oxidized portion 189B is formed at the end of the third conductive layer 149B. The N2O plasma treatment also oxidizes the upper part of the third conductive layer 149B, which is the top layer of the first electrode 140B, but this is omitted for the sake of explanation.

[0074] Of the oxidized portion 180B, the second oxidized portion 187B disappears during the process until the first insulating layer 150B covering the first electrode 140B is formed. As a result, as shown in Figure 22, only the first oxidized portion 185B and the third oxidized portion 189B remain at the end of the first electrode 140B.

[0075] In this embodiment, an example is shown in which the second oxide portion 187B completely disappears, but a portion of the second oxide portion 187B may remain. Alternatively, the second oxide portion 187B may not disappear, and the first insulating layer 150B may be formed on top of the structure shown in Figure 21.

[0076] After forming the first insulating layer 150B described above, heat treatment is performed, causing indium to segregate in the first oxide semiconductor layer 130B in the region that overlaps with the first electrode 140B in a plan view.

[0077] [Uneven distribution of indium in the first oxide semiconductor layer 130B] Figures 23 to 28 illustrate the uneven distribution of indium in the channel region 131B, the first region 133B, and the second region 135B of the first oxide semiconductor layer 130B. The cross-sectional images of the semiconductor device 10B shown in Figures 23 to 28 are of a sample after manufacturing the semiconductor device 10B but before reliability testing.

[0078] Figure 23 is a cross-sectional TEM image of a semiconductor device according to one embodiment of the present invention. In Figure 23, as described above, Ti is used as the first conductive layer 145B and the third conductive layer 149B, Al is used as the second conductive layer 147B, and IGZO is used as the first oxide semiconductor layer 130B. The first conductive layer 145B (Ti) and the second conductive layer 147B (Al) have different patterns in cross-section due to their different crystalline states. In the first oxide semiconductor layer 130B, the region where the first electrode 140B is not provided above is the channel region 131B, and the region where the first electrode 140B is provided above corresponds to the first region 133B and the second region 135B. A mixed crystal region formed by the reaction of Ti and Al is formed between the first conductive layer 145B and the second conductive layer 147B.

[0079] In Figure 23, the dotted line connecting the first conductive layer 145B and the third conductive layer 149B indicates the location where the end of the second conductive layer 147B is presumed to have existed, based on the shapes of these conductive layers. As described above, at least a portion of the second conductive layer 147B disappears, resulting in the shape shown in Figure 23.

[0080] Figure 24 is a cross-sectional HAADF (High-Angle Annular Dark Field)-STEM image of a semiconductor device according to one embodiment of the present invention. Figure 24 is an enlarged STEM image of a portion of Figure 23. Figure 24 shows a portion of the first oxide semiconductor layer 130B, the first conductive layer 145B, and the second conductive layer 147B. Figures 25 to 28 are the EDX mapping measurement results of semiconductor devices according to one embodiment of the present invention. Figure 25 is the EDX mapping measurement result of Ti. Figure 26 is the EDX mapping measurement result of O. Figure 27 is the EDX mapping measurement result of In. Figure 28 is the EDX mapping measurement result of Al. In each figure, the regions where the first oxide semiconductor layer 130B, the first conductive layer 145B, and the second conductive layer 147B are provided are indicated by dotted lines.

[0081] Referring to Figures 24 to 26, Ti is detected in the region enclosed by the dotted line representing the first conductive layer 145B. However, near the left end of this dotted line, the signal intensity of Ti is weaker and the signal intensity of oxygen is stronger compared to other regions. This indicates that the first oxide region 185B (Ti oxide) is formed at the left end of the first conductive layer 145B. The first oxide region 185B has a partially missing shape (a concave shape in this embodiment). From Figures 25 and 26, oxygen is detected in the lower region of the first conductive layer 145B. This indicates that Ti oxide is formed below the Ti.

[0082] Referring to Figures 24 and 27, in the contrast of the STEM image in Figure 24, the region that is brighter than other regions (hereinafter referred to as "bright region 200B") is a region with a higher indium concentration than other regions, as shown in Figure 27. In Figure 24, the region that is darker than other regions (hereinafter referred to as "dark region 210B") is a region with a lower indium concentration than other regions, as shown in Figure 27.

[0083] As shown in Figure 24, the size of the clump of light region 200B in the second region 135B is larger than the size of the clump of light region 200B in the first region 133B. In Figure 24, no clear clumps of light region 200B and dark region 210B are observed in the channel region 131B, so it is judged that indium is not unevenly distributed. Small light regions are also observed in the first region 133B, which is thought to be due to the reduction of oxygen in the oxide semiconductor on the surface of the first oxide semiconductor layer 130B during or after the Ti film deposition process, forming regions with partially high indium concentrations. It is thought that the oxide semiconductor is converted to n-type by the reduction of oxygen on the surface of the first oxide semiconductor layer 130B in this way. On the other hand, in the first oxide semiconductor layer 130B in the first region 133B and the second region 135B, light region 200B and dark region 210B are localized, so it is judged that indium is unevenly distributed.

[0084] To rephrase the above description of the indium segregation, the degree of indium segregation in the first oxide semiconductor layer 130B in the first region 133B and the second region 135B is greater than the degree of indium segregation in the first oxide semiconductor layer 130B in the channel region 131B. In other words, in a plan view, the degree of indium segregation in the first oxide semiconductor layer 130B in the region overlapping with the first oxide part 185B is less than the degree of indium segregation in the first oxide semiconductor layer 130B in the region overlapping with the first electrode 140B. In the above example, in a plan view, the indium in the first oxide semiconductor layer 130B in the region overlapping with the first oxide part 185B is not segregated. The degree of indium segregation in the first oxide semiconductor layer 130B in the second region 135B is greater than the degree of indium segregation in the first oxide semiconductor layer 130B in the first region 133B. Here, the uneven distribution of indium is thought to be due to the crystallization of indium. Therefore, it can be said that the grain size of unevenly distributed indium in the first oxide semiconductor layer 130B in the second region 135B is larger than the grain size of unevenly distributed indium in the first oxide semiconductor layer 130B in the first region 133B.

[0085] As shown in Figures 24 and 27, the region in the second region 135B where indium is unevenly distributed does not reach the edge of the first conductive layer 145B on the channel region 131B side. In other words, in this state, no abnormal rise in the ON current of the semiconductor device 10B occurs.

[0086] Referring to Figures 24, 26, and 28, the regions where oxygen is not detected and the regions where Al is detected almost coincide. In other words, it is thought that almost no Al oxide is formed at the edges of the second conductive layer 147B. At least, there is no Al oxide on the order of tens of nanometers at the edges of the second conductive layer 147B. However, it is possible that Al oxide on the order of a few nanometers is present at the edges of the second conductive layer 147B.

[0087] <Third Embodiment> A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 29 to 33. In the embodiments described below, a configuration will be described in which the semiconductor device described in the first and second embodiments above is applied to the circuit of a liquid crystal display device.

[0088] [Overview of Display Device 20C] Figure 29 is a plan view showing an overview of a display device according to one embodiment of the present invention. As shown in Figure 29, the display device 20C has an array substrate 300C, a sealing portion 400C, a counter substrate 500C, a flexible printed circuit board 600C (FPC600C), and an IC chip 700C. The array substrate 300C and the counter substrate 500C are bonded together by the sealing portion 400C. Multiple pixel circuits 310C are arranged in a matrix in the liquid crystal region 22C surrounded by the sealing portion 400C. The liquid crystal region 22C is the region that overlaps with the liquid crystal element 410C, which will be described later, in a plan view.

[0089] The sealing region 24C, where the sealing portion 400C is provided, is the area surrounding the liquid crystal region 22C. The FPC 600C is provided in the terminal region 26C. The terminal region 26C is the area where the array substrate 300C is exposed from the opposing substrate 500C, and is provided outside the sealing region 24C. Note that "outside the sealing region 24C" means the area outside the area where the sealing portion 400C is provided and the area enclosed by the sealing portion 400C. The IC chip 700C is provided on the FPC 600C. The IC chip 700C supplies signals to drive each pixel circuit 310C.

[0090] [Circuit configuration of display device 20C] Figure 30 is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. As shown in Figure 30, a source driver circuit 320C is provided at a position adjacent to the liquid crystal area 22C where the pixel circuit 310C is located in the D1 direction (column direction), and a gate driver circuit 330C is provided at a position adjacent to the liquid crystal area 22C in the D2 direction (row direction). The source driver circuit 320C and the gate driver circuit 330C are provided in the seal area 24C. However, the area in which the source driver circuit 320C and the gate driver circuit 330C are provided is not limited to the seal area 24C, but can be any area outside the area in which the pixel circuit 310C is provided.

[0091] Source wiring 321C extends from source driver circuit 320C in the D1 direction and is connected to multiple pixel circuits 310C arranged in the D1 direction. Gate wiring 331C extends from gate driver circuit 330C in the D2 direction and is connected to multiple pixel circuits 310C arranged in the D2 direction.

[0092] A terminal section 333C is provided in the terminal area 26C. The terminal section 333C and the source driver circuit 320C are connected by a connection wire 341C. Similarly, the terminal section 333C and the gate driver circuit 330C are connected by a connection wire 341C. When the FPC 600C is connected to the terminal section 333C, the external device to which the FPC 600C is connected is connected to the display device 20C, and each pixel circuit 310C provided in the display device 20C is driven by a signal from the external device.

[0093] The semiconductor devices 10 and 10A shown in the first and second embodiments are applied to transistors included in the pixel circuit 310C, the source driver circuit 320C, and the gate driver circuit 330C.

[0094] [Pixel circuit 310C of display device 20C] Figure 31 is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention. As shown in Figure 31, the pixel circuit 310C includes elements such as a transistor 800C, a retaining capacitor 890C, and a liquid crystal element 410C. The transistor 800C has a first gate electrode 810C, a first source electrode 830C, and a first drain electrode 840C. The first gate electrode 810C is connected to the gate wiring 331C. The first source electrode 830C is connected to the source wiring 321C. The first drain electrode 840C is connected to the retaining capacitor 890C and the liquid crystal element 410C. The semiconductor devices 10 and 10A shown in the first and second embodiments are applied to the transistor shown in Figure 31. In this embodiment, for the sake of explanation, 830C is referred to as the source electrode and 840C as the drain electrode, but the functions of the source and drain of each electrode may be reversed.

[0095] [Cross-sectional structure of display device 20C] Figure 32 is a cross-sectional view of a display device according to one embodiment of the present invention. As shown in Figure 32, the display device 20C is a display device in which transistors 800C and 900C with different structures are provided on the same substrate. The structure of transistor 800C is different from the structure of transistor 900C. Specifically, transistor 800C is a bottom-gate type transistor in which a first oxide semiconductor layer 820C is used as the channel. Transistor 900C is a top-gate type transistor in which a semiconductor layer 920C is used as the channel. For example, transistor 800C is used in the pixel circuit 310C, and transistor 900C is used in the source driver circuit 320C and the gate driver circuit 330C. Note that transistor 900C may also be used in the pixel circuit 310C.

[0096] Transistor 800C is a transistor formed on substrate 301C and is a transistor with one or more insulating layers as the underlying layers. In this embodiment, insulating layers 340C, 342C, 344C, and 346C are used as the underlying layers. A first gate electrode 810C is provided on insulating layer 346C. A first oxide semiconductor layer 820C is provided above the first gate electrode 810C. The first gate electrode 810C faces the first oxide semiconductor layer 820C. An insulating layer 348C, which functions as a gate insulating layer, is provided between the first gate electrode 810C and the first oxide semiconductor layer 820C. A first source electrode 830C is provided at one end of the pattern of the first oxide semiconductor layer 820C, and a first drain electrode 840C is provided at the other end. The first source electrode 830C and the first drain electrode 840C are connected to the first oxide semiconductor layer 820C on the top surface and side surface, respectively.

[0097] First insulating layers 350C and 352C are provided on the first oxide semiconductor layer 820C, the first source electrode 830C, and the first drain electrode 840C. Openings 851C and 861C are provided in the first insulating layers 350C and 352C. A first source wiring 850C is provided on the first insulating layer 352C and inside the opening 851C. A first drain wiring 860C is provided on the first insulating layer 352C and inside the opening 861C. An oxide layer 853C is provided between the upper surface of the first insulating layer 352C and the first source wiring 850C. An oxide layer 855C is provided between the upper surface of the first insulating layer 352C and the first drain wiring 860C.

[0098] A second insulating layer 354C is provided on the first source wiring 850C and the first drain wiring 860C. A common electrode 880C, which is provided in common to multiple pixels, is provided on the second insulating layer 354C. A second insulating layer 356C is provided on the common electrode 880C. A third aperture 871C is provided on the second insulating layers 354C and 356C. A pixel electrode 870C is provided on the second insulating layer 356C and inside the third aperture 871C. The pixel electrode 870C is connected to the first drain wiring 860C.

[0099] Figure 33 is a plan view of the pixel electrode and common electrode of a display device according to one embodiment of the present invention. As shown in Figure 33, the common electrode 880C has an overlapping region that overlaps with the pixel electrode 870C in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 870C. When a voltage is supplied between the pixel electrode 870C and the common electrode 880C, a transverse electric field is formed from the pixel electrode 870C in the overlapping region toward the common electrode 880C in the non-overlapping region. This transverse electric field causes the liquid crystal molecules contained in the liquid crystal element 410C to operate, thereby determining the grayscale of the pixels.

[0100] In the above structure, the semiconductor device 10 shown in Figure 1 can be used as the transistor 800C. In this case, comparing Figure 1 and Figure 32, the components in each drawing correspond as follows: The first gate electrode 110 corresponds to the first gate electrode 810C. The first gate insulating layer 120 corresponds to the insulating layer 348C. The first oxide semiconductor layer 130 corresponds to the first oxide semiconductor layer 820C. The first source electrode 141 corresponds to the first source electrode 830C. The first drain electrode 143 corresponds to the first drain electrode 840C. The first insulating layer 150 corresponds to the first insulating layers 350C and 352C. The first opening 151 corresponds to the opening 851C. The first opening 153 corresponds to the opening 861C. The oxide layer 160 corresponds to the oxide layers 853C and 855C. The first source wiring 171 corresponds to the first source wiring 850C. The first drain wiring 173 corresponds to the first drain wiring 860C.

[0101] Transistor 900C is a transistor formed on substrate 301C, and is a transistor with an insulating layer 340C as the base layer. A light-shielding layer 910C is provided on the insulating layer 340C. An insulating layer 342C is provided on the light-shielding layer 910C. A semiconductor layer 920C is provided on the insulating layer 342C. A second gate electrode 930C is provided above the semiconductor layer 920C. An insulating layer 344C, which functions as a gate insulating layer, is provided between the semiconductor layer 920C and the second gate electrode 930C. Insulating layers 346C, 348C, 350C, and 352C are provided on the second gate electrode 930C. Openings 941C and 951C are provided in these insulating layers. A second source wiring 940C is provided on insulating layer 352C and inside opening 941C. A second drain wiring 950C is provided on insulating layer 352C and inside opening 951C. An insulating layer 354C is provided on the second source wiring 940C and the second drain wiring 950C. In other words, the second gate electrode 930C is located below the same layer (insulating layer 348C) as the gate insulating layer of transistor 800C.

[0102] <Fourth Embodiment> A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 34 and 35. In the embodiments described below, a configuration in which the semiconductor device described in the first and second embodiments above is applied to the circuit of an organic EL display device will be described. The overview and circuit configuration of the display device 20D are the same as those shown in Figures 29 and 30, so the explanation will be omitted.

[0103] [Pixel circuit 310D of display device 20D] Figure 34 is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. As shown in Figure 34, the pixel circuit 310D includes elements such as a drive transistor 960D, a selection transistor 970D, a retention capacitor 980D, and a light-emitting element DO. The source electrode of the selection transistor 970D is connected to the signal line 971D, and the gate electrode of the selection transistor 970D is connected to the gate line 973D. The source electrode of the drive transistor 960D is connected to the anode power line 961D, and the drain electrode of the drive transistor 960D is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 963D. The gate electrode of the drive transistor 960D is connected to the drain electrode of the selection transistor 970D. The retention capacitor 980D is connected to the gate electrode and drain electrode of the drive transistor 960D. The signal line 971D is supplied with a gradation signal that determines the light emission intensity of the light-emitting element DO. The gate line 973D is supplied with a signal to select the pixel row on which the above gradation signal is written.

[0104] [Cross-sectional structure of display device 20D] Figure 35 is a cross-sectional view of a display device according to one embodiment of the present invention. The configuration of the display device 20D shown in Figure 35 is similar to that of the display device 20C shown in Figure 32, but the structure of the display device 20D above the insulating layer 354D differs from the structure of the display device 20C above the insulating layer 354C. In the following description, the configuration of the display device 20D shown in Figure 35 that is the same as that of the display device 20C shown in Figure 32 will be omitted, and the differences from the display device 20C will be explained.

[0105] As shown in Figure 35, the display device 20D has a pixel electrode 981D, a light-emitting layer 983D, and a common electrode 985D above an insulating layer 354D. The pixel electrode 981D is provided on the insulating layer 354D and inside the third aperture 871D. An insulating layer 358D is provided on the pixel electrode 981D. An aperture 359D is provided in the insulating layer 358D. The aperture 359D corresponds to the light-emitting region. In other words, the insulating layer 358D defines the pixel. The light-emitting layer 983D and the common electrode 985D are provided on the pixel electrode 981D exposed by the aperture 359D. The pixel electrode 981D and the light-emitting layer 983D are provided individually for each pixel. On the other hand, the common electrode 985D is provided in common for multiple pixels. Different materials are used for the light-emitting layer 983D depending on the display color of the pixel.

[0106] In the third and fourth embodiments, examples were given of configurations in which the semiconductor device described in the first and second embodiments is applied to a liquid crystal display device and an organic EL display device. However, the semiconductor device may also be applied to display devices other than these (for example, self-emissive display devices other than organic EL displays or electronic paper display devices). Furthermore, the above-mentioned semiconductor device can be applied to a wide range of display devices, from small to medium-sized to large, without any particular limitations.

[0107] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, devices based on the display devices of each embodiment, in which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0108] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0109] 10: Semiconductor device, 20C: Display device, 22C: Liquid crystal region, 24C: Seal region, 26C: Terminal region, 100: Substrate, 110: First gate electrode, 120: First gate insulating layer, 130: First oxide semiconductor layer, 131: Channel region, 133: First region, 135B: Second region, 137: First surface, 138: Second surface, 139: Nitrogen-containing region, 139Z: Region, 140: First electrode, 141: First source electrode, 143: First drain electrode, 145B: First conductive layer, 147B: Second conductive layer, 149B: Third conductive layer, 150: First insulating layer, 151: First aperture, 153: First aperture, 160: Oxide layer, 161: Second aperture, 163: Second aperture, 170: First conductive layer, 171: First source wiring, 173: First drain wiring, 180B: Oxidation area, 185B: First oxidation area, 187B: Second oxidation area, 189B: Third oxidation area, 200B: Bright area, 201: Designated line, 202: Line extraction width, 210B: Dark area, 219Z, 229Z: Spectrum, 300C: Array substrate, 301C: Substrate, 310C: Pixel circuit, 320C: Source driver circuit, 321C: Source wiring, 330C: Gate driver circuit, 331C: Gate wiring, 333C: Terminal area 340C, 342C, 344C, 346C, 348C, 350C, 352C, 354C, 354D, 358D: Insulating layer, 341C: Connection wiring, 359D: Aperture, 400C: Seal area, 410C: Liquid crystal element, 500C: Opposing substrate, 600C: Flexible printed circuit board, 700C: Chip, 800C: Transistor, 810C: First gate electrode, 820C: First oxide semiconductor layer, 830C: First source electrode, 840C: First drain electrode, 850C: First source wiring, 851C, 861C: Aperture, 853C, 855C: Oxide layer, 860C: First drain wiring, 870C: Pixel electrode, 871C: Third aperture, 880C: Common electrode, 890C: Holding capacitance, 900C: Transistor, 910C: Light shielding layer, 920C: Semiconductor layer, 930C: Second gate electrode, 940C: Second source wiring, 941C, 951C: Aperture, 950C: Second drain wiring, 960D: Drive transistor, 961D: Anode power line, 963D: Cathode power line970D: Selection transistor, 971D: Signal line, 973D: Gate line, 980D: Holding capacitance, 981D: Pixel electrode, 983D: Light-emitting layer, 985D: Common electrode

Claims

1. An oxide semiconductor layer having a first surface and a second surface opposite to the first surface, A gate electrode facing the oxide semiconductor layer, A gate insulating layer between the oxide semiconductor layer and the gate electrode, Each comprises a pair of first electrodes in contact with the first surface of the oxide semiconductor layer, The oxide semiconductor layer has a first peak in the nitrogen composition ratio within a depth of 2 nanometers from the first surface in a region near the end of at least one of the pair of first electrodes, and a second peak in the nitrogen composition ratio smaller than the first peak in a depth of 2 nanometers or more from the first surface. A semiconductor device having a nitrogen composition ratio of 2 percent or more at the first peak.

2. It further has an insulating layer, The semiconductor device according to claim 1, wherein the insulating layer covers the first surface of the oxide semiconductor layer sandwiched between the pair of first electrodes.

3. The semiconductor device according to claim 1 or 2, wherein the nitrogen composition ratio in the first peak is 6 percent or more.

4. The semiconductor device according to claim 1 or 2, wherein the nitrogen composition ratio is a composition ratio measured using an energy-dispersive X-ray spectrometer (EDX) provided in a scanning transmission electron microscope (STEM).

5. An oxide portion is formed at the end of the first electrode above the oxide semiconductor layer and further comprises an oxide portion which is the oxide of the first electrode. The semiconductor device according to claim 1 or 2, wherein the first electrode is in contact with the oxide semiconductor layer from above.

6. The semiconductor device according to claim 5, wherein indium is unevenly distributed in the region of the oxide semiconductor layer that overlaps with the first electrode in a plan view.

7. The semiconductor device according to claim 5, wherein the degree of indium segregation in the region of the oxide semiconductor layer that overlaps with the oxidized portion in a plan view is smaller than the degree of indium segregation in the region that overlaps with the first electrode.

8. The semiconductor device according to claim 7, wherein indium is not unevenly distributed in the region that overlaps with the oxidized portion in a plan view.

9. The semiconductor device according to claim 5, wherein the oxidized portion is conductive.

10. It further comprises a second electrode provided above the first electrode, The semiconductor device according to claim 5, wherein the oxidized portion is located on the channel region side of the end of the second electrode.

11. The semiconductor device according to claim 1 or 2, wherein the gate electrode and the gate insulating layer are provided below the oxide semiconductor layer.

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