Three-dimensional NAND flash memory element for electron diffusion suppression based on a selective dipole layer and its manufacturing method

Abstract

This invention provides a three-dimensional NAND flash memory element for suppressing electron diffusion based on a selective dipole layer, and a method for manufacturing the same. [Solution] The three-dimensional NAND flash memory element includes a plurality of gate electrodes arranged spaced apart from each other along one direction, an insulating film arranged between the gate electrodes along the direction, a channel layer extending through the gate electrodes and insulating film along the direction, a charge trapping layer surrounding the channel layer between the gate electrodes and insulating film and the channel layer, and a dipole layer disposed between the gate electrodes and insulating film and the charge trapping layer, each exhibiting different polarities with respect to the gate electrodes and insulating film.

Description

Technical Field

[0001] The present disclosure relates to memory semiconductor technology, and more specifically, to a technology for preventing the diffusion of electrons in the charge trap layer of a three-dimensional NAND flash memory using a selective dipole layer to improve data retention characteristics and minimize the influence such as cell-to-cell interference. This patent was supported by the Korea Research Foundation (RS-2023-00280841) with funds from the Ministry of Science and ICT.

Background Art

[0002] Charge trap flash memory is a non-volatile memory device that operates on the principle of injecting electrons into the trapping sites of a charge trap layer as a method of storing data. A typical structure of flash memory is the SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure. As the charge trap layer, a silicon nitride film is used, and electrons are injected from the channel into the charge trap layer through the tunnel oxide film or released from the charge trap layer to the channel.

[0003] However, in a general three-dimensional NAND flash memory, electron diffusion occurs between adjacent cells, and the density of electrons stored in each cell decreases. This leads to a deterioration of the memory window characteristics and a deterioration of the data retention characteristics.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a three-dimensional NAND flash memory device and a method for manufacturing the same for suppressing electron diffusion based on a selective dipole layer.

Means for Solving the Problems

[0005] In this disclosure, a three-dimensional NAND flash memory element may include a plurality of gate electrodes arranged spaced apart from each other along one direction, an insulating film arranged between the gate electrodes along that direction, a channel layer extending through the gate electrodes and the insulating film along that direction, a charge trapping layer surrounding the channel layer between the gate electrodes and the insulating film and the channel layer, and dipole layers disposed between the gate electrodes and the insulating film and the charge trapping layer, each exhibiting a different polarity with respect to the gate electrodes and the insulating film.

[0006] In this disclosure, a method for manufacturing a three-dimensional NAND flash memory element may include the steps of alternately stacking a plurality of insulating films and a plurality of gate electrodes along one direction; forming holes that extend through the insulating films and gate electrodes along that direction; forming dipole layers on the insulating films and gate electrodes exposed inside the holes to exhibit different polarities with respect to the gate electrodes and insulating films, respectively; forming a charge trapping layer on the dipole layers inside the holes; and forming a channel layer on the charge trapping layers inside the holes. [Effects of the Invention]

[0007] This disclosure suppresses the diffusion of electrons trapped in the charge trapping layer by using dipole layers exhibiting different polarities in the gate electrode and insulating film, respectively. More specifically, the dipole layers can be formed such that the anode region of the dipole portion corresponding to the gate electrode faces the barrier layer, and the anode region of the dipole portion corresponding to the insulating film faces the insulating film. As a result, an attractive force is generated for electrons trapped in the charge trapping layer by the anode region of the dipole portion corresponding to the gate electrode, and a repulsive force is generated by the cathode region of the dipole portion corresponding to the insulating film, thereby suppressing the diffusion of electrons. In other words, the dipole layers can more effectively confine electrons stored in each memory cell. This reduces the electrical influence between memory cells and significantly improves the data retention characteristics of each memory cell. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 2] This is a cross-sectional view showing a portion of Figure 1, specifically region A. [Figure 3] This is an enlarged view showing a portion of Figure 2, specifically area B. [Figure 4a] Figure 1 is a diagram illustrating the electron distribution within the charge trapping layer when the three-dimensional NAND flash memory structure does not include a dipole layer. [Figure 4b] Figure 4b is a diagram illustrating the electron distribution within the charge trapping layer when the three-dimensional NAND flash memory structure of Figure 1 includes a dipole layer. [Figure 5] This figure illustrates a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6a] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6b] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6c] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6d] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6e] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6f] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6g] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6h]This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6i] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6j] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6k] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6l] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Figure 6m] This is an illustrative diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure according to various embodiments. [Modes for carrying out the invention]

[0009] This disclosure provides a three-dimensional NAND flash memory element for electron diffusion suppression based on a selective dipole layer and a method for manufacturing the same. Various embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0010] Figure 1 is a perspective view showing a three-dimensional NAND flash memory structure 100 according to various embodiments. Figure 2 is a cross-sectional view showing a portion of Figure 1, i.e., region A. Figure 3 is an enlarged view showing a portion of Figure 2, i.e., region B. Figure 4a is a diagram illustrating the electron distribution in the charge trapping layer 150 when the three-dimensional NAND flash memory structure 100 of Figure 1 does not include the dipole layer 170. Figure 4b is a diagram illustrating the electron distribution in the charge trapping layer 150 when the three-dimensional NAND flash memory structure 100 of Figure 1 includes the dipole layer 170.

[0011] Referring to FIGS. 1 and 2, the three-dimensional NAND flash memory structure 100 may show a structure in which a plurality of memory cells for storing data respectively are three-dimensionally arranged between a pair of substrates. In other words, a number of cell stacks are arranged on a plane (X-Y) defined parallel to the substrate, and each cell stack may show a structure in which a number of memory cells are stacked in a direction (Z) perpendicular to that plane (X-Y). Specifically, the three-dimensional NAND flash memory structure 100 may include a pair of substrates 110, a plurality of gate electrodes 120, a plurality of insulating films 130, a channel layer 140, a charge trapping layer 150, a blocking layer 160, a dipole layer 17, and a tunnel layer 180.

[0012] The substrate 110 may support other components of the three-dimensional NAND flash memory structure 100. Also, the substrate 110 may have a source region and a drain region that serve as an inlet and outlet for current to the memory cells. For this reason, the substrate 110 may be disposed at both ends of the three-dimensional NAND flash memory structure 100 respectively. For example, the substrate 110 may be an n-type semiconductor substrate.

[0013] The gate electrode 120 may be provided to control the operation of the memory cell. For this reason, the gate electrode 120 may be electrically connected to a word line. The gate electrodes 120 may be arranged to be spaced apart from each other along a direction (Z). In one embodiment, one gate electrode 120 may be used to control the operation of one memory cell. In other embodiments, one gate electrode 120 may be used to control a plurality of memory cells collectively.

[0014] The insulating film 130 may isolate the gate electrodes 120 from each other. For this reason, the insulating film 130 may be arranged between the gate electrodes 120 along a direction (Z).

[0015] The channel layer 140 may be provided as an electron transport path. The channel layer 140 may extend through the gate electrode 120 and the insulating film 130 along one direction (Z). For example, the channel layer 140 may be formed of silicon (Si), but is not limited to this.

[0016] The charge trapping layer 150 may be provided to trap electrons tunneled from the channel layer 140 during the memory cell's programming operation and to release the trapped electrons to the channel layer 140 during the memory cell's erasure operation. For this reason, the charge trapping layer 150 may surround the channel layer 140 between the gate electrode 120 and the insulating film 130 and the channel layer 140. The charge trapping layer 150 may be formed of, for example, Si3N4, but is not limited to this. For example, the charge trapping layer 150 may be formed of a high dielectric constant material with excellent charge trapping properties.

[0017] The barrier layer 160 may be provided to prevent direct contact between the gate metal 120 and the insulating film 130 and the charge trapping layer 150, thereby blocking the emission of electrons trapped in the charge trapping layer 150 to the gate metal 120. For this reason, the barrier layer 160 may surround the charge trapping layer 150 between the gate electrode 120 and the insulating film 130 and the charge trapping layer 150. The barrier layer 160 may be formed of, for example, SiO2, but is not limited thereto. For example, the barrier layer 160 may be formed of a high dielectric constant material.

[0018] The dipole layer 170 may be provided to prevent electrons trapped in the charge trapping layer 150 from diffusing within the charge trapping layer 150, thereby stably confining them within the charge trapping layer 150. For this reason, the dipole layer 170 may be placed between the gate electrode 120 and the insulating film 130 and the charge blocking layer 160. Furthermore, the dipole layer 170 may exhibit dipole properties at the interface between the high-dielectric-constant material and the low-dielectric-constant material, and may exhibit different polarities with respect to the gate electrode 120 and the insulating film 130, as shown in Figure 3.

[0019] Specifically, the dipole layer 170 may include a first dipole portion 171 and a second dipole portion 173. The first dipole portion 171 may be positioned corresponding to each of the insulating films 130. As shown in Figure 3, the first dipole portion 171 may have a cathode region facing the barrier layer 160 and an anode region facing one of the insulating films 130. For this reason, the first dipole portion 171 may be formed of at least one insulating material such that the anode region of the first dipole portion 171 faces the insulating film 130, depending on the electronegativity between the insulating film 130 and the barrier layer 160. The second dipole portion 173 may be positioned corresponding to each of the gate electrodes 120. As shown in Figure 3, the second dipole portion 173 may have an anode region facing the barrier layer 160 and a cathode region facing one of the gate electrodes 120. Therefore, the second dipole portion 173 may be formed of at least one insulating material such that the anode region of the second dipole portion 173 faces the barrier layer 160, depending on the electronegativity between the gate electrode 120 and the barrier layer 160 material. For example, at least one insulating material of the first dipole portion 171 or the second dipole portion 173 may include at least one of lanthanum oxide (e.g., La2O3), aluminum oxide (e.g., Al2O3), or silicon oxide. Here, the first dipole portion 171 and the second dipole portion 173 may have the same height as the barrier layer 160 or different heights. For example, the height of the first dipole portion 171 may be greater than or equal to the height of the second dipole portion 173, and vice versa.

[0020] The tunnel layer 180 may be provided for electron tunneling between the channel layer 140 and the charge trapping layer 150. Therefore, the tunnel layer 180 may surround the channel layer 140 between the channel layer 140 and the charge trapping layer 150. The tunnel layer 180 may be formed of, for example, SiO2, but is not limited to this. For example, the tunnel layer 180 may be formed of a high dielectric constant oxide material.

[0021] Thus, in the three-dimensional NAND flash memory structure 100, a channel layer 140, a tunnel layer 180, a charge trapping layer 150, a blocking layer 160, a dipole layer 170, and a gate electrode 120 and an insulating film 130 may be stacked in order along the radial direction (XY) perpendicular to one direction (Z). The dipole layer 170 is positioned between the gate electrode 120 and the insulating film 130 and the charge blocking layer 160, and may exhibit a different, i.e., opposite polarity to the gate electrode 120 and the insulating film 130. That is, the anode region of the first dipole portion 171 may face the blocking layer 160, and the cathode region of the second dipole portion 173 may face the blocking layer 160.

[0022] In various embodiments, a three-dimensional NAND flash memory structure 100 may perform program and erase operations on memory cells. During the program operation of at least one memory cell, a positive (+) voltage is applied to the gate electrode 120, causing electrons that had moved from the source region to the drain region to flow into the channel layer 140 and be injected into the charge trapping layer 150. Here, the electrons injected in the charge trapping layer 150 may be stored in trap sites or energy bandwells. On the other hand, during the erase operation of at least one memory cell, a negative (-) voltage is applied to the gate electrode 120, causing the charge trapping layer 150 to release the trapped electrons to the channel layer 140. Here, the charge trapping layer 150 may become empty. Through these operations, the data state ("1" / "0") may be distinguished.

[0023] As shown in Figure 4a, if the three-dimensional NAND flash memory structure 100 does not include a dipole layer 170, electrons trapped in the charge trapping layer 150 may diffuse within the charge trapping layer 150. More specifically, during the programming operation of any memory cell, in the initial stages, as shown on the left side of Figure 4a, electrons trapped in the charge trapping layer 150 are concentrated towards the corresponding gate electrode 120. However, over time, as shown on the right side of Figure 4a, electrons trapped in the electron trapping layer 150 may diffuse within the charge trapping layer 150 to correspond to the adjacent insulating film 130 from the corresponding gate electrode 120. This may affect adjacent memory cells.

[0024] In contrast, as shown in Figure 4b, when the three-dimensional NAND flash memory structure 100 includes a dipole layer 170, electrons trapped in the charge trapping layer 150 can be stably confined within the charge trapping layer 150. More specifically, an attractive force is generated for electrons trapped in the charge trapping layer 150 by the anode region of the second dipole portion 173, and a repulsive force is generated by the cathode region of the first dipole portion 171. As a result, during the initial stages of programming any memory cell, as shown on the left side of Figure 4b, electrons trapped in the electron trapping layer 150 are more concentratedly distributed towards the corresponding gate electrode 120, and even as time passes, as shown on the right side of Figure 4b, electrons trapped in the electron trapping layer 150 remain concentratedly distributed towards the corresponding gate electrode 120. That is, electrons trapped in the electron trapping layer 150 do not diffuse within the charge trapping layer 150. In this way, the dipole layer 170 can more effectively confine electrons stored in each memory cell. This reduces electrical interference between memory cells and significantly improves the data retention characteristics of each memory cell.

[0025] Figure 5 shows a diagram illustrating a method for manufacturing a three-dimensional NAND flash memory structure 100 according to various embodiments. Figures 6a to 6m are illustrative diagrams illustrating a method for manufacturing a three-dimensional NAND flash memory structure 100 according to various embodiments.

[0026] Referring to Figure 5, first, in step 510, multiple gate electrodes 120 and multiple insulating films 130 may be stacked along one direction (Z). Specifically, a substrate 110 may be provided. Here, the substrate 110 may be cleaned to remove organic matter, metal ions, particles, etc. from the surface of the substrate 110. After that, as shown in Figure 6a, gate electrodes 120 and insulating films 130 may be alternately stacked on the substrate 110 along one direction (Z). Here, one insulating film 130 and one gate metal 120 may form one stacked layer, and for example, 32 stacked layers or 128 stacked layers may be stacked, but are not limited to these.

[0027] Next, in step 520, a hole 611 may be formed that extends through the gate electrode 120 and the insulating film 130 in one direction (Z). Specifically, as shown in Figure 6b, the hole 611 may be formed by etching the gate electrode 120 and the insulating film 130 in one direction (Z).

[0028] Next, in step 530, a dipole layer 170 may be formed on the gate electrode 120 and the insulating film 130 that are exposed inside the hole 611. The dipole layer 170 may be formed to exhibit dipole properties at the interface between the high dielectric constant material and the low dielectric constant material, and to exhibit different polarities with respect to the gate electrode 120 and the insulating film 130, respectively. The dipole layer 170 may include a first dipole portion 171 and a second dipole portion 173. The first dipole portion 171 may be positioned corresponding to the insulating film 130, respectively. The second dipole portion 173 may be positioned corresponding to the gate electrode 120, respectively.

[0029] Specifically, as shown in Figure 6c, the insulating film 130 may be partially removed from inside the hole 161. Here, a portion of the insulating film 130 may be removed from the surface of the insulating film 130 exposed inside the hole 161 to a predetermined depth. Then, as shown in Figure 6d, a first dipole layer 613 may be formed on the gate electrode 120 and insulating film 130 exposed inside the hole 161. Here, the first dipole layer 613 may be deposited by atomic layer deposition (ALD) over several to tens of cycles (Å to nm). Next, as shown in Figure 6e, the first dipole layer 613 may be partially removed so that the gate electrode 120 is exposed inside the hole 161. As a result, a first dipole portion 171 may be formed from the remaining first dipole layer 613 corresponding to the insulating film 130. Next, as shown in Figure 6f, the gate electrode 120 may be partially removed from inside the hole 161. Here, a portion of the gate electrode 120 may be removed from the surface of the gate electrode 120 exposed inside the hole 161 to a predetermined depth. Next, as shown in Figure 6g, a second dipole layer 615 may be formed on the first dipole portion 171 and the gate electrode 120 exposed inside the hole 161. Here, the second dipole layer 615 may be deposited by atomic layer deposition over several to tens of cycles (Å to nm). Next, as shown in Figure 6h, the second dipole layer 615 may be partially removed so that the first dipole portion 171 is exposed inside the hole 161. As a result, a second dipole portion 173 may be formed from the second dipole layer 615 remaining on the gate electrode 120.

[0030] Next, in step 540, a charge trapping layer 150 may be formed on the dipole layer 170 inside the hole 161. Specifically, as shown in Figure 6i, a barrier layer 160 may be formed on the dipole layer 170 inside the hole 161. Then, as shown in Figure 6j, a charge trapping layer 150 may be formed on the barrier layer 160 inside the hole 161.

[0031] Next, in step 550, a channel layer 140 may be formed on the charge trapping layer 150 inside the hole 161. Specifically, as shown in Figure 6k, a tunnel layer 180 may be formed on the charge trapping layer 150 inside the hole 161. Next, as shown in Figure 6l, a silicon layer 617 may be formed on the tunnel layer 180 inside the hole 161. Next, as shown in Figure 6m, an insulating layer 619 may be formed inside the silicon layer 617 inside the hole 161. As a result, the silicon layer 617 and the insulating layer 619 may form a channel layer 140.

[0032] As a result, the first dipole portion 171 in the dipole layer 170 may have a cathode region facing the barrier layer 160 and an anode region facing one of the insulating films 130, as shown in Figure 3. For this reason, the first dipole portion 171, i.e., the first dipole layer 613, may be formed of at least one insulating material such that the anode region of the first dipole portion 171 faces the insulating film 130, depending on the electronegativity between the insulating film 130 and the barrier layer 160. On the other hand, the second dipole portion 173 in the dipole layer 170 may have an anode region facing the barrier layer 160 and a cathode region facing one of the gate electrodes 120, as shown in Figure 3. For this purpose, the second dipole portion 173, i.e., the second dipole layer 615, may be formed of at least one insulating material such that the anode region of the second dipole portion 173 faces the barrier layer 160, depending on the electronegativity between the gate electrode 120 and the barrier layer 160. For example, at least one insulating material of the first dipole portion 171 or the second dipole portion 173 may include at least one of lanthanum oxide (e.g., La2O3), aluminum oxide (e.g., Al2O3), or silicon oxide. Here, the first dipole portion 171 and the second dipole portion 173 may have the same height as the barrier layer 160, or they may have different heights. For example, the height of the first dipole portion 171 may be greater than or equal to the height of the second dipole portion 173, and vice versa.

[0033] Therefore, this disclosure suppresses the diffusion of electrons trapped in the charge trapping layer 150 by using a dipole layer 170 exhibiting different polarities to the gate electrode 120 and the insulating film 130, respectively. More specifically, the dipole layer 170 may be formed such that the anode region of the dipole portion corresponding to the gate electrode 120, i.e., the second dipole portion 173, faces the barrier layer 160, and the anode region of the dipole portion corresponding to the insulating film 130, i.e., the first dipole portion 171, faces the insulating film 130. As a result, an attractive force is generated on the electrons trapped in the charge trapping layer 150 by the anode region of the second dipole portion 173, and a repulsive force is generated by the cathode region of the first dipole portion 171, thereby suppressing the diffusion of electrons. In other words, the dipole layer 170 can more effectively confine electrons stored in each memory cell. This reduces the electrical influence between memory cells and significantly improves the data retention characteristics of each memory cell.

[0034] In short, this disclosure provides a three-dimensional NAND flash memory element 100 for electron diffusion suppression based on a selective dipole layer 170 and a method for manufacturing the same.

[0035] In various embodiments, the three-dimensional NAND flash memory element 100 may include a plurality of gate electrodes 120 arranged spaced apart from each other along one direction (Z), an insulating film 130 arranged between the gate electrodes 120 along the direction (Z), a channel layer 140 extending through the gate electrodes 120 and the insulating film 130 along the direction (Z), a charge trapping layer 150 surrounding the channel layer 140 between the gate electrodes 120 and the insulating film 130 and the channel layer 140, and a dipole layer 170 disposed between the gate electrodes 120 and the insulating film 130 and the charge trapping layer 150, each exhibiting different polarities with respect to the gate electrodes 120 and the insulating film 130.

[0036] In various embodiments, the three-dimensional NAND flash memory element 100 may further include a shielding layer 160 surrounding the charge trapping layer 150 between the dipole layer 170 and the charge trapping layer 150.

[0037] In various embodiments, the dipole layer 170 may include a first dipole portion 171, each corresponding to an insulating film 130 and having a cathode region facing the barrier layer 160 and an anode region facing one of the insulating films 130, and a second dipole portion 173, each corresponding to a gate electrode 120 and having an anode region facing the barrier layer 160 and a cathode region facing one of the gate electrodes 120.

[0038] In various embodiments, the first dipole portion 171 may be formed of at least one material such that the anode region of the first dipole portion 171 faces the insulating film 130 depending on the electronegativity between the insulating film 130 and the barrier layer 160, and the second dipole portion 173 may be formed of at least one material such that the anode region of the second dipole portion 173 faces the barrier layer 160 depending on the electronegativity between the gate electrode 120 and the barrier layer 160.

[0039] In various embodiments, the first dipole portion 171 and the second dipole portion 173 may have the same height or different heights relative to the barrier layer 160.

[0040] In various embodiments, the three-dimensional NAND flash memory element 100 may further include a tunnel layer 180 surrounding the channel layer 140 between the charge trapping layer 150 and the channel layer 140.

[0041] In various embodiments, a method for manufacturing a three-dimensional NAND flash memory element 100 may include the steps of: alternately stacking a plurality of insulating films 130 and a plurality of gate electrodes 120 along one direction (Z) (510); forming holes 161 that extend through the insulating films 130 and gate electrodes 120 along the direction (Z) (520); forming dipole layers 170 on the insulating films 130 and gate electrodes 120 exposed inside the holes 161 to exhibit different polarities with respect to the gate electrodes 120 and insulating films 130, respectively (530); forming a charge trapping layer 150 on the dipole layers 170 inside the holes 161 (540); and forming a channel layer 140 on the charge trapping layer 150 inside the holes 161 (550).

[0042] In various embodiments, the step (540) of forming the charge trapping layer 150 may include the step of forming a barrier layer 160 on the dipole layer 170 inside the hole 161, and the step of forming the charge trapping layer 150 on the barrier layer 160 inside the hole 161.

[0043] In various embodiments, the dipole layer 170 may include a first dipole portion 171, each corresponding to an insulating film 130 and having a cathode region facing the barrier layer 160 and an anode region facing one of the insulating films 130, and a second dipole portion 173, each corresponding to a gate electrode 120 and having an anode region facing the barrier layer 160 and a cathode region facing one of the gate electrodes 120.

[0044] In various embodiments, the step (530) of forming the dipole layer 170 may include the steps of: partially removing the insulating film 130 from inside the hole 161; forming first dipole layers 163, 170 on the insulating film 130 and gate electrode 120 exposed inside the hole 161; partially removing the first dipole layers 163, 170 so that the gate electrode 120 is exposed inside the hole 161 to generate a first dipole portion 171 corresponding to the insulating film 130; partially removing the gate electrode 120 from inside the hole 161; forming second dipole layers 165, 170 on the first dipole portion 171 and gate electrode 120 exposed inside the hole 161; and partially removing the second dipole layers 165, 170 so that the first dipole portion 171 is exposed inside the hole 161 to generate a second dipole portion 173 corresponding to the gate electrode 120.

[0045] In various embodiments, the first dipole portion 171 may be formed of at least one material such that the anode region of the first dipole portion 171 faces the insulating film 130 depending on the electronegativity between the insulating film 130 and the barrier layer 160, and the second dipole portion 173 may be formed of at least one material such that the anode region of the second dipole portion 173 faces the barrier layer 160 depending on the electronegativity between the gate electrode 120 and the barrier layer 160.

[0046] In various embodiments, the first dipole portion 171 and the second dipole portion 173 may have the same height or different heights relative to the barrier layer 160.

[0047] In various embodiments, the first dipole layers 163, 170 and the second dipole layers 165, 170 may be formed by atomic layer deposition.

[0048] In various embodiments, the step (550) of forming the channel layer 140 may include the step of forming a tunnel layer 180 on the charge trapping layer 150 inside the hole 161, and the step of forming the channel layer 140 on the tunnel layer 180 inside the hole 161.

[0049] In various embodiments, the step of forming the channel layer 140 on the tunnel layer 180 may include the step of forming a silicon layer on the tunnel layer 180 inside the hole 161, and the step of forming an insulating layer inside the silicon layer.

[0050] The various embodiments and terminology used herein are not intended to limit the technology described herein to any particular embodiment, but should be understood to include various modifications, equivalents, and / or substitutes of such embodiments. In relation to the description of the drawings, similar reference numerals may be used for similar components. A singular expression may include a plural expression unless the context clearly indicates a different meaning. In this document, expressions such as "A or B," "A and / or B," "A, B, or C," or "A, B, and / or C" may include any possible combination of the listed items. Expressions such as "first," "second," "primary," or "secondary" are used to modify the component in question, regardless of its order or importance, and to distinguish one component from another; they are not intended to limit the component. When one component (e.g., component 1) is described as being "connected (functionally or communicatively)" to another component (e.g., component 2), that component may be directly connected to the other component, or it may be connected via another component (e.g., component 3).

[0051] According to various embodiments, each component of the described component (e.g., a module or program) may include one or more entities. According to various embodiments, one or more components or steps of the aforementioned components may be omitted, or one or more other components or programs may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the component of the multiple components before integration. According to various embodiments, steps performed by a module, program, or other component may be performed sequentially, in parallel, iteratively, or heuristically, or one or more steps may be performed in a different order, omitted, or one or more other programs may be added.

Claims

1. A three-dimensional NAND flash memory element, Multiple gate electrodes arranged spaced apart from each other along one direction, An insulating film disposed between the gate electrodes along the aforementioned direction, A channel layer extending through the gate electrode and the insulating film in the aforementioned direction, Between the gate electrode and the insulating film and the channel layer, a charge trapping layer surrounding the channel layer, A dipole layer disposed between the gate electrode and the insulating film and the charge trapping layer, exhibiting different polarities with respect to the gate electrode and the insulating film, respectively. including, Three-dimensional NAND flash memory element.

2. A barrier layer surrounding the charge trapping layer between the dipole layer and the charge trapping layer. Further including, The three-dimensional NAND flash memory element according to claim 1.

3. The aforementioned dipole layer is A first dipole portion is arranged corresponding to each of the insulating films and has a cathode region facing the barrier layer and an anode region facing one of the insulating films, and A second dipole portion is arranged corresponding to each of the aforementioned gate electrodes and has an anode region facing the barrier layer and a cathode region facing one of the gate electrodes. including, The three-dimensional NAND flash memory element according to claim 2.

4. The first dipole portion is formed of at least one material such that the anode region of the first dipole portion faces the insulating film, depending on the electronegativity between the insulating film and the barrier layer material. The second dipole portion is formed of at least one material such that the anode region of the second dipole portion faces the barrier layer, depending on the electronegativity between the gate electrode and the barrier layer material. The three-dimensional NAND flash memory element according to claim 3.

5. The first dipole portion and the second dipole portion have the same height or different heights with respect to the barrier layer. The three-dimensional NAND flash memory element according to claim 3.

6. A tunnel layer surrounding the channel layer between the charge trapping layer and the channel layer. Further including, The three-dimensional NAND flash memory element according to claim 1.

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