Semiconductor equipment

Abstract

To provide a semiconductor device whose characteristics can be improved.SOLUTION: According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating member. The first layer includes SiC. The second layer includes AlxInyGa1-x-yN (x+y=1, 0≤x<1, 0≤y≤1). The third layer includes AlzGa1-zN (x<z≤1). The second layer includes a first compound region provided between a third partial region of the first layer and the third electrode. The second layer does not include a region overlapping a fourth partial region of the first layer and does not include a region overlapping a fifth partial region of the first layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] For example, there are semiconductor devices that use SiC. Good performance characteristics are desired in semiconductor devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-182247 [Overview of the project] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device capable of improving its characteristics. [Means for solving the problem]

[0005] According to embodiments of the present invention, the semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating member. The position of the third electrode in a first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction. The first layer includes SiC. The first layer includes a first subregion, a second subregion, a third subregion, a fourth subregion, and a fifth subregion. The direction from the first subregion to the first electrode is along a second direction intersecting the first direction. The direction from the second subregion to the second electrode is along the second direction. The direction from the third subregion to the third electrode is along the second direction. The fourth subregion is between the first subregion and the third subregion in the first direction. The fifth subregion is between the third subregion and the second subregion in the first direction. The second layer is Al x In y Ga1-x-y N(x + y ≦ 1. It includes 0 ≦ x < 1, 0 ≦ y ≦ 1). The second layer includes a first compound region provided between the third partial region and the third electrode. The third layer is Al z Ga 1-z It includes N(x < z ≦ 1). The third layer includes a first part, a second part, and a third part. The direction from the fourth partial region to the first part is along the second direction. The direction from the fifth partial region to the second part is along the second direction. The third part is between the third partial region and the first compound region. The insulating member includes a first insulating region. The first insulating region is between the first compound region and the third electrode. The second layer does not include a region overlapping with the fourth partial region in the second direction and does not include a region overlapping with the fifth partial region in the second direction. Or, the second layer includes a second compound region and a third compound region. The direction from the fourth partial region to the second compound region and the direction from the fifth partial region to the third compound region are along the second direction. The first thickness of the first compound region along the second direction is thicker than the second thickness of the second compound region along the second direction and thicker than the third thickness of the third compound region along the second direction.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 5] FIGS. 5(a) to 5(d) are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. [Figure 6] FIGS. 6(a) to 6(c) are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first layer 11, a second layer 12, a third layer 13, and an insulating member 41.

[0009] The first direction D1 from the first electrode 51 to the second electrode 52 is defined as the X-axis direction. One direction perpendicular to the X-axis direction is defined as the Z-axis direction. The directions perpendicular to both the X-axis direction and the Z-axis direction are defined as the Y-axis direction.

[0010] The position of the third electrode 53 in the first direction D1 is between the position of the first electrode 51 and the position of the second electrode 52 in the first direction D1. These electrodes are aligned, for example, along the Y-axis direction (for example, the third direction D3).

[0011] The first layer 11 includes SiC. The first layer 11 may include, for example, a SiC substrate. The first layer 11 includes a first subregion 11a, a second subregion 11b, a third subregion 11c, a fourth subregion 11d, and a fifth subregion 11e. The direction from the first subregion 11a to the first electrode 51 is along the second direction D2. The second direction D2 intersects the first direction D1. The second direction D2 is, for example, the Z-axis direction.

[0012] The direction from the second partial region 11b to the second electrode 52 is along the second direction D2. The direction from the third partial region 11c to the third electrode 53 is along the second direction D2. At least a part of the first partial region 11a overlaps with the first electrode 51 in the second direction D2. At least a part of the second partial region 11b overlaps with the second electrode 52 in the second direction D2. At least a part of the third partial region 11c overlaps with the third electrode 53 in the second direction D2.

[0013] The fourth partial region 11d is between the first partial region 11a and the third partial region 11c in the first direction D1. The fifth partial region 11e is between the third partial region 11c and the second partial region 11b in the first direction D1. In the first to fifth partial regions 11a to 11e, the boundaries between each other may be unclear.

[0014] The second layer 12 is Al x In y Ga 1-x-y N(x + y ≦ 1, 0 ≤ x < 1, 0 ≤ y ≤ 1). In one example, the second layer 12 contains AlGaN. In one example, the second layer 12 contains InGaN. In one example, the second layer 12 contains AlInGaN.

[0015] The second layer 12 includes a first compound region 12a. The first compound region 12a is provided between the third partial region 11c and the third electrode 53. As will be described later, the second layer 12 may further include another region.

[0016] The third layer 13 is Al z Ga 1-z N(x < z ≤ 1). In one example, the composition ratio z is not less than 0.8. For example, the third layer 13 contains AlN.

[0017] The third layer 13 includes a first portion 13a, a second portion 13b, and a third portion 13c. The direction from the fourth sub-region 11d to the first portion 13a is along the second direction D2. The direction from the fifth sub-region 11e to the second portion 13b is along the second direction D2. The third portion 13c is located between the third sub-region 11c and the first compound region 12a.

[0018] The insulating member 41 includes a first insulating region 41a. The first insulating region 41a is located between the first compound region 12a and the third electrode 53.

[0019] The first electrode 51 is electrically connected, for example, to the first subregion 11a. The first electrode 51 may also be electrically connected, for example, to the first portion 13a. The second electrode 52 is electrically connected, for example, to the second subregion 11b. The second electrode 52 may also be electrically connected, for example, to the second portion 13b.

[0020] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential referenced to the potential of the first electrode 51. The first electrode 51 functions, for example, as a source electrode. The second electrode 52 functions, for example, as a drain electrode. The third electrode 53 functions, for example, as a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0021] The fourth subregion 11d includes the region opposite the first subregion 13a. The fifth subregion 11e includes the region opposite the second subregion 13b. Carrier regions 10c are formed in these regions. The carrier regions 10c are, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (high electron mobility transistor).

[0022] As shown in Figure 1, in one example of the embodiment, the second layer 12 does not include the region that overlaps with the fourth subregion 11d in the second direction D2, nor does it include the region that overlaps with the fifth subregion 11e in the second direction D2. As will be described later, the second layer 12 may include other regions. In this case, the first thickness t1 of the first compound region 12a along the second direction D2 may be thinner than the thickness of the other regions.

[0023] Because the second layer 12 does not include a region that overlaps with the fourth subregion 11d in the second direction D2, and does not include a region that overlaps with the fifth subregion 11e in the second direction D2, carrier regions 10c are formed in the region of the fourth subregion 11d that faces the first portion 13a, and in the region of the fifth subregion 11e that faces the second portion 13b.

[0024] On the other hand, in the region overlapping with the third electrode 53, the first compound region 12a of the second layer 12 is provided. In the region of the first layer 11 overlapping with the first compound region 12a, the formation of the carrier region 10c is suppressed. As a result, for example, a high threshold voltage can be obtained. For example, normally-off operation can be obtained. According to this embodiment, a semiconductor device with improved characteristics can be provided.

[0025] For example, there is a first reference example that uses a recessed gate electrode. There is a second reference example that uses impurity doping. In these reference examples as well, it is possible to obtain a high threshold voltage. However, these reference examples involve complex processes.

[0026] In the embodiment, for example, a recessed gate electrode is not required. Impurity doping is not required. In the embodiment, a stable high threshold voltage can be obtained through a simple process.

[0027] In this embodiment, for example, a second layer 12 is provided locally. This allows for appropriate control of polarization. A carrier region 10c is provided locally. High carrier mobility and low on-resistance are obtained. For example, by providing a first layer 11 containing SiC, high heat dissipation is obtained. Stable operating characteristics are easily obtained.

[0028] In the embodiment, the second layer 12 has polarity. The third layer 13 has polarity, for example.

[0029] For example, in the third layer 13, the grid length in the intersecting direction that intersects with the second direction D2 is shorter than the grid length along the intersecting direction in the second layer 12. The intersecting direction is, for example, along the XY plane. The intersecting direction is, for example, the a-axis direction. For example, the grid length along the a-axis in the third layer 13 is shorter than the grid length along the a-axis in the second layer 12. In the portion where the second layer 12 is provided, the formation of the carrier region 10c is suppressed.

[0030] In the embodiment, the composition ratio z in the third layer 13 is preferably 0.8 or higher. This facilitates the proper formation of the carrier region 10c. The third layer 13 contains, for example, AlN. The carrier region 10c is properly formed.

[0031] In one example, the composition ratio x in the second layer 12 may be 0.1 or less. In this case, the composition ratio z is 0.8 or more (e.g., AlN), the composition ratio y is 0.01 or more and 0.2 or less, and the thickness t13c of the third portion 13c along the second direction D2 is 3 nm or more and 5 nm or less.

[0032] In one example, the composition ratio z is 0.8 or greater (e.g., AlN), the composition ratio x is between 0.1 and 0.5, and the thickness t13c of the third portion 13c along the second direction D2 is between 2 nm and 4 nm.

[0033] For example, the first thickness t1 is thicker than the thickness t13c along the second direction D2 of the third portion 13c. This causes the carrier region 10c to be concentrated, making it easier to obtain a stable high threshold voltage.

[0034] For example, the first thickness t1 is preferably 1.05 times or more the thickness t13c along the second direction D2 of the third portion 13c. This makes it less likely for the carrier region 10c to occur locally and stably. A high threshold voltage can be easily obtained stably. The first thickness t1 may also be 1.5 times or more the thickness t13c. The first thickness t1 may also be 2 times or more the thickness t13c.

[0035] As shown in Figure 1, the insulating member 41 may further include a second insulating region 41b and a third insulating region 41c. The first portion 13a is located between the fourth portion region 11d and the second insulating region 41b. For example, the first portion 13a is in contact with the fourth portion region 11d and the second insulating region 41b. The second portion 13b is located between the fifth portion region 11e and the third insulating region 41c. The second portion 13b is in contact with the fifth portion region 11e and the third insulating region 41c.

[0036] The thickness t41 along the second direction D2 of the first insulating region 41a is preferably, for example, 20 nm or more and 100 nm or less. A thickness t41 of 20 nm or more makes it easier to stably obtain a continuous film shape in the first insulating region 41a. A thickness t41 of 100 nm or less makes it easier to obtain practical properties.

[0037] In this embodiment, the third layer 13 is in contact with the first layer 11. In this example, the first compound region 12a is in contact with the third layer 13.

[0038] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 2, the semiconductor device 111 according to this embodiment includes a fourth layer 14. The configuration of the semiconductor device 111, excluding this layer, may be the same as that of the semiconductor device 110.

[0039] At least a portion of the fourth layer 14 lies between the third layer 13 and the second layer 12. The fourth layer 14 is, for example, Al α Ga 1-αIt includes N(x < α < z). For example, the third layer 13 contains AlN, and the fourth layer 14 contains AlGaN. Even in such a semiconductor device 111, by providing the second layer 12, the polarization is appropriately controlled. The carrier region 10c is locally provided. For example, a high threshold voltage can be obtained. For example, a normally-off operation can be obtained. A semiconductor device with improved characteristics can be provided. In the semiconductor device 111, the third layer 13 and the fourth layer 14 may be regarded as regions where the Al composition ratio changes.

[0040] FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in FIG. 3, in the semiconductor device 112 according to the embodiment, the second layer 12 includes a second compound region 12b and a third compound region 12c. The configuration of the semiconductor device 112 except this may be the same as the configuration of the semiconductor device 110.

[0041] The direction from the fourth partial region 11d to the second compound region 12b and the direction from the fifth partial region 11e to the third compound region 12c are along the second direction D2. Let the thickness along the second direction D2 of the second compound region 12b be the second thickness t2. Let the thickness along the second direction D2 of the third compound region 12c be the third thickness t3. The first thickness t1 (the thickness of the first compound region 12a along the second direction D2) is thicker than the second thickness t2 and thicker than the third thickness t3.

[0042] For example, in the first layer 11, in the region overlapping the second compound region 12b in the second direction D2, the carrier region 10c is formed. In the first layer 11, in the region overlapping the third compound region 12c in the second direction D2, the carrier region 10c is formed. On the other hand, in the region overlapping the first compound region 12a in the second direction D2, the formation of the carrier region is suppressed. The polarization is appropriately controlled. The carrier region 10c is locally provided. For example, a high threshold voltage can be obtained. For example, a normally-off operation can be obtained. A semiconductor device with improved characteristics can be provided.

[0043] In the semiconductor device 112, it is preferable that the first thickness t1 is 1.05 times or more the second thickness t2 and 1.05 times or more the third thickness t3. This allows for more appropriate control of polarization. High threshold voltage and high carrier mobility are easily obtained. For example, the first thickness t1 may be 1.5 times or more the second thickness t2 and 1.5 times or more the third thickness t3. In the embodiment, the first thickness t1 may be 2 times or more the second thickness t2 and 2 times or more the third thickness t3. A high threshold voltage can be obtained more stably.

[0044] In the semiconductor device 112, the first compound region 12a is located between a part of the third layer 13 and another part of the third layer 13 in the first direction D1. For example, a recess is provided in the third layer 13, and a part of the second layer 12 is provided in the recess.

[0045] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 4, in the semiconductor device 113 according to this embodiment, the second layer 12 also includes a second compound region 12b and a third compound region 12c. The configuration of the semiconductor device 113 other than this can be the same as the configuration of the semiconductor device 112.

[0046] In the semiconductor device 113, the first thickness t1 is thicker than the second thickness t2 and thicker than the third thickness t3. In the semiconductor device 113, the first compound region 12a is located between a part of the insulating member 41 and another part of the insulating member 41 in the first direction D1. Polarization is appropriately controlled in the semiconductor device 113 as well. A carrier region 10c is provided locally. For example, a high threshold voltage can be obtained. For example, normally-off operation can be obtained. A semiconductor device with improved characteristics can be provided.

[0047] A fourth layer 14 may be provided in semiconductor devices 112 and 113. In semiconductor devices 111 to 113, for example, high carrier mobility and low on-resistance can be obtained. For example, high heat dissipation can be obtained. Stable operating characteristics can be easily obtained.

[0048] In semiconductor devices 110 to 113, for example, the second layer 12 does not need to contain impurities. For example, the second layer 12 does not contain the first element, or the concentration of the first element in the second layer 12 is 1 × 10⁻⁶. 17 / cm 3 It is acceptable to be less than [a certain value]. The first element includes, for example, at least one selected from the group consisting of Mg, Zn, and C.

[0049] In semiconductor devices 110 to 113, for example, the third electrode 53 may include a region that does not overlap with the first compound region 12a in the second direction D2.

[0050] In semiconductor devices 110 to 113, the SiC included in the first layer 11 includes, for example, at least one selected from the group consisting of 4H-SiC and 6H-SiC. Good properties are easily obtained.

[0051] In the example above, the second layer 12 is Al x In y Ga 1-x-y N(x+y ≦ Includes 1, 0≦x<1, 0≦y≦1).

[0052] In embodiments (for example, the second embodiment), the second layer 12 may contain other materials. For example, the second layer 12 may contain a first material. The first material may contain at least one selected from the group consisting of zinc oxide, a first compound, and a second compound. The first compound contains group II and group VI elements. The second compound contains group III and group V elements. The second layer 12 is polar. In this case as well, the second layer 12 includes a first compound region 12a (see Figures 1 to 4). The first compound region 12a is provided between the third subregion 11c and the third electrode 53. In this case as well, the third portion 13c of the third layer 13 is located between the third subregion 11c and the first compound region 12a. In the third layer 13, the lattice length in the crossing direction intersecting the second direction D2 is shorter than the lattice length along the crossing direction in the second layer 12. The crossing direction is, for example, along the a-axis.

[0053] Even in such semiconductor devices, polarization is appropriately controlled. A carrier region 10c is locally provided. For example, a high threshold voltage can be obtained. For example, normally-off operation can be achieved. A semiconductor device with improved characteristics can be provided.

[0054] In one example where the second layer 12 contains the first material described above, the second layer 12 contains zinc oxide, and the third layer 13 contains AlN (or AlGaN). In semiconductor devices 111 to 113, the second layer 12 may contain the first material described above. Normally-off operation is possible. Even when the second layer 12 contains the first material described above, for example, high carrier mobility and low on-resistance can be obtained. For example, high heat dissipation can be obtained. Stable operating characteristics are easily obtained. Even when the second layer 12 contains the first material described above, the SiC included in the first layer 11 includes, for example, at least one selected from the group consisting of 4H-SiC and 6H-SiC.

[0055] The following describes an example of a method for manufacturing a semiconductor device according to the embodiment. Figures 5(a) to 5(d) and Figures 6(a) to 6(c) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. As shown in Figure 5(a), the first layer 11 is prepared. The first layer 11 may be, for example, a SiC substrate.

[0056] As shown in Figure 5(b), a third film 13f, which will become the third layer 13, is formed on the first layer 11. As shown in Figure 5(c), a second film 12f, which will become the second layer 12, is formed on the third film 13f. These films can be formed, for example, by the MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0057] As shown in Figure 5(d), a portion of the second film 12f is removed. This yields the first compound region 12a of the second layer 12. In this case, thin portions (second compound region 12b and third compound region 12c) may be formed in the second layer 12.

[0058] As shown in Figure 6(a), an insulating film 41f, which will serve as the insulating member 41, is formed on the third film 13f and the second layer 12. The insulating film 41f can be formed, for example, by CVD (Chemical Vapor Deposition).

[0059] As shown in Figure 6(b), a portion of the insulating film 41f and a portion of the third film 13f are removed, exposing a portion of the first layer 11. The insulating member 41 is obtained from the insulating film 41f. The third layer 13 is obtained from the third film 13f.

[0060] As shown in Figure 6(c), the first electrode 51, the second electrode 52, and the third electrode 53 are formed. This gives rise to the semiconductor device 110.

[0061] In the embodiment, the first electrode 51 and the second electrode 52 include, for example, Al. The third electrode 53 includes, for example, at least one selected from the group consisting of TiN and Au. The insulating member 41 includes, for example, at least one selected from the group consisting of oxygen and nitrogen, and at least one selected from the group consisting of silicon and aluminum.

[0062] Information regarding shape, length, and thickness can be obtained, for example, through electron microscopy. Information regarding the material's composition can be obtained through SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy Dispersive X-ray Spectroscopy).

[0063] According to the embodiment, a semiconductor device capable of improving characteristics can be provided.

[0064] Embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configuration of each element such as electrodes, layers, and insulating members included in a semiconductor device is included within the scope of the present invention as long as those skilled in the art can appropriately select from the known range to implement the present invention and obtain similar effects.

[0065] Combinations of two or more elements from each example, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0066] All semiconductor devices that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0067] Within the scope of the concept of this invention, a person skilled in the art would be able to conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of this invention.

[0068] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0069] 10c...Carrier region, 11-14...1st-4th layers, 11a-11e...1st-5th subregions, 12a-12c...1st-3rd compound regions, 12f...2nd film, 13a-13c...1st-3rd subregions, 13f...3rd film, 41...Insulating material, 41a-41c...1st-3rd insulating regions, 41f...Insulating film, 51-53...1st-3rd electrodes, 110-113...Semiconductor device, D1-D3...1st-3rd directions, t1-t3...1st-3rd thicknesses, t13c...Thickness, t41...Thickness

Claims

1. First electrode and, The second electrode and A third electrode, wherein the position of the third electrode in the first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction, A first layer made of SiC, the first layer comprising a first subregion, a second subregion, a third subregion, a fourth subregion and a fifth subregion, wherein the direction from the first subregion to the first electrode follows a second direction intersecting the first direction, the direction from the second subregion to the second electrode follows the second direction, the direction from the third subregion to the third electrode follows the second direction, the fourth subregion is located between the first subregion and the third subregion in the first direction, and the fifth subregion is located between the third subregion and the second subregion in the first direction, Al ｘ In ｙ Ga １－ｘ－ｙ A second layer consisting of N (x + y ≤ 1, 0 ≤ x < 1, 0 ≤ y ≤ 1), wherein the second layer includes a first compound region provided between the third partial region and the third electrode, Al ｚ Ga １－ｚ A third layer comprising N (x < z ≤ 1), wherein the third layer includes a first portion, a second portion, and a third portion, the direction from the fourth portion region to the first portion is along the second direction, the direction from the fifth portion region to the second portion is along the second direction, and the third portion is located between the third portion region and the first compound region, and the third layer is... An insulating member including a first insulating region, wherein the first insulating region is located between the first compound region and the third electrode, Equipped with, The third layer is in contact with the first and second layers, and the second layer does not include a region that overlaps with the fourth sub-region in the second direction, nor does it include a region that overlaps with the fifth sub-region in the second direction, or A semiconductor device wherein the third layer is in contact with the first and second layers, the second layer includes a second compound region and a third compound region, the direction from the fourth subregion to the second compound region and the direction from the fifth subregion to the third compound region are along the second direction, the first thickness of the first compound region along the second direction is greater than the second thickness of the second compound region along the second direction, and the third thickness of the third compound region along the second direction.

2. The semiconductor device according to claim 1, wherein the composition ratio z is 0.8 or greater.

3. The semiconductor device according to claim 1, wherein the third layer comprises AlN.

4. The semiconductor device according to any one of claims 1 to 3, wherein the composition ratio x is 0.1 or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first thickness is greater than the thickness of the third portion along the second direction.

6. The semiconductor device according to any one of claims 1 to 4, wherein the first thickness is 1.05 times or more the thickness of the third portion along the second direction.

7. The aforementioned composition ratio z is 0.8 or greater. The aforementioned composition ratio y is 0.01 or more and 0.2 or less. The semiconductor device according to claim 5 or 6, wherein the thickness of the third portion along the second direction is 3 nm or more and 5 nm or less.

8. The aforementioned composition ratio z is 0.8 or greater. The aforementioned composition ratio x is 0.01 or more and 0.5 or less. The semiconductor device according to claim 5 or 6, wherein the thickness of the third portion along the second direction is 2 nm or more and 4 nm or less.

9. The insulating member further includes a second insulating region and a third insulating region, The first portion is located between the fourth portion region and the second insulating region, and is in contact with the fourth portion region and the second insulating region. The semiconductor device according to any one of claims 1 to 8, wherein the second portion is located between the fifth subregion and the third insulating region and is in contact with the fifth subregion and the third insulating region.

10. The semiconductor device according to any one of claims 1 to 9, wherein the thickness of the first insulating region along the second direction is 20 nm or more and 100 nm or less.

11. The aforementioned second layer includes the aforementioned second compound region and the aforementioned third compound region, The semiconductor device according to any one of claims 1 to 8, wherein the first thickness is 1.05 times or more the second thickness and 1.05 times or more the third thickness.

12. The aforementioned second layer includes the aforementioned second compound region and the aforementioned third compound region, The semiconductor device according to any one of claims 1 to 8, wherein the first thickness is 1.5 times or more the second thickness and the third thickness is 1.5 times or more.

13. The aforementioned second layer includes the aforementioned second compound region and the aforementioned third compound region, The semiconductor device according to any one of claims 1 to 8, wherein the first compound region is located between a part of the third layer and another part of the third layer in a first direction.

14. The aforementioned second layer includes the aforementioned second compound region and the aforementioned third compound region, The semiconductor device according to any one of claims 1 to 8, wherein the first compound region is located between a part of the insulating member and another part of the insulating member in the first direction.

15. The second layer does not contain the first element, or the concentration of the first element in the second layer is 1 × 10⁻⁶ １７ cm ３ It is less than, The semiconductor device according to any one of claims 1 to 14, wherein the first element comprises at least one selected from the group consisting of Mg, Zn, and C.

16. The semiconductor device according to any one of claims 1 to 15, wherein the third electrode includes a region that does not overlap with the first compound region in the second direction.

17. A semiconductor device according to any one of claims 1 to 16, capable of performing normally-off operation.

18. First electrode and, The second electrode and A third electrode, wherein the position of the third electrode in the first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction, A first layer made of SiC, the first layer comprising a first subregion, a second subregion, a third subregion, a fourth subregion and a fifth subregion, wherein the direction from the first subregion to the first electrode follows a second direction intersecting the first direction, the direction from the second subregion to the second electrode follows the second direction, the direction from the third subregion to the third electrode follows the second direction, the fourth subregion is located between the first subregion and the third subregion in the first direction, and the fifth subregion is located between the third subregion and the second subregion in the first direction, Al ｘ In ｙ Ga １－ｘ－ｙ A second layer consisting of N (x + y ≤ 1, 0 ≤ x < 1, 0 ≤ y ≤ 1), wherein the second layer includes a first compound region provided between the third partial region and the third electrode, the second layer, and Al ｚ Ga １－ｚ A third layer comprising N (x < z ≤ 1), wherein the third layer includes a first portion, a second portion, and a third portion, the direction from the fourth portion region to the first portion is along the second direction, the direction from the fifth portion region to the second portion is along the second direction, and the third portion is located between the third portion region and the first compound region, and the third layer is... An insulating member including a first insulating region, wherein the first insulating region is located between the first compound region and the third electrode, The fourth layer, Equipped with, At least a portion of the fourth layer lies between the third layer and the second layer, the fourth layer comprises Al α Ga 1-α N (x < α < z), the third layer is in contact with the first and fourth layers, the fourth layer is in contact with the second layer, the second layer does not include a region that overlaps with the fourth sub-region in the second direction, nor does it include a region that overlaps with the fifth sub-region in the second direction, or A semiconductor device wherein at least a portion of the fourth layer lies between the third layer and the second layer, the fourth layer comprises Al α Ga 1-α N (x < α < z), the third layer is in contact with the first layer and the fourth layer, the fourth layer is in contact with the second layer, the second layer comprises a second compound region and a third compound region, the direction from the fourth partial region to the second compound region and the direction from the fifth partial region to the third compound region are along the second direction, the first thickness of the first compound region along the second direction is greater than the second thickness of the second compound region along the second direction, and the third thickness of the third compound region along the second direction.

19. First electrode and, The second electrode and A third electrode, wherein the position of the third electrode in the first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction, A first layer made of SiC, the first layer comprising a first subregion, a second subregion, a third subregion, a fourth subregion and a fifth subregion, wherein the direction from the first subregion to the first electrode follows a second direction intersecting the first direction, the direction from the second subregion to the second electrode follows the second direction, the direction from the third subregion to the third electrode follows the second direction, the fourth subregion is located between the first subregion and the third subregion in the first direction, and the fifth subregion is located between the third subregion and the second subregion in the first direction, Al ｘ In ｙ Ga １－ｘ－ｙ A second layer consisting of N (x + y ≤ 1, 0 ≤ x < 1, 0 ≤ y ≤ 1), wherein the second layer includes a first compound region provided between the third partial region and the third electrode, Al ｚ Ga １－ｚ A third layer comprising N (x < z ≤ 1), wherein the third layer includes a first portion, a second portion, and a third portion, the direction from the fourth portion region to the first portion is along the second direction, the direction from the fifth portion region to the second portion is along the second direction, and the third portion is located between the third portion region and the first compound region, and the third layer is... An insulating member including a first insulating region, wherein the first insulating region is located between the first compound region and the third electrode, Equipped with, The second layer does not include a region that overlaps with the fourth subregion in the second direction, nor does it include a region that overlaps with the fifth subregion in the second direction, or A semiconductor device wherein the second layer includes a second compound region and a third compound region, the direction from the fourth subregion to the second compound region and the direction from the fifth subregion to the third compound region are along the second direction, the first thickness of the first compound region along the second direction is greater than the second thickness of the second compound region along the second direction and greater than the third thickness of the third compound region along the second direction, and the first compound region is located in the first direction between a part of the third layer and another part of the third layer.

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