Differential amplifier circuit

Abstract

To provide a differential amplifier circuit that reduces or suppresses changes of a threshold voltage in a differential pair using MOS transistors that are attributable to NBTIs and PBTIs, without incurring an increase in current consumption.SOLUTION: In the differential amplifier circuit, a voltage limiting circuit 301 that limits the drain voltages of transistors 1, 2 for a differential pair that constitute an input differential pair 101 within a prescribed voltage range is such that a voltage value, equivalent to the voltage difference between the drain potential and the gate potential of the transistors 1, 2 for the differential pair, which is needed for the variation of an input offset voltage due to changes of the threshold voltages of the transistors 1, 2 for the differential pair attributable to an NBTI to be a desired magnitude, is its upper limit value in the prescribed voltage range. On the other hand, a voltage value, equivalent to the drain voltages of the transistors 1, 2 for the differential pair when a current inflow from the input differential pair 101 to the voltage limiting circuit 301 becomes zero in an equilibrium state in which the gate voltages of the transistors 1, 2 for the differential pair are at the same potential, is its lower limit value in the prescribed voltage range.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a differential amplifier circuit used in an operational amplifier or a comparator, and particularly relates to suppressing and reducing the secular change of an input offset voltage caused by a change in the threshold voltage of a MOS transistor due to NBTI (Negative Bias Temperature Instability) or PBTI (Positive Bias Temperature Instability).

Background Art

[0002] The input offset voltage of an operational amplifier or a comparator is one of the important parameters that determine the performance of a device. One of the causes of this input offset voltage is a so-called element mismatch, which is an inconsistency in the electrical characteristics of various elements constituting the differential amplifier circuit used in the first stage of the operational amplifier or the comparator. Therefore, reducing the element mismatch of the differential amplifier circuit is important for improving the input offset voltage of the operational amplifier or the comparator.

[0003] By the way, in a general differential amplifier circuit with an active load, this input offset voltage is known to vary with a change in the threshold voltage Vth of a PMOS (P-channel Metal-Oxide Semiconductor) transistor (hereinafter referred to as "PMOS") due to the above-mentioned NBTI. Here, the change in the threshold voltage Vth means, for example, a change such that Vth = -0.7V becomes -0.8V. Regarding the change in the threshold voltage Vth due to this NBTI, an explanation will be given while referring to FIGS. 14 and 15. First, FIG. 14 shows a configuration example of a general differential amplifier circuit with an active load.

[0004] In other words, the differential amplifier circuit shown in Figure 14 is composed of a differential pair consisting of PMOS transistors M1 and M2, and an active load consisting of NMOS (N-channel Metal-Oxide Semiconductor) transistors M3 and M4 (hereinafter referred to as "NMOS").

[0005] In a differential amplifier circuit with this configuration, the change in threshold voltage Vth due to NBTI becomes significantly apparent under the bias conditions shown in Figure 15. Figure 14 shows the voltages of the main nodes under the bias conditions shown in Figure 15. First, the bias conditions are: positive power supply voltage VDD = 5.5V, negative power supply voltage VSS = 0V, inverting input terminal voltage Vinm = 5.5V, and non-inverting input terminal voltage Vg = 0 (see Figure 15).

[0006] Under these bias conditions, the element whose threshold voltage Vth changes due to the influence of NBTI is transistor M2. Under the bias conditions described above, the gate voltage Vg of transistor M2 is Vg=0V, the source potential Vs is Vs=5.3V, and the drain potential Vd is Vd=5.3V. Thus, when the gate potential is low and the source and drain potentials are high, the threshold voltage Vth changes due to the influence of NBTI. As shown in Figure 17, the change in this threshold voltage Vth tends to increase exponentially as the difference between the gate potential and the drain potential increases.

[0007] The fluctuations in the threshold voltage Vth shown in Figure 17 represent the estimated change in the threshold voltage Vth when the gate potential Vg=0V, drain potential Vd=source potential Vs=5.3V conditions, as described above and affected by NBTI, are maintained for approximately 10 years, based on temperature acceleration tests. The amount of variation in the threshold voltage Vth corresponds to the amount of variation in the input offset voltage in the operational amplifier or comparator. In other words, if an operational amplifier or comparator with a differential amplifier circuit as shown in Figure 14 is used for 10 years under the bias conditions described earlier (see Figure 15), the input offset voltage will fluctuate by approximately 80mV, which is the amount of variation indicated as "conventional technology" in Figure 17. Generally, the input offset voltage of operational amplifiers and comparators is specified to be a few millivolts or less, so the aging of the input offset voltage as described above becomes a major problem.

[0008] One way to address this age-related change in input offset voltage is to use a differential amplifier circuit with a circuit configuration such as that disclosed in Patent Document 1. Figure 16 shows the differential amplifier circuit disclosed in Patent Document 1, and this circuit will be described below with reference to the figure. This differential amplifier circuit has a configuration in which transistors M101 and M102 using NMOS and a current source I2 are added to the differential amplifier circuit shown earlier in Figure 14. The addition of such elements will alleviate the NBTI state of transistor M2.

[0009] The extent to which the NBTI state is relaxed in the differential amplifier circuit shown in Figure 16 will be explained below. First, as a premise, in the differential amplifier circuit shown in Figure 16, the bias conditions are the same as those shown in Figure 15. In Figure 16, the voltages at the main nodes are shown when the bias conditions described above are applied. In the configuration shown in Figure 14, both the drain and source potentials of transistor M2 were 5.3V, whereas in the differential amplifier circuit shown in Figure 16, under the same bias conditions, both are 1.5V. Therefore, the difference between the drain potential Vd and the gate potential Vg of transistor M2 (Vd-Vg) is (Vd-Vg)=1.5V, which is significantly smaller than the difference between the drain potential and gate potential in the differential amplifier circuit shown in Figure 14.

[0010] In Figure 17, the amount of variation in the threshold voltage Vth with respect to the difference between the drain potential of 1.5V and the gate potential is plotted at the location indicated by "Patent Document," and it can be confirmed that the specific amount of variation is approximately 0mV. Thus, the drain and source potentials of transistor M2 can be reduced because the gate potential of transistor M2 is transmitted to transistor M1 via transistors M102 and M101.

[0011] The gate potential Vy of transistor M1 is suppressed to Vy = 0.2V by the aforementioned element. As a result, the source potentials Vs of transistors M1 and M2 are also low, at Vs = 1.5V. Since the source potential of transistor M2 is Vs = 1.5V, the drain potential Vd is also suppressed to Vd = 1.5V.

[0012] Note that the threshold voltage Vth fluctuation in the characteristic curve shown in Figure 17 is an estimated value obtained from the temperature-accelerated test, as described above. Furthermore, for example, Patent Document 2 discloses that the amount of fluctuation in the threshold voltage Vth due to the influence of NBTI increases with increasing temperature, thereby accelerating device degradation. Furthermore, it is known that the longer the stress application time, the greater the fluctuation in the threshold voltage Vth. Therefore, by accelerating the differential amplifier circuit under high-temperature environmental conditions, it is possible to estimate the fluctuation in the threshold voltage Vth when used continuously for 10 years. [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] Japanese Patent Publication No. 2020-120320 [Patent Document 2] Patent No. 4989261 [Overview of the project] [Problems that the invention aims to solve]

[0014] However, in the case of the differential amplifier circuit disclosed in Patent Document 1, as explained in Figure 16 above, although it is certainly possible to suppress changes in the input offset voltage, a new problem arises: the addition of the current source I2 leads to an increase in current consumption.

[0015] This invention has been made in view of the above circumstances, and provides a highly reliable and stable differential amplifier circuit that suppresses and reduces fluctuations in input offset voltage by suppressing threshold voltage fluctuations in a differential pair using MOS transistors caused by NBTI and PBTI without increasing current consumption. [Means for solving the problem]

[0016] To achieve the above-mentioned objectives of the present invention, the differential amplifier circuit according to the present invention is: A differential amplifier circuit comprising a first input differential pair configured to be differentially amplified using a P-channel MOSFET, and an active load circuit that serves as a load for the first input differential pair, The drain voltage of the P-channel MOSFET constituting the first input differential pair is limited to a predetermined voltage range. Second A voltage limiting circuit is provided. The aforementioned Second The voltage limiting circuit sets the upper limit of the predetermined voltage range to a voltage value corresponding to the voltage difference between the drain potential and gate potential of the P-channel MOSFET, which is necessary to set the amount of input offset voltage fluctuation due to fluctuations in the threshold voltage of the P-channel MOSFET caused by negative bias temperature instability to a desired magnitude. In an equilibrium state where the gate voltages of the P-channel MOSFETs constituting the first input differential pair are at the same potential, from the first input differential pair to the Second The voltage value corresponding to the drain voltage of the P-channel MOSFET constituting the first input differential pair when the current flowing into the voltage limiting circuit becomes zero is configured to be the lower limit value of the predetermined voltage range the law of nature, The first input differential pair has first and second transistors for the first differential pair, each using a P-channel MOSFET. An inverting input signal can be applied to the gate of the first transistor for the first differential pair, and a non-inverting input signal can be applied to the gate of the second transistor for the first differential pair. The sources of the first and second transistors of the first differential pair are interconnected and a positive power supply voltage can be applied via a constant current source, while the drains of the first and second transistors of the first differential pair are connected to the active load circuit. The second voltage limiting circuit comprises first to third limiting transistors using N-channel MOSFETs, the first to third limiting transistors each being in a diode connection state with their gates and drains interconnected, the drain of the first limiting transistor connected to the drain of the first differential pair first transistor, the drain of the second limiting transistor connected to the drain of the first differential pair second transistor, the sources of the first and second limiting transistors interconnected and connected to the drain of the third limiting transistor, and a negative power supply voltage can be applied to the source of the third limiting transistor. It is configured as such.

Effect of the Invention

[0017] According to the present invention, the voltage at the connection point between the active load circuit and the transistor, which is a factor causing variations in the threshold voltage of the MOS transistors constituting the differential pair that causes variations in the input offset voltage, is restricted by the voltage limiting circuit to a predetermined voltage range where variations in the threshold voltage can be suppressed. This enables suppression of variations in the threshold voltage in a differential pair using MOS transistors caused by NBTI or PBTI without causing an increase in the consumption current. As a result, variations in the input offset voltage can be suppressed and reduced, and an effect is achieved in that a differential amplifier circuit with high reliability and stability can be provided.

Brief Description of the Drawings

[0018] [Figure 1] It is a circuit diagram showing a first basic circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 2] It is a circuit diagram showing a first specific circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 3] It is a circuit diagram showing the potentials at the main nodes in the case of an equilibrium state in the first specific circuit configuration example shown in FIG. 2. [Figure 4] It is a circuit diagram showing a second specific circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 5]This is a circuit diagram showing a third specific circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 6] This is a circuit diagram showing a second basic circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 7] This is a circuit diagram showing a fourth specific circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 8] This is a circuit diagram showing a third basic circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 9] This is a circuit diagram showing a fifth specific circuit configuration example of a differential amplifier circuit in an embodiment of the present invention. [Figure 10] This is a circuit diagram showing an example of a conventional differential amplifier circuit configuration used to explain PBTI. [Figure 11] This is a characteristic curve showing the change in the amount of threshold voltage fluctuation with respect to the difference between the drain potential and gate potential of a MOS transistor constituting a differential amplifier circuit in an embodiment of the present invention. [Figure 12] This is a characteristic curve showing the change in the amount of fluctuation of the input offset voltage of the PMOS differential pair before and after the bias state of the differential amplifier circuit in an embodiment of the present invention. [Figure 13] This is a characteristic curve showing the change in the amount of fluctuation of the input offset voltage of an NMOS differential pair before and after the bias state of a differential amplifier circuit in an embodiment of the present invention. [Figure 14] This is a circuit diagram showing an example of a conventional differential amplifier circuit configuration. [Figure 15] This circuit diagram shows an example of bias conditions under which NBTI (Non-Blocked Transistor Influence) occurs. [Figure 16] This circuit diagram shows an example of a conventional differential amplifier circuit configuration that incorporates measures to address the aging-related changes in input offset voltage. [Figure 17] This characteristic curve shows the characteristic change in the threshold voltage variation with respect to the difference between the drain potential and the gate potential in a conventional differential amplifier circuit. [Modes for carrying out the invention]

[0019] Hereinafter, embodiments of the present invention will be described with reference to Figures 1 to 13. The components, arrangements, etc., described below are not intended to limit the present invention and can be modified in various ways within the scope of the spirit of the present invention. First, a first basic circuit configuration example of a differential amplifier circuit in an embodiment of the present invention will be described with reference to Figure 1. The operational amplifier in the embodiment of the present invention is broadly composed of an input differential pair 101, an active load circuit (indicated as "AC-L" in Figure 1) 201, and a voltage limiting circuit (indicated as "V-LIM" in Figure 1) 301.

[0020] The input differential pair 101 is mainly composed of first and second differential pair transistors 1 and 2 (labeled "M1" and "M2" respectively in Figure 1), which are PMOS transistors. The first and second differential transistors 1 and 2 have their sources connected to each other, and a constant current source 41 is connected between the connection point and the positive power supply terminal 53. The positive power supply terminal 53 is supplied with an external power supply voltage VDD.

[0021] Furthermore, the gate of the first differential transistor 1 is connected to the inverting input terminal (indicated as "INM" in Figure 1) 51 to which an inverting input signal is applied, and the gate of the second differential transistor 2 is connected to the non-inverting input terminal (indicated as "INP" in Figure 1) 52 to which a non-inverting input signal is applied. The drain of the first differential transistor 1 is connected to the active load circuit 201 via the first load input terminal A1, and also to the voltage limiting circuit 301 via the first limiting input terminal C1.

[0022] Similarly, the drain of the second differential transistor 2 is connected to the active load circuit 201 via the first load second input terminal A2, and to the voltage limiting circuit 301 via the second limiting input terminal C2, and is also connected to the output terminal (labeled "OUT" in Figure 1) 55. Furthermore, the negative power supply voltage line of the active load circuit 201 is connected to the negative power supply terminal (indicated as "VSS" in Figure 1) 54 via the first load reference terminal A3, and the negative power supply voltage line of the voltage limiting circuit 301 is connected to the negative power supply terminal (indicated as "VSS" in Figure 1) via the limiting reference terminal C3.

[0023] The active load circuit 201 is a circuit that functions as a load for the input differential pair 101, and is made up of so-called active elements, and basically has the same configuration as conventional circuits. The voltage limiting circuit 301 is configured to suppress fluctuations in the threshold voltage by limiting the voltage at the connection point with the active load circuit 201, which is a factor in fluctuations in the threshold voltage of the MOS transistors constituting the input differential pair 101, to a predetermined voltage range, thereby suppressing and reducing fluctuations in the input offset voltage (details will be described later). The circuit operation of the differential amplifier circuit in this first basic circuit configuration example in such a configuration will be replaced by the explanation of the circuit operation in the first specific circuit configuration example described below.

[0024] Figure 2 shows a specific circuit example of the first basic circuit configuration example shown in Figure 1. The first specific circuit configuration example will be explained below with reference to Figure 2. Note that components identical to those shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. Furthermore, in Figure 2, the notations for terminals A1-A3 and C1-C3 shown in Figure 1 will be omitted. First, the active load circuit 201 is configured with first and second load transistors 3 and 4 (labeled "M3" and "M4" respectively in Figure 2) that use NMOS transistors.

[0025] The first and second load transistors 3 and 4 constitute a current mirror as described below. In other words, the first and second load transistors 3 and 4 have their gates interconnected and are connected to the drain of the first load transistor 3. Furthermore, the sources of the first and second load transistors 3 and 4 are both connected to the negative power supply terminal 54. The drain of the first load transistor 3 is connected to the drain of the first differential pair transistor 1. The drain of the second load transistor 4 is connected to the drain of the second differential pair transistor 2, and is also connected to the output terminal 55.

[0026] On the other hand, the voltage limiting circuit 301 is composed of first to fourth limiting transistors 11 to 14 using NMOS (denoted as "M11", "M12", "M13", and "M14" respectively in Figure 2). The first to fourth limiting transistors 11 to 14 all have their gates and drains connected, creating a so-called diode connection. Furthermore, first and third limiting transistors 11 and 13 are connected in series between the drain of the first differential pair transistor 1 and the negative power supply terminal 54, while second and fourth limiting transistors 12 and 14 are connected in series between the drain of the second differential pair transistor 2 and the negative power supply terminal 54.

[0027] Specifically, the source of the first limiting transistor 11 and the drain of the third limiting transistor 13 are connected, while the drain of the first limiting transistor 11 is connected to the drain of the first differential pair transistor 1, and the source of the third limiting transistor 13 is connected to the negative power supply terminal 54. Furthermore, the source of the second limiting transistor 12 and the drain of the fourth limiting transistor 14 are connected, while the drain of the second limiting transistor 12 is connected to the drain of the second differential pair transistor 2, and the source of the fourth limiting transistor 14 is connected to the negative power supply terminal 54.

[0028] Next, the circuit operation in this configuration will be described. In the differential amplifier circuit according to the embodiment of the present invention, an important feature is that the drain potential of the second differential transistor 2 is limited to a predetermined voltage range by the voltage limiting circuit 301. That is, the drain potential of the second differential transistor 2 is limited to a voltage approximately 1 Vgs higher than the operating voltage of the first and second load transistors 3 and 4, and not exceeding a voltage that reduces or suppresses the effects of NBTI. Here, approximately 1 Vgs is specifically about the potential difference between the gate and source of a CMOS transistor.

[0029] The following explains this point in detail. First, as a premise, the bias conditions are the same as those in conventional circuits, and specifically, they are in accordance with the bias conditions shown in Figure 15, which was previously described in the explanation of the prior art. In Figure 2, the voltages indicated at the main nodes are those under the bias conditions described above. The drain potential Vd of the second transistor 2 for the differential pair is suppressed to Vd = 1.7V, as shown in Figure 2. This Vd = 1.7V is the value obtained by adding 1Vgs to the operating voltage of the first and second load transistors 3 and 4.

[0030] Thus, the drain potential Vd of the second differential transistor 2 was set to a value obtained by adding 1Vgs to the operating voltage of the first and second load transistors 3 and 4 in order to prevent current from flowing from the first limiting transistor 11 to the negative power supply terminal 54, and from the second limiting transistor 12 to the negative power supply terminal 54, in the balanced state. Here, "equilibrium state" refers to the state in which the gate potentials of the first and second differential pair transistors 1 and 2 are the same. Figure 3 shows the voltages of the main nodes when the differential amplifier circuit shown in Figure 2 is in the equilibrium state. Such a state of equilibrium occurs in operational amplifiers when feedback is applied, and in comparators when the output switches from a logic high to a logic low.

[0031] In this equilibrium state, as described above, if current flows from the first limiting transistor 11 to the negative power supply terminal 54, and from the second limiting transistor 12 to the negative power supply terminal 54, a problem arises in which the voltage gain of the differential amplifier circuit decreases. This decrease in voltage gain occurs because, as described above, current flows through the first to fourth limiting transistors 11 to 14, resulting in a state equivalent to a decrease in the output impedance of the active load.

[0032] Furthermore, in this equilibrium state, if a difference in current flows between the first limiting transistor 11 and the second limiting transistor 12 due to manufacturing element mismatches or the like, a problem arises in which an input offset voltage is generated. To avoid these problems, the differential amplifier circuit in the embodiment of the present invention adopts a configuration in which the transistors of the voltage limiting circuit 301 are stacked in two stages so that, in the equilibrium state, no current flows from the first limiting transistor 11 to the negative power supply terminal 54, nor from the second limiting transistor 12 to the negative power supply terminal 54, as described above. In other words, the first and third limiting transistors 11 and 13 are connected in series and stacked in two stages, and similarly, the second and fourth limiting transistors 12 and 14 are connected in series and stacked in two stages.

[0033] As a result, under the bias conditions described above (see Figure 15), the drain potential of the second differential pair transistor 2 is limited to a voltage approximately 1 Vgs higher than the operating voltage of the first and second load transistors 3 and 4, Vd = 1.7 V. On the other hand, if the focus is solely on preventing the current described above from flowing through the first to fourth limiting transistors 11 to 14 in the equilibrium state, then the transistors in the voltage limiting circuit 301 could be stacked in three stages instead of two. However, if three stages are used, the NBTI countermeasure effect will decrease, and the original purpose of the present invention will be undermined.

[0034] Here, we will explain the effect of the number of transistor stages on the variation in the transistor threshold voltage, referring to Figure 11. Figure 11 is a characteristic curve showing an example of how the threshold voltage Vth changes in response to a change in the difference between the drain potential and gate potential of a MOS transistor. On the characteristic curve in the figure, black dots are indicated at points corresponding to the variation in the threshold voltage Vth with respect to the difference between the drain potential and the gate potential for each of the single-stage, double-stage, and triple-stage transistor configurations. Furthermore, on the same characteristic curve, black dots are indicated at points corresponding to the variation in the threshold voltage Vth with respect to the difference between the drain potential and gate potential in a conventional differential amplifier circuit (see Figure 14).

[0035] As shown in Figure 11, it can be confirmed that as the number of transistor stages increases, the potential difference (Vd-Vg) between the drain and gate of the second differential transistor 2 increases, and the threshold voltage Vth fluctuation becomes larger. In the case of a three-stage stack, the threshold voltage Vth fluctuation is several millivolts. Considering that the input offset voltage specifications of op-amps and comparators are usually several millivolts or less, a threshold voltage Vth fluctuation of several millivolts in a three-stage stack is practically problematic.

[0036] Therefore, in the differential amplifier circuit according to the embodiment of the present invention, it is important to know in advance the fluctuation characteristics of the threshold voltage Vth due to NBTI when setting the circuit constants. Then, by knowing these characteristics, the target value of the potential difference (Vd-Vg) between the drain and gate of the second transistor 2 for the differential pair is determined. In the embodiment of the present invention, the target value of the potential difference (Vd-Vg) when the fluctuation of the threshold voltage Vth becomes almost zero is set to (Vd-Vg) = 2.2V or less (see Figure 11). In the differential amplifier circuit according to the embodiment of the present invention, as mentioned above, the voltage limiting circuit 301 employs a two-stage transistor configuration, resulting in (Vd-Vg) = 1.7V, which satisfies the aforementioned target value.

[0037] Thus, what is important in the differential amplifier circuit according to the embodiment of the present invention is that the voltage limiting circuit 301 limits the drain potential of the second transistor 2 for the differential pair to a voltage that does not reduce the output impedance of the active load circuit 201 (a voltage approximately 1 Vgs higher than the operating voltage of the first and second load transistors 3 and 4 in the embodiment of the present invention), and that reduces and suppresses the effects of NBTI. In other words, the drain potential of the second transistor 2 for the differential pair is limited by the voltage limiting circuit 301 to a predetermined voltage range defined by a lower limit and an upper limit. Here, the lower limit of the predetermined voltage range of the voltage limiting circuit 301 is the drain voltage of the second transistor 2 for the differential pair when the current inflow from the input differential pair 101 to the voltage limiting circuit 301 is zero in the equilibrium state. The upper limit of the predetermined voltage range of the voltage limiting circuit 301 is the voltage value corresponding to the potential difference (Vd-Vg) between the drain and gate of the second transistor 2 for the differential pair when the fluctuation of the threshold voltage Vth is approximately zero, as described above. Specifically, the circuit constants are determined so that the potential difference (Vd-Vg) between the drain and gate of the second differential transistor 2 falls within the range of 1.7V to 2.2V (the range indicated by the horizontal arrow in Figure 11). However, the lower limit is not limited to 1.7V; it only needs to be set to a voltage value such that the current flowing through the first and second differential transistors 1 and 2 in the balanced state does not flow through the voltage limiting circuit 301.

[0038] In the differential amplifier circuit according to the embodiment of the present invention, under the bias conditions described above, the drain potential Vd of the second transistor 2 for differential pair is suppressed to Vd = 1.7V, so there is almost no fluctuation in the threshold voltage Vth due to NBTI (see Figure 11). Therefore, in the differential amplifier circuit according to the embodiment of the present invention, there is almost no change in the input offset voltage over time due to NBTI, and moreover, unlike conventional circuits such as those in Patent Document 1, it does not lead to an increase in current consumption due to the circuit configuration for NBTI countermeasures.

[0039] Next, we will explain a second specific circuit configuration example with reference to Figure 4. Note that components identical to those shown in the example configuration in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This second specific circuit configuration example differs from the first specific circuit configuration example in that it includes a second voltage limiting circuit 301A, which is configured using three transistors, instead of the voltage limiting circuit 301 configured using four transistors as shown in the first specific circuit configuration example. The remaining circuit configuration is the same as the specific circuit configuration example shown in Figure 2.

[0040] The second voltage limiting circuit 301A is constructed using first to third limiting transistors 11 to 13, which are NMOS transistors. The second voltage limiting circuit 301A has a configuration similar to the previous voltage limiting circuit 301, with two transistors stacked between the drain of the first differential pair transistor 1 and the negative power supply terminal 54, and between the drain of the second differential pair transistor 2 and the negative power supply terminal 54. However, as will be described in detail below, it differs from the configuration of the voltage limiting circuit 301 in that there is only one second-stage transistor located on the negative power supply voltage VSS side.

[0041] To explain the specific circuit configuration below, firstly, the first to third limiting transistors 11 to 13 are all connected in a so-called diode configuration, similar to the voltage limiting circuit 301. Furthermore, similar to the voltage limiting circuit 301, the drain of the first limiting transistor 11 is connected to the drain of the first differential pair transistor 1, and the drain of the second limiting transistor 12 is connected to the drain of the second differential pair transistor 1.

[0042] The sources of the first limiting transistor 11 and the second limiting transistor 12 are interconnected and connected to the drain of the third limiting transistor 13, while the source of the third limiting transistor 13 is connected to the negative power supply terminal 54. In this second specific circuit configuration example, as in the first specific circuit configuration example, the voltage limiting circuit 301A limits the drain potential of the second differential pair transistor 2 to a voltage approximately 1 Vgs higher than the operating voltages of the first and second load transistors, and within a range that does not exceed a voltage that reduces and suppresses the effects of NBTI.

[0043] Therefore, in this second specific circuit configuration example as well, when setting the circuit constants, the fluctuation characteristics of the threshold voltage Vth due to NBTI, as shown in Figure 11, should be understood in advance, and a target value for the potential difference (Vd-Vg) between the drain and gate of the second differential transistor 2 should be determined. This target value is preferably (Vd-Vg) = 2.2V or less, as in the first specific circuit configuration example. On the other hand, in the second voltage limiting circuit 301A, as mentioned earlier, the transistors are stacked in two stages so that no current flows through the first and second limiting transistors 11 and 12 in the balanced state.

[0044] Furthermore, for operational amplifiers with extremely small input offset voltages, often referred to as high-precision operational amplifiers, it is effective to use a differential amplifier circuit to which this second specific circuit configuration example is applied. Furthermore, although it was explained that no current flows through the first and second limiting transistors 11 and 12 when the differential amplifier circuit in the embodiment of the present invention is in a balanced state, an extremely small leakage current of about nanoamperes is generated at high temperatures.

[0045] If the magnitude of this leakage current is exactly the same for both the first limiting transistor 11 and the second limiting transistor 12, then there is no problem. However, in reality, a small difference occurs between the leakage current of the first limiting transistor 11 and the leakage current of the second limiting transistor 12, and this difference in leakage current appears as an input offset voltage. Therefore, in order to reduce the input offset voltage, that is, to reduce the difference in leakage current between the first and second limiting transistors 11 and 12, it is necessary to make the node potentials of the first and second limiting transistors 11 and 12 as similar as possible.

[0046] Therefore, in the differential amplifier circuit of this second specific circuit configuration example, the source potentials of the first and second limiting transistors 11 and 12 are set to a common potential, and a third limiting transistor 13 is provided to create a two-stage stacked configuration. In Figure 4, the voltage values ​​indicated on the main nodes are those under the bias conditions described earlier (see Figure 15). In this case, the drain voltage Vd of the second differential pair transistor 2 is suppressed to Vd = 1.7V, and as in the first specific circuit configuration example above, the fluctuation of the threshold voltage Vth due to NBTI is suppressed (see Figure 11).

[0047] Thus, the differential amplifier circuit in this second specific circuit configuration example has one fewer element than the first specific circuit configuration example, resulting in a smaller circuit size. Furthermore, by making the source potentials of the first and second limiting transistors 11 and 12 common, the leakage current difference between the first and second limiting transistors 11 and 12 at high temperatures is suppressed. Therefore, this second specific circuit configuration example suppresses the deterioration of the input offset voltage at high temperatures more effectively than the first specific circuit configuration example. For this reason, this second specific circuit configuration example is suitable for high-precision operational amplifiers.

[0048] Next, we will explain a third specific circuit configuration example with reference to Figure 5. Note that components identical to those shown in the example configuration in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This third specific circuit configuration example differs from the first specific circuit configuration example in that it includes a third voltage limiting circuit 301B, which is configured using two transistors, instead of the voltage limiting circuit 301 configured using four transistors as shown in the first specific circuit configuration example. The remaining circuit configuration is the same as the specific circuit configuration example shown in Figure 2.

[0049] The third voltage limiting circuit 301B is constructed using second and fourth limiting transistors 12 and 14, which are NMOS transistors. Specifically, the second to fourth limiting transistors 12 and 14 are each in a diode connection state, with the source of the second limiting transistor 12 and the drain of the fourth limiting transistor 14 being interconnected. The drain of the second limiting transistor 12 is connected to the drain of the second differential pair transistor 2, while the source of the fourth limiting transistor 14 is connected to the negative power supply terminal 54.

[0050] In this third specific circuit configuration example, as in the first specific circuit configuration example, the voltage limiting circuit 301B limits the drain potential of the second differential pair transistor 2 to a voltage approximately 1 Vgs higher than the operating voltage of the first and second load transistors 3 and 4, and within a range that does not exceed a voltage that reduces and suppresses the effects of NBTI. Therefore, in this third specific circuit configuration example as well, when setting the circuit constants, the fluctuation characteristics of the threshold voltage Vth due to NBTI, as shown in Figure 11, should be understood in advance, and a target value for the potential difference (Vd-Vg) between the drain and gate of the second differential transistor 2 should be determined. This target value is preferably (Vd-Vg) = 2.2V or less, as in the first specific circuit configuration example mentioned earlier.

[0051] Furthermore, in the third voltage limiting circuit 301B, as mentioned earlier, two transistors are stacked to prevent current from flowing to the second limiting transistor 12 in the equilibrium state. Furthermore, for devices capable of responding in relatively short time intervals, such as high-speed operational amplifiers and high-speed comparators, it is preferable to use a differential amplifier circuit to which this third specific circuit configuration example is applied.

[0052] Furthermore, the voltage control circuit 301B in this third specific circuit configuration example has a configuration in which the first limiting transistor 11 used in the first and second specific circuit configuration examples (see Figures 2 and 4) has been removed. The first limiting transistor 11 has a gate capacitance, which leads to the disadvantage of a longer response time while this gate capacitance is being charged and discharged. However, in this third specific circuit configuration example, as described above, the configuration is adopted in which the first limiting transistor 11 is removed, thus achieving a shorter response time compared to the first and second specific circuit configuration examples.

[0053] In Figure 5, the voltage values ​​indicated on the main nodes are those under the bias conditions described earlier (see Figure 15). In this case, the drain voltage Vd of the second differential pair transistor 2 is suppressed to Vd = 1.7V, and as in the first specific circuit configuration example above, the fluctuation of the threshold voltage Vth due to NBTI is suppressed (see Figure 11).

[0054] Thus, the differential amplifier circuit in this third specific circuit configuration example can suppress fluctuations in the threshold voltage Vth due to NBTI without increasing power consumption. Furthermore, the differential amplifier circuit in this third specific circuit configuration example has two fewer elements than the first specific circuit configuration example, resulting in a smaller circuit size. In addition, by eliminating the limiting first transistor 11, the differential amplifier circuit in this third specific circuit configuration example reduces parasitic capacitance within the circuit, enabling a shorter circuit response time compared to the first and second specific circuit configuration examples. For this reason, the differential amplifier circuit in this third specific circuit configuration example is particularly suitable for high-speed operational amplifiers and high-speed comparators.

[0055] Next, we will explain the second basic circuit configuration example with reference to Figure 6. Note that components identical to those shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This second basic circuit configuration example has a configuration in which a folded cascode circuit (indicated as "F-CA" in Figure 6) 401 is added to the first basic circuit configuration example shown in Figure 1. The folded cascode circuit 401 has the same circuit configuration as conventional circuits and is provided to amplify and output the output signal of the input differential pair 101.

[0056] A positive power supply line (not shown) of the folded cascode circuit 401 is connected to the positive power supply terminal 53 via the cascode reference terminal F1. Furthermore, one input stage of the folded cascode circuit 401 is connected to the drain of the first differential transistor 1 via the first cascode input terminal F2, and the other input stage of the folded cascode circuit 401 is connected to the drain of the second differential transistor 2 via the second cascode input terminal F3. The output stage of the folded cascode circuit 401 is connected to output terminal 55. The circuit operation of the differential amplifier circuit in this second basic circuit configuration example in such a configuration will be replaced by the explanation of the circuit operation in the fourth specific circuit configuration example described below.

[0057] Figure 7 shows a fourth specific circuit configuration example, which is a concrete example of the second basic circuit configuration example described above. The fourth specific circuit configuration example will be explained below with reference to this figure. Note that components identical to those shown in the configuration examples in Figures 4 and 6 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. Furthermore, in Figure 7, the notations for terminals A1-A3, C1-C3, and F1-F3 shown in Figure 6 will be omitted.

[0058] The folded cascode circuit 401 in this fourth specific circuit configuration example is mainly composed of first and second cascode transistors 5 and 6 using PMOS (labeled "M5" and "M6" respectively in Figure 7), and third and fourth cascode transistors 7 and 8 using NMOS (labeled "M7" and "M8" respectively in Figure 7). In other words, the sources of the first and second cascode transistors 5 and 6 are both connected to the positive power supply terminal 53, while their gates are interconnected. A first constant voltage source 45 is connected between the gate and the positive power supply terminal 53, such that the positive side faces the positive power supply terminal 53.

[0059] Furthermore, the drain of the first cascode transistor 5 is connected to the drain of the third cascode transistor 7, and also to the gates of the first and second load transistors 3 and 4. Furthermore, the drain of the second cascode transistor 6 is connected to the drain and output terminal 55 of the fourth cascode transistor 8. On the other hand, the gates of the third and fourth transistors 7 and 8 for the cascode are interconnected, and a second constant voltage source 46 is connected between the gate and the negative power supply terminal 54 such that the positive side is the gate side.

[0060] Furthermore, the source of the third cascode transistor 7 is connected to the drain of the first load transistor 3, and the source of the fourth cascode transistor 8 is connected to the drain of the second load transistor 4. In this fourth specific circuit configuration example, as in the first specific circuit configuration example, the voltage limiting circuit 301A limits the drain potential of the second differential pair transistor 2 to a voltage approximately 1 Vgs higher than the operating voltage of the first and second load transistors 3 and 4, and within a range that does not exceed a voltage that reduces and suppresses the effects of NBTI.

[0061] Therefore, in this fourth specific circuit configuration example as well, when setting the circuit constants, the fluctuation characteristics of the threshold voltage Vth due to NBTI, as shown in Figure 11, should be understood in advance, and a target value for the potential difference (Vd-Vg) between the drain and gate of the second differential transistor 2 should be determined. This target value is preferably (Vd-Vg) = 2.2V or less, as in the first specific circuit configuration example mentioned earlier. On the other hand, in the second voltage limiting circuit 301A, as mentioned earlier, the transistors are stacked in two stages so that no current flows through the first and second limiting transistors 11 and 12 in the balanced state.

[0062] Furthermore, in Figure 7, the voltage values ​​indicated for the main nodes are those under the bias conditions described earlier (see Figure 15). In this case, the drain voltage Vd of the second differential pair transistor 2 is suppressed to Vd = 1.7V, and, as in the first specific circuit configuration example above, the fluctuation of the threshold voltage Vth due to NBTI is suppressed (see Figure 11). Thus, the differential amplifier circuit in this fourth specific circuit configuration example is capable of suppressing fluctuations in the threshold voltage Vth due to NBTI without increasing current consumption.

[0063] Furthermore, because the differential amplifier circuit in this fourth specific circuit configuration example is equipped with a folded cascode circuit 401, it is possible to obtain an output signal with a larger amplitude at the output terminal 55 compared to the previous specific circuit configuration examples. In this fourth specific circuit configuration example, the second voltage limiting circuit 301A may be replaced with the voltage limiting circuit 301 shown in Figure 2, or similarly, with the third voltage limiting circuit 301B shown in Figure 5.

[0064] Next, we will explain the third basic circuit configuration example with reference to Figure 8. Note that components identical to those shown in Figure 1 or Figure 6 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This third basic circuit configuration example is equipped with first and second input differential pairs 101 and 102 to accommodate a full-swing input configuration, and accordingly, first and second active load circuits 201 and 202 are provided, along with a switching circuit 501, a second voltage limiting circuit 301A, and a folded cascode circuit 401. In this third basic circuit configuration example, the input differential pair 101 shown in Figure 2 will be referred to as the "first input differential pair 101" for the sake of explanation, but the two circuits themselves are identical and not different.

[0065] First, the second input differential pair 102 is composed of first and second transistors 21 and 22 for the second differential pair, which use NMOS transistors (denoted as "M21" and "M22" respectively in Figure 8). The gate of the first transistor 21 for the second differential pair is connected to the gate of the first transistor 1 for the first differential pair, and the gate of the second transistor 22 for the second differential pair is connected to the gate of the second transistor 2 for the first differential pair.

[0066] Furthermore, the first and second differential pair transistors 21 and 22 have their sources interconnected and are connected to the drains of a third switching transistor 33, which uses an NMOS transistor and constitutes a switching circuit 501 described later. Meanwhile, the drain of the first transistor 21 for the second differential pair is connected to the second active load circuit 202 via the first input terminal B1 of the second load, and the drain of the second transistor 22 for the second differential pair is connected to the second active load circuit 202 via the second input terminal B2 of the second load. The second active load circuit 202 is connected to the positive power supply terminal 53 via the second load reference terminal B3, and the positive power supply voltage VDD is supplied to it.

[0067] Furthermore, the drain of the first transistor 21 for the second differential pair is connected to the folded cascode circuit 401 via the third cascode input terminal F4, and the drain of the second transistor 22 for the second differential pair is connected via the fourth cascode input terminal F5. Note that the circuit connections at the first and second cascode input terminals F2 and F3 are the same as those described in Figure 6, so a further detailed explanation is omitted here.

[0068] The switching circuit 501 switches the operation of the first input differential pair 101 and the second input differential pair 102 according to the level of the input signal, and is composed of a first switching transistor 31 using PMOS (labeled "M31" in Figure 8), second and third switching transistors 32 and 33 using NMOS (labeled "M32" and "M33" respectively in Figure 8), and a switching constant voltage power supply 47.

[0069] The specific circuit configuration of the switching circuit 501 will be described below. First, the switching constant voltage power supply 47 has its positive terminal connected to the positive power supply terminal 53, while its negative terminal is connected to the gate of the first switching transistor 31. The first switching transistor 31 has its source connected to the connection point between the sources of the first and second differential pair transistors 1 and 2 and the constant current source 41, while its drain is connected to the drain of the second switching transistor 32.

[0070] The second switching transistor 32 is provided in a so-called diode connection state. That is, the gate and drain of the second switching transistor 32 are interconnected, and it is also connected to the gate of the third switching transistor 33. The sources of the second and third switching transistors 32 and 33 are both connected to the negative power supply terminal 54. The circuit operation of the differential amplifier circuit in this third basic circuit configuration example in such a configuration will be replaced by the explanation of the circuit operation in the fifth specific circuit configuration example described below.

[0071] Figure 9 shows a fifth specific circuit configuration example, which is a concrete example of the third basic circuit configuration example described above. This specific circuit configuration example will be explained below with reference to this figure. Components identical to those shown in the configuration examples in Figures 7 and 8 are given the same reference numerals, and their detailed explanations will be omitted. The explanation below will focus on the differences. Furthermore, in Figure 9, the notations for terminals A1-A3, B1-B3, C1-C3, and F2-F5 shown in Figure 8 will be omitted.

[0072] In this fifth specific circuit configuration example, the first input differential pair 101 and the voltage limiting circuit 301A are identical to those shown in Figure 7, so a further detailed explanation will be omitted here. The second active load circuit 202 is configured with first and second transistors for the second load (labeled "M23" and "M24" respectively in Figure 9) 23 and 24, which use PMOS technology, and a constant voltage source 48 for the second load.

[0073] The first and second transistors 23 and 24 for the second load have their sources both connected to the positive power supply terminal 53, while their gates are connected to each other. A constant voltage source 48 for the second load is connected between the gate and the positive power supply terminal 53, with the positive side facing the positive power supply terminal 53. On the other hand, the drain of the first transistor 23 for the second load is connected to the drain of the first transistor 21 for the second differential pair, and the drain of the second transistor 24 for the second load is connected to the drain of the second transistor 22 for the second differential pair.

[0074] The folded cascode circuit 401 is the same as the one described earlier in Figure 7, in that it is mainly composed of first and second cascode transistors 5 and 6 using PMOS and third and fourth cascode transistors 7 and 8 using NMOS. However, as described below, the source connections of the first and second cascode transistors 5 and 6 differ from the circuit connections shown in Figure 7. In other words, the source of the first cascode transistor 5 is connected to the drain of the first second load transistor 23, and the source of the second cascode transistor 6 is connected to the drain of the second second load transistor 24.

[0075] In this fifth specific circuit configuration example, as in the first specific circuit configuration example, the voltage limiting circuit 301A limits the drain potential of the second differential pair transistor 2 to a voltage approximately 1 Vgs higher than the operating voltage of the first and second load transistors 3 and 4, and within a range that does not exceed a voltage that reduces and suppresses the effects of NBTI. Therefore, in this fifth specific circuit configuration example as well, when setting the circuit constants, the fluctuation characteristics of the threshold voltage Vth due to NBTI, as shown in Figure 11, should be understood in advance, and a target value for the potential difference (Vd-Vg) between the drain and gate of the second transistor 2 for the first differential pair should be determined. This target value is preferably (Vd-Vg) = 2.2V or less, as in the first specific circuit configuration example mentioned earlier.

[0076] On the other hand, in the second voltage limiting circuit 301A, as mentioned earlier, two transistors are stacked in a row to prevent current from flowing to the second limiting transistor 12 in the balanced state. In Figure 9, the voltage values ​​indicated on the main nodes are those under the bias conditions described earlier (see Figure 15). In this case, the drain voltage Vd of the second transistor 2 for the first differential pair is suppressed to Vd = 1.7V, and as in the first specific circuit configuration example above, the fluctuation of the threshold voltage Vth due to NBTI is suppressed (see Figure 11).

[0077] Furthermore, in this fifth specific circuit configuration example, it is also possible to suppress fluctuations in the threshold voltage Vth by the PBTI of the first transistor 21 for the second differential pair. In other words, under the bias conditions described above, the first transistor 21 for the second differential pair has a gate potential Vinm of Vinm = 5.5V, a drain potential Vd2 of Vd2 = 5.3V, and a source potential Vs2 of Vs2 = 5.3V, resulting in small potential differences at each node (see Figure 9).

[0078] Now, let me explain PBTI. PBTI (Potential-Based Transistor Tension) is a degradation phenomenon in NMOS transistors where the threshold voltage Vth changes when the gate potential is high and the drain and source potentials are low. Figure 10 shows the resulting potential state, which is the circuit with the second voltage limiting circuit 301A removed from the fifth specific circuit configuration example shown in Figure 9. The voltage values ​​at the main nodes are under the bias conditions described earlier (see Figure 15).

[0079] In Figure 10, it can be seen that the drain potential and source potential of the first transistor 21 for the second differential pair, which is an NMOS transistor, are both low at 0.9V, compared to the gate potential Vinm = 5.5V. Furthermore, in Figure 10, the destination of the tail current I1 supplied by the constant current source 41 is important. In Figure 10, first, with a positive power supply voltage VDD = 5.5V, the gate potential Vinm of the first differential pair transistor 1 is Vinm = 5.5V, so no current flows through the first differential pair transistor 1.

[0080] Furthermore, the second transistor 2 for the first differential pair has a source potential Vs of Vs=5.3V and a gate potential Vg of Vg=0V, and although there is a sufficient potential difference between the gate and source, almost no current flows through the second transistor 2 for the first differential pair because the drain potential Vd is high at Vd=5.3V. On the other hand, the first switching transistor 31 has a source potential Vs of Vs = 5.3V and a gate potential Vg31 of Vg31 = 4V, which is a sufficient gate-source potential difference for the transistor to operate. Furthermore, the drain potential Vs31 of the first switching transistor 31 is Vs31 = 0.9V, which is a sufficient source-drain potential difference. As a result, the tail current I1 of the first input differential pair 101, which is a PMOS differential pair, flows into the first switching transistor 31 (see the dotted arrow in Figure 10).

[0081] This tail current I1 flows only into the first transistor 21 for the second differential pair, which has a higher gate potential, in the second input differential pair 102, which is an NMOS differential pair (see the dotted arrow in Figure 10). Here, the gate potential Vinm of the first transistor 21 for the second differential pair is a very high value of Vinm = 5.5V. On the other hand, the source potential Vs2 of the first transistor 21 for the second differential pair tries to maintain the same potential Vs2 = 0.9V as the drain potential Vs31 of the second switching transistor 32, which is the mirror source of the third switching transistor 33. As a result, the gate-source potential difference of the first transistor 21 for the second differential pair becomes very large, and the first transistor 21 for the second differential pair operates in the linear region.

[0082] Due to the operation of the first transistor 21 for the second differential pair in the linear region, its drain potential and source potential become approximately the same, Vd = 0.9V. As a result, as mentioned earlier, with respect to the gate voltage Vinm = 5.5V of the first transistor 21 for the second differential pair, the source potential and drain potential are the same at 0.9V, resulting in a PBTI state.

[0083] On the other hand, in the fifth specific circuit configuration example shown in Figure 9, the PBTI described above can be avoided. The reason for this is explained below. First, in the fifth specific circuit configuration example, a voltage limiting circuit 301A consisting of limiting first to third transistors 31 to 33 is provided as a drain voltage suppression circuit for the first input differential pair 101, which is a PMOS differential pair. These limiting first to third transistors 31 to 33 limit the drain voltage Vd of the second transistor 2 for the first differential pair to Vd = 1.7V. As a result, the source voltage Vs of the second transistor 2 for the first differential pair is also limited to Vs = 1.7V.

[0084] Here, the gate voltage Vg31 of the first switching transistor 31 is Vg31 = 4V, so the potential difference between the gate and source is insufficient, and therefore the first switching transistor 31 cannot supply current. Also, the first differential pair transistor 1 has a gate potential Vinm which is the same as the positive power supply voltage, Vinm = 5.5V, so it cannot supply current either. Therefore, the tail current I1 flows through the second transistor 2 for the first differential pair, which operates in the linear region. The current flowing through this second transistor 2 for the first differential pair then flows through the second and third limiting transistors 12 and 13 (see the dashed arrows in Figure 9).

[0085] Thus, since no current flows through the first switching transistor 31, no current flows through the second and third switching transistors 32 and 33 either. As a result, no current flows through the first transistor 21 for the second differential pair. The fact that no current flows through the first transistor 21 for the second differential pair means that there is almost no potential difference between the gate and source of the first transistor 21 for the second differential pair. Therefore, the source potential Vs2 of the first transistor 21 for the second differential pair is Vs2 = 5.3V. Also, the drain potential Vd2 of the first transistor 21 for the second differential pair is Vd2 = 5.3V. As a result, as mentioned earlier, the first transistor 21 for the second differential pair has a gate potential Vinm of Vinm = 5.5V, a drain potential Vd2 of Vd2 = 5.3V, and a source potential Vs2 of Vs2 = 5.3V, resulting in a state where the potential difference between each node is small, and the threshold voltage Vth does not change due to the effect of PBTI.

[0086] Thus, this fifth specific circuit configuration example is configured to suppress not only the fluctuation of the threshold voltage Vth caused by NBTI of the second transistor 2 for the first differential pair constituting the PMOS differential pair (NBTI countermeasure), but also the fluctuation of the threshold voltage Vth caused by PBTI of the first transistor 21 for the second differential pair constituting the NMOS differential pair (PBTI countermeasure). Furthermore, in this fifth specific circuit configuration example, as a countermeasure against PBTI, it is not necessary to know in advance the variation characteristics of the threshold voltage Vth with respect to the difference between the drain potential and the gate potential (see Figure 11), as in the case of the NBTI countermeasure described earlier. This is because the PBTI countermeasure is fundamentally achieved by not operating the NMOS differential pair (the second input differential pair 102).

[0087] Here, we will explain the measurement results obtained to confirm the effectiveness of NBTI countermeasures in a high-precision amplifier using this fifth specific circuit configuration example, with reference to Figure 12. Figure 12 shows the time variation of the input offset voltage Vio of the first input differential pair 101, which is composed of the first and second transistors 1 and 2 for the first differential, before and after setting the bias conditions described earlier (see Figure 15). In the figure, the horizontal axis represents time, and the vertical axis represents the input offset voltage Vio of the first input differential pair 101, which is a PMOS differential pair. The initial input offset voltage before setting the bias conditions is Vio = 0 μV.

[0088] Figure 12 shows the results of measuring the input offset voltage again immediately after the initial input offset voltage was checked in the fifth specific circuit configuration example, under the bias conditions described above (see Figure 15), stress was applied for 30 seconds (see the thick horizontal arrow in Figure 12), and the input offset voltage was measured again immediately after the stress application ended. In the figure, the point immediately after the end of stress application is set to 0 seconds on the horizontal axis, which represents time. In Figure 12, the dotted characteristic curve represents the measurement results described above for a conventional differential amplifier circuit, and it can be seen that the input offset voltage changes immediately after the end of stress application. This change in input offset voltage is due to NBTI, and in this measurement example, a change of more than 100 μV was observed.

[0089] On the other hand, in Figure 12, the same measurement results for the fifth specific circuit configuration example are shown by the solid characteristic curve, confirming that the input offset voltage remains unchanged and the initial voltage Vio = 0 μV is maintained. In other words, the specific effectiveness of the fifth specific circuit example for NBTI can be confirmed.

[0090] Furthermore, Figure 13 shows the change characteristics of the input offset voltage of the second input differential pair 102, which is an NMOS differential pair, in the same measurement as in Figure 12 to confirm the PBTI countermeasure effect, along with the similar change characteristics of the conventional circuit. The following explanation will describe this figure. In Figure 13, the horizontal axis represents time, and the vertical axis represents the input offset voltage Vio of the second input differential pair 102, which is an NMOS differential pair. In Figure 13, the dotted characteristic curve, as in Figure 12, represents the measurement results of the conventional circuit, and it can be confirmed that the change in input offset voltage due to PBTI after the stress application is completed is 400 μV or more.

[0091] Furthermore, in Figure 13, the same measurement results for the fifth specific circuit configuration example are shown by solid characteristic curves, similar to Figure 12. It can be confirmed that, as with the first input differential pair 101 which is a PMOS differential pair, the input offset voltage remains unchanged before and after stress application, maintaining the initial voltage Vio = 0 μV. This confirms its effectiveness against PBTI. In addition, the voltage limiting circuit 301 shown in Figure 2 may be used instead of the second voltage limiting circuit 301A in this fifth specific circuit configuration example, and similarly, the configuration may also use the third voltage limiting circuit 301B shown in Figure 5.

[0092] The circuit configurations of the first and second active load circuits 201, 202, voltage limiting circuits 301, 301A, 302B, and folded cascode circuit 401 in the above-described embodiment of the present invention are merely examples and are not limited thereto, and can be modified in various ways. For example, the first active load circuit 201 may not consist solely of NMOS transistors, but may also have a circuit configuration with a resistor between the NMOS transistor and the negative power supply terminal 54. Similarly, the voltage limiting circuits 301, 301A, and 302B may not consist solely of transistors, but may also utilize diodes. Furthermore, the second active load circuit 202 may not consist solely of PMOS transistors, but may also have a circuit configuration with a resistor between the PMOS transistor and the positive power supply terminal 53. Moreover, in the folded cascode circuit 401, the first and second active load circuits 201 and 202, and the voltage limiting circuits 301, 301A, and 301B, bipolar transistors may be used instead of CMOS transistors. As described above, the differential amplifier circuit according to the present invention can be modified in various ways within the scope of the spirit of the present invention. [Industrial applicability]

[0093] This technology can be applied to differential amplifier circuits where suppression of threshold voltage fluctuations in differential pairs using MOS transistors caused by NBTI or PBTI is desired, without increasing current consumption. [Explanation of symbols]

[0094] 101...First input differential pair 102...Second input differential pair 201...First active load circuit 202...Second active load circuit 301...Voltage limiting circuit 301A...Second voltage limiting circuit 301B...Third voltage limiting circuit 401... Folded Cascode Circuit 501…Switching circuit

Claims

1. A differential amplifier circuit comprising a first input differential pair configured to be differentially amplified using P-channel MOSFETs, and an active load circuit that loads the first input differential pair, A second voltage limiting circuit is provided to limit the drain voltage of the P-channel MOSFETs constituting the first input differential pair to a predetermined voltage range. The second voltage limiting circuit sets the upper limit of the predetermined voltage range to a voltage value corresponding to the voltage difference between the drain potential and gate potential of the P-channel MOSFET, which is necessary to set the amount of fluctuation in the input offset voltage due to fluctuations in the threshold voltage of the P-channel MOSFET caused by negative bias temperature instability to a desired magnitude, In an equilibrium state where the gate voltages of the P-channel MOSFETs constituting the first input differential pair are at the same potential, the voltage value corresponding to the drain voltage of the P-channel MOSFETs constituting the first input differential pair when the current inflow from the first input differential pair to the second voltage limiting circuit becomes zero is set to the lower limit of the predetermined voltage range. The first input differential pair has first and second transistors for the first differential pair, each using a P-channel MOSFET. An inverting input signal can be applied to the gate of the first transistor for the first differential pair, and a non-inverting input signal can be applied to the gate of the second transistor for the first differential pair. The sources of the first and second transistors of the first differential pair are interconnected and a positive power supply voltage can be applied via a constant current source, while the drains of the first and second transistors of the first differential pair are connected to the active load circuit. The second voltage limiting circuit comprises first to third limiting transistors using N-channel MOSFETs, the first to third limiting transistors are each in a diode connection state with their gates and drains interconnected, the drain of the first limiting transistor is connected to the drain of the first differential pair first transistor, the drain of the second limiting transistor is connected to the drain of the first differential pair second transistor, the sources of the first and second limiting transistors are interconnected and also connected to the drain of the third limiting transistor, and a negative power supply voltage can be applied to the source of the third limiting transistor.

2. The differential amplifier circuit according to claim 1, characterized in that a second input differential pair using an N-channel MOSFET is provided so as to have a common input with the first input differential pair, a second active load circuit that loads the second input differential pair, and a folded cascode circuit that adds, amplifies, and outputs the output of the first input differential pair and the output of the second input differential pair.

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