Semiconductor equipment

Abstract

To provide a semiconductor device capable of preventing a hump phenomenon from occurring in drain current-gate voltage (Ids-Vgs) characteristics.SOLUTION: Provided is a semiconductor device 1 including: a p type source region 25p formed in an n type well of a chip; a p type drain region 26p formed in the n type well and surrounding a periphery of the p type source region 25p in planar view; a gate electrode 43 formed on the n type well between the p type source region 25p and the p type drain region 26p and surrounding the periphery of the p type source region 25p in planar view; a gate insulating film formed between the gate electrode 43 and the n type well; a gate contact portion 44 formed on a trench insulating structure 13; and a gate connection portion 45 that crosses the p type drain region 26p from a boundary 18 between the trench insulating structure 13 and a p side active region 14p and connects the gate contact portion 44 and the gate electrode 43.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] For example, Patent Document 1 discloses a method for limiting the formation of divots in a shallow groove isolation (STI) structure. The method of Patent Document 1 includes the steps of providing an oxide deposited in a trench formed in a silicon region, oxidizing the upper layer of the silicon region to form a thermal oxide layer on the upper surface of the silicon region, and selectively etching the thermal oxide with respect to the deposited oxide. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Special Publication No. 2005-510080 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment of the present disclosure provides a semiconductor device that can suppress the occurrence of a hump phenomenon in the drain current-gate voltage (Ids-Vgs) characteristics. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment of the present disclosure includes a chip having a main surface, a trench insulating structure defining an active region on the main surface, a well region of a first conductivity type formed in the active region, a first impurity region of a second conductivity type formed in the well region, a second impurity region formed in the well region and surrounding the first impurity region in a plan view, a gate electrode formed on the well region between the first impurity region and the second impurity region and surrounding the first impurity region in a plan view, a gate insulating film formed between the gate electrode and the well region, a gate contact portion formed on the trench insulating structure, and a gate connection portion that crosses the second impurity region from the boundary between the trench insulating structure and the active region and connects the gate contact portion and the gate electrode. [Effects of the Invention]

[0006] According to a semiconductor device according to one embodiment of the present disclosure, a second impurity region surrounds the first impurity region. This allows substantially or entirely the area surrounding the first impurity region to be used as the transistor channel. The periphery of the channel is separated from the trench insulating structure via the second impurity region. As a result, it is possible to suppress the occurrence of a hump phenomenon in the drain current-gate voltage (Ids-Vgs) characteristic caused, for example, by divots in the trench insulating structure. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic plan view of a semiconductor device according to the first embodiment of this disclosure. [Figure 2] Figure 2 is an enlarged plan view of the semiconductor device shown in Figure 1. [Figure 3] Figure 3 shows the semiconductor device from Figure 2 with the gate electrodes and other components removed. [Figure 4] Figure 4 shows a cross-section along the line IV-IV in Figure 2. [Figure 5] Figure 5 shows a cross-section along the VV line in Figure 2. [Figure 6]FIG. 6 is an enlarged view of the portion surrounded by the two-dot chain line VI in FIG. 5. [Figure 7] FIG. 7 is a diagram for explaining the channel formation process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram for explaining the channel formation process of the semiconductor device according to the second embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing the static characteristics of the transistor. [Figure 10] FIG. 10 is a schematic plan view showing a part of the semiconductor device according to the third embodiment of the present disclosure. [Figure 11] FIG. 11 is a schematic plan view showing a part of the semiconductor device according to the fourth embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic plan view showing a part of the semiconductor device according to the fifth embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic plan view showing a part of the semiconductor device according to the sixth embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a part of the semiconductor device according to the seventh embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0008] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] Hereinafter, the arrangement direction of a plurality of transistors is defined as the first direction X, the direction orthogonal to the arrangement direction is defined as the second direction Y, and the thickness direction of the chip 2 is defined as the third direction Z. The definitions of the first direction X, the second direction Y, and the third direction Z are not limited to this.

[0010] ≪Overview of Semiconductor Device 1≫ Figure 1 is a schematic plan view of a semiconductor device 1 according to the first embodiment of the present disclosure. Referring to Figure 1, the semiconductor device 1 is, for example, a composite device in which a plurality of elements are mounted on a common chip 2, and includes a CMOS area 3. A CMOS transistor 4 is formed in the CMOS area 3. Although not shown in Figure 1, in addition to the CMOS area 3, the chip 2 may also have a DMOS area in which a DMOS transistor is formed, a bipolar area in which a bipolar transistor is formed, a passive element area in which passive elements such as resistors and capacitors are formed, and so on.

[0011] In the CMOS area 3, CMOS transistors 4 may be formed, for example, a low-voltage CMOS transistor 5, a medium-voltage CMOS transistor, and a high-voltage transistor. The low-voltage CMOS transistor 5 may be, for example, a CMOS transistor having a rated voltage of 1.0V to 4.0V. The medium-voltage CMOS transistor may be, for example, a CMOS transistor having a rated voltage of 4.0V to 7.0V. The high-voltage CMOS transistor may be, for example, a CMOS transistor having a rated voltage of 7V to 60V. The rated voltage may be defined as the range of the maximum allowable voltage applied between the source and drain of each CMOS transistor. Alternatively, the rated voltage of each CMOS transistor may be rephrased as the breakdown voltage of each CMOS transistor 4.

[0012] The following describes in detail the structure of the low-voltage CMOS transistor 5, particularly the structure of the low-voltage p-type channel transistor 6p. However, the structure of the low-voltage p-type channel transistor 6p can also be applied to the low-voltage n-type channel transistor 6n, the medium-voltage CMOS transistor, and the high-voltage CMOS transistor.

[0013] ≪Structure of a low-voltage p-type channel transistor 6p≫ FIG. 2 is an enlarged plan view of the semiconductor device 1 of FIG. 1. FIG. 3 is a view of the semiconductor device 1 of FIG. 2 with the p-side planar gate structure 42p removed. FIG. 4 is a view showing a cross section taken along line IV-IV of FIG. 2. FIG. 5 is a view showing a cross section taken along line V-V of FIG. 2. FIG. 6 is an enlarged view of the portion surrounded by the two-dot chain line VI in FIG. 5.

[0014] As described above, the low-voltage CMOS transistor 5 includes a low-voltage p-type channel transistor 6p and a low-voltage n-type channel transistor 6n. The low-voltage p-type channel transistor 6p and the low-voltage n-type channel transistor 6n are formed on a common chip 2.

[0015] Referring to FIGS. 4 and 5, the chip 2 may include a semiconductor substrate 7 and an epitaxial layer 8 in this embodiment. The semiconductor substrate 7 may be a p-type silicon substrate. The impurity concentration of the semiconductor substrate 7 may be, for example, 1.0×10 13 cm -3 or more and 1.0×10 20 cm -3 or less. The semiconductor substrate 7 has a first main surface 9 and a second main surface 10 on the opposite side thereof. The first main surface 9 and the second main surface 10 may be alternatively referred to as the front surface and the back surface of the semiconductor substrate 7, respectively. The notations "p + ", "p - ", "n + ", "n", and "n - " in the drawings of the present application merely show the relative magnitude relationship of the respective impurity regions (semiconductor regions) containing p-type impurities or n-type impurities for convenience, and do not define a specific range of impurity concentrations.

[0016] The epitaxial layer 8 is formed on the semiconductor substrate 7. The epitaxial layer 8 may be an n-type silicon semiconductor layer in this embodiment. The impurity concentration of the epitaxial layer 8 may be, for example, 1.0×10 13 cm -3 or more and 1.0×10 17 cm -3The following is also possible: The epitaxial layer 8 may have a first main surface 11 and a second main surface 12 on the opposite side. The first main surface 11 and the second main surface 12 may be referred to as the front and back surfaces of the epitaxial layer 8, respectively. The second main surface 12 of the epitaxial layer 8 may be the bonding surface with the first main surface 9 of the chip 2.

[0017] Referring to Figures 1 to 6, the epitaxial layer 8 has a trench insulating structure 13 that divides the region on the first main surface 11 into a plurality of active regions. The trench insulating structure 13 may also be called an element isolation region. Referring to Figure 1, the trench insulating structure 13 divides the first main surface 11 of the epitaxial layer 8 into an LV-active region 14 for a low-voltage CMOS transistor 5. The LV-active region 14 includes a p-side active region 14p for a low-voltage p-type channel transistor 6p and an n-side active region 14n for a low-voltage n-type channel transistor 6n.

[0018] The p-side active region 14p and the n-side active region 14n are adjacent to each other in the first direction X, separated by the trench insulating structure 13. The p-side active region 14p and the n-side active region 14n may be formed as rectangles of the same size, elongated in the second direction Y, in a plan view taken from the direction normal to the first main surface 11.

[0019] Referring to Figure 5, the p-side active region 14p may have a first end 15 on one side, a second end 16 on the opposite side, and a central portion 17 between the first end 15 and the second end 16 in the second direction Y. There does not need to be a clear boundary between the first end 15 and the second end 16 and the central portion 17.

[0020] For example, in the p-side active region 14p, the region occupied by the p-type drain region 26p (described later) may be the first end 15 and the second end 16, and the region surrounded by the p-type drain region 26p may be the central region 17. Alternatively, the range from the boundary 18 between the p-side active region 14p and the trench insulating structure 13 toward the inside in the first direction X may be the first end 15 and the second end 16, and the remaining portion may be the central region 17.

[0021] Referring to Figures 4 to 6, in this embodiment, the trench insulation structure 13 includes trenches 19 formed in the epitaxial layer 8 and embedded insulators 20 embedded in the trenches 19.

[0022] The trench 19 has side walls 21 and a bottom wall 22. The side walls 21 of the trench 19 may be surfaces perpendicular to the first main surface 11 of the epitaxial layer 8, as shown in Figures 4 and 5, or they may be surfaces inclined with respect to the first main surface 11 of the epitaxial layer 8, as shown in Figure 6. In the case of Figure 6, the trench 19 may have a tapered shape in cross-sectional view, where the width narrows in the third direction Z from the first main surface 11 towards the bottom wall 22.

[0023] The embedded insulator 20 may be, for example, silicon oxide (SiO2) or silicon nitride (SiN). In this embodiment, the embedded insulator 20 is made of silicon oxide. The embedded insulator 20 exposes the open end 23 of the trench 19. The trench insulation structure 13 may also be commonly referred to as STI (Shallow Trench Isolation).

[0024] An n-type well 24 for a low-voltage p-type channel transistor 6p is formed on the surface of the epitaxial layer 8. The impurity concentration in the n-type well 24 is higher than the impurity concentration in the epitaxial layer 8, for example, 1.0 × 10⁻⁶ 17 cm -3 The above 1.0 × 10 19 cm -3The following may also apply: A low-voltage p-type channel transistor 6p is formed within this n-type well 24.

[0025] In the surface layer of the n-type well 24, a p-type source region 25p (first impurity region) and a p-type drain region 26p (second impurity region) are formed, spaced apart from each other. The impurity concentrations in the p-type source region 25p and the p-type drain region 26p are higher than the impurity concentrations in the n-type well 24, for example, 1.0 × 10⁻⁶ 19 cm -3 The above 1.0 × 10 21 cm -3 The following is also possible: The p-type source region 25p and the p-type drain region 26p are formed from the first main surface 11 to the same depth. The p-type drain region 26p is in contact with the embedded insulator 20 of the trench insulating structure 13 from the first main surface 11 to the entire depth direction of the epitaxial layer 8. In Figure 1, the n-type source region 25n and the n-type drain region 26n are shown as low-voltage n-type channel transistor 6n structures corresponding to the p-type source region 25p and the p-type drain region 26p, respectively.

[0026] Referring to Figure 3, the p-type source region 25p is formed in an inward region away from the outer edge of the n-type well 24. The p-type source region 25p may be formed with a gap inward from the boundary 18 between the trench insulating structure 13 and the p-side active region 14p. The p-type source region 25p has an outer edge 27 that is inward from the boundary 18 all around.

[0027] In this embodiment, the p-type source region 25p is formed in a shape longitudinal in the second direction Y when viewed from above. More specifically, the p-type source region 25p is formed in a substantially elliptical shape longitudinal in the second direction Y when viewed from above. The outer edge 27 of the p-type source region 25p may include a pair of straight sections 28 extending parallel to the second direction Y and a pair of curved sections 29 extending along the first direction X and connecting the ends of the pair of straight sections 28. Referring to Figure 2, the width W1 of the p-type source region 25p in the first direction X may be, for example, 3 μm or more and 10 μm or less.

[0028] The p-type drain region 26p is formed to be set back from the outer peripheral edge 27 of the p-type source region 25p and to surround the p-type source region 25p in a plan view. The p-type drain region 26p may also be a region occupying a predetermined width inward from the boundary 18 between the trench insulating structure 13 and the p-side active region 14p. In this embodiment, the p-type drain region 26p is formed in an endless ring shape surrounding the p-type source region 25p in a plan view.

[0029] Referring to Figure 3, the p-type drain region 26p has an outer peripheral edge 30 that forms the boundary 18 and an inner peripheral edge 31 that is spaced apart from and opposite to the outer peripheral edge 27 of the p-type source region 25p. The annular region sandwiched between the outer peripheral edge 30 and the inner peripheral edge 31 is the p-type drain region 26p. The outer peripheral edge 30 of the p-type drain region 26p is formed as a rectangular annular shape that is longitudinal in the second direction Y in a plan view. The outer peripheral edge 30 of the p-type drain region 26p may include a pair of first linear portions 32 that extend parallel along the first direction X and a pair of second linear portions 33 that extend parallel along the second direction Y and connect the ends of the pair of first linear portions 32.

[0030] The inner periphery 31 of the p-type drain region 26p is formed in a substantially elliptical ring shape that is longitudinal in the second direction Y when viewed from above. The inner periphery 31 of the p-type drain region 26p may include a pair of straight sections 34 extending parallel to the second direction Y, and a pair of curved sections 35 extending along the first direction X and connecting the ends of the pair of straight sections 34. The inner periphery 31 of the p-type drain region 26p may be similar in shape to the outer periphery 27 of the p-type source region 25p.

[0031] As a result, when perpendiculars are drawn between the outer edge 27 of the p-type source region 25p and the inner edge 31 of the p-type drain region 26p, their lengths may all be equal. In Figure 3, the perpendiculars to the pair of straight sections 28 and the pair of curved sections 29 of the p-type source region 25p include perpendiculars P1, P2, P3, and P4. The lengths L1, L2, L3, and L4 of the perpendiculars P1, P2, P3, and P4 are equal to each other.

[0032] The p-type drain region 26p may include a pair of first parts 36 and a pair of second parts 37. The pair of first parts 36 and the pair of second parts 37 are regions occupying a predetermined area of ​​the surface layer of the n-type well 24, and together they form the p-type drain region 26p. The first parts 36 and the second parts 37 may be referred to as the first region and the second region, or the first area and the second area, respectively. In Figure 3, the pair of first parts 36 are regions with diagonal hatching, and the pair of second parts 37 are regions with cross-hatching.

[0033] The pair of first parts 36 are formed along the pair of first straight sections 32 of the p-type drain region 26p, and the pair of second parts 37 are formed along the pair of second straight sections 33 of the p-type drain region 26p. There is no clear boundary between the first parts 36 and the second parts 37, but it may be defined, for example, by a perpendicular line to the curved section 35 of the inner periphery 31. Alternatively, as shown in Figure 3, for example, the boundary between the first parts 36 and the second parts 37 may be defined by a virtual boundary line 38 drawn from the center C of the circles of each curved section 29 of the source-side periphery 27 to the intersection of the first straight section 32 and the second straight section 33 of the drain-side periphery 30. In this embodiment, since the curved section 29 on the source side and the curved section 35 on the drain side are similar semicircles, the virtual boundary line 38 drawn from the center C is a perpendicular line to the curved section 35 on the drain side.

[0034] A pair of first portions 36 are spaced apart in the second direction Y, flanking a p-type source region 25p, and facing each other through the p-type source region 25p. Each first portion 36 is formed along the first direction X and may be a region sandwiched in the second direction Y between the first straight portion 32 and the drain-side curved portion 35 of the p-type drain region 26p. The width W2 of each first portion 36 in the second direction Y (for example, the distance between the drain-side curved portion 35 and the drain-side first straight portion 32) may be, for example, 0.1 μm or more and 1.0 μm or less.

[0035] A pair of second portions 37 are spaced apart in the first direction X, flanking a p-type source region 25p, and facing each other through the p-type source region 25p. Each second portion 37 is formed along the second direction Y and may be a region sandwiched in the first direction X between the second linear portion 33 and the drain-side linear portion 34 of the p-type drain region 26p. The width W3 of each second portion 37 in the first direction X (for example, the distance between the drain-side linear portion 34 and the drain-side second linear portion 33) may be, for example, 0.4 μm or more and 1.5 μm or less.

[0036] In the n-type well 24, the region sandwiched between the p-type source region 25p and the p-type drain region 26p is the channel region 39 where the transistor channel is formed. Referring to Figure 3, the channel region 39 is formed to surround the p-type source region 25p in a plan view. In this embodiment, the channel region 39 is formed as a substantially elliptical ring that is elongated in the second direction Y surrounding the p-type source region 25p.

[0037] The channel region 39 may include a first channel region 40 and a second channel region 41. In this embodiment, one first channel region 40 is formed on one side and one on the other side of the p-type source region 25p in the second direction Y, and one second channel region 41 is formed on one side and one on the other side of the p-type source region 25p in the first direction X. In other words, the channel region 39 may include a pair of first channel regions 40 and a pair of second channel regions 41.

[0038] The pair of first channel regions 40 are portions of the channel region 39 formed along the first direction X, and the pair of second channel regions 41 are portions of the channel region 39 formed along the second direction Y. There is no clear boundary between the first channel region 40 and the second channel region 41, but it may be defined, for example, by a perpendicular line to the curved portion 29 of the outer edge 27. Alternatively, as shown in Figure 3, the boundary between the first channel region 40 and the second channel region 41 may be defined by the aforementioned virtual boundary line 38. The first channel region 40 may be the region sandwiched between the drain-side curved portion 35 and the source-side curved portion 29 in the second direction Y. The second channel region 41 may be the region sandwiched between the drain-side straight portion 34 and the source-side straight portion 28 in the first direction X.

[0039] In this embodiment, the inner peripheral edge 31 of the p-type drain region 26p is formed equidistant from the outer peripheral edge 27 of the p-type source region 25p over its entire circumference. As a result, the channel length of the first channel region 40 and the channel length of the second channel region 41 are equal to or approximately equal to each other. "Approximately equal" means that a small error occurs between the channel length of the first channel region 40 and the channel length of the second channel region 41 during the manufacturing process of the semiconductor device 1. In Figure 3, the channel length of the first channel region 40 may be the lengths L1 and L3 of the aforementioned perpendiculars P1 and P3, and the channel length of the second channel region 41 may be the lengths L2 and L4 of the aforementioned perpendiculars P2 and P4.

[0040] In the p-side active region 14p, a p-side planar gate structure 42p is formed on the first main surface 11 of the epitaxial layer 8. In Figure 1, the n-side planar gate structure 42n is shown as a low-voltage n-type channel transistor 6n structure corresponding to the p-side planar gate structure 42p. The p-side planar gate structure 42p is formed on the first main surface 11 so as to cover the channel region 39. Referring to Figure 2, the p-side planar gate structure 42p integrally includes a gate electrode 43 that controls the on / off state of the channel region 39, a gate contact portion 44 that receives voltage, and a gate connection portion 45 that connects the gate contact portion 44 and the gate electrode 43.

[0041] Referring to Figure 2, the gate electrode 43 is formed entirely within the p-side active region 14p. The gate electrode 43 has an outer peripheral edge 46 that is set inward from the boundary 18. The gate electrode 43 is formed on the channel region 39. Like the channel region 39, the gate electrode 43 is formed to surround the p-type source region 25p in a plan view. In this embodiment, the gate electrode 43 is formed in a substantially elliptical ring shape that is longitudinal in the second direction Y surrounding the p-type source region 25p. The gate electrode 43 may include a pair of curved portions 47 facing a pair of first channel regions 40 and a pair of straight portions 48 facing a pair of second channel regions 41.

[0042] A gate opening 50 is formed in the central part of the gate electrode 43, demarcated by the inner peripheral edge 49 of the gate electrode 43. A p-type source region 25p is exposed through the gate opening 50. The gate opening 50 is formed in a substantially elliptical shape in plan view. Referring to Figures 4 and 5, the p-type source region 25p may be formed self-aligned with the inner peripheral edge 49 of the gate electrode 43, and the p-type drain region 26p may be formed self-aligned with the outer peripheral edge 46 of the gate electrode 43.

[0043] The gate contact portion 44 is formed on the trench insulating structure 13 and faces the gate electrode 43 across a boundary 18. The gate contact portion 44 is positioned, for example, at a distance from the gate electrode 43 in a first direction X or a second direction Y. In this embodiment, the gate contact portion 44 is selectively positioned on one side of the gate electrode 43 in the second direction Y. The width W5 of the gate contact portion 44 in the first direction X may be narrower than the width W4 of the gate electrode 43 in the first direction X. Although not shown, the gate contact portion 44 may be formed to surround the p-side active region 14p.

[0044] The gate connection portion 45 is connected to the gate electrode 43 by crossing the p-type drain region 26p from the boundary 18 between the trench insulating structure 13 and the p-side active region 14p. Referring to Figure 3, in this embodiment, the gate connection portion 45 selectively crosses one of the first portions 36 of the pair of first portions 36 and the pair of second portions 37 of the p-type drain region 26p.

[0045] The connection position of the gate connection portion 45 on the gate electrode 43 is not particularly limited. Preferably, as shown in Figure 2, the gate connection portion 45 is connected to the top 51 of the curved portion 47 of the gate electrode 43 (the outermost part of the curved portion 47 in the second direction Y). This allows the gate contact portion 44 and the gate electrode 43 to be connected over the shortest distance, thereby suppressing the voltage drop caused by the gate connection portion 45, which is a resistive component. For example, the length L5 of the gate connection portion 45 may be 0.3 μm or more and 1.2 μm or less.

[0046] The gate connection portion 45 has a width W6 that is narrower than the width W1 of the p-type source region 25p in the direction (first direction X in Figure 2) perpendicular to the direction in which the gate connection portion 45 crosses the p-type drain region 26p (second direction Y in Figure 2). Since width W1 < width W4 and width W1 < width W5, the width W6 of the gate connection portion 45 is narrower than the width W4 of the gate electrode 43 and the width W5 of the gate contact portion 44. The width W6 of the gate connection portion 45 may be, for example, 0.08 μm or more and 0.3 μm or less. Also, the width W5 may be, for example, 0.3 μm or more.

[0047] A gate insulating film 52 is formed between the p-side planar gate structure 42p and the first main surface 11. The gate insulating film 52 may contain a silicon oxide film. Preferably, the gate insulating film 52 contains a silicon oxide film made of the oxide of the epitaxial layer 8.

[0048] Referring to Figure 6, the cross-sectional structure of the p-side planar gate structure 42p at the first end 15 and second end 16 of the p-side active region 14p will be described in detail. In Figure 6, the structure at the first end 15 is shown as an example, but the structure of the first end 15 can also be applied to the second end 16. Furthermore, the structure of the first end 15 can also be applied to both ends of the p-side active region 14p in the first direction X.

[0049] In the vicinity of the first end 15 of the p-side active region 14p, a recess 53 is selectively formed in the embedded insulator 20. The recess 53 is a recess that occurs due to a cleaning process (such as light etching with hydrofluoric acid solution) that is performed each time before the thermal oxidation process for forming the gate insulating film 52. The recess 53 may also be called a divot. This recess 53 may be formed continuously around the entire periphery of the p-side active region 14p so as to surround the p-side active region 14p.

[0050] The gate insulating film 52 covers the open end 23 of the trench 19 so as to be integrally connected to the embedded insulator 20 within the recess 53. At the boundary 54 between the embedded insulator 20 and the gate insulating film 52 near the recess 53, a significant thin film portion 55 is formed in the gate insulating film 52. For example, the thickness T1 of the gate insulating film 52 in the central portion 17 is 50 Å or more and 250 Å or less, and the thickness T2 of the thin film portion 55 is smaller than the thickness T1 of the gate insulating film 52 in the central portion 17. The thin film portion 55 causes leakage and leads to a decrease in the breakdown voltage of the gate insulating film 52. In addition, the thin film portion 55 partially forms a low threshold region, which leads to deterioration of the static characteristics of the low breakdown voltage p-type channel transistor 6p (e.g., the threshold becomes unstable). Therefore, this embodiment provides a structure that does not cause such deterioration of static characteristics.

[0051] The gate connection portion 45 covers the boundary portion 54 and the recess 53 of the embedded insulator 20, and may include an embedded portion 56 embedded in the recess 53. As a result, at the first end 15 of the p-side active region 14p, the gate connection portion 45 straddles both the trench insulation structure 13 side and the p-side active region 14p side with respect to the boundary portion 54.

[0052] Referring to Figures 4 and 5, a silicide 57 is formed on the upper surface layer of the p-side planar gate structure 42p. The silicide 57 is integrally formed throughout the entire p-side planar gate structure 42p.

[0053] A sidewall 58 is formed around the p-side planar gate structure 42p. The sidewall 58 is continuously formed around the entire perimeter of the p-side planar gate structure 42p so as to cover the side surface of the p-side planar gate structure 42p. The sidewall 58 may be made of, for example, silicon oxide (SiO2) or silicon nitride (SiN).

[0054] An n-type back gate region 59 is formed on the surface of the n-type well 24. The n-type back gate region 59 is electrically connected to the n-type well 24. In Figure 1, the n-type back gate region 59 is omitted.

[0055] An interlayer insulating film 60 is formed on the first main surface 11 of the epitaxial layer 8. The interlayer insulating film 60 may be, for example, silicon oxide (SiO2) or silicon nitride (SiN). In this embodiment, the interlayer insulating film 60 is made of silicon oxide.

[0056] The interlayer insulating film 60 has source contacts 61, drain contacts 62, and gate contacts 63 formed on it. These contacts 61-63 are embedded in the interlayer insulating film 60. The contacts 61-63 may be made of a metallic material such as tungsten (W). Referring to Figure 2, multiple source contacts 61 and drain contacts 62 are formed, each spaced apart from one another along the second direction Y. Multiple gate contacts 63 are formed, spaced apart from one another along the first direction X.

[0057] Referring to Figures 4 and 5, source wiring 64, drain wiring 65, and gate wiring 66 are formed on the interlayer insulating film 60. The wirings 64-66 may be made of a metallic material such as aluminum (Al). The source wiring 64 is electrically connected to the p-type source region 25p via a source contact 61. The drain wiring 65 is electrically connected to the p-type drain region 26p via a drain contact 62. The gate wiring 66 is electrically connected to the p-side planar gate structure 42p (gate contact portion 44) via a gate contact 63.

[0058] <<Effects of Semiconductor Device 1>> Next, the technical advantages of semiconductor device 1 will be explained based on a comparison between semiconductor device 1 and semiconductor device 81.

[0059] Figure 7 is a diagram illustrating the channel formation process of semiconductor device 1 according to the first embodiment of this disclosure. Figure 8 is a diagram illustrating the channel formation process of semiconductor device 81 according to the second embodiment of this disclosure.

[0060] First, the configuration of the semiconductor device 81 will be described with reference to Figure 8. In the following, structures corresponding to the structures described for semiconductor device 1 will be given the same reference numerals and their descriptions will be omitted.

[0061] In the semiconductor device 1 described above, an example was described in which a p-type drain region 26p is formed to surround a p-type source region 25p. In contrast, in semiconductor device 81, a pair of p-type drain regions 82p are formed flanking the p-type source region 25p in a first direction X. The region between the pair of p-type drain regions 82p in the first direction X is a channel region 83 consisting of a part of an n-type well 24.

[0062] The channel region 83 may include a pair of first channel regions 84 and a pair of second channel regions 85. The pair of first channel regions 84 and the pair of second channel regions 85 occupy a predetermined area of ​​the surface portion of the channel region 83 and combine with each other to form the channel region 83. The pair of first channel regions 84 are portions of the channel region 83 formed along a first direction X and form a boundary 86 with the trench insulating structure 13. The pair of second channel regions 85 are portions of the channel region 83 formed along a second direction Y and form a boundary 87 with the p-type drain region 82p. The semiconductor device 81 differs from the semiconductor device 1 in that a portion of the boundary 18 between the trench insulating structure 13 and the p-side active region 14p is formed by the channel region 83, whereas the boundary 18 is formed by the outer peripheral edge 30 of the p-type drain region 26p around its entire circumference.

[0063] In the semiconductor device 81, both end portions of the gate electrode 43 in the second direction Y are formed along the boundary 86. The gate contact portion 44 is connected to the gate electrode 43 at the boundary 86 without passing through the gate connection portion 45. The p-side planar gate structure 42p is formed in a substantially square ring shape in a plan view by the gate electrode 43 and the gate contact portion 44.

[0064] In the semiconductor device 81 having the above configuration, the first channel region 84 forms a boundary 86 with the trench insulating structure 13. Since this boundary 86 is a part of the boundary 18 between the trench insulating structure 13 and the p-side active region 14p, as described above, the thin film portion 55 of the gate insulating film 52 caused by the depression 53 occurs (see FIG. 6). Therefore, at the initial stage of applying a voltage to the gate electrode 43, a channel is preferentially formed in the first channel region 84 along the boundary 86. By this operation, the first current path 88 indicated by the solid line arrow in FIG. 8 is formed. Subsequently to the formation of the first current path 88, a second current path 89 indicated by the broken line arrow in FIG. 8 is formed in the second channel region 85 away from the boundary 86. In this configuration, when the length L6 from the boundary 86 to the p-type source region 25p in the second direction Y is shorter than the length L7 from the p-type drain region 82p to the p-type source region 25p in the first direction X (L6 < L7), it causes a hump phenomenon in the static characteristics of the transistor.

[0065] The hump phenomenon can be explained with reference to Figure 9. Figure 9 shows an example of the static characteristics of a transistor. In Figure 9, the change in drain current Ids with respect to the gate voltage Vgs is shown when the source is common and the drain voltage Vds = 0.1V. The dashed line shows the characteristics when the hump phenomenon occurs, and the solid line shows the characteristics when the hump phenomenon does not occur. The multiple characteristic curves shown in Figure 9 show the characteristics when the back gate voltage BGV is set to 0V, -1V, -2V, -3V, -4V, and -5V, respectively. From Figure 9, it can be seen that the tendency of the hump phenomenon becomes more pronounced as the back gate voltage BGV increases. The cause of the hump is that a thin film portion 55 (see Figure 6) corresponding to a depression 53 is formed in the gate oxide film, and partial conduction occurs in the thin film portion 55.

[0066] Therefore, the inventors of this application considered a measure to suppress the hump phenomenon by setting L6 >> L7. By adopting L6 >> L7, even if the first channel region 84 is preferentially turned on, the conduction of the first current path 88 can be delayed compared to the conduction of the second current path 89, making the hump characteristic less noticeable. However, this measure requires that the length of L6 be made much larger than the length of L7, which reduces the area efficiency of the transistor.

[0067] In contrast, with the configuration of semiconductor device 1, it is possible to avoid the decrease in area efficiency while suppressing the occurrence of a hump phenomenon in the drain current-gate voltage (Ids-Vgs) characteristic. More specifically, referring to Figure 7, the p-type drain region 26p surrounds the p-type source region 25p. This allows the entire area around the p-type source region 25p to be used as the transistor channel.

[0068] The periphery of the channel region 39 (in this embodiment, the inner periphery 31 of the p-type drain region 26p) is separated from the trench insulating structure 13 via the p-type drain region 26p. Furthermore, the gate electrode 43 and the gate contact portion 44 are connected by a gate connection portion 45 that crosses the boundary 18. Since the gate connection portion 45 does not cover the channel region 39 and is formed on the p-type drain region 26p, it is not a gate for a parasitic transistor, but rather a resistive component of the current path from the gate contact portion 44 to the gate electrode 43. Therefore, a channel is not formed directly beneath the gate connection portion 45 due to the voltage applied to it. Consequently, the current path 67 can be formed uniformly throughout the entire channel region 39. As a result, it is possible to suppress the occurrence of a hump phenomenon in the drain current-gate voltage (Ids-Vgs) characteristic caused, for example, by a divot 53 in the trench insulating structure 13. This allows for good static characteristics to be achieved even with a high back gate voltage. Therefore, the structure of the semiconductor device 1 is suitable as a transistor structure for analog circuits where a relatively large amount of back gate voltage is applied.

[0069] For example, the divots 53 that cause the hump phenomenon are caused by stress from the trench insulating structure 13 (e.g., STI), and therefore there is variation even within the plane of a common chip 2. As a result, depending on the layout of the transistor region, the hump phenomenon may occur frequently in some transistor regions, while it may hardly occur in other transistor regions. With the configuration of the semiconductor device 1, the variation in the occurrence of the hump phenomenon on a common chip 2 can be suppressed, thereby improving the matching characteristics of multiple transistors.

[0070] Also, referring to Figure 2, in semiconductor device 1, the width W6 of the gate connection portion 45 is narrower than the width W1 of the p-type source region 25p, the width W4 of the gate electrode 43, and the width W5 of the gate contact portion 44. For example, the gate connection portion 45 may be formed to the minimum size that can be machined (minimum size that can be patterned) when forming the p-side planar gate structure 42p. The portion of the p-type drain region 26p directly below the gate connection portion 45 is the part that faces the gate connection portion 45, which is a resistive component, and therefore may not be able to fully perform its function as a drain of the transistor. By making the width W6 of the gate connection portion 45 as small as possible, the impact on the p-type drain region 26p can be minimized.

[0071] ≪Description of the structure of semiconductor device 101 (third embodiment)≫ Figure 10 is a schematic plan view showing a part of the semiconductor device 101 according to the third embodiment of this disclosure. In the following, structures corresponding to the structures described for the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0072] In the third embodiment, the width W6 of the gate connection portion 45 is narrower than the width W4 of the gate electrode 43 and is the same as the width W5 of the gate contact portion 44.

[0073] As described above, the semiconductor device 101 according to the third embodiment can achieve the same effects as those described for the semiconductor device 1. Furthermore, with the configuration of the semiconductor device 101, the width W6 of the gate connection portion 45 is wider than in the first embodiment, so the voltage drop caused by the gate connection portion 45, which is a resistive component, can be suppressed.

[0074] ≪Description of the structure of semiconductor device 111 (fourth embodiment)≫ Figure 11 is a schematic plan view showing a part of the semiconductor device 111 according to the fourth embodiment of this disclosure. Hereinafter, structures corresponding to the structures described for the semiconductor device 1 according to the first embodiment will be given the same reference numerals and their descriptions will be omitted.

[0075] In the fourth embodiment, the width W6 of the gate connection portion 45 is narrower than the width W4 of the gate electrode 43 and wider than the width W5 of the gate contact portion 44.

[0076] As described above, the semiconductor device 111 according to the fourth embodiment can achieve the same effects as those described for the semiconductor device 1. Furthermore, with the configuration of the semiconductor device 111, the width W6 of the gate connection portion 45 is wider than in the first and third embodiments, so the voltage drop caused by the gate connection portion 45, which is a resistive component, can be further suppressed.

[0077] ≪Description of the structure of semiconductor device 121 (5th embodiment)≫ Figure 12 is a schematic plan view showing a part of the semiconductor device 121 according to the fifth embodiment of this disclosure. In the following description, structures corresponding to the structures described for the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0078] In the fifth embodiment, the gate contact portion 44 is located on one side of the gate electrode 43 in the second direction Y, as well as on one side of the gate electrode 43 in the first direction X. In other words, there may be multiple gate contact portions 44 located at multiple locations around the gate electrode 43, independently of each other. The multiple gate contact portions 44 may be connected to the gate electrode 43 by gate connection portions 45 that are physically independent of each other.

[0079] As described above, the semiconductor device 121 according to the fifth embodiment can achieve the same effects as those described for the semiconductor device 1. Furthermore, the configuration of the semiconductor device 121 provides multiple gate contact portions 44. This allows, for example, if a processing defect occurs in one gate connection portion 45 when forming the gate connection portion 45 with the minimum processing dimensions, potentially affecting the transistor characteristics, a stable voltage can still be applied to the gate electrode 43 via the other gate connection portions 45.

[0080] ≪Description of the structure of semiconductor device 131 (sixth embodiment)≫ Figure 13 is a schematic plan view showing a part of the semiconductor device 131 according to the sixth embodiment of this disclosure. In the following, structures corresponding to the structures described for the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0081] In the sixth embodiment, the p-type drain region 26p is formed in a terminal annular shape surrounding the p-type source region 25p in a plan view. Although the p-type drain region 26p surrounds the p-type source region 25p, it may be partially divided by a blank region 132 extending from the inner peripheral edge 31 toward the outer peripheral edge 30. The blank region 132 may be formed in only one location, as shown in Figure 13, or in multiple locations. It is preferable that the blank region 132 be formed in the region directly below the gate connection portion 45. The portion directly below the gate connection portion 45 is the portion facing the gate connection portion 45, which is a resistive component. Therefore, even if the p-type drain region 26p is formed, it may not be able to fully perform its function as a drain of the transistor.

[0082] ≪Description of the structure of semiconductor device 141 (7th embodiment)≫ Figure 14 is a schematic cross-sectional view showing a part of the semiconductor device 141 according to the seventh embodiment of this disclosure. Hereinafter, structures corresponding to the structures described for the semiconductor device 1 according to the first embodiment will be given the same reference numerals and their descriptions will be omitted.

[0083] In the seventh embodiment, the p-side active region 14p further includes a p-type source extension region 142 and a p-type drain extension region 143 that extend integrally along the first direction X from the p-type source region 25p and the p-type drain region 26p, respectively. The impurity concentration in the p-type source extension region 142 and the p-type drain extension region 143 is lower than the impurity concentration in the p-type source region 25p and the p-type drain region 26p, for example, 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21 cm -3The following is also possible: The p-type source extension region 142 and the p-type drain extension region 143 are formed in a self-aligned manner with respect to the gate electrode 43.

[0084] The p-side active region 14p further has n-type source pocket implant region 144 and n-type drain pocket implant region 145 that extend integrally along the first direction X from the p-type source region 25p and p-type drain region 26p, respectively. The impurity concentration in the n-type source pocket implant region 144 and n-type drain pocket implant region 145 is higher than that in the n-type well 24, for example, 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 20 cm -3 The following is also possible: The n-type source pocket implant region 144 and the n-type drain pocket implant region 145 cross the boundary with the sidewall 58 and the gate electrode 43 along the first direction X, and face the gate electrode 43 with the gate insulating film 52 in between.

[0085] The n-type source pocket implantation region 144 and the n-type drain pocket implantation region 145 cover the bottom and sides of the p-type source extension region 142 and the p-type drain extension region 143, respectively.

[0086] Furthermore, since both the p-type source region 25p and the p-type source extension region 142 are p-type and form a single integrated p-type impurity region, they may be collectively referred to simply as the p-type source region 25p. Similarly, since both the p-type drain region 26p and the p-type drain extension region 143 are p-type and form a single integrated p-type impurity region, they may be collectively referred to simply as the p-type drain region 26p.

[0087] Furthermore, the p-type source extension region 142 and the n-type source pocket implant region 144 extending downward from the p-type source region 25p to the gate electrode 43 may be collectively referred to as the p-side source LDD (Lightly Doped Drain) region. Similarly, the p-type drain extension region 143 and the n-type drain pocket implant region 145 extending downward from the p-type drain region 26p to the gate electrode 43 may be collectively referred to as the p-side drain LDD (Lightly Doped Drain) region.

[0088] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0089] For example, in the description of the above embodiment and the attached drawings, replace the n-type region with a p-type region Well, you can also replace the p-type region with an n-type region.

[0090] The embodiments described herein are illustrative in all respects and should not be construed restrictively, and are intended to be modified in all respects.

[0091] The following features can be extracted from the description in this specification and drawings.

[0092] [Note 1-1] A chip (2) having a main surface (11), The main surface (11) includes a trench insulating structure (13) that demarcates the active region (14, 14p, 14n), A first conductivity type well region (24) formed in the active region (14, 14p, 14n), The first impurity region (25p, 25n) of the second conductivity type formed in the well region (24), A second impurity region (26p, 26n) is formed in the well region (24) and surrounds the first impurity region (25p, 25n) in a plan view, A gate electrode (43) is formed on the well region (24) between the first impurity region (25p, 25n) and the second impurity region (26p, 26n), and surrounds the first impurity region (25p, 25n) in a plan view, A gate insulating film (52) formed between the gate electrode (43) and the well region (24), A gate contact portion (44) formed on the trench insulating structure (13), A semiconductor device (1,101,111,121,131,141) includes a gate connection portion (45) that extends from the boundary (18) between the trench insulating structure (13) and the active region (14,14p,14n) across the second impurity region (26p,26n) and connects the gate contact portion (44) and the gate electrode (43).

[0093] In this configuration, the second impurity region surrounds the first impurity region. This allows almost the entire or all of the area surrounding the first impurity region to be used as the transistor channel. The periphery of the channel is separated from the trench insulating structure via the second impurity region. As a result, it is possible to suppress the occurrence of a hump phenomenon in the drain current-gate voltage (Ids-Vgs) characteristic caused, for example, by divots in the trench insulating structure.

[0094] [Appendix 1-2] The semiconductor device described in Appendix 1-2 (1,101,111,121,131,141) includes a pair of first portions (36) formed along a first direction (X) and flanking the first impurity region (25p,25n) in a second direction (Y) perpendicular to the first direction (X), and a pair of second portions (37) formed along the second direction (Y) and flanking the first impurity region (25p,25n) in the first direction (X).

[0095] [Appendix 1-3] The semiconductor device described in Appendix 1-2 (1,101,111,121,131,141), wherein the gate connection portion (45) selectively crosses at least one of the pair of first portions (36) and the pair of second portions (37) to connect the gate contact portion (44) and the gate electrode (43).

[0096] [Appendix 1-4] The semiconductor device (1,101,111,121,131,141) according to any one of the appendices 1-1 to 1-3, wherein the well region (24) includes a first channel region (40) formed between the first impurity region (25p,25n) and the first portion (36) of the second impurity region (26p,26n), in which a channel is formed along the second direction (Y), and a second channel region (41) formed between the first impurity region (25p,25n) and the second portion (37) of the second impurity region (26p,26n), in which a channel is formed along the first direction (X).

[0097] [Appendix 1-5] The semiconductor device described in Appendix 1-4 (1,101,111,121,131,141), wherein the channel lengths (L1,L3) of the first channel region (40) and the channel lengths (L2,L4) of the second channel region (41) are approximately equal.

[0098] [Appendix 1-6] The first impurity region (25p, 25n) is formed in a shape that is elongated in the second direction (Y), The gate electrode (43) is formed in a substantially elliptical ring shape that is elongated in the second direction (Y) surrounding the first impurity region (25p, 25n), as described in any one of the appendices 1-1 to 1-4 (1,101,111,121,131,141).

[0099] [Appendix 1-7] The gate connection portion (45) is formed at a position opposite to the first impurity region (25p, 25n) in the second direction (Y), and has a width (W6) narrower than the first impurity region (25p, 25n) in the first direction (X), as described in any one of the appendices 1-1 to 1-6 (1,121,131,141).

[0100] [Appendix 1-8] The width (W6) of the gate connection portion (45) is 0.08 μm or more and 0.3 μm or less, as described in Appendix 1-7 (1,121,131,141).

[0101] [Appendix 1-9] The second impurity region (26p, 26n) is formed in an endless ring shape in a plan view, as described in any one of the appendices 1-1 to 1-8 (1,101,111,121,141).

[0102] [Appendix 1-10] The semiconductor device (1,121,131,141) described in any one of the appendices 1-1 to 1-3, wherein the gate connection portion (45) has a narrower width (W6) than the gate electrode (43) and the gate contact portion (44) in a direction perpendicular to the direction in which the gate connection portion (45) crosses the second impurity region (26p,26n).

[0103] [Appendix 1-11] The semiconductor device (1,121,131,141) described in any one of the appendices 1-1 to 1-3, wherein the gate connection portion (45) has a width (W6) that is narrower than the first impurity region (25p,25n) in a direction perpendicular to the direction in which the gate connection portion (45) crosses the second impurity region (26p,26n).

[0104] [Appendix 1-12] The width (W6) of the gate connection portion (45) is 0.08 μm or more and 0.3 μm or less, as described in Appendix 1-10 or Appendix 1-11 (1,121,131,141).

[0105] [Appendix 1-13] The trench insulating structure (13) includes a trench (19) formed in the main surface (11), an insulator (20) embedded in the main surface (11) so as to expose the open end (23) of the trench (19), and a recess (53) at the upper end of the insulator (20) that is recessed toward the bottom wall (22) of the trench (19). The gate connection portion (45) is formed to cover the recess (53), as described in any one of the appendices 1-1 to 1-12 (1,101,111,121,131,141).

[0106] [Appendix 1-14] A semiconductor device (1,101,111,121,131,141) as described in any one of the appendices 1-1 to 1-13, wherein the first impurity region (25p,25n) is the source region and the second impurity region (26p,26n) is the drain region.

[0107] [Appendix 1-15] The active region (14, 14p, 14n) includes a CMOS region (3) for the CMOS transistor (4). The source region and the drain region are part of the CMOS transistor (4) of the semiconductor device described in Appendix 1-14 (1,101,111,121,131,141). [Explanation of Symbols]

[0108] 1: Semiconductor device 2: Tip 3: CMOS area 4: CMOS transistor 5: Low-voltage CMOS transistor 6n: Low-voltage n-type channel transistor 6p: Low-voltage p-type channel transistor 7: Semiconductor substrates 8: Epitaxial layer 9: First main surface 10: Second main surface 11: First main surface 12: Second main surface 13: Trench insulation structure 14: LV-Active Area 14n: n-side active region 14p : p-side active area 15: First end 16:Second end 17: Central part 18 :Boundary 19: Trench 20: Embedded insulator 21: Side wall 22: Bottom wall 23: Open end 24: n-type well 25n : n-type source area 25p:p type source region 26n: n-type drain region 26p: p-type drain region 27: Peripheral edge 28: Straight section 29:Curve section 30: Outer edge 31: Inner periphery 32: 1st straight section 33: 2nd straight section 34: Straight section 35:Curve section 36: 1st part 37:Second part 38: Virtual Boundary 39: Channel area 40: First channel region 41: Second channel region 42n: n-side planar gate structure 42p: p-side planar gate structure 43: Guard gate 44: Gate contact section 45: Gate connection section 46: Peripheral edge 47:Curve section 48: Straight section 49: Inner periphery 50: Gate opening 51:Top 52: Gate Insulator 53: Indentation 54: Boundary 55: Thin film section 56: Embedded part 57: Silicide 58: Sidewall 59: n-type back gate region 60: Interlayer insulating film 61: Source Contact 62: Drain Contact 63: Gate Contact 64: Source Wiring 65: Drain wiring 66: Gate wiring 67: Current Path 81: Semiconductor equipment 82p: p-type drain region 83: Channel area 84: First channel region 85: Second channel region 86: Boundary 87: Boundary 88: First current path 89: Second current path 101: Semiconductor Device 111: Semiconductor Device 121: Semiconductor equipment 131: Semiconductor device 132 :Blank area 141: Semiconductor Equipment 142: p-type source extension area 143: p-type drain extension region 144: n-type source pocket implant area 145: n-type drain pocket implant area X: 1st direction Y: Second direction Z: 3rd direction

Claims

1. A chip having a main surface, The main surface comprises a trench insulating structure that demarcates the active region, A first conductivity type well region formed in the active region, A first impurity region of the second conductivity type formed in the well region, A second impurity region is formed in the well region and surrounds the first impurity region in a plan view, A gate electrode is formed on the well region between the first impurity region and the second impurity region, and surrounds the first impurity region in a plan view, A gate insulating film formed between the gate electrode and the well region, A gate contact portion formed on the trench insulating structure, A semiconductor device comprising a gate connection portion that extends from the boundary between the trench insulating structure and the active region across the second impurity region and connects the gate contact portion and the gate electrode.

2. The semiconductor device according to claim 1, wherein the second impurity region includes a pair of first portions formed along a first direction and flanking the first impurity region in a second direction perpendicular to the first direction, and a pair of second portions formed along the second direction and flanking the first impurity region in the first direction.

3. The semiconductor device according to claim 2, wherein the gate connection portion selectively crosses at least one of the pair of first portions and the pair of second portions to connect the gate contact portion and the gate electrode.

4. The semiconductor device according to claim 2 or 3, wherein the well region includes a first channel region formed between the first impurity region and the first portion of the second impurity region, where a channel is formed along the second direction, and a second channel region formed between the first impurity region and the second portion of the second impurity region, where a channel is formed along the first direction.

5. The semiconductor device according to claim 4, wherein the channel length of the first channel region and the channel length of the second channel region are substantially equal.

6. The first impurity region is formed in a shape that is elongated in the second direction, The semiconductor device according to claim 4, wherein the gate electrode is formed in a substantially elliptical ring shape that is elongated in the second direction and surrounds the first impurity region.

7. The semiconductor device according to claim 6, wherein the gate connection portion is formed at a position facing the first impurity region in the second direction and has a narrower width than the first impurity region in the first direction.

8. The semiconductor device according to claim 7, wherein the width of the gate connection portion is 0.08 μm or more and 0.3 μm or less.

9. The semiconductor device according to claim 4, wherein the second impurity region is formed in an endless ring shape in a plan view.

10. The semiconductor device according to any one of claims 1 to 3, wherein the gate connection portion has a narrower width than the gate electrode and the gate contact portion in a direction perpendicular to the direction in which the gate connection portion crosses the second impurity region.

11. The semiconductor device according to any one of claims 1 to 3, wherein the gate connection portion has a narrower width than the first impurity region in a direction perpendicular to the direction in which the gate connection portion crosses the second impurity region.

12. The semiconductor device according to claim 10, wherein the width of the gate connection portion is 0.08 μm or more and 0.3 μm or less.

13. The trench insulating structure includes a trench formed on the main surface, an insulator embedded in the main surface so as to expose the open end of the trench, and a recess at the upper end of the insulator that is recessed toward the bottom wall of the trench. The semiconductor device according to any one of claims 1 to 3, wherein the gate connection portion is formed to cover the recess.

14. The semiconductor device according to any one of claims 1 to 3, wherein the first impurity region is a source region and the second impurity region is a drain region.

15. The active region includes a CMOS region for a CMOS transistor. The semiconductor device according to claim 14, wherein the source region and the drain region are part of the CMOS transistor.

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