Semiconductor equipment

Abstract

To provide a semiconductor device that is highly resistant to a surge current.SOLUTION: A semiconductor device includes: a first electrode; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer located on a first portion of the second semiconductor layer, and being of the first conductivity type; a fourth semiconductor layer located on a second portion of the second semiconductor layer, the fourth semiconductor layer being of the second conductivity type and having a higher carrier concentration than that of the second semiconductor layer; a fifth semiconductor layer located on a third portion of the second semiconductor layer, the fifth semiconductor layer being of the second conductivity type and having a higher carrier concentration than that of the second semiconductor layer, and having a length in a second direction being greater than a length in the second direction of the fourth semiconductor layer; a second electrode facing, via an insulating film, the second semiconductor layer; a third electrode connected to the third, fourth, and fifth semiconductor layers; and a metal film connected to the third electrode and located in a region that includes a region directly above the fifth semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to semiconductor devices. [Background technology]

[0002] Some semiconductor devices for power control utilize silicon carbide (SiC). Silicon carbide has a higher dielectric breakdown field strength than silicon (Si), enabling the realization of high-performance power control semiconductor devices. Power control semiconductor devices need to withstand surge currents exceeding the rated current, albeit for a short period, in the event of system failures. In particular, because silicon carbide allows for lower element resistance than silicon, semiconductor devices using silicon carbide are often used at higher current densities. Therefore, semiconductor devices using silicon carbide are required to withstand high surge currents. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6649183 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The objective of this embodiment is to provide a semiconductor device that has high resistance to surge currents. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor layer of a first conductivity type connected to the first electrode and containing silicon and carbon, a second semiconductor layer of a second conductivity type disposed on a part of the first semiconductor layer and in contact with the first semiconductor layer and containing silicon and carbon, a third semiconductor layer of a first conductivity type disposed on a first part of the second semiconductor layer and containing silicon and carbon, a fourth semiconductor layer disposed on a second part of the second semiconductor layer, containing silicon and carbon, of a second conductivity type, and having a carrier concentration higher than that of the second semiconductor layer, and a third semiconductor layer disposed on a third part of the second semiconductor layer and containing silicon and carbon, The device comprises: a 2-conductivity fifth semiconductor layer having a carrier concentration higher than that of the second semiconductor layer, and a length in a second direction intersecting the first direction from the first electrode toward the first semiconductor layer that is longer than the length of the fourth semiconductor layer toward the second direction; a second electrode facing the portion of the second semiconductor layer located between the first semiconductor layer and the third semiconductor layer via an insulating film; a third electrode connected to the third semiconductor layer, the fourth semiconductor layer and the fifth semiconductor layer; and a metal film located on the third electrode in a region including the area directly above the fifth semiconductor layer and connected to the third electrode.

[0006] The semiconductor device according to the embodiment includes: a first electrode; a first semiconductor layer of a first conductivity type, connected to the first electrode and containing silicon and carbon; a second semiconductor layer of a second conductivity type, disposed on a part of the first semiconductor layer and in contact with the first semiconductor layer and containing silicon and carbon; a third semiconductor layer, disposed on a part of the second semiconductor layer and in contact with the second semiconductor layer, containing silicon and carbon, of a second conductivity type, and having a carrier concentration higher than that of the second semiconductor layer; a metal layer disposed on the first semiconductor layer and forming a Schottky junction with the first semiconductor layer; a second electrode disposed on the metal layer and connected to the metal layer; and a metal film disposed on the second electrode in a region including the area directly above the third semiconductor layer and connected to the second electrode. [Brief explanation of the drawing]

[0007] [Figure 1]FIG. 1(a) is a plan view showing a semiconductor device according to the first embodiment, and FIG. 1(b) is a plan view showing a semiconductor portion of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing a gate electrode structure and a surge trigger layer in the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along the line A-A' shown in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along the line B-B' shown in FIG. 1(b). [Figure 5] FIGS. 5(a) and (b) are schematic cross-sectional views showing the operation of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6(a) is a plan view showing a semiconductor device according to a comparative example, and FIG. 6(b) is a cross-sectional view taken along the line D-D' shown in FIG. 6(a). [Figure 7] FIG. 7 is a plan view showing a semiconductor portion of a semiconductor device according to a first modification of the first embodiment. [Figure 8] FIG. 8 is a plan view showing a semiconductor portion of a semiconductor device according to a second modification of the first embodiment. [Figure 9] FIG. 9 is a plan view showing a semiconductor portion of a semiconductor device according to a third modification of the first embodiment. [Figure 10] FIG. 10 is a plan view showing a semiconductor portion of a semiconductor device according to a fourth modification of the first embodiment. [Figure 11] FIG. 11 is a plan view showing a semiconductor portion of a semiconductor device according to a fifth modification of the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along the line E-E' shown in FIG. 11. [Figure 13] FIG. 13(a) is a plan view showing a semiconductor device according to the second embodiment, and FIG. 13(b) is a plan view showing a semiconductor portion of the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along the line F-F' shown in FIG. 13(a).

BEST MODE FOR CARRYING OUT THE INVENTION

[0008] <First Embodiment> The semiconductor device according to this embodiment is a vertical semiconductor device for power control, and is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0009] Figure 1(a) is a plan view showing a semiconductor device according to this embodiment, and Figure 1(b) is a plan view showing the semiconductor portion of the semiconductor device according to this embodiment. Figure 2 is a plan view showing the gate electrode structure and surge trigger layer in the semiconductor device according to this embodiment. Figure 3 is a cross-sectional view taken along the line A-A' shown in Figure 2. Figure 4 is a cross-sectional view taken along the line B-B' shown in Figure 1(b).

[0010] As shown in Figures 1(a) to 4, the semiconductor device 1 according to this embodiment is provided with a drain electrode 11 (first electrode), a semiconductor portion 20, a source electrode 12 (third electrode), a gate electrode structure 13, an insulating film 30, and a metal film 14. The shape of the semiconductor portion 20 is, for example, a rectangular plate. The drain electrode 11, the source electrode 12, and the metal film 14 are formed of, for example, metal.

[0011] Hereafter, for the sake of explanation, the XYZ Cartesian coordinate system will be adopted in this specification. The direction from the drain electrode 11 toward the source electrode 12 will be referred to as the "Z direction" (first direction), and the two directions in which the outer edge of the semiconductor device 1 extends when viewed from the Z direction will be referred to as the "Y direction" (second direction) and the "X direction" (third direction). If necessary, a "+" sign may be added to the forward direction and a "-" sign to the reverse direction of each direction. In addition, the Z direction (+Z direction) will also be referred to as "up," and its reverse direction (-Z direction) will be referred to as "down," but this expression is also for convenience and is unrelated to the direction of gravity.

[0012] The drain electrode 11 is provided across the entire lower surface of the semiconductor portion 20. The gate electrode structure 13 includes a gate pad 13a, gate peripheral wiring 13b, gate main wiring 13c, and a gate electrode 13d (second electrode).

[0013] An example of the gate electrode structure 13 is described below. The gate pad 13a is located on the upper surface of the semiconductor portion 20, at the center in the X direction at the +Y direction end. The gate circuit wiring 13b is drawn out from the +Y direction end of the gate pad 13a to both sides in the X direction and circles along the outer edge of the semiconductor device 1. The gate pad 13a and the gate circuit wiring 13b are made of a conductive material, for example, made of metal.

[0014] The gate trunk wiring 13c extends in the Y direction, and both ends are connected to the -Y direction end of the gate pad 13a and to the portion of the gate circumferential wiring 13b that extends along the -Y direction end of the semiconductor portion 20. In this specification, "connection" means an electrical connection. Multiple gate electrodes 13d are provided, each gate electrode 13d extending in the X direction. Both ends of each gate electrode 13d are connected to the gate pad 13a and the gate circumferential wiring 13b, or to the gate trunk wiring 13c and the gate circumferential wiring 13b. The gate trunk wiring 13c and gate electrodes 13d are made of a conductive material, for example, made of conductive polysilicon containing impurities.

[0015] The source electrode 12 is positioned on the upper surface of the semiconductor portion 20 in a region separated from the gate pad 13a and the gate surrounding wiring 13b. Therefore, when viewed from the Z direction, the shape of the source electrode 12 is U-shaped, surrounded by the gate surrounding wiring 13b and enclosing the gate pad 13a from three directions.

[0016] The gate core wiring 13c and gate electrode 13d are positioned between the semiconductor portion 20 and the source electrode 12. The insulating film 30 is positioned between the semiconductor portion 20 and the gate pad 13a, between the semiconductor portion 20 and the gate surrounding wiring 13b, and surrounding the gate core wiring 13c and gate electrode 13d. The insulating film 30 is made of an insulating material, for example, silicon dioxide (SiO2). As a result, the gate electrode structure 13 is insulated from the semiconductor portion 20 and the source electrode 12 by the insulating film 30.

[0017] As shown in Figure 3, the semiconductor portion 20 is made of a semiconductor material containing silicon (Si) and carbon (C), for example, a single crystal of silicon carbide (SiC). By introducing impurities into each part of the semiconductor portion 20, the conductivity type of each part is made p-type or n-type. The semiconductor portion 20 is provided with a drain layer 21, a drift layer 22, a base layer 23 (second semiconductor layer), a source layer 24 (third semiconductor layer), a base contact layer 25 (fourth semiconductor layer), and a surge trigger layer 26 (fifth semiconductor layer).

[0018] The following "n" represents the conductivity type. + ``type'', ``n type'', ``n - The notation "type" indicates the relative magnitude of carrier concentrations, and "n + The "n-type" indicates that the carrier concentration is higher than that of the "n-type". - The "n-type" indicates a lower carrier concentration than the "n-type". The same applies to the p-type. + The "p-type" designation indicates a higher carrier concentration than the "p-type" designation. "Carrier concentration" refers to the effective impurity concentration that contributes to the conductivity of a semiconductor material. If a region contains both donor and acceptor impurities, it corresponds to the net impurity concentration after deducting the canceling-out portion.

[0019] The conductivity type of the drain layer 21 is n + It is of type 2. The carrier concentration in the drain layer 21 is, for example, 5 × 10⁻⁶. 19 cm -3is the case. The drain layer 21 constitutes the lower surface of the semiconductor portion 20. The drain layer 21 is disposed on the drain electrode 11. The drain layer 21 is in contact with the drain electrode 11 and is thus connected to the drain electrode 11.

[0020] The conductivity type of the drift layer 22 is n - type. The drift layer 22 is disposed on the drain layer 21 and is in contact with the drain layer 21. The carrier concentration of the drift layer 22 is lower than the carrier concentration of the drain layer 21. The carrier concentration of the drift layer 22 is, for example, 1×10 15 cm -3 or more and 5×10 16 cm -3 or less. The carrier concentration at the boundary between the drain layer 21 and the drift layer 22 is, for example, 5×10 17 cm -3 . The drain layer 21 and the drift layer 22 constitute the first semiconductor layer.

[0021] The conductivity type of the base layer 23 is p-type. The base layer 23 is disposed on a part of the drift layer 22 and is in contact with the drift layer 22. Therefore, the interface between the p-type base layer 23 and the n - type drift layer 22 forms a pn junction. The base layer 23 is divided into a plurality of portions 23a and a plurality of portions 23b. Each of the portions 23a and 23b extends in the X direction, that is, the same direction as the gate electrode 13d, and is spaced apart from each other along the Y direction. For example, one portion 23b is disposed for every several or several tens of portions 23a. The length of the portion 23b in the Y direction is longer than the length of the portion 23a in the Y direction. A portion 22a of the drift layer 22 is interposed between adjacent portions 23a and between the portion 23a and the portion 23b.

[0022] The conductivity type of the source layer 24 is n + type. Therefore, between the p-type base layer 23 and the n +The interface with the source layer 24 forms a pn junction. The carrier concentration in the source layer 24 is higher than that of the drift layer 22. The source layer 24 is located on a portion (first portion) of each portion 23a and a portion (first portion) of each portion 23b of the base layer 23, and is in contact with the base layer 23. On the other hand, the source layer 24 is separated from the drift layer 22. Each source layer 24 extends in the X direction.

[0023] The conductivity type of the base contact layer 25 is p + This is the type. The carrier concentration in the base contact layer 25 is higher than the carrier concentration in the base layer 23. That is, the effective acceptor concentration in the base contact layer 25 is higher than the effective acceptor concentration in the base layer 23. The base contact layer 25 is located on each portion 23a of the base layer 23, on a portion (second portion) of the base layer 23 where the source layer 24 is not provided. The base contact layer 25 is in contact with the portion 23a of the base layer 23. The base contact layer 25 may also be in contact with the source layer 24. Each base contact layer 25 extends in the X direction.

[0024] The conductivity type of the surge trigger layer 26 is p + This is the type. The carrier concentration in the surge trigger layer 26 is higher than the carrier concentration in the base layer 23. That is, the effective acceptor concentration in the surge trigger layer 26 is higher than the effective acceptor concentration in the base layer 23. The surge trigger layer 26 is located on each portion 23b of the base layer 23, on a portion (third portion) where the source layer 24 is not provided. The surge trigger layer 26 is in contact with the portion 23b of the base layer 23. The surge trigger layer 26 may also be in contact with the source layer 24.

[0025] Thus, the source layer 24 is positioned on both portion 23a and portion 23b of the base layer 23, and the base contact layer 25 teeth The surge trigger layer 26 is located only on portion 23a, while the surge trigger layer 26 is located only on portion 23b.

[0026] As shown in Figure 2, multiple surge trigger layers 26 are provided and arranged in a matrix along the X and Y directions. In this embodiment, for example, eight surge trigger layers 26 are arranged in four rows along the Y direction and two columns along the X direction. The length of each surge trigger layer 26 in the X direction is longer than its length in the Y direction.

[0027] As shown in Figure 3, in portion 23a of the base layer 23, the source layer 24 is positioned away from both edges in the Y direction of portion 23a, and the base contact layer 25 is positioned between the two source layers 24. The portion of the drift layer 22 in portion 23a that is located between portion 22a and the source layer 24 is referred to as the "channel portion 23c".

[0028] In portion 23b of the base layer 23, the source layer 24 is positioned away from both edges of portion 23b in the Y direction. The surge trigger layer 26 is positioned between the two source layers 24. The portion of the drift layer 22 in portion 23b that is located between portion 22a and the source layer 24 is referred to as the "channel portion 23d".

[0029] The upper surface of the semiconductor portion 20 is formed by portion 22a of the drift layer 22, channel portions 23c and 23d of the base layer 23, source layer 24, base contact layer 25, and surge trigger layer 26.

[0030] The gate electrode 13d is located on the semiconductor portion 20, directly above portion 22a of the drift layer 22, directly above the portion of the source layer 24 on the 22a side, and directly above the channel portions 23c and 23d of the base layer 23. The gate electrode 13d faces the channel portions 23c and 23d through a portion of the insulating film 30.

[0031] The source electrode 12 is positioned on the semiconductor portion 20 and covers the insulating film 30. The source electrode 12 is connected to the source layer 24, the base contact layer 25, and the surge trigger layer 26. A silicide layer (not shown) may be formed on at least a portion of the area in contact with the source electrode 12 on the upper surface of the semiconductor portion 20. The silicide layer is made of, for example, nickel silicide.

[0032] As shown in Figures 1(b) and 3, the metal film 14 is located on the source electrode 12 in a region that includes the area directly above the surge trigger layer 26. In other words, when viewed from the Z direction, the surge trigger layer 26 is located inside the metal film 14. The metal film 14 is connected to the source electrode 12. The metal film 14 is preferably made of a metal with high conductivity and thermal conductivity, for example, copper (Cu). The metal film 14 may also be made of nickel (Ni). The metal film 14 is preferably thicker than the source electrode 12.

[0033] Viewed from the Z direction, the metal film 14 is positioned inside the source electrode 12. This prevents the metal film 14 from contacting the gate pad 13a or gate surrounding wiring 13b of the gate electrode structure 13, and also prevents the metal film 14 from reaching the edge of the semiconductor device 1 and causing malfunctions. An external terminal bonding region 14a is provided on the upper surface of the metal film 14, to which external terminals such as bonding wires or connectors are joined.

[0034] As shown in Figure 4, the shortest distance D1 between the outer edge of the surge trigger layer 26 and the outer edge of the metal film 14, as viewed from the Z direction, is greater than or equal to the shortest distance D2 between the drain layer 21 and the base layer 23 in the Z direction. That is, D1 ≥ D2. The distance D2 corresponds to the thickness of the drift layer 22 excluding portion 22a.

[0035] Next, the operation of this embodiment will be described. Figures 5(a) and (b) are schematic cross-sectional views illustrating the operation of the semiconductor device according to this embodiment.

[0036] As shown in Figures 1(a) and 3, the drain electrode 11 of the semiconductor device 1, the external terminal junction region 14a of the metal film 14, and the gate pad 13a of the gate electrode structure 13 are connected to external terminals 200 (see Figure 5(a)), respectively.

[0037] First, let's explain the normal operation of semiconductor device 1. A voltage is applied between the drain electrode 11 and the source electrode 12, with the drain electrode 11 as the positive electrode and the source electrode 12 as the negative electrode. As a result, a depletion layer (not shown) expands starting from the interface between the drift layer 22 and the base layer 23.

[0038] In this state, when a potential above the threshold is applied to the gate electrode 13d, an inversion layer (not shown) is formed in the channel portions 23c and 23d of the base layer 23, causing current to flow from the drain electrode 11 to the source electrode 12, and the semiconductor device 1 turns ON. On the other hand, when a potential below the threshold is applied to the gate electrode 13d, the inversion layer disappears, and the semiconductor device 1 turns OFF.

[0039] Next, we will explain the operation of passing surge current in the reverse direction. As shown in Figure 5(a), when the semiconductor device 1 is in the off state, a large reverse current may flow from the source electrode 12 to the drain electrode 11 due to external factors such as a system failure. In this case, the surge current often starts flowing from the region directly below the metal film 14, where the surge voltage is easily transmitted, particularly from the region directly below the external terminal junction region 14a to which the external terminal 200 is joined.

[0040] At this time, the hole current 201 is introduced into the semiconductor portion 20 from the source electrode 12 via the surge trigger layer 26 in the region directly below the external terminal 200. Then, induced by this hole current 201, an electron current 202 is introduced into the semiconductor portion 20 via the drain electrode 11 and the drain layer 21. The hole current 201 and the electron current 202 constitute a surge current.

[0041] Then, as shown in Figure 5(b), the plasma-state holes and electrons generated within the semiconductor portion 20 spread along the surge trigger layer 26, and consequently, the region through which the hole current 201 and electron current 202 flow also expands, allowing more current to flow. In this way, in the semiconductor device 1, the region through which the hole current 201 and electron current 202 flow is restricted by the surge trigger layer 26. Once the applied surge current has flowed completely, the hole current 201 and electron current 202 stop, returning to their original state.

[0042] Next, the effects of this embodiment will be described. As described above, in the semiconductor device 1 according to this embodiment, the region through which surge current flows is almost entirely limited to the region where the surge trigger layer 26 is located. The surge trigger layer 26 is located directly beneath the metal film 14. Therefore, the surge current flows mainly within the region directly beneath the metal film 14, and its flow outside of this region can be suppressed. As a result, the concentration of surge current at the edges of the metal film 14 and the region directly beneath the source electrode 12 can be suppressed. This improves the resistance of the semiconductor device 1 to surge current. In particular, by suppressing current concentration at the edges of the source electrode 12, the resistance of the semiconductor device 1 to surge current can be improved.

[0043] Furthermore, in this embodiment, as shown in Figure 4, the shortest distance D1 between the outer edge of the surge trigger layer 26 and the outer edge of the metal film 14, as viewed from the Z direction, is greater than or equal to the shortest distance D2 between the drain layer 21 and the base layer 23 in the Z direction. As a result, the electron current 202 induced by the hole current 201 that passes through the surge trigger layer 26 and the base layer 23 and flows through the drift layer 22 at an angle of 45 degrees with respect to the Z direction is also introduced from the region directly below the metal film 14, thereby more effectively suppressing the concentration of surge current at the edges of the metal film 14 and the region directly below the source electrode 12.

[0044] Furthermore, since the metal film 14 is positioned directly above the region where surge current flows in the semiconductor portion 20, heat dissipation is high. This also helps to prevent the semiconductor portion 20 from overheating and being damaged.

[0045] <Comparative Example> Figure 6(a) is a plan view showing the semiconductor device according to this comparative example, and Figure 6(b) is a cross-sectional view taken along the line D-D' shown in Figure 6(a). As shown in Figures 6(a) and (b), the semiconductor device 101 in this comparative example does not have a surge trigger layer 26.

[0046] In the semiconductor device 101, when a surge voltage is applied, a surge current begins to flow from one of the parts. The starting point of the surge current is likely to be the region directly below the metal film 14, particularly the region directly below the external terminal 200. However, as the plasma-state holes and electrons introduced into the semiconductor portion 20 diffuse along the XY plane, and as the voltage applied to the drift layer 22 and the base layer 23 increases, a surge current also begins to flow in the region outside the region directly below the metal film 14.

[0047] As a result, surge currents can flow within the semiconductor portion 20 in both the region directly beneath the metal film 14 and other regions. Meanwhile, the electron current 202 is concentrated at the external terminal 200 via the metal film 14. The hole current 201 diffuses from the metal film 14 into the semiconductor portion 20. Consequently, surge currents accumulate at the edges of the metal film 14 from the semiconductor portion 20 excluding the region directly beneath the metal film 14, causing current concentration. Therefore, current also concentrates in the portion 20a near the edges of the metal film 14 in the semiconductor portion 20, making this portion 20a susceptible to damage. Furthermore, if surge currents flow in the semiconductor portion 20 excluding the region directly beneath the metal film 14, the heat dissipation effect of the metal film 14 is low, making it prone to overheating. This also makes the semiconductor device 101 susceptible to damage near the edges of the metal film 14.

[0048] <First variation of the first embodiment> Figure 7 is a plan view showing the semiconductor portion of the semiconductor device according to this modified example. As shown in Figure 7, the semiconductor device 1a according to this modified example has a different arrangement of the surge trigger layer 26 compared to the semiconductor device 1 according to the first embodiment.

[0049] In this modified example, similar to the first embodiment, multiple surge trigger layers 26 are provided and positioned directly beneath the metal film 14. Specifically, two surge trigger layers 26 are provided on each side of the gate pad 13a in the X direction. Additionally, on the -Y direction side of the gate pad 13a, two surge trigger layers 26 are provided along approximately the entire length of the metal film 14 in the X direction. The combined length of these two surge trigger layers 26 in the X direction is longer than the combined length of the surge trigger layers 26 provided on both sides of the gate pad 13a in the X direction. Thus, in this modified example, a total of six surge trigger layers 26 are provided.

[0050] In this modified example, the length of some of the surge trigger layers 26 in the X direction is longer, which allows the area through which the surge current flows to be more widely diffused. This makes it possible to more effectively suppress the concentration of surge current in one place, which could destroy the semiconductor device 1a. The configuration, operation, and effects of this modified example other than those described above are the same as those of the first embodiment.

[0051] <Second variation of the first embodiment> Figure 8 is a plan view showing the semiconductor portion of the semiconductor device according to this modified example. As shown in Figure 8, the semiconductor device 1b according to this modified example has a different arrangement of the surge trigger layer 26 compared to the semiconductor device 1 according to the first embodiment.

[0052] In this modified example, multiple surge trigger layers 26 are arranged in a matrix along the X and Y directions. The length of each surge trigger layer 26 in the X direction is shorter than its length in the Y direction. In this modified example, the area over which surge current flows extends from one surge trigger layer 26 beyond the area where no surge trigger layer 26 is provided in the adjacent surge trigger layer 26. According to this modified example, the area over which surge current flows can be expanded isotropically along the XY plane, and the concentration of surge current can be suppressed more effectively. The configuration, operation, and effects of this modified example other than those described above are the same as in the first embodiment.

[0053] <Third Modification of the First Embodiment> Figure 9 is a plan view showing the semiconductor portion of the semiconductor device according to this modified example. As shown in Figure 9, the semiconductor device 1c according to this modified example has a different arrangement of the surge trigger layer 26 compared to the semiconductor device 1 according to the first embodiment.

[0054] In this modified example, surge trigger layers 26 are arranged on both sides in the X direction of the gate pad 13a and gate main wiring 13c of the gate electrode structure 13. Each surge trigger layer 26 has four portions 26a extending in the X direction and one portion 26b extending in the Y direction. The portion 26b extending in the Y direction is in contact with the four portions 26a extending in the X direction. Compared to the second modified example, this modified example allows for a reduction in the area of ​​the surge trigger layer 26, ensuring the area of ​​the active area that functions as a MOSFET, while expanding the range over which surge current flows isotropically along the XY plane. The configuration, operation, and effects of this modified example other than those described above are the same as those of the first embodiment.

[0055] <Fourth variation of the first embodiment> Figure 10 is a plan view showing the semiconductor portion of the semiconductor device according to this modified example. As shown in Figure 10, the semiconductor device 1d according to this modified example has a different arrangement of the surge trigger layer 26 compared to the semiconductor device 1 according to the first embodiment.

[0056] In this modified example, the multiple surge trigger layers 26 are arranged along the X direction, and each surge trigger layer 26 extends along the Y direction. That is, the length of each surge trigger layer 26 in the Y direction is longer than its length in the X direction. Also, the length of the surge trigger layer 26 located on the -Y direction side of the gate pad 13a in the Y direction is shorter than the length of the other surge trigger layers 26 in the Y direction. According to this modified example, the range over which surge current flows can be preferentially expanded along the Y direction. Depending on the characteristics required of the semiconductor device 1d, this modified example may be advantageous. The configuration, operation, and effects of this modified example other than those described above are the same as in the first embodiment.

[0057] <Fifth Modification of the First Embodiment> Figure 11 is a plan view showing the semiconductor portion of the semiconductor device according to this modified example. Figure 12 is a cross-sectional view taken along the line E-E' shown in Figure 11.

[0058] As shown in Figures 11 and 12, the semiconductor device 1e according to this modified example differs from the semiconductor device 1 according to the first embodiment in that, when viewed from above, an SBD (Schottky Barrier diode) region 27 is arranged inside the surge trigger layer 26, and gate electrodes 13d are not provided on both sides of the surge trigger layer 26 in the X direction.

[0059] In the semiconductor device 1e according to this modified example, the surge trigger layer 26 has a conductivity type n -A portion 22b of the drift layer 22 is positioned, and a metal layer 28 is provided on portion 22b. Similar to portion 22a, portion 22b is the portion of the drift layer 22 in which the base layer 23 is not positioned above. The metal layer 28 is positioned between portion 22b and the source electrode 12, is in contact with portion 22b, and is connected to the source electrode 12. The metal layer 28 is made of a material that forms a Schottky junction with portion 22b of the drift layer 22, and is, for example, made of titanium (Ti), vanadium (V), molybdenum (Mo), nickel (Ni), or compounds thereof. The portion 22b of the drift layer 22 and the metal layer 28 constitute the SBD region 27.

[0060] According to this modified example, by arranging the SBD region 27, the voltage across the PN junction in the low-current region can be reduced. This makes it possible to suppress bipolar operation during rated current operation and adjust the surge trigger region to operate only in the current range where surge current flows. In this modified example, the SBD region 27 is shown as being located inside the surge trigger layer 26 when viewed from above, but the location of the SBD region 27 is not limited to this. For example, the SBD region 27 may be located in the MOSFET region in addition to inside the surge trigger layer 26. The configuration, operation, and effects of this modified example other than those described above are the same as in the first embodiment.

[0061] <Second Embodiment> The semiconductor device according to this embodiment is a vertical semiconductor device for power control, and is, for example, a JBS (Junction Barrier Controlled Schottky) diode. Figure 13(a) is a plan view showing a semiconductor device according to this embodiment, and Figure 13(b) is a plan view showing the semiconductor portion of the semiconductor device according to this embodiment. Figure 14 is a cross-sectional view taken along the line F-F' shown in Figure 13(a).

[0062] As shown in Figures 13(a) to 14, the semiconductor device 2 according to this embodiment is provided with a cathode electrode 61 (first electrode), a semiconductor portion 70, a metal layer 62, an anode electrode 63 (second electrode), and a metal film 64. The shape of the semiconductor portion 70 is, for example, a rectangular plate.

[0063] The semiconductor portion 70 is made of a semiconductor material containing silicon (Si) and carbon (C), for example, a single crystal of silicon carbide (SiC). By introducing impurities into each part of the semiconductor portion 70, the conductivity type of each part is made p-type or n-type. The semiconductor portion 70 is provided with a cathode layer 71, a drift layer 72, an anode layer 73 (second semiconductor layer), and a surge trigger layer 74 (third semiconductor layer).

[0064] The conductivity type of the cathode layer 71 is n + It is of the type. The carrier concentration in the cathode layer 71 is, for example, 5 × 10⁻⁶. 19 cm -3 The cathode layer 71 constitutes the lower surface of the semiconductor portion 70. The cathode layer 71 is positioned on the cathode electrode 61, is in contact with the cathode electrode 61, and is therefore connected to the cathode electrode 61. The cathode electrode 61 is positioned over the entire surface of the lower surface of the semiconductor portion 70.

[0065] The conductivity type of the drift layer 72 is n - This is the type. The drift layer 72 is located on the cathode layer 71 and is in contact with the cathode layer 71. The carrier concentration of the drift layer 72 is lower than the carrier concentration of the cathode layer 71. The carrier concentration of the drift layer 72 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3 The following applies: The carrier concentration at the boundary between the cathode layer 71 and the drift layer 72 is, for example, 5 × 10⁻⁶. 17 cm -3 The first semiconductor layer is composed of a cathode layer 71 and a drift layer 72.

[0066] The conductivity type of the anode layer 73 is p-type. The anode layer 73 is located on a portion of the drift layer 72 and is in contact with the drift layer 72. Therefore, the p-type anode layer 73 and n - The interface with the drift layer 72 forms a pn junction. The anode layer 73 is divided into multiple portions 73a and multiple portions 73b. Each portion 73a and 73b extends in the X direction and is arranged spaced apart from each other along the Y direction. For example, one portion 73b is placed for every several or tens of portions 73a. The length of a portion 73b in the Y direction is longer than the length of a portion 73a in the Y direction. A portion 72a of the drift layer 72 is interposed between adjacent portions 73a and between portions 73a and portions 73b.

[0067] The conductivity type of the surge trigger layer 74 is p + This is the type. The carrier concentration in the surge trigger layer 74 is higher than the carrier concentration in the anode layer 73. The surge trigger layer 74 is located on each portion 73b of the anode layer 73, in a region away from the portion 72a of the drift layer 72. The surge trigger layer 74 is in contact with the portion 73b of the anode layer 73. Note that the surge trigger layer 74 is not located on the portion 73a of the anode layer 73.

[0068] Multiple surge trigger layers 74 are provided and are arranged in a matrix along the X and Y directions. In this embodiment, as shown in Figure 11(b), for example, eight surge trigger layers 74 are arranged in four rows along the Y direction and two columns along the X direction. Each surge trigger layer 74 extends in the X direction.

[0069] The upper surface of the semiconductor portion 70 is formed by portion 72a of the drift layer 72, portion 73a of the anode layer 73, portion 73b of the anode layer 73 in which the surge trigger layer 74 is not placed, and the surge trigger layer 74.

[0070] The metal layer 62 is positioned over the entire upper surface of the semiconductor portion 70 and is in contact with the upper surface of the semiconductor portion 70. Therefore, it is in contact with portion 72a of the drift layer 72, the anode layer 73, and the surge trigger layer 74. The metal layer 62 forms a Schottky junction with the drift layer 72. The metal layer 62 is made of, for example, titanium, vanadium, molybdenum, nickel, or compounds thereof.

[0071] The anode electrode 63 is positioned over substantially the entire upper surface of the metal layer 62 and is connected to the metal layer 62. The metal film 64 is connected to the anode electrode 63. The metal film 64 is positioned over the upper surface of the anode electrode 63, excluding the edges, and includes the area directly above the surge trigger layer 74. In other words, when viewed from the Z direction, the surge trigger layer 74 is positioned inside the metal film 64. The metal film 64 is made of a metallic material, specifically copper or nickel. The metal film 64 is preferably thicker than the anode electrode 63.

[0072] Viewed from the Z direction, the metal film 64 is positioned inside the anode electrode 63. This prevents the metal film 64 from reaching the edge of the semiconductor device 2 and causing malfunctions. An external terminal bonding region 64a is provided on the upper surface of the metal film 64, to which external terminals such as bonding wires or connectors are joined.

[0073] As described with reference to Figure 4 in the first embodiment, the shortest distance D1 between the outer edge of the surge trigger layer 74 and the outer edge of the metal film 64, as viewed from the Z direction, is greater than or equal to the shortest distance D2 between the cathode layer 71 and the anode layer 73 in the Z direction. The distance D2 corresponds to the thickness of the portion of the drift layer 72 excluding portion 72a.

[0074] Next, the operation of this embodiment will be described. First, let's explain the normal operation of semiconductor device 2. When a voltage is applied between the anode electrode 63 and the cathode electrode 61, with the anode electrode 63 as the negative electrode and the cathode electrode 61 as the positive electrode, a reverse voltage is applied to the Schottky barrier diode, which consists of a metal layer 62 and a drift layer 72. In addition, a depletion layer is formed between the anode layer 73 and the drift layer 72. Therefore, no current flows through the semiconductor device 2.

[0075] On the other hand, when a voltage is applied between the anode electrode 63 and the cathode electrode 61, with the anode electrode 63 as the positive electrode and the cathode electrode 61 as the negative electrode, a forward voltage is applied to the Schottky barrier diode consisting of the metal layer 62 and the drift layer 72, causing current to flow. Furthermore, when the forward voltage becomes higher, a forward current flows through the pn junction between the anode layer 73 and the drift layer 72.

[0076] Next, we will explain the operation of passing a forward surge current. When a forward surge voltage is applied to the semiconductor device 2 due to external factors such as system failure, a surge current flows through the semiconductor device 2. The surge current often begins to flow in the region directly beneath the metal film 64, particularly in the region directly beneath the external terminal junction region 64a to which the external terminal 200 (see Figure 5(a)) is joined.

[0077] At this time, a hole current is introduced into the semiconductor portion 70 in the region directly below the external terminal via the metal film 64, anode electrode 63, metal layer 62, and surge trigger layer 74. Then, induced by this hole current, an electron current is introduced into the semiconductor portion 70 from the cathode electrode 61 via the cathode layer 71.

[0078] Then, the plasma-like holes and electrons generated within the semiconductor portion 70 spread along the surge trigger layer 74, and consequently, the region through which the hole current and electron current flow also expands, allowing more current to flow. After the applied surge current has flowed completely, it returns to its original state.

[0079] Next, the effects of this embodiment will be described. In the semiconductor device 2 according to this embodiment, similar to the semiconductor device 1 according to the first embodiment, the region through which surge current flows is limited to the region where the surge trigger layer 74 is located. The surge trigger layer 74 is located directly beneath the metal film 64. Therefore, the surge current flows mainly within the region directly beneath the metal film 64, and its flow outside this region is suppressed. As a result, the concentration of surge current around the region directly beneath the edges of the metal film 64 is suppressed. Thus, the semiconductor device 2 has high resistance to surge current.

[0080] Furthermore, in this embodiment, the shortest distance D1 between the outer edge of the surge trigger layer 74 and the outer edge of the metal film 64, as viewed from the Z direction, is greater than or equal to the shortest distance D2 between the cathode layer 71 and the anode layer 73 in the Z direction. This makes it possible to more effectively suppress the concentration of surge current in the region directly below the edge of the metal film 64. The configuration, operation, and effects of this embodiment other than those described above are the same as in the first embodiment.

[0081] The arrangement of the surge trigger layer 74 in this embodiment is not limited to the example shown in Figure 13(b). For example, it may be any of the first to fourth modifications of the first embodiment, or any other arrangement. Furthermore, while the first embodiment shows an example where the semiconductor device is a MOSFET, and the second embodiment shows an example where the semiconductor device is a JBS diode, the semiconductor device according to the present invention is not limited to these.

[0082] According to the embodiments described above, a semiconductor device with high resistance to surge current can be realized.

[0083] Although several embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0084] The present invention includes the following embodiments.

[0085] (Note 1) First electrode and, Connected to the first electrode, a first semiconductor layer of first conductivity type containing silicon and carbon, A second semiconductor layer of a second conductivity type, which is disposed on a portion of the first semiconductor layer, is in contact with the first semiconductor layer, and contains silicon and carbon, A third semiconductor layer of first conductivity type, disposed on a first portion of the second semiconductor layer, comprising silicon and carbon, A fourth semiconductor layer is disposed on a second portion of the second semiconductor layer, contains silicon and carbon, is of a second conductivity type, and has a carrier concentration higher than that of the second semiconductor layer. A fifth semiconductor layer is disposed on the third portion of the second semiconductor layer, contains silicon and carbon, is of the second conductivity type, has a carrier concentration higher than that of the second semiconductor layer, and has a length in a second direction intersecting the first direction from the first electrode toward the first semiconductor layer that is longer than the length of the fourth semiconductor layer toward the second direction. A second electrode is positioned in the portion of the second semiconductor layer that is located between the first semiconductor layer and the third semiconductor layer, with an insulating film between them. A third electrode connected to the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, A metal film is disposed on the third electrode and in a region including the area directly above the fifth semiconductor layer, and is connected to the third electrode, A semiconductor device equipped with the following features.

[0086] (Note 2) The first semiconductor layer is A first layer disposed on the first electrode, A second layer is placed on the first layer and has a carrier concentration lower than that of the first layer, It has, The semiconductor device according to Appendix 1, wherein the shortest distance between the outer edge of the fifth semiconductor layer and the outer edge of the metal film as viewed from the first direction is greater than or equal to the shortest distance between the first layer and the second semiconductor layer in the first direction.

[0087] (Note 3) The semiconductor device according to Appendix 1 or 2, wherein a plurality of fifth semiconductor layers are provided, and the plurality of fifth semiconductor layers are spaced apart from each other.

[0088] (Note 4) The plurality of fifth semiconductor layers are arranged along the second direction in the semiconductor device described in Appendix 3.

[0089] (Note 5) The semiconductor device according to Appendix 4, wherein the plurality of fifth semiconductor layers are also arranged along a third direction intersecting planes parallel to the first and second directions.

[0090] (Note 6) The semiconductor device according to Appendix 3, wherein the plurality of fifth semiconductor layers are arranged along a third direction intersecting planes parallel to the first and second directions.

[0091] (Note 7) The fifth semiconductor layer is The portion extending in the second direction, A portion extending along a third direction intersecting planes parallel to the first and second directions, A semiconductor device as described in Appendix 1 or 2, having the following characteristics:

[0092] (Note 8) The semiconductor device according to Appendix 1 or 2, further comprising a metal layer disposed between the portion of the first semiconductor layer not above which the second semiconductor layer is not disposed and the third electrode, connected to the third electrode, and forming a Schottky junction with the first semiconductor layer.

[0093] (Note 9) First electrode and, Connected to the first electrode, a first semiconductor layer of first conductivity type containing silicon and carbon, A second semiconductor layer of a second conductivity type, which is disposed on a portion of the first semiconductor layer, is in contact with the first semiconductor layer, and contains silicon and carbon, A third semiconductor layer is disposed on a portion of the second semiconductor layer, is in contact with the second semiconductor layer, contains silicon and carbon, is of the second conductivity type, and has a carrier concentration higher than that of the second semiconductor layer. A metal layer disposed on the first semiconductor layer and forming a Schottky junction with the first semiconductor layer, A second electrode is disposed on the metal layer and connected to the metal layer, A metal film is disposed on the second electrode and in a region including the area directly above the third semiconductor layer, and is connected to the second electrode, A semiconductor device equipped with the following features.

[0094] (Note 10) The first semiconductor layer is A first layer disposed on the first electrode, A second layer is placed on the first layer and has a carrier concentration lower than that of the first layer, It has, The semiconductor device according to Appendix 9, wherein the shortest distance between the outer edge of the third semiconductor layer and the outer edge of the metal film, as viewed from the first direction, is greater than or equal to the shortest distance between the first layer and the second semiconductor layer in the first direction.

[0095] (Note 11) The metal layer is in contact with the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, as described in Appendix 9 or 10. [Explanation of Symbols]

[0096] 1, 1a, 1b, 1c, 1d, 1e, 2 Semiconductor devices 11 Drain electrode 12 Source electrodes 13. Grid gate structure 13a Gate pad 13b Gate circuit wiring 13c gate backbone wiring 13d Gel 14 Metal film 14a External terminal bonding area 20 Semiconductor part 20a part 21 Drain layer 22 Drift Layers 22a, 22b part 23 Base Layer 23a, 23b part 23c, 23d channel section 24 Source Layers 25 Base contact layer 26. Surge Trigger Layer 26a, 26b part 27 SBD area 28 Metal layer 30 insulating film 61 Cathode electrode 62 Metal layer 63 Anode electrode 64 Metal film 64a External terminal connection area 70 Semiconductor part 71 Cathode Layer 72 Drift Layers 72a part 73 Anode Layer 73a, 73b part 74 Surge Trigger Layer 101 Semiconductor Equipment 200 External terminals 201 Hole current 202 Electron current D1, D2 distance

Claims

1. First electrode and, A first semiconductor layer of a first conductivity type, comprising silicon and carbon, is connected to the first electrode. A second semiconductor layer of a second conductivity type, which is disposed on a portion of the first semiconductor layer, in contact with the first semiconductor layer, and contains silicon and carbon, A third semiconductor layer of first conductivity type, comprising silicon and carbon, is disposed on a first portion of the second semiconductor layer. A fourth semiconductor layer is disposed on a second portion of the second semiconductor layer, contains silicon and carbon, is of a second conductivity type, and has a carrier concentration higher than that of the second semiconductor layer. A fifth semiconductor layer is disposed on the third portion of the second semiconductor layer, contains silicon and carbon, is of the second conductivity type, has a carrier concentration higher than that of the second semiconductor layer, and has a length in a second direction intersecting the first direction from the first electrode toward the first semiconductor layer that is longer than the length of the fourth semiconductor layer toward the second direction, A second electrode is positioned in the portion of the second semiconductor layer that is located between the first semiconductor layer and the third semiconductor layer, with an insulating film between them. A third electrode connected to the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, A metal film is disposed on the third electrode and in a region including the area directly above the fifth semiconductor layer, and is connected to the third electrode, Equipped with, Viewed from the first direction, the fifth semiconductor layer is a semiconductor device disposed inside the third electrode.

2. The first semiconductor layer is A first layer disposed on the first electrode, A second layer is placed on the first layer and has a carrier concentration lower than that of the first layer, It has, The semiconductor device according to claim 1, wherein the shortest distance between the outer edge of the fifth semiconductor layer and the outer edge of the metal film as viewed from the first direction is greater than or equal to the shortest distance between the first layer and the second semiconductor layer in the first direction.

3. The semiconductor device according to claim 1 or 2, wherein a plurality of fifth semiconductor layers are provided, and the plurality of fifth semiconductor layers are spaced apart from each other.

4. The semiconductor device according to claim 3, wherein the plurality of fifth semiconductor layers are arranged along the second direction.

5. The semiconductor device according to claim 4, wherein the plurality of fifth semiconductor layers are also arranged along a third direction intersecting planes parallel to the first and second directions.

6. The semiconductor device according to claim 3, wherein the plurality of fifth semiconductor layers are arranged along a third direction intersecting planes parallel to the first and second directions.

7. The fifth semiconductor layer is A portion whose length in the second direction is longer than the length in the third direction that intersects the planes parallel to the first and second directions, A portion whose length in the third direction is longer than the length in the second direction, A semiconductor device according to claim 1 or 2, having the following features.

8. The present invention further comprises a metal layer disposed between the portion of the first semiconductor layer not above which the second semiconductor layer is not disposed and the third electrode, connected to the third electrode, and forming a Schottky junction with the first semiconductor layer. The semiconductor device according to claim 1 or 2, wherein, when viewed from the first direction, the metal layer is arranged inside the fifth semiconductor layer.

9. First electrode and, A first semiconductor layer of a first conductivity type, comprising silicon and carbon, is connected to the first electrode. A second semiconductor layer of a second conductivity type, which is disposed on a portion of the first semiconductor layer, in contact with the first semiconductor layer, and contains silicon and carbon, A third semiconductor layer is disposed on a portion of the second semiconductor layer, is in contact with the second semiconductor layer, contains silicon and carbon, is of a second conductivity type, and has a carrier concentration higher than that of the second semiconductor layer. A metal layer is disposed on the first semiconductor layer, forms a Schottky junction with the first semiconductor layer, and the entire upper surface of the third semiconductor layer is in contact with the metal layer, A second electrode is disposed on the metal layer and connected to the metal layer, A metal film is disposed on the second electrode and in a region including the area directly above the third semiconductor layer, and is connected to the second electrode, A semiconductor device equipped with the following features.

10. The first semiconductor layer is A first layer disposed on the first electrode, A second layer is placed on the first layer and has a carrier concentration lower than that of the first layer, It has, The semiconductor device according to claim 9, wherein the shortest distance between the outer edge of the third semiconductor layer and the outer edge of the metal film, as viewed from a first direction toward the second electrode, is greater than or equal to the shortest distance between the first layer and the second semiconductor layer in the first direction.

11. The semiconductor device according to claim 9 or 10, wherein the metal layer is in contact with the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

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