Gas inlet pipe and method for manufacturing a gas inlet pipe

Abstract

To suppress localized formation of depot membranes in a gas introduction pipe.SOLUTION: A gas introduction pipe 6 is used to introduce gas into a semiconductor processing apparatus 1. The gas introduction pipe 6 has a Si-SiC substrate 61 and CVD-SiC films 62,63. The Si-SiC substrate 61 is a tubular Si-SiC substrate with a plurality of voids 61a. The CVD-SiC films 62,63 are CVD-SiC films formed on the face of the Si-SiC substrate 61.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a gas introduction pipe for introducing gas into a semiconductor processing apparatus.

Background Art

[0002] Conventionally, heat treatment processes such as LP-CVD (low-pressure CVD) and annealing of semiconductors have been performed using a vertical semiconductor heat treatment furnace. In this vertical semiconductor heat treatment furnace, a gas introduction pipe for introducing a processing gas is provided in a processing space of a vertically arranged furnace core tube. A conventional gas introduction pipe is, for example, made of a quartz glass tube body that is excellent in purity and workability, has a substantially L shape, and has a vertical portion extending into the furnace core tube, a bent portion, and a horizontal portion disposed near the bottom of the furnace core tube.

[0003] When a deposition film is formed in the gas introduction pipe and the thickness of the deposition film becomes large with respect to the inner diameter of the gas introduction pipe, the gas supply ability by the gas introduction pipe decreases, and finally clogging occurs. Since it is difficult to suppress the generation of the deposition film itself, it is necessary to perform cleaning for removing the deposition film before clogging occurs. Patent Document 1 and Patent Document 2 describe forming a CVD-SiC film on the inner and outer surfaces of the introduction pipe in order to avoid shortening the life of the introduction pipe due to this cleaning.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] The longer the gas inlet tube, the greater the variation in the deposition rate along the axial direction of the gas inlet tube due to variations in ambient temperature. This leads to localized deposition within the gas inlet tube, making it more prone to clogging. When the gas inlet tube becomes clogged, it becomes difficult to completely remove the deposition film even with cleaning. Furthermore, even if it is not completely clogged, the gas supply capacity of the gas inlet tube decreases, posing a risk of causing abnormal wafer film thickness.

[0006] This invention was made to solve the above-mentioned problems and aims to suppress the localized formation of deposit films in gas introduction pipes. [Means for solving the problem]

[0007] The disclosed gas inlet pipe is, A gas introduction tube for introducing gas into a semiconductor processing device, Having a tubular Si-SiC substrate with multiple voids, It is.

[0008] The method for manufacturing the gas introduction pipe disclosed is: A method for manufacturing a gas introduction tube for introducing gas into a semiconductor processing apparatus, The process includes forming a tubular Si-SiC substrate having multiple voids, It is. [Effects of the Invention]

[0009] According to the present invention, it is possible to suppress the localized formation of deposit films in gas introduction pipes. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing a semiconductor processing apparatus 1, which is an example of a semiconductor processing apparatus to which the gas introduction pipe according to this embodiment can be applied. [Figure 2] This is a cross-sectional view showing a gas inlet pipe 6, which is an example of a gas inlet pipe according to this embodiment, cut by a plane passing through the axis of the gas inlet pipe 6. [Figure 3]This is a cross-sectional view showing the gas inlet pipe 6 cut by a plane perpendicular to the axis of the gas inlet pipe 6. [Figure 4] This is a cross-sectional view showing a modified example of the gas introduction pipe 6. [Modes for carrying out the invention]

[0011] Hereinafter, an example of a gas introduction tube for a semiconductor device according to this embodiment will be described with reference to the drawings.

[0012] <Configuration of semiconductor processing equipment> Figure 1 is a cross-sectional view showing a semiconductor processing apparatus 1, which is an example of a semiconductor processing apparatus to which the gas introduction tube according to this embodiment can be applied. Figure 2 is a cross-sectional view showing a gas introduction tube 6, which is an example of a gas introduction tube according to this embodiment, cut by a plane passing through the axis of the gas introduction tube 6. Figure 3 is a cross-sectional view showing a gas introduction tube 6 cut by a plane perpendicular to the axis of the gas introduction tube 6. The axis of the gas introduction tube 6 is the center line of the tubular gas introduction tube 6. Therefore, the axis of an L-shaped gas introduction tube 6 (for example, the gas introduction tube 6 in Figures 1 and 2) is L-shaped, and the axis of a straight gas introduction tube 6 (for example, the gas introduction tube 6 in Figure 4) is straight.

[0013] The vertical semiconductor processing apparatus 1 shown in Figure 1 is equipped with a cylindrical core tube 2. This core tube 2 has an opening 3 at the bottom, through which numerous semiconductor wafers W mounted on a wafer boat 4 are inserted and removed.

[0014] The reactor core tube 2 is made of quartz glass, and a processing space 5 is formed inside it. Within the processing space 5, for example, two gas introduction pipes 6 of different lengths are provided, allowing a predetermined gas (for example, silane gas) to be introduced into the processing space 5.

[0015] The gas introduction pipe 6 is a pipe having a gas inlet 6a and a gas outlet 6b, and is formed in an L shape in the example shown in FIGS. 1 and 2. That is, the gas introduction pipe 6 is composed of a horizontal portion 6h horizontally disposed in the core pipe 2, a bent portion 6c bent at about 90 degrees, and a vertical portion 6v vertically disposed in the core pipe 2.

[0016] In addition, in the semiconductor processing apparatus 1, a lifting device 10 for opening and closing the opening 3 is provided near the bottom of the core pipe 2, and a boat table 11 for supporting the wafer boat 4 is placed thereon. A heater 12 for heating the core pipe 2 is provided around the core pipe 2. An exhaust port 13 for the processing gas is provided at the top of the core pipe 2.

[0017] <Configuration of the gas introduction pipe 6> The axis A1 shown in FIGS. 2 and 3 is the axis of the gas introduction pipe 6. In the examples of FIGS. 1 to 3, since the gas introduction pipe 6 is L-shaped, the axis A1 is also L-shaped.

[0018] Further, as shown in FIG. 3, the gas introduction pipe 6 is composed of a tubular Si-SiC substrate 61 and CVD-SiC films 62 and 63. The Si-SiC substrate 61 is a substrate made of Si-SiC (silicon silicon carbide) and having a large number of voids. Si-SiC is a composite material of Si (silicon) and SiC (silicon carbide), and is formed by bonding Si and SiC at a specific ratio.

[0019] The CVD-SiC films 62 and 63 are SiC films formed by CVD (Chemical Vapor Deposition) treatment. The CVD-SiC film 62 is formed on the outer surface (outside) of the Si-SiC substrate 61. The CVD-SiC film 63 is formed on the inner surface (inside) of the Si-SiC substrate 61.

[0020] For example, the inner diameter of the Si-SiC substrate 61 is 5 to 6 mm, and the outer diameter of the Si-SiC substrate 61 is 8 to 10 mm. Further, for example, the length of the Si-SiC substrate 61 in the horizontal portion 6h is 8 to 10 cm, and the length of the Si-SiC substrate 61 in the vertical portion 6v is 40 to 120 cm.

[0021] The CVD-SiC film 62 formed on the outer surface of the Si-SiC substrate 61 has a thickness of, for example, 30 to 60 μm and is formed with a uniform thickness in the horizontal portion 6h and the vertical portion 6v.

[0022] The CVD-SiC film 63 formed on the inner surface of the Si-SiC substrate 61 has a surface roughness in the range of 20 μm ≤ Rzjis (ten-point mean roughness) ≤ 70 μm and 5 μm ≤ Ra (arithmetic mean roughness) ≤ 15 μm. By setting the roughness in this way, it is possible to improve the adhesion of the deposit film (deposited film) due to the anchoring effect while suppressing the influence on the gas flow.

[0023] To manufacture the gas introduction pipe 6 as described above, first, an L-shaped Si-SiC substrate 61 is formed. Specifically, Si-SiC powder is used to form a tube and then sintered at 1500°C. This forms a Si-SiC sintered body with numerous voids. Next, CVD-SiC films 62 and 63 are formed on the outer and inner surfaces of this Si-SiC substrate 61 by CVD treatment.

[0024] After forming CVD-SiC films 62 and 63 on the outer and inner surfaces of the Si-SiC substrate 61, the inner CVD-SiC film 63 is processed to have a predetermined surface roughness, specifically within the range of 20 μm ≤ Rzjis (ten-point mean roughness) ≤ 70 μm and 5 μm ≤ Ra (arithmetic mean roughness) ≤ 15 μm. This process can be carried out by blasting the inner surface of the tube with SiC particles of a predetermined size for a predetermined time, thereby imparting a CVD film thickness of a predetermined thickness. In this way, the gas introduction tube 6 can be manufactured.

[0025] <Heat treatment of wafers in semiconductor processing apparatus 1> In the semiconductor processing apparatus 1 configured as described above, first, a wafer boat 4 on which many semiconductor wafers W are placed is placed on a boat table 11 mounted on a lifting device 10 and then housed in a furnace tube 2 heated by a heater 12.

[0026] Then, the temperature inside the reactor core tube 2 is further increased, and for example, a process gas doped with heated boron is introduced into the reactor core tube 2 from the gas introduction tube 6. The introduced process gas deposits a silicon film onto the semiconductor wafer W, and then the process gas is exhausted from the exhaust port 13.

[0027] In this processing step, a silicon film (deposit film) generated from the processing gas is deposited on the inner and outer surfaces of the gas inlet pipe 6. However, CVD-SiC films 62 and 63 are formed on the inner and outer surfaces of the gas inlet pipe 6, and the difference between the thermal expansion coefficient of SiC and the thermal expansion coefficient of the deposited silicon film is not large. Therefore, when the gas flow velocity is not high (for example, less than 50 sccm), rupture and partial peeling of the deposited film (deposit film) caused by the difference in thermal expansion coefficients can be suppressed.

[0028] <Suppression of localized formation of deposit membranes> In the semiconductor processing apparatus 1, for example, Si-SiC is used as the substrate for peripheral components of the Si wafer processing section (e.g., core tube 2, wafer boat 4, gas inlet tube 6), which has a thermal expansion coefficient close to that of Si compared to SiC. In this case, by using Si-SiC as the substrate for the gas inlet tube 6, the thermal expansion coefficient with that of the peripheral components can be approximated, reducing the risk of damage due to expansion differences. However, since typical Si-SiC substrates are dense, when Si-SiC is used as the substrate for the gas inlet tube 6, if there is a large temperature variation in the external environment of the gas inlet tube 6, the temperature variation inside the gas inlet tube 6 with respect to the axial direction of the gas inlet tube 6 (direction along axis A1) becomes large, and a deposit film is locally generated in the gas inlet tube 6.

[0029] Therefore, a Si-SiC substrate 61 having numerous voids 61a was used as the base material for the gas introduction tube 6. This improves the thermal insulation of the gas introduction tube 6, and even if there is a large temperature variation in the external environment surrounding the gas introduction tube 6, the temperature variation inside the gas introduction tube 6 relative to the axial direction of the gas introduction tube 6 can be reduced. As a result, the localized formation of deposit films in the gas introduction tube 6 can be suppressed. This reduces the risk of abnormal wafer film thickness and also reduces the frequency of cleaning.

[0030] <Modified Example of Gas Introduction Pipe 6> FIG. 4 is a cross-sectional view showing a modified example of the gas introduction pipe 6. Similar to FIG. 2, FIG. 4 shows the gas introduction pipe 6 cut along a plane passing through the axis of the gas introduction pipe 6. As shown in FIG. 4, the gas introduction pipe 6 according to the embodiment is not limited to the L shape shown in FIG. 2 and may be linear. Further, the gas introduction pipe 6 is not limited to the L shape or the linear shape, and may be, for example, a shape bent at a plurality of locations. Which shape of the gas introduction pipe 6 is used is determined according to the structure of the semiconductor processing apparatus (for example, the semiconductor processing apparatus 1) to which the gas introduction pipe 6 is applied.

[0031] <Size of Void 61a in Si-SiC Substrate 61> The size of the void 61a in the Si-SiC substrate 61 is preferably 1 μm or more and 150 μm or less. This is because if the size of the void 61a is smaller than 1 μm, the heat insulation performance of the Si-SiC substrate 61 becomes weak, and if the size of the void 61a is larger than 150 μm, the risk of rupture of the Si-SiC substrate 61 starting from the void 61a during use increases due to expansion during heat treatment. Note that the size of the void 61a is, for example, the equivalent diameter (volume equivalent diameter or surface area equivalent diameter) of the void 61a in the Si-SiC substrate 61.

[0032] <Void Ratio of Si-SiC Substrate 61>​​​​​For example, as shown in Figure 3, let r1 be the radius of the inner surface of the Si-SiC substrate 61, and let T be the thickness of the Si-SiC substrate 61. Then, assume a cylindrical interface 61b (dashed line in Figure 3) whose distance from axis A1 is equal to r1 + T / 2. In this case, the region of the Si-SiC substrate 61 inside the interface 61b (on the side of axis A1) is defined as the inner tubular region Ri, and the region of the Si-SiC substrate 61 outside the interface 61b is defined as the outer tubular region Ro. That is, both the outer tubular region Ro and the inner tubular region Ri are tubular regions having a thickness T / 2, which is half the thickness T of the Si-SiC substrate 61.

[0034] It is preferable that the porosity of the outer tubular region Ro be 3% or more and 10% or less, and the porosity of the inner tubular region Ri of the Si-SiC substrate 61 be 0% or more and 2% or less. This is because if the porosity of one of the regions, the outer tubular region Ro or the inner tubular region Ri, is not 3% or more, the thermal insulation performance will be weak, and if the porosity of the other region, the outer tubular region Ro or the inner tubular region Ri, is not 2% or less, the necessary strength for the gas introduction pipe 6 as a semiconductor processing member cannot be secured.

[0035] Furthermore, the outer tubular region Ro tends to become hotter due to heat being received from the outside during processing, and its expansion is likely to be greater than that of the inner tubular region Ri. In contrast, by setting the porosity of the outer tubular region Ro to be greater than that of the inner tubular region Ri, the outside of the gas introduction pipe 6 becomes more easily deformable, and the stress due to deformation can be reduced.

[0036] Table 1 shows the results of evaluating the presence or absence of blockage and strength in the gas inlet pipe 6 for each combination of porosity of the outer tubular region Ro and the inner tubular region Ri. In this example, the experiment was conducted using a straight gas inlet pipe 6 with a length of 1500 mm (for example, the gas inlet pipe 6 shown in Figure 4).

[0037] [Table 1]

[0038] In Table 1, the presence or absence of clogging is indicated as "Yes" if clogging occurs in the gas inlet pipe 6 after using it a predetermined number of times, and as "No" if clogging does not occur in the gas inlet pipe 6. The predetermined number of uses is the same as the number of times the gas inlet pipe 6 becomes clogged when the porosity of the outer tubular region Ro and the inner tubular region Ri is 0%.

[0039] In Table 1, the strength is indicated as "○" if a strength of 250 MPa or higher, which is acceptable for semiconductor processing materials, was obtained, and as "×" if a strength of 250 MPa or higher was not obtained.

[0040] As shown in Table 1, clogging of the gas inlet pipe 6 can be suppressed by setting the porosity of the outer tubular region Ro to 3% or more. However, if the porosity of the inner tubular region Ri is made too high, micro-damage is more likely to occur in the inner tubular region Ri, which is the part that comes into contact with the gas, and there is a risk that micro-fragments from the inner tubular region Ri will be dispersed into the furnace. In contrast, by keeping the porosity of the inner tubular region Ri low (for example, 2% or less) and setting the porosity of the outer tubular region Ro to 3% or more, the above risks can be suppressed while also suppressing clogging of the gas inlet pipe 6.

[0041] Furthermore, as shown in Table 1, by setting the porosity of the outer tubular region Ro to 3% or more and 10% or less, and the porosity of the inner tubular region Ri to 0% or more and 2% or less, it is possible to suppress clogging of the gas introduction pipe 6 while ensuring the strength (250 MPa) required for semiconductor processing.

[0042] As described above, according to the gas introduction tube of the embodiment, by using a Si-SiC substrate having numerous voids as the substrate, even if there is a large temperature variation in the outside environment, the numerous voids in the Si-SiC substrate provide high thermal insulation, and the temperature variation inside the gas introduction tube in the axial direction of the gas introduction tube can be reduced. As a result, the localized formation of deposit films in the gas introduction tube can be suppressed. Therefore, the risk of abnormal wafer film thickness is reduced, and the frequency of cleaning can also be reduced.

[0043] Also, by setting the size of the voids in the Si-SiC substrate to be 1 μm or more and 150 μm or less, it is possible to suppress a decrease in the heat insulation performance of the Si-SiC substrate and suppress cracking of the Si-SiC substrate during use of the gas introduction tube.

[0044] Also, by setting the porosity of the outer tubular region of the Si-SiC substrate to be 3% or more and 10% or less, and the porosity of the inner tubular region of the Si-SiC substrate to be 0% or more and 2% or less, it is possible to suppress a decrease in heat insulation performance and ensure the strength required for a member for semiconductor processing. Further, by making the porosity of the outer tubular region higher than the porosity of the inner tubular region, the outer side of the Si-SiC substrate becomes more easily deformable, and the stress due to deformation can be reduced.

[0045] <Modified Example of Method for Forming Roughness of CVD-SiC Film 63> In the above embodiment, as a method for forming the roughness of the CVD-SiC film 63 on the inner surface of the gas introduction tube 6, blasting treatment was performed for a prescribed time using SiC particles of a prescribed size on the inner surface of the tube, and a CVD film thickness of a prescribed film thickness was applied. However, the method for forming the roughness of the CVD-SiC film 63 is not limited to this. For example, roughness may be formed by adhering powder of the same material as the substrate to the CVD-SiC film 63 on the inner surface of the gas introduction tube 6.

[0046] At least the following matters are described in this specification.

[0047] (1) A gas introduction tube for introducing gas into a semiconductor processing apparatus, having a tubular Si-SiC substrate having a plurality of voids, gas introduction tube.

[0048] (2) The gas introduction tube according to (1), where the size of the voids is 1 μm or more and 150 μm or less, gas introduction tube.

[0049] (3) (1) or (2) the gas introduction pipe, Of the above Si-SiC substrate, the region including the outer surface of the Si-SiC substrate is defined as the outer tubular region. If the region of the Si-SiC substrate described above that is different from the outer tubular region and includes the inner surface of the Si-SiC substrate is defined as the inner tubular region, The void ratio of the outer tubular region is 3% or more. Gas inlet pipe.

[0050] (4) (3) The gas introduction pipe described above, The porosity of the outer tubular region described above is 3% to 10%. The porosity of the inner tubular region is between 0% and 2%. Gas inlet pipe.

[0051] (5) (3) or (4) the gas introduction pipe, Each of the above-mentioned outer tubular region and the above-mentioned inner tubular region is a tubular region having a thickness of half the thickness of the Si-SiC substrate. Gas inlet pipe.

[0052] (6) A method for manufacturing a gas introduction tube for introducing gas into a semiconductor processing apparatus, The process includes forming a tubular Si-SiC substrate having multiple voids, A method for manufacturing gas inlet pipes. [Explanation of Symbols]

[0053] 1. Semiconductor processing unit 2 core tubes 3 aperture 4 wafer boats 5 Processing space 6. Gas inlet pipe 6b Gas outlet 6c Bend part 6h horizontal section 6v vertical part 10 Lifting device 11 Boat Table 12 Heaters 13 Exhaust vent 61 Si-SiC base material 61a void 61b Boundary surface 62,63 CVD-SiC film A1 axis

Claims

1. A gas introduction tube for introducing gas into a semiconductor processing device, Having a tubular Si-SiC substrate with multiple voids, The region of the Si-SiC substrate that includes the outer surface of the Si-SiC substrate is defined as the outer tubular region. If the region of the Si-SiC substrate that is different from the outer tubular region and includes the inner surface of the Si-SiC substrate is defined as the inner tubular region, The void ratio of the outer tubular region is 3% or more. Gas inlet pipe.

2. A gas introduction pipe according to claim 1, The size of the aforementioned void is between 1 μm and 150 μm. Gas inlet pipe.

3. A gas introduction pipe according to Claim 1, The void ratio of the outer tubular region is 3% or more and 10% or less. The porosity of the inner tubular region is 0% or more and 2% or less. Gas inlet pipe.

4. A gas introduction pipe according to any one of claims 1 to 3, Each of the outer tubular region and the inner tubular region is a tubular region having a thickness of half the thickness of the Si-SiC substrate. Gas inlet pipe.

5. A method for manufacturing a gas introduction tube for introducing gas into a semiconductor processing apparatus, The process includes forming a tubular Si-SiC substrate having multiple voids, The region of the Si-SiC substrate that includes the outer surface of the Si-SiC substrate is defined as the outer tubular region. If the region of the Si-SiC substrate that is different from the outer tubular region and includes the inner surface of the Si-SiC substrate is defined as the inner tubular region, The step of forming the Si-SiC substrate is a step of forming the Si-SiC substrate such that the porosity of the outer tubular region is 3% or more. A method for manufacturing gas inlet pipes.

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