Stacked component array structure

Abstract

A structure is disclosed in which an array of electronic components is disposed between two laminated printed circuit boards (600, 606). Electronic components (502) of the array may be connected to the printed circuit boards (600, 606) via solder connections. Examples of electronic components (502) include capacitors. An associated method of manufacture is disclosed that includes applying heat to a solder paste array on the printed circuit boards (600, 606) to form solid conductors electrically connected to the electronic components (502).

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims priority to U.S. Provisional Application No. 63 / 127,018, filed on December 17, 2020, entitled "STACKED PCBS PASSIVE / ACTIVE COMPONENTS ARRAY STRUCTURE", the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

[0002] The present disclosure generally relates to electronic devices, and more specifically, to passive components (such as capacitors, inductors, resistors, and combinations thereof) and / or active components (such as integrated circuit chips) in the form of arrays of electronic devices.

Background Art

[0003] Switching power supplies are generally known. One use of a switching power supply is to convert an input voltage, such as an input DC voltage, to a lower DC voltage to drive an integrated circuit (IC). A voltage regulator module (VRM) can be used to convert the voltage received from a battery or other DC source to a lower voltage for use by the IC. High power requirements for an IC, for example, exceeding 500 watts, pose problems for the VRM at relatively low voltages, for example, less than 1 volt. The VRM has to supply a relatively low DC voltage of several hundred amperes. Generally, the VRM is spatially constrained but still includes components (such as LC filters) for generating clean power at low voltage and high current.

[0004] VRMs generally require a considerable amount of capacitance to regulate their output DC voltage. It is difficult to incorporate this significant capacitance into devices with a small form factor, such as a small footprint. Conventional capacitor arrays generally require a relatively large footprint, thus limiting the footprint size of VRMs. This drawback of conventional capacitor arrays has led to similar problems in other electronic devices that have both high capacitance requirements and small footprint requirements. [Overview of the project]

[0005] Each of the technological innovations described in the claims has several aspects, and not just one of them alone embodies the desired attributes. Without limiting the scope of the claims, some notable features of this disclosure are briefly described here.

[0006] One aspect of this disclosure is a multilayer printed circuit board (PCB) electronic component array structure comprising a first PCB, a second PCB stacked with the first PCB, and an electronic component array having a plurality of electronic components disposed between the first PCB and the second PCB. The plurality of electronic components are electrically coupled to the first PCB via first solder connections. The plurality of electronic components are electrically coupled to the second PCB via second solder connections.

[0007] The first sides of multiple electronic components can be electrically coupled to both a first PCB and a second PCB, and the second sides of multiple electronic components can be electrically coupled to both a first PCB and a second PCB. The inner surface of the first PCB can be coupled to multiple electronic components of an electronic component array, and the inner surface of the second PCB can be coupled to multiple electronic components of an electronic component array. The structure may include a first ball grid array disposed on the outer surface of the first PCB, in which multiple electronic components are electrically coupled to the first ball grid array via first vias in the first PCB, and a second ball grid array disposed on the outer surface of the second PCB, in which multiple electronic components are electrically coupled to the second first ball grid array via second vias in the second PCB.

[0008] Multiple electronic components comprise multiple distinct passive elements. These distinct passive elements may comprise a first group of distinct passive elements electrically connected in series with each other, and a second group of distinct passive elements electrically connected in parallel with each other. Multiple electronic components may comprise multiple capacitors. Multiple electronic components may comprise multiple active components.

[0009] Another aspect of this disclosure is a multilayer printed circuit board (PCB) capacitor array structure comprising a lower PCB, an upper PCB, and a capacitor array having a plurality of capacitors located between the lower PCB and the upper PCB and electrically coupled to both the lower PCB and the upper PCB.

[0010] A first set of solder connections allows multiple capacitors in the capacitor array to be electrically coupled to the upper PCB, and a second set of solder connections allows multiple capacitors in the capacitor array to be electrically coupled to the lower PCB. The first sides of the multiple capacitors can be electrically coupled to both the upper and lower PCBs, and the second sides of the multiple capacitors can be electrically coupled to both the upper and lower PCBs.

[0011] The inner surface of the upper PCB can be coupled to multiple capacitors of the capacitor array, and the inner surface of the lower PCB can be coupled to multiple capacitors of the capacitor array. The structure may include a first ball grid array located on the outer surface of the upper PCB and a second ball grid array located on the outer surface of the lower PCB.

[0012] Another aspect of this disclosure is a method for assembling a multilayer printed circuit board (PCB) electronic component array. The method includes preparing a first PCB having a first solder paste array thereon, positioning a plurality of electronic components of the electronic component array relative to the first PCB such that the first solder paste array on the first PCB corresponds to the electronic component array, positioning a second PCB relative to the plurality of electronic components such that a second solder paste array on the second PCB aligns with the plurality of electronic components, and applying heat to convert the second solder paste array into a second solid conductor electrically connected to the plurality of electronic components, such that the electronic components are electrically connected to the first solid conductor on the first PCB and the second solid conductor on the second PCB after the heating is applied to convert the second solder paste array.

[0013] The method may include applying a first solder paste array to the surface of the first PCB before preparing the first PCB. The first solder paste array can also be converted to a first solid conductor by applying heat to convert the second solder paste array into a second solid conductor. The method may include applying heat to convert the first solder paste array into a first solid conductor before positioning the second PCB.

[0014] Applying heat to convert the first second paste array into a second solid conductor may include an induction press reflow process. Applying heat to convert the second solder paste array into a second solid conductor may include a laser welding process.

[0015] Multiple electronic components may include separate passive components. Separate passive components may include multiple capacitors. In the method, the electronic components of a first group of multiple electronic components can be electrically connected in series with each other. In the method, the electronic components of a second group of multiple electronic components can be electrically connected in parallel with each other.

[0016] The method allows the first side of multiple electronic components to be electrically connected to both the first PCB and the second PCB. The method also allows the second side of multiple electronic components to be electrically connected to both the first PCB and the second PCB.

[0017] Another aspect of this disclosure is a method for constructing a multilayer printed circuit board (PCB) capacitor array, the method comprising: applying a first solder paste array to the inner surface of a lower PCB; arranging a plurality of capacitors of the capacitor array on the first solder paste array such that the pattern of the first solder paste array corresponds to the capacitor array; applying a second solder paste array to the inner surface of an upper PCB; positioning the upper PCB on the capacitor array such that the second solder paste array of the upper PCB aligns with the plurality of capacitors of the capacitor array; and applying heat to convert the first and second solder paste arrays into solid conductors.

[0018] The process of applying heat to convert the first and second solder paste arrays into solid conductors may include an induction press reflow process.

[0019] Applying heat to convert the first and second solder paste arrays into solid conductors can include a laser welding process.

[0020] Another aspect of this disclosure is a method for constructing a multilayer printed circuit board (PCB) capacitor array, the method comprising: applying a first solder paste array to the inner surface of a lower PCB; arranging a plurality of capacitors of the capacitor array on the solder paste array such that the pattern of the solder paste array corresponds to the capacitor array; applying heat to convert the first solder paste array into a solid conductor; applying a second solder paste array to the inner surface of an upper PCB; arranging the upper PCB on the capacitor array such that the second solder paste array of the upper PCB aligns with the plurality of capacitors of the capacitor array; and applying heat to convert the second solder paste array into a solid conductor.

[0021] The process of applying heat to convert the first and second solder paste arrays into solid conductors may include an induction press reflow process.

[0022] Applying heat to convert the first and second solder paste arrays into solid conductors can include a laser welding process.

[0023] For the purpose of summarizing this disclosure, specific aspects, advantages, and novel features of the technological innovation are described herein. It should be understood that not all of such advantages can necessarily be achieved according to any particular embodiment. Thus, the technological innovation may be embodied or performed to achieve or optimize one or more advantages or groups of advantages as taught herein, without necessarily achieving other advantages that can be taught or suggested herein. [Brief explanation of the drawing]

[0024] [Figure 1] This is a block diagram showing a processing system including multiple multi-circuit board high-power voltage regulator modules (VRMs) configured in accordance with this disclosure.

[0025] [Figure 2] It is a block schematic diagram showing a multi-circuit board high-power source VRM according to the present disclosure.

[0026] [Figure 3A] It is a block schematic diagram showing the first capacitor circuit board of the multi-circuit board high-power source VRM in FIG. 2.

[0027] [Figure 3B] It is a block schematic diagram showing the second capacitor circuit board of the multi-circuit board high-power source VRM in FIG. 2.

[0028] [Figure 4] It is a block schematic diagram showing the cooling system components of the multi-circuit board high-power source VRM according to the present disclosure.

[0029] [Figure 5] It is a transparent perspective view of a capacitor array mutually coupled by a conductive structure according to the present disclosure.

[0030] [Figure 6] It is a partial side cross-sectional view of a stacked printed circuit board (PCB) capacitor array structure according to the present disclosure.

[0031] [Figure 7] It is a top view of an unassembled stacked PCB capacitor array structure according to the present disclosure.

[0032] [Figure 8A] It is a side cross-sectional view of a stacked PCB capacitor array structure constructed according to the present disclosure.

[0033] [Figure 8B] It is a top view of a stacked PCB capacitor array structure partially constructed according to the present disclosure.

[0034] [Figure 9A]This is a side cross-sectional view of a lower PCB on which a first solder paste array, including multiple first solder paste pads, is formed.

[0035] [Figure 9B] This is a side cross-sectional view of the lower PCB of Figure 9A during the mounting of the capacitor relating to this disclosure.

[0036] [Figure 10A] This is a flowchart showing a first embodiment for constructing a stacked PCB capacitor array structure according to this disclosure.

[0037] [Figure 10B-C] This is a side cross-sectional view of a multilayer PCB capacitor array structure under construction, consistent with Figure 10A.

[0038] [Figure 11A] This is a flowchart showing a second embodiment for constructing the stacked PCB capacitor array structure according to this disclosure.

[0039] [Figure 11B] This is a side cross-sectional view of a multilayer PCB capacitor array structure under construction, consistent with Figure 11A. [Figure 11C-D] This is a side cross-sectional view of a multilayer PCB capacitor array structure under construction, consistent with Figure 11A. [Modes for carrying out the invention]

[0040] Figure 1 is a block diagram showing a processing system including a plurality of multi-circuit board high-power voltage regulator modules (VRMs) configured according to the present disclosure. The processing system 100 in Figure 1 includes a plurality of multi-circuit board high-power sources VRMs 102A, 102B, 102C, and 102D, configured according to the present disclosure, mounted on a substrate panel 104. The plurality of multi-circuit board high-power sources VRMs 102A, 102B, 102C, and 102D are supplied by a DC power supply voltage 108, such as 40 volts, 48 ​​volts, or another relative voltage, and correspond to a plurality of integrated circuits (ICs) 106A, 106B, 106C, and 106D, respectively. The DC power supply voltage 108 can be in the range of 40 volts to 60 volts for specific applications. In some embodiments, each of the multiple multi-circuit board high-power sources VRM102A, 102B, 102C, and 102D generates an output of approximately 0.8 volts, supplying more than 600 watts of power to each of the multiple ICs 106A, 106B, 106C, and 106D. Thus, each of the multiple multi-circuit board high-power sources VRM102A, 102B, 102C, and 102D generates more than 100 amperes of current to the multiple ICs 106A, 106B, 106C, and 106D.

[0041] Each of the multiple multi-circuit board high-power sources VRM102A, 102B, 102C, and 102D generates an output of approximately 0.8 volts to each of the multiple ICs 106A, 106B, 106C, and 106D, and it is desirable that the footprint of the VRMs 102A-102D be approximately the same as the footprint of the multiple ICs 106A-106D, thus limiting the footprint of the multiple VRMs 102A-102D. In some embodiments, the footprint is approximately 3 cm x 3 cm, 4 cm x 4 cm, or other relatively small dimensions that approximate the cross-section of the multiple ICs 106A, 106B, 106C, and 106D. However, to generate power at low voltage and high power, the multiple VRMs 102A-102D generally contain a relatively large number of separate components.

[0042] Accordingly, according to this disclosure, the multiple multi-circuit board high-power sources VRM102A, 102B, 102C, and 102D include circuit boards arranged in both a plane parallel to the substrate panel 104 and a plane perpendicular to the substrate panel 104. One embodiment described with reference to Figures 2, 3A, and 3B includes two circuit boards oriented perpendicular to the substrate panel 104 and two circuit boards oriented parallel to the substrate panel 104. Thus, the VRM102A, 102B, 102C, and 102D extend above the substrate panel 104 and in a direction perpendicular to the substrate panel. One or more of the VRM102A, 102B, 102C, and 102D may include and / or be implemented in relation to any suitable principles and advantages described in reference to Figures 5 to 11D. For example, VRM102A may include a capacitor array soldered to two stacked PCBs and positioned between them.

[0043] Figure 2 is a schematic block diagram showing a multi-circuit board high-power source VRM according to the present disclosure. The multi-circuit board high-power source VRM 200 includes a first voltage rail circuit board 202A, a second voltage rail circuit board 202B, a first capacitor circuit board 216, and a second capacitor circuit board 218. These components are mounted on rails 212A and 212B, and on rails 212A and 212B that are coupled to a substrate panel 210, for example, using screws. The second capacitor board 218 can be coupled to the substrate panel 210 via solder balls which may have a pitch of 1 mm. The electrical connections formed by the substrate panel 210 couple the first rail voltage and the second rail voltage to a die 214 mounted on the opposite side of the substrate panel 210.

[0044] The first voltage rail circuit board 202A is oriented in a first plane and has a plurality of first conductors (in multiple layers) formed thereon, on which a plurality of first VRM elements 206A, a plurality of first inductors 208A coupled to the plurality of first VRM elements 206A, and a plurality of first capacitors 204A are mounted. The first voltage rail circuit board 202A is configured to receive a first voltage and generate a first rail voltage. The second voltage rail circuit board 202B is oriented in a second plane substantially parallel to the first plane and includes a plurality of second conductors (in multiple layers) formed therein, on which a plurality of second VRM elements 206B, a plurality of second inductors 208B coupled to the plurality of second VRM elements 206B, and a plurality of second capacitors 204B are mounted. The second voltage rail circuit board 202B is configured to receive a second voltage and generate a second rail voltage. The first and second voltages can be obtained from the battery pack inside the electric vehicle.

[0045] The first capacitor circuit board 216 is oriented in a third plane substantially perpendicular to the first plane, and a third plurality of conductors are formed thereon. The third plurality of capacitors are mounted on the first capacitor circuit board. The second capacitor circuit board 218 is positioned in a fourth plane substantially parallel to the third plane, and a fourth plurality of conductors are formed thereon, and a fourth plurality of capacitors are mounted thereon.

[0046] The multi-circuit board high-power source VRM200 further includes a fifth plurality of conductors 216A and 217A that connect the first voltage rail circuit board 202A to the first capacitor circuit board 216 and the second capacitor circuit board 218. The multi-circuit board high-power source VRM200 further includes a sixth plurality of conductors 216B and 217B that connect the second voltage rail circuit board 202B to the first capacitor circuit board 216 and the second capacitor circuit board 216. The illustrated high-power source VRM further includes a seventh plurality of conductors 220 and 222 that connect the first capacitor circuit board 216 to the second capacitor circuit board 218.

[0047] Figure 3A is a schematic block diagram showing the first capacitor circuit board of the multi-circuit board high-power source VRM of Figure 2. The first capacitor circuit board 216 has a third set of capacitors 302A, 304A, 302B, and 304B. Capacitors 302A and 304A are located on one side of the first capacitor circuit board 216, and capacitors 302B and 304B are located on the other side of the first capacitor circuit board 216. A fifth set of conductors 216A and 217A are connected to the connector 308 of the first capacitor circuit board 216. A sixth set of conductors 216B and 217B are connected to the connector 306 of the first capacitor circuit board 216. A seventh set of conductors 220 and 222 are connected to the connector 310 of the first capacitor circuit board 216.

[0048] Figure 3B is a schematic block diagram showing the second capacitor circuit board of the multi-circuit board high-power source VRM of Figure 2. The second capacitor circuit board 218 has a fourth set of capacitors 352A, 354A, 352B, and 354B. Capacitors 352A and 354A are located on one side of the second capacitor circuit board 218, while capacitors 352B and 354B are located on the other side. A fifth set of conductors 216A and 217A are connected to the connector 356 of the second capacitor circuit board 218. Furthermore, a sixth set of conductors 216B and 217B are connected to the connector 354 of the second capacitor circuit board 218. A seventh set of conductors 220 and 222 are connected to the connector 358 of the second capacitor circuit board 218.

[0049] Referring to both Figures 3A and 3B, the fifth set of conductors 216A and 217A are coupled to the first outer portion 312 of the first capacitor circuit board 216 and the first outer portion 362 of the second capacitor circuit board 218. Furthermore, the sixth set of conductors 216B and 217B are coupled to the second outer portion 314 of the first capacitor circuit board 216 and the second outer portion 364 of the second capacitor circuit board 218. In addition, the seventh set of conductors 220 and 222 connect the central portion 316 of the first capacitor circuit board 216 and the central portion 366 of the second capacitor circuit board 318.

[0050] Referring further to both Figures 3A and 3B, the third set of capacitors 302A, 304A, 302B, and 304B are configured to filter the low-frequency components from the mid-frequency components of the first and second rail voltages, and the fourth set of capacitors 352A and 352B are configured to filter the high-frequency components of the first and second rail voltages.

[0051] In the embodiments of Figures 2, 3A, and / or 3B, the input voltages received by the first voltage rail circuit board 202A and the second voltage rail circuit board 202B may be a 40 voltage having a 0.8-volt signal used for communication with them.

[0052] Figure 4 is a schematic block diagram showing the cooling system components of a multi-circuit board high-power source VRM according to this disclosure. The difference between Embodiment 200 in Figure 2 and Embodiment 400 in Figure 4 is the inclusion of cooling system components. The first plurality of VRM elements 206A, the first plurality of inductors 208A, the second plurality of VRM elements 206B, and the second plurality of inductors 208B generate considerable heat during their operation. Therefore, the multi-circuit board high-power source VRM includes a cooling system for cooling these components. The cooling system source / sink 402 is coupled to piping 404 to supply a flow of coolant to cool the VRM elements 206A / 206B and inductors 208A / 208B. Piping 404 may include a number of segments. Piping 404 can be directly coupled to the VRM elements 206A / 206B and inductors 208A / 208B, or thermally coupled to them by an intermediate structure. The source / sink 402 of the cooling system can accommodate a multi-circuit board high-power source VRM, as shown in Figure 1.

[0053] Figure 5 is a transparent perspective view of a capacitor array interconnected by a conductive structure according to the present disclosure. The figure in Figure 5 is a portion of a larger capacitor array including capacitors 502 extending in a plane in two dimensions, x and y. Capacitors 502 are essentially separate elements organized in the xy plane. Each capacitor 502 has a first side and a second side that are located in the xy plane. Capacitors 502 can be surface mount technology (SMT) capacitors in certain applications. Figure 5 also shows conductive strips 504, 506, 508, 510, 512, 514, 516, and 518. A first group of capacitors 520 and a second group of capacitors 522 are shown. Conductive strips 504 and 508 electrically couple the first side of the first group of capacitors 520, and conductive strips 506 and 510 electrically couple the second side of the first group of capacitors 520. Similarly, conductive strips 512 and 516 electrically couple the first sides of the second group of capacitors 522, and conductive strips 514 and 518 electrically couple the second sides of the second group of capacitors 522. Conductive strips 504-506 can hold the capacitors 502 in place in an array configuration, in addition to providing electrical connections. In other embodiments, non-conductive strips serve only to hold the capacitors 502 in place before assembling with the PCB in between, and in such cases do not function as electrical connections.

[0054] Figure 6 is a side cross-sectional view of a portion of a multilayer printed circuit board (PCB) capacitor array structure according to the present disclosure. The cross-section in Figure 6 shows a single capacitor 502 sandwiched between an upper PCB 600 and a lower PCB 606. PCBs 606 and 600 may be referred to as the first PCB and the second PCB. PCBs 606 and 600 can mount PCBs associated with a VRM. For example, PCBs 606 and 600 can be mounted in place of capacitor circuit boards 216 and 218 in Figure 2 in certain applications. Capacitor 502 has a first side surface 614 that is electrically coupled to the upper PCB 600 via a conductive strip 504 and to the lower PCB 606 via a conductive strip 508. Capacitor 502 has a second side surface 616 that is electrically coupled to the upper PCB 600 via a conductive strip 506 and to the lower PCB 606 via a conductive strip 510. The upper PCB 600 includes vias 604 and 605 connecting the first side 614 and the second side 616 of the capacitor 502 to the ball grid array 610 and / or other components. The lower PCB 606 includes vias 608 and 609 connecting the first side 614 and the second side 616 of the capacitor 502 to the ball grid array 612 and / or other components.

[0055] Figure 7 is a top view of an unassembled multilayer PCB capacitor array structure according to the present disclosure. The multilayer PCB capacitor array structure includes a lower PCB 600, an upper PCB 606, and a capacitor array located between the lower PCB 600 and the upper PCB 606, having a plurality of capacitors 502 that are electrically coupled to both the upper PCB 600 and the lower PCB 606 when construction is complete. The multilayer PCB capacitor array structure includes a first plurality of solder connections that electrically couple the plurality of capacitors of the capacitor array to the upper PCB, and a second plurality of solder connections that electrically couple the plurality of capacitors of the capacitor array to the lower PCB. Before assembly / construction, the first plurality of solder connections is an array of first solder paste pads 602, and the second plurality of solder connections is an array of second solder paste pads 608.

[0056] Figure 8A is a side cross-sectional view of a multilayer PCB capacitor array structure constructed according to this disclosure. Figure 8B is a top view of a multilayer PCB capacitor array structure partially constructed according to this disclosure. Referring to both Figures 8A and 8B, the plurality of capacitors 502 are electrically coupled to both the upper PCB 600 via a first plurality of solder connections 602 and to the lower PCB 606 via a second plurality of solder connections 608. Ball grid arrays 610 and 612 provide electrical connection paths to the multilayer PCB capacitor array. As shown in Figure 8A, the first sides of the plurality of capacitors 502 are electrically coupled to both the upper PCB 600 and the lower PCB 606, and the second sides of the plurality of capacitors 502 are electrically coupled to both the upper PCB 600 and the lower PCB 606. Furthermore, as shown in Figure 8A, the inner surface of the upper PCB 606 is coupled to the plurality of capacitors 502 of the capacitor array, and the inner surface of the lower PCB 606 is coupled to the plurality of capacitors 502 of the capacitor array. In the structures shown in Figures 8A and 8B, the capacitor 502 includes a first group of capacitors connected in series with each other and a second group of capacitors connected in series with each other.

[0057] Figure 9A is a side cross-sectional view of a lower PCB 606 on which a first solder paste array, comprising a plurality of first solder paste pads 608, is formed. In some embodiments, a double solder mask (or higher-order solder mask) can be used to compensate for the different thicknesses of the capacitors in the capacitor array. As is understood, the capacitor array has a number of capacitors, and in some embodiments, it has capacitors of different sizes and values. Therefore, if different capacitors in the capacitor array have different thicknesses, solder paste pads 608 of different thicknesses can be used. The same structure may be used with the upper PCB 600, but different to reflect the different configuration of the capacitor array from the upper side.

[0058] Figure 9B is a side cross-sectional view of the lower PCB of Figure 9A during the mounting of the capacitors according to the present disclosure. Using a robot, the capacitors 502 of the capacitor array can be placed on the first solder paste array using XYZ position and vision. At this point, during construction, the capacitors 502 are placed on the first solder paste array but are not melted into it. Therefore, there must be sufficient friction between the solder paste pads 608 and the capacitors 502 to prevent relative movement between them during construction.

[0059] Figure 10A is a flowchart showing a first embodiment for constructing a multilayer PCB capacitor array structure according to the present disclosure. Figures 10B and 10C are side cross-sectional views of the multilayer PCB capacitor array structure under construction, consistent with Figure 10A. Referring together to Figures 10A, 10B, and 10C, Method 1000 for constructing a multilayer PCB capacitor array includes applying a first solder paste array having a plurality of first solder paste pads 608 to the inner surface of a lower PCB 606 (Step 1002). Method 1000 is followed by applying a second solder paste array having a plurality of second solder paste pads to the inner surface of an upper PCB 600 (Step 1004). Method 1000 is followed by placing a plurality of capacitors 502 of the capacitor array onto the first solder paste array of the lower PCB 606, such that the pattern of the first solder paste array corresponds to the capacitor array (Step 1006). Method 1000 proceeds to position the upper PCB 600 on the capacitor array such that the second solder paste array on the upper PCB 600 aligns with the capacitors of the capacitor array (step 1010). Method 1000 proceeds to apply heat to convert the first and second solder paste arrays into solid conductors 1014 and 1016, respectively (step 1012). The first solder paste array on the upper PCB 600 can be converted into a solid conductor using an induction press reflow process or laser welding to bond the capacitor array to the upper PCB 600, and the second solder paste on the lower PCB 606 can be converted into a solid conductor to bond the capacitor array to the lower PCB 606.

[0060] Figure 11A is a flowchart showing a second embodiment for constructing a multilayer PCB capacitor array structure according to the present disclosure. Figures 11B, 11C, and 11D are side cross-sectional views of the multilayer PCB capacitor array structure under construction, consistent with Figure 11A. Referring to all of Figures 11A, 11B, 11C, and 11D, the method 1100 for constructing a multilayer PCB capacitor array includes applying a first solder paste array having a plurality of first solder paste pads 608 to the inner surface of a lower PCB 606 (step 1102). The method 1100 is followed by applying a second solder paste array having a plurality of second solder paste pads to the inner surface of an upper PCB 600 (step 1104). The method 1100 is followed by placing a plurality of capacitors 502 of the capacitor array onto the first solder paste array of the lower PCB 606, such that the pattern of the first solder paste array corresponds to the capacitor array (step 1006). Method 1100 continues by applying heat to convert the first solder paste array into a solid conductor 1114 (step 1008). Method 1100 continues by positioning the upper PCB 600 on the capacitor array so that the second solder paste array on the upper PCB 600 aligns with the capacitors of the capacitor array (step 1010). Method 1100 continues by applying heat to convert the second solder paste array into a solid conductor 1116 (step 1012). The solder paste on the upper PCB 600 can be converted into a solid conductor using an induction press reflow process or laser welding to bond the capacitor array to the upper PCB 600, and the solder paste on the lower PCB 606 can be converted into a solid conductor to bond the capacitor array to the lower PCB 606. Note that the solid conductor 1114 undergoes two reflow processes in step 1012.

[0061] The description and figures herein may relate to components located between an upper PCB and a lower PCB, which are separate capacitors, but these components may be different (passive and / or active) components. For example, the components may be an array of separate inductors, or an array of both separate inductors and separate capacitors. Furthermore, these components may be in a package containing package components, such as multiple capacitors, multiple inductors, a combination of capacitors and inductors, or a combination of capacitors, inductors, and resistors. In some applications, the electronic components may include active components such as integrated circuit chips. Such integrated circuit chips may include transistors. Any suitable electronic components can be placed between PCBs according to any suitable principles and advantages disclosed herein. For example, any suitable combination of features described with reference to Figures 5 to 11D can be implemented in relation to any suitable electronic components instead of separate capacitors. The embodiments disclosed herein may relate to capacitors placed between two PCBs, but any suitable principles and advantages disclosed herein can be applied to arrays of electronic components placed between various groups of two PCBs from a stack of three or more PCBs.

[0062] The systems and methods described above are explained in general terms to help understand the details of the preferred embodiments of this disclosure. Other preferred embodiments of this disclosure include the described applications for electric vehicles. The description herein provides numerous specific details, such as examples of components and / or methods, to give a full understanding of the embodiments disclosed herein. However, as those skilled in the art will see, embodiments can be carried out without one or more of the specific details, or with other devices, systems, assemblies, methods, components, materials, parts, etc. In other examples, well-known structures, materials, or operations are not specifically shown or described in detail so as not to obscure the aspects of the embodiments disclosed herein.

[0063] Throughout this specification, any reference to “one embodiment,” “one embodiment,” or “a particular embodiment” means that a particular feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment of this disclosure, but not necessarily in all embodiments. Therefore, each occurrence of the phrase “in one embodiment,” “in one embodiment,” or “in a particular embodiment” in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, any particular feature, structure, or characteristic of any particular embodiment of this disclosure may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of this disclosure described and illustrated herein are possible in light of the teachings herein and should be considered part of the spirit and scope of this disclosure.

[0064] Furthermore, it can be seen that one or more elements depicted in a drawing / figure can be implemented in a more separated or integrated manner to be useful for a specific purpose, or even removed or rendered in a non-functional manner in certain cases.

[0065] Furthermore, any signal arrows in drawings / figures should be considered merely illustrative and not restrictive unless otherwise specifically mentioned. Moreover, the term “or” as used herein is intended to generally mean “and / or” unless otherwise suggested. Combinations of components or steps are also considered to be mentioned, and it is anticipated that the terminology may be unclear in giving the ability to separate or combine.

[0066] As used throughout this specification and the following claims, “one (a),” “one (a),” and “the” refer to multiple objects unless the context otherwise explicitly indicates. Furthermore, as used throughout this specification and the following claims, “in” refers to both “in” and “on” unless the context otherwise explicitly indicates.

[0067] The foregoing description of the illustrated embodiments of this disclosure, including those described in the abstract, is not intended to be exhaustive or to limit the invention to the exact forms disclosed herein. Specific embodiments and examples of the technological innovations are described herein for illustrative purposes only, but various equivalent modifications are possible within the spirit and scope of this disclosure, as will be recognized and understood by those skilled in the art. As suggested, these modifications may be made to the embodiments disclosed in light of the foregoing description of the illustrated embodiments and should be included within the spirit and scope of this disclosure.

[0068] Therefore, although the present disclosure has been described herein in relation to its specific embodiments, a range of modifications, various changes and substitutions are intended in the aforementioned disclosure, and it can be understood that, in some cases, certain features of the embodiments may be adopted without departing from the scope and spirit of the described disclosure and without corresponding use of other features. Thus, many modifications can be made to adapt a particular situation or material to the essential scope and spirit of the present disclosure. The present disclosure is not limited to the specific terms used in the following claims and / or the specific embodiments disclosed as the best mode intended to carry out the invention, and the invention is intended to include all embodiments and equivalents that fall within the scope of the appended claims. Therefore, the scope of the invention should be determined by the appended claims.

Claims

1. A multilayer printed circuit board (PCB) electronic component array structure, The first PCB and A second PCB, which is stacked with the first PCB, An electronic component array comprising a plurality of electronic components disposed between the first PCB and the second PCB, wherein the plurality of electronic components are electrically coupled to the first PCB via a first solder connection and electrically coupled to the second PCB via a second solder connection, Equipped with, One of the first solder connections electrically connects a group of electronic components from the plurality of electronic components to the first PCB, and One of the second solder connections is a stacked PCB electronic component array structure that electrically connects a group of electronic components from the plurality of electronic components to the second PCB.

2. The first side surfaces of the plurality of electronic components are electrically coupled to both the first PCB and the second PCB. The laminated PCB electronic component array structure according to claim 1, wherein the second sides of the plurality of electronic components are electrically coupled to both the first PCB and the second PCB.

3. The inner surface of the first PCB is bonded to the plurality of electronic components of the electronic component array, The laminated PCB electronic component array structure according to claim 2, wherein the inner surface of the second PCB is bonded to the plurality of electronic components of the electronic component array.

4. A first ball grid array disposed on the outer surface of the first PCB, wherein the plurality of electronic components are electrically coupled to the first ball grid array via first vias in the first PCB, The laminated PCB electronic component array structure according to claim 2, further comprising: a second ball grid array disposed on the outer surface of the second PCB, wherein the plurality of electronic components are electrically coupled to the second ball grid array via second vias in the second PCB.

5. The laminated PCB electronic component array structure according to claim 1, wherein the plurality of electronic components comprises a plurality of separate passive elements.

6. The laminated PCB electronic component array structure according to claim 5, wherein the plurality of separate passive elements comprises a first group of separate passive elements electrically connected in series with each other, and a second group of separate passive elements electrically connected in parallel with each other.

7. The stacked PCB electronic component array structure according to claim 1, wherein the plurality of electronic components comprises a plurality of capacitors.

8. The stacked PCB electronic component array structure according to claim 1, wherein the plurality of electronic components comprises a plurality of active components.

9. A method for assembling a multilayer printed circuit board (PCB) electronic component array, The steps include preparing a first PCB having a first solder paste array thereon, A step of positioning a plurality of electronic components of an electronic component array relative to a first PCB, wherein the first solder paste array on the first PCB corresponds to the electronic component array. The steps include positioning the second PCB relative to the plurality of electronic components such that the second solder paste array on the second PCB aligns with the plurality of electronic components, A step of applying heat to the second solder paste array to convert it into a second solid conductor electrically connected to the plurality of electronic components, wherein the electronic components are electrically connected to the first solid conductor on the first PCB and the second solid conductor on the second PCB after the second solder paste array has been heated to convert it. Includes, One of the first solid conductors electrically connects a group of electronic components from the plurality of electronic components to the first PCB, and A method for electrically connecting a group of electronic components from the plurality of electronic components to the second PCB, wherein one of the second solid conductors is the second solid conductor.

10. The method according to claim 9, further comprising the step of applying the first solder paste array onto the surface of the first PCB before preparing the first PCB.

11. The method according to claim 9, wherein the step of applying heat to convert the second solder paste array into a second solid conductor also converts the first solder paste array into a first solid conductor.

12. The method according to claim 9, further comprising the step of heating the first solder paste array to convert it into a first solid conductor before the step of positioning the second PCB.

13. The method according to claim 9, wherein the step of applying heat to convert the second paste array into a second solid conductor comprises an induction press reflow process.

14. The method according to claim 9, wherein the step of applying heat to convert the second solder paste array into a second solid conductor includes a laser welding process.

15. The method according to claim 9, wherein the plurality of electronic components each comprise a separate passive component.

16. The method according to claim 9, wherein the plurality of electronic components comprises a plurality of capacitors.

17. The method according to claim 9, wherein the electronic components of the first group of the plurality of electronic components are electrically connected in series with each other.

18. The method according to claim 17, wherein the electronic components of the second group of the plurality of electronic components are electrically connected in parallel with one another.

19. The method according to claim 9, wherein the first side surfaces of the plurality of electronic components are electrically connected to both the first PCB and the second PCB.

20. The method according to claim 19, wherein the second sides of the plurality of electronic components are electrically connected to both the first PCB and the second PCB.

Images