Global sensing current generation circuit and a device containing the same

Abstract

To improve luminance degradation due to accumulation of usage time of a display device.SOLUTION: There are provided a global sensing current generating circuit which senses a global current in a display region and a display device which compensates for fluctuation in the global current based on a current value of the sensed global current. The global sensing current generating circuit includes a plurality of sensing current generating circuits. The sensing current generating circuit includes: a driving transistor configured to generate the sensing current based on its gate-source voltage; a capacitor configured to charge the gate-source voltage of the driving transistor; and a plurality of switch transistors electrically connected to the driving transistor and the capacitor and configured to sample a threshold voltage of the driving transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0007]

[0001] This embodiment relates to a global sensing current generation circuit and a display device including the same.

Background Art

[0002] The drive circuit of a display device includes a data drive circuit that supplies a data voltage to a data line, a gate drive circuit that supplies a scan signal (or a gate signal) to a gate line (or a scan line), and the like. The gate drive circuit can be directly formed on the same substrate together with the circuit elements of the pixel array that constitutes the screen.

[0003] The circuit elements of the pixel array constitute pixel circuits formed in each pixel defined in a matrix form by the data lines and gate lines of the pixel array.

[0004] Here, each of the circuit elements of the pixel array includes a plurality of transistors. In other words, a plurality of transistors are included in one pixel circuit.

[0005] Generally, as the drive time of the display device accumulates, electrical characteristics such as the threshold voltage of the transistors change.

[0006] When the electrical characteristics of the transistors change, the global current, which is the total current flowing through the pixel array, fluctuates, and thereby the luminance of the display device may decrease.

Summary of the Invention

Problems to be Solved by the Invention

[0007] The present invention provides a global sensing current generation circuit that senses the global current in a display area and a display device that compensates for fluctuations in the global current based on the sensed current value of the global current.

[0008] [[ID=The problems that this embodiment aims to solve are not limited to those mentioned above, and other problems not mentioned here will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] One aspect of the present invention provides a global sensing current generation circuit that includes a plurality of sensing current generation circuits; and a single current sensing line connected to the plurality of sensing current generation circuits, through which sensing currents generated from each of the plurality of sensing current generation circuits during a current sensing period flows, wherein the sensing current generation circuit includes a drive transistor that generates the sensing current by a gate-source voltage; a capacitor that charges the gate-source voltage of the drive transistor; and a plurality of switch transistors that are electrically connected to the drive transistor and the capacitor and sample the threshold voltage of the drive transistor.

[0010] Another aspect of the present invention provides a display device including: a plurality of sensing current generation circuits arranged adjacent to one side of a display area; a single current sensing line connected to the plurality of sensing current generation circuits, through which sensing currents generated from each of the plurality of sensing current generation circuits during a current sensing period flow; and an integrated circuit including a current summing circuit that receives sensing currents generated by the plurality of sensing current generation circuits through the single current sensing line during the current sensing period and outputs a global current sensing value obtained by summing the current values ​​of the sensing currents; and a timing controller that receives the global current sensing value output by the current summing circuit, uses the global current sensing value to check the amount of global current fluctuation in the display area, and compensates for the amount of global current fluctuation.

[0011] As explained above, according to this embodiment, the display device senses the global current flowing through the pixel array and compensates for fluctuations in the global current using the sensed global current value, thereby improving the decrease in brightness due to the cumulative usage time of the display device.

[0012] The diverse yet beneficial advantages and effects of the embodiments are not limited to those described above and will become more readily apparent as we explain the specific embodiments of the examples. [Brief explanation of the drawing]

[0013] [Figure 1] A block diagram showing a display device according to one embodiment of the present invention. [Figure 2] A block diagram showing a display device according to one embodiment of the present invention. [Figure 3] This is a diagram illustrating the configuration of a gate drive circuit according to one embodiment of the present invention. [Figure 4] This is a cross-sectional view showing the stacked configuration of a display device according to one embodiment of the present invention. [Figure 5] This is a drawing illustrating the arrangement of a sensing area according to one embodiment of the present invention. [Figure 6] This is a drawing illustrating the arrangement of a sensing area according to one embodiment of the present invention. [Figure 7] This is a diagram illustrating a typical pixel circuit. [Figure 8] This figure illustrates a sensing current generation circuit according to one embodiment of the present invention. [Figure 9] This is a diagram illustrating the driving method of a global sensing current generation circuit according to one embodiment of the present invention. [Figure 10] This diagram illustrates the fluctuation in global current due to the cumulative use of a display device. [Figure 11] This diagram illustrates the fluctuation in global current due to the cumulative use of a display device. [Figure 12]A drawing for explaining a method of compensating for fluctuations in global current in a display device according to an embodiment of the present invention. [Figure 13] A drawing exemplarily showing a look-up table stored in a display device according to an embodiment of the present invention. [Figure 14] A drawing showing waveforms of a scan signal and an EM signal generated for driving a sensing current generation circuit. [Figure 15] A circuit diagram stepwise showing the operation of a sensing current generation circuit during the driving period of the sensing current generation circuit. [Figure 16] A circuit diagram stepwise showing the operation of a sensing current generation circuit during the driving period of the sensing current generation circuit. [Figure 17] A circuit diagram stepwise showing the operation of a sensing current generation circuit during the driving period of the sensing current generation circuit. [Figure 18] A circuit diagram stepwise showing the operation of a sensing current generation circuit during the driving period of the sensing current generation circuit. [Figure 19] A circuit diagram stepwise showing the operation of a sensing current generation circuit during the driving period of the sensing current generation circuit. [Figure 20] A block diagram showing a global sensing current generation circuit according to another embodiment of the present invention. [Figure 21] A drawing exemplarily showing a sensing current generation circuit according to another embodiment of the present invention. [Figure 22] A drawing exemplarily showing a sensing current generation circuit according to another embodiment of the present invention. [Figure 23] A drawing for explaining a driving method of a global sensing current generation circuit according to another embodiment of the present invention. [Figure 24] A block diagram showing a global sensing current generation circuit according to still another embodiment of the present invention. [Figure 25] A drawing exemplarily showing a sensing current generation circuit according to still another embodiment of the present invention.

Mode for Carrying Out the Invention

[0014] The advantages and features of the present invention, and how they are achieved, will become clearer with reference to the examples described below in detail with the accompanying drawings. The present invention is not limited to the examples disclosed below and can be embodied in a variety of different forms, however the examples are provided to complete the disclosure of the present invention and to inform those who are ordinary skill in the art to which the invention pertains, of the full scope of the invention, and the present invention is defined only by the scope of the claims.

[0015] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the drawings illustrating embodiments of the present invention are illustrative only, and the present invention is not limited to those shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. Furthermore, in describing the present invention, if it is determined that a specific explanation of related prior art may unnecessarily obscure the gist of the present invention, such detailed explanation will be omitted.

[0016] When words such as "equipped with," "include," "possess," and "consist of" are used in this invention, other parts may be added unless "only" is used. When a component is expressed singularly, it can be interpreted as plural unless otherwise explicitly stated.

[0017] In interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0018] When describing spatial relationships, for example, when describing the spatial relationship and mutual connection between two components using phrases such as "above," "above," "below," "next to," "connect or couple," or "crossing" or "intersecting," one or more other components may be interposed between those components unless there is a specific mention such as "immediately" or "directly."

[0019] While terms such as "first," "second," etc., may be used to distinguish components, the function and structure of these components are not limited by the ordinal numbers preceding them or by their names. Since the claims primarily describe essential components, the ordinal numbers preceding the component names in the claims do not necessarily have to match those preceding the component names in the embodiments.

[0020] The following embodiments can be partially or entirely combined or linked with one another, allowing for a variety of technically diverse interconnections and drives. Each embodiment may be implemented independently of the others, or they may be implemented together in relation to one another.

[0021] In the display device of the present invention, the display panel driving circuit, pixel circuit, level shifter, etc., may include transistors. Transistors can be embodied as oxide thin-film transistors containing oxide semiconductors, polycrystalline thin-film transistors containing low-temperature polysilicon (LTPS), etc.

[0022] A transistor is a three-terminal device consisting of a gate, source, and drain. The source is the terminal that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the terminal through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In the case of an N-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an N-channel transistor, the direction of current is from the drain to the source. In the case of a P-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. Note that the source and drain of a transistor are not fixed. For example, the source and drain can be changed by the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first terminal and the second terminal.

[0023] The scan signal swings between the gate-on voltage and the gate-off voltage. The gate-off voltage can be interpreted as the first voltage, and the gate-on voltage as the second voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. For an N-channel transistor, the gate-on voltage can be the gate high voltage (VGH), and the gate-off voltage can be the gate low voltage (VGL). For a P-channel transistor, the gate-on voltage can be the gate low voltage (VGL), and the gate-off voltage can be the gate high voltage (VGH).

[0024] The present invention is applicable to any planar display device that requires an integrated circuit and a power supply circuit to drive pixel circuits, such as an Organic Light Emitting Display (OLED Display).

[0025] Various embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0026] Figures 1 and 2 are block diagrams showing a display device according to one embodiment of the present invention.

[0027] Referring to Figures 1 and 2, the display device according to one embodiment includes a display panel 100 and a display panel driving circuit.

[0028] The display area AA of the display panel 100 includes a pixel array for displaying images. Data voltages corresponding to image data are input to the pixel circuits P of the pixel array. The pixel array includes data lines DL, a number of gate lines GL that intersect with the data lines DL, and pixel circuits P arranged in a matrix configuration. The display panel 100 may further include power lines commonly connected to the pixel circuits P. Here, the power lines may include a low-voltage power line LVL that supplies a low-voltage power supply ELVSS, and a high-voltage power line (not shown) that supplies a high-voltage power supply ELVDD.

[0029] When the resolution of a pixel array is n (where n is a natural number) × m (where m is a natural number), the pixel array contains n pixel columns and m pixel lines that intersect the pixel columns. Each pixel line contains a pixel circuit P arranged along a first direction X. Each pixel column contains a pixel circuit P arranged along a second direction Y. Generally, one horizontal period 1H can be the time obtained by dividing one frame period by the number of pixel lines, which is m. A data voltage can be input to the pixel circuit P of one pixel line during one horizontal period 1H.

[0030] A pixel circuit P can be divided into two or more subpixel circuits to realize color. For example, three pixel circuits arranged sequentially in a first direction X can be divided into a red subpixel circuit, a green subpixel circuit, and a blue subpixel circuit.

[0031] Alternatively, the four pixel circuits arranged sequentially in the first direction X may be divided into a red subpixel circuit, a green subpixel circuit, a blue subpixel circuit, and a white subpixel circuit.

[0032] The pixel circuit P described above is connected to the data line DL and the gate line GL. In one embodiment, when the display device is an organic light-emitting display device, the pixel circuit P is as shown in Figure 7.

[0033] Referring to Figure 7, the pixel circuit P may include a light-emitting element EL, a drive transistor DT that generates a drive current by its gate-source voltage and supplies the drive current to the light-emitting element EL, a capacitor Cst connected between a node on a power line supplied with a high-voltage power supply ELVDD and a second node n2, which charges the gate-source voltage of the drive transistor DT, a number of switch transistors (e.g., ST1, ST2) electrically connected to the drive transistor DT and capacitor Cst to sample the threshold voltage of the drive transistor DT, and other remaining switch transistors for driving the pixels. In the drawings of the present invention, the pixel circuit P is shown as consisting of eight transistors and one capacitor, but the present invention is not limited thereto. In other words, the pixel circuit P may include three or more transistors and one or more capacitors.

[0034] In Figure 7, the light-emitting element (EL) can be embodied in an OLED that includes an organic compound layer formed between the anode and cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode terminals of the OLED, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) are moved to the emission layer (EML) to form excitons, and visible light is emitted from the emission layer (EML). An OLED used as a light-emitting element may have a tandem structure in which multiple emission layers are stacked. Tandem OLED structures can improve the brightness and lifespan of pixels.

[0035] On the other hand, the display panel 100 may further include a touch sensor. Here, the touch sensor may be on-cell type or add-on type and placed on the screen of the display panel 100.

[0036] Furthermore, the touch sensor may be implemented as an in-cell type embedded in the pixel array.

[0037] In this invention, the display panel drive circuit writes video data to the pixel circuit P of the display panel 100 under the control of the timing controller 130. Such a display panel drive circuit may include a data drive circuit 110, a gate drive circuit 120, a timing controller 130 for controlling the operating timing of the drive circuits 110 and 120, and a level shifter 140 connected between the timing controller 130 and the gate drive circuit 120. The display panel drive circuit may further include a power supply unit (not shown) that outputs a low-voltage power supply ELVSS, a high-voltage power supply ELVDD, etc. Here, the level shifter 140 may be included in the timing controller 130.

[0038] The data drive circuit 110 converts the video data received as a digital signal from the timing controller 130 into an analog gamma-compensated voltage for each frame and outputs a data voltage. The data voltage output from the data drive circuit 110 is supplied to the corresponding data line. The data drive circuit 110 outputs the data voltage using a digital-to-analog converter that converts the digital signal into an analog gamma-compensated voltage.

[0039] Such a data driving circuit 110 can be integrated into a Source Driver Integrated Circuit (SDIC). The Source Driver IC can be connected to the bonding pad of the display panel 100 using either tape automated bonding (TAB) or chip-on-glass (COG) technology. Alternatively, the Source Driver IC may be implemented using a chip-on-film (COF) method.

[0040] If the display panel 100 further includes a touch sensor, the source driver IC may incorporate a touch sensor driver circuit for driving the touch sensor.

[0041] The gate drive circuit 120 may be formed in a non-display area (e.g., the bezel area) of the display panel 100 where no image is displayed, or at least a portion of it may be located in the display area AA. The gate drive circuit 120 receives a clock signal input from the level shifter 140 and outputs a scan signal to the gate line GL.

[0042] The switch transistor of the pixel circuit P connected to the gate line GL can be turned on in response to the gate-on voltage of the scan signal and turned off in response to the gate-off voltage.

[0043] Such a gate drive circuit 120 may include a configuration as shown in Figure 3.

[0044] Referring to Figure 3, the gate drive circuit 120 includes a light emission control signal drive circuit 310 and a scan drive circuit 320. The scan drive circuit 320 may consist of first to fourth scan drive circuits 321, 322, 323, and 324. The second scan drive circuit 322 may consist of odd-numbered second scan drive circuits 322_O and even-numbered second scan drive circuits 322_E.

[0045] The gate drive circuit 120 may have shift registers configured symmetrically on both sides of the display area AA. Furthermore, the gate drive circuit 120 may be configured such that the shift register on one side of the display area AA includes the second scan drive circuits 322_O, 322_E, the fourth scan drive circuit 324, and the light emission control signal drive circuit 310, while the shift register on the other side of the display area AA includes the first scan drive circuit 321, the second scan drive circuits 322_O, 322_E, and the third scan drive circuit 323. However, it is not limited to this configuration, and the light emission control signal drive circuit 310 and the first to fourth scan drive circuits 321, 322, 323, and 324 may be arranged differently depending on the embodiment.

[0046] Each of the shift register stages STG1 to STGn can contain the first scan signal generation circuits SC1(1) to SC1(n), the second scan signal generation circuits SC2_O(1) to SC2_O(n), SC2_E(1) to SC2_E(n), the third scan signal generation circuits SC3(1) to SC3(n), the fourth scan signal generation circuits SC4(1) to SC4(n), and the light emission control signal generation circuits EM(1) to EM(n), respectively.

[0047] The first scan signal generation circuits SC1(1) to SC1(n) output the first scan signals SC1(1) to SC1(n) through the first gate line of the display panel 100. The second scan signal generation circuits SC2(1) to SC2(n) output the second scan signals SC2(1) to SC2(n) through the second gate line of the display panel 100. The third scan signal generation circuits SC3(1) to SC3(n) output the third scan signals SC3(1) to SC3(n) through the third gate line of the display panel 100. The fourth scan signal generation circuits SC4(1) to SC4(n) output the fourth scan signals SC4(1) to SC4(n) through the fourth gate line of the display panel 100. The light emission control signal generation circuits EM(1) to EM(n) output the light emission control signal EM(1) to EM(n) through the light emission control line of the display panel 100.

[0048] The first scan signals SC1(1) to SC1(n) can be used to drive the A transistor (e.g., compensation transistor) included in the pixel circuit. The second scan signals SC2(1) to SC2(n) can be used to drive the B transistor (e.g., data gong transistor) included in the pixel circuit. The third scan signals SC3(1) to SC3(n) can be used to drive the C transistor (e.g., bias transistor) included in the pixel circuit. The fourth scan signals SC4(1) to SC4(n) can be used to drive the D transistor (e.g., initialization transistor) included in the pixel circuit. The light emission control signals EM(1) to EM(n) can be used to drive the E transistor (e.g., light emission control transistor) included in the pixel circuit. For example, by using the light emission control signals EM(1) to EM(n) to control the light emission control transistor of the pixel, the light emission time of the light-emitting element can be varied.

[0049] Referring to Figure 3, a bias voltage bus line VobsL, a first initialization voltage bus line VarL, and a second initialization voltage bus line ViniL may be arranged between the gate drive circuit 120 and the display area AA.

[0050] The bias voltage bus line VobsL, the first initialization voltage bus line VarL, and the second initialization voltage bus line ViniL can supply the bias voltage Vobs, the first initialization voltage Var, and the second initialization voltage Vini from the power supply circuit of the display device to the pixel circuit, respectively.

[0051] In the drawings, the bias voltage bus line VobsL, the first initialization voltage bus line VarL, and the second initialization voltage bus line ViniL are shown as being located only on one side of the display area AA, either the left or the right. However, the drawings are not limited to this arrangement; they may be located on both sides, and even if they are located on one side, their position is not restricted to the left or right side.

[0052] Referring to Figure 3, one or more optical regions OA1 and OA2 may be arranged in the display region AA.

[0053] One or more optical regions OA1, OA2 may be arranged to overlap with one or more optical electronic devices such as a camera (image sensor) or other imaging device, a proximity sensor or an illuminance sensor or other sensing sensor.

[0054] One or more optical regions OA1, OA2 may have a light-transmitting structure formed therein to provide a transmittance above a certain level for the operation of the optical electronic device. In other words, the number of pixels per unit area in one or more optical regions OA1, OA2 may be smaller than the number of pixels per unit area in the general area of ​​the display region AA excluding the optical regions OA1, OA2. That is, the resolution of one or more optical regions OA1, OA2 may be lower than the resolution of the general area of ​​the display region AA.

[0055] In one or more optical regions OA1, OA2, the light-transmitting structure can be constructed by patterning cathode electrodes in areas where pixels are not located. In this case, the patterned cathode electrodes may be removed using a laser, or the cathode electrodes may be selectively formed and patterned by using the same material as the cathode deposition prevention layer.

[0056] Furthermore, in one or more optical regions OA1, OA2, the light-transmitting structure may be formed by separating the light-emitting element EL and the pixel circuit with pixels. In other words, the light-emitting element EL of the pixels is located on the optical regions OA1, OA2, and multiple transistor TFTs constituting the pixel circuit are arranged around the optical regions OA1, OA2, and the light-emitting element EL and the pixel circuit can be electrically connected through a transparent metal layer.

[0057] The timing controller 130 can multiply the input frame frequency by i, thereby controlling the operating timing of the display panel drive circuits 110 and 120 at a frame frequency of input frame frequency × i (where i is a natural number) Hz. The input frame frequency can be 60 Hz for the NTSC (National Television Standards Committee) system or 50 Hz for the PAL (Phase-Alternating Line) system.

[0058] The timing controller 130 receives video data and a timing signal synchronized with it from the host system 200. The video data received by the timing controller 130 is a digital signal. The timing controller 130 can convert the video data to a format suitable for use by the data drive circuit 110 and transmit it to the data drive circuit 110. Here, the timing signal may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and a data enable signal. Here, the data enable signal has a period of 1 horizontal period of 1H.

[0059] The timing controller 130 can generate data timing control signals for controlling the data drive circuit 110 and gate timing control signals for controlling the gate drive circuit 120, based on timing signals received from the host system 200. The gate timing control signals can be generated as a clock at the digital signal voltage level.

[0060] The host system 200 may be any one of the following: TV (Television), set-top box, navigation system, personal computer (PC), home theater, mobile system, or wearable system. In mobile and wearable devices, the data drive circuit 110, timing controller 130, level shifter 140, etc., may be integrated into a single drive IC (not shown). In a mobile system, the host system 200 may be implemented as an AP (Application Processor). The host system 200 can transmit video data to the drive IC via MIPI (Mobile Industry Processor Interface). The host system 200 may be connected to the drive IC via a flexible printed circuit board (FPCB).

[0061] On the other hand, in the present invention, the switch transistor of the pixel circuit P can be implemented as an N-channel oxide thin-film transistor.

[0062] Furthermore, some of the switch transistors in the pixel circuit P may be implemented as oxide thin-film transistors with low off-current characteristics, while the rest may be implemented as polycrystalline thin-film transistors with high on-current characteristics.

[0063] For example, in Figure 7, the switch transistors ST1 and ST2 (indicated by dotted squares), which are electrically connected to the drive transistor DT and capacitor Cst, can be implemented as oxide thin-film transistors, while the remaining transistors ST3 to ST7 can be implemented as polycrystalline thin-film transistors.

[0064] Here, the off-current can refer to the leakage current of the transistor. Furthermore, oxide thin-film transistors can be N-channel, while polycrystalline thin-film transistors can be P-channel or N-channel.

[0065] The gate-on voltage of an N-channel oxide thin-film transistor or an N-channel polycrystalline thin-film transistor is the gate-high voltage, and the gate-off voltage can be the gate-low voltage.

[0066] Furthermore, the gate-on voltage of a P-channel polycrystalline thin-film transistor is the gate-low voltage, and the gate-off voltage can be the gate-high voltage.

[0067] As described above, when the switch transistor is composed of an oxide thin-film transistor and a polycrystalline thin-film transistor, the display panel 100 can have the following cross-sectional structure.

[0068] Figure 4 is a cross-sectional view showing the stacked configuration of a display panel according to one embodiment of the present invention.

[0069] In Figure 4, we will refer to the switch transistor as a switching thin-film transistor.

[0070] Referring to Figure 4, a cross-sectional view is shown including two switching thin-film transistors TFT1 and TFT2 and one capacitor CST. The two switching thin-film transistors TFT1 and TFT2 include a polycrystalline thin-film transistor TFT1 containing a polycrystalline semiconductor material and an oxide thin-film transistor TFT2 containing an oxide semiconductor material.

[0071] The polycrystalline thin-film transistor TFT1 shown in Figure 4 is an emission switching thin-film transistor connected to a light-emitting element EL, and the oxide thin-film transistor TFT2 is one of the switching thin-film transistors connected to a capacitor CST.

[0072] In Figure 4, one pixel includes a light-emitting element (EL) and a pixel driving circuit that applies a driving current to the light-emitting element (EL). The pixel driving circuit is placed on the substrate 411, and the light-emitting element (EL) is placed on the pixel driving circuit. A sealing layer 420 is placed on the light-emitting element (EL). The sealing layer 420 protects the light-emitting element (EL).

[0073] A pixel driving circuit may refer to a single pixel array section including a driving thin-film transistor, a switching thin-film transistor, and a capacitor. A light-emitting element (EL) may refer to an array section for light emission including an anode electrode, a cathode electrode, and a light-emitting layer placed between them.

[0074] The substrate 411 can be realized as a multi-layer structure in which organic and inorganic films are alternately stacked. For example, the substrate 411 may consist of alternating layers of organic films such as polyimide and inorganic films such as silicon oxide (SiO2).

[0075] A lower buffer layer 412a is formed on the substrate 411. The lower buffer layer 412a is for blocking moisture and other substances that may penetrate from the outside, and can be used by laminating multiple silicon oxide (SiO2) films or the like. An auxiliary buffer layer 412b may be further placed on the lower buffer layer 412a to protect the device from moisture permeability.

[0076] A polycrystalline thin-film transistor TFT1 is formed on the substrate 411. The polycrystalline thin-film transistor TFT1 can use a polycrystalline semiconductor as its active layer. The polycrystalline thin-film transistor TFT1 includes a first active layer ACT1 containing a channel through which electrons or holes move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0077] The first active layer ACT1 includes a first channel region, a first source region located on one side of the first channel region, and a first drain region located on the other side.

[0078] The first source region and the first drain region are regions in which an intrinsic polycrystalline semiconductor material is doped with group 5 or group 3 impurity ions, such as yne (P) or boron (B), at predetermined concentrations to make it conductive. The first channel region is where the polycrystalline semiconductor material maintains its intrinsic state and provides pathways for electron and hole movement.

[0079] On the other hand, the polycrystalline thin-film transistor TFT1 includes a first gate electrode GE1 in the first active layer ACT1 that overlaps with the first channel region. A first gate insulating layer 413 is placed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 413 can be made of a single or multi-layer inorganic layer such as a silicon oxide (SiO2) film or silicon nitride (SiNx).

[0080] In one embodiment, the polycrystalline thin-film transistor TFT1 has a top-gate structure in which the first gate electrode GE1 is located above the first active layer ACT1. Accordingly, the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the oxide thin-film transistor TFT2 can be formed from the same material as the first gate electrode GE1. The number of masking steps can be reduced by forming the first gate electrode GE1, the first electrode CST1, and the light-shielding layer LS through a single masking step. However, the light-shielding layer LS may be formed on the lower buffer layer 412a and the auxiliary buffer layer 412b through a separate masking step. In this case, the light-shielding layer LS is not limited to the oxide thin-film transistor TFT2, but can be formed below all transistors. Furthermore, the light-shielding layer LS may be positioned to overlap the bottom of the capacitor CST to form a double capacitor.

[0081] The first gate electrode GE1 is composed of a metallic material. For example, the first gate electrode GE1 may be a single layer or multiple layers made of one of the following materials or an alloy thereof: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0082] A first interlayer insulating layer 414 is placed on the first gate electrode GE1. The first interlayer insulating layer 414 can be made of silicon oxide (SiO2), silicon nitride (SiNx), or the like.

[0083] The display panel 100 may further include an upper buffer layer 415, a second gate insulating layer 416, and a second interlayer insulating layer 417 arranged in order on the first interlayer insulating layer 414, and the polycrystalline thin-film transistor TFT1 includes a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 417 and connected to a first source region and a first drain region, respectively.

[0084] The first source electrode SD1 and the first drain electrode SD2 may be, but are not limited to, a single layer or multiple layer made of one of the following materials or alloys: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0085] The upper buffer layer 415 separates the second active layer ACT2 of the oxide thin-film transistor TFT2, which is made of an oxide semiconductor material, from the first active layer ACT1, which is made of a polycrystalline semiconductor material, and provides a substrate on which the second active layer ACT2 can be formed.

[0086] The second gate insulating layer 416 covers the second active layer ACT2 of the oxide thin-film transistor TFT2. Since the second gate insulating layer 416 is formed on the second active layer ACT2 which is made of an oxide semiconductor material, it is made of an inorganic film. For example, the second gate insulating layer 416 may be silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0087] The second gate electrode GE2 is composed of a metallic material. For example, the second gate electrode GE2 may be a single layer or multiple layers made of one of the following or an alloy thereof: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0088] On the other hand, the oxide thin-film transistor TFT2 includes a second active layer ACT2 formed on the upper buffer layer 415 and embodied in an oxide semiconductor material, a second gate electrode GE2 placed on the second gate insulating layer 416, and a second source electrode SD3 and a second drain electrode SD4 placed on the second interlayer insulating layer 417.

[0089] The second active layer ACT2 is embodied in an oxide semiconductor material and includes an intrinsic second channel region that is not doped with impurities, and a second source region and a second drain region that are doped with impurities to make them conductive.

[0090] The oxide thin-film transistor TFT2 is located below the upper buffer layer 415 and further includes a light-shielding layer LS that overlaps with the second active layer ACT2. The light-shielding layer LS can ensure the reliability of the oxide thin-film transistor TFT2 by blocking light incident on the second active layer ACT2. The light-shielding layer LS may be formed of the same material as the first gate electrode GE1 and may be formed on the upper surface of the first gate insulating layer 413. The light-shielding layer LS may be electrically coupled with the second gate electrode GE2 to form a dual gate.

[0091] The second source electrode SD3 and the second drain electrode SD4 are formed simultaneously on the second interlayer insulating layer 417 using the same material as the first source electrode SD1 and the first drain electrode SD2, thereby reducing the number of masking steps.

[0092] On the other hand, a capacitor CST can be realized by arranging a second electrode CST2 on the first interlayer insulating layer 414 so as to overlap with the first electrode CST1. The second electrode CST2 may be a single layer or multiple layers made of one of the following materials or an alloy thereof: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0093] The capacitor CST stores the data voltage applied through the data line DL for a certain period of time before supplying it to the light-emitting element EL. The capacitor CST includes two electrodes corresponding to each other and a dielectric placed between them. A first interlayer insulating layer 414 is located between the first electrode CST1 and the second electrode CST2.

[0094] Of the capacitor CSTs, the first electrode CST1 or the second electrode CST2 may be electrically connected to the oxide thin-film transistor TFT2, the second source electrode SD3, or the second drain electrode SD4. However, the connection relationships of the capacitor CSTs may change depending on the pixel driving circuit, but this is not limited to this.

[0095] On the other hand, a first planarization layer 418 and a second planarization layer 419 are arranged in order on top of the pixel driving circuit to flatten the upper end of the pixel driving circuit. The first planarization layer 418 and the second planarization layer 419 may be organic films such as polyimide or acrylic resin.

[0096] Then, a light-emitting element EL is formed on the second planarization layer 419.

[0097] The light-emitting element EL includes an anode electrode ANO, a cathode electrode CAT, and a light-emitting layer LEL positioned between the anode electrode ANO and the cathode electrode CAT. When implemented with a pixel driving circuit that uses a common low potential voltage connected to the cathode electrode CAT, the anode electrode ANO is provided as a separate electrode for each subpixel. However, when implemented with a pixel driving circuit that uses a common high potential voltage, the cathode electrode CAT may be provided as a separate electrode for each subpixel.

[0098] The light-emitting element EL is electrically connected to the driving element through an intermediate electrode CNE placed on the first planarization layer 418. Specifically, the anode electrode ANO of the light-emitting element EL and the first source electrode SD1 of the polycrystalline thin-film transistor TFT1 that constitutes the pixel driving circuit are connected by the intermediate electrode CNE.

[0099] The anode electrode ANO is connected to the intermediate electrode CNE, which is exposed through a contact hole penetrating the second planarization layer 419. The intermediate electrode CNE is also connected to the first source electrode SD1, which is exposed through a contact hole penetrating the first planarization layer 418.

[0100] The intermediate electrode CNE acts as a mediator connecting the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE can be formed from conductive materials such as copper (Cu), silver (Ag), molybdenum (Mo), and titanium (Ti).

[0101] The anode electrode ANO can be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film may consist of a material with a relatively high work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), while the opaque conductive film may consist of a single-layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode electrode ANO may be formed as a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially stacked, or as a structure in which a transparent conductive film and an opaque conductive film are sequentially stacked.

[0102] The light-emitting layer LEL is formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer on the anode electrode ANO in either order or reverse order.

[0103] The bank layer BNK may be a pixel-defining film that exposes the anode electrode ANO of each pixel. The bank layer BNK may be formed of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer BNK contains a light-shielding material consisting of at least one of a color pigment, organic black, and carbon. Spacers may be further placed on the bank layer BNK.

[0104] The cathode electrode CAT is formed on the upper and side surfaces of the light-emitting layer LEL, facing the anode electrode ANO across the LEL. The cathode electrode CAT can be formed integrally with the entire display area AA. When applied to a front-emitting organic light-emitting display device, the cathode electrode CAT may consist of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0105] A sealing layer 420 that suppresses moisture penetration may be further placed on the cathode electrode CAT.

[0106] The sealing layer 420 can block external moisture and oxygen from penetrating the light-emitting element EL, which is vulnerable to external moisture and oxygen. For this purpose, the sealing layer 420 may, but is not limited to, comprise at least one inorganic sealing layer and at least one organic sealing layer. In this invention, the structure of the sealing layer 420, in which a first sealing layer 421, a second sealing layer 422, and a third sealing layer 423 are sequentially laminated, will be described as an example.

[0107] The first sealing layer 421 is formed on the substrate 411 on which the cathode electrode CAT is formed. The third sealing layer 423 is formed on the substrate 411 on which the second sealing layer 422 is formed, and together with the first sealing layer 421, it may be formed to surround the top, bottom, and sides of the second sealing layer 422. Such first sealing layers 421 and third sealing layers 423 can minimize or prevent external moisture and oxygen from penetrating the light-emitting element EL. The first sealing layer 421 and third sealing layer 423 may be formed from inorganic insulating materials that can be deposited at low temperatures, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first sealing layer 421 and third sealing layer 423 are deposited in a low-temperature atmosphere, damage to the light-emitting element EL, which is vulnerable to high-temperature atmospheres, can be prevented during the deposition process of the first sealing layer 421 and third sealing layer 423.

[0108] The second sealing layer 422 acts as a buffer to alleviate stress between layers caused by bending of the display device 40, and can flatten the steps between layers. This second sealing layer 422 may be formed on the substrate 411 on which the first sealing layer 421 is formed from, but is not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and non-photosensitive organic insulating materials such as polyethylene or silicon oxycarbon (SiOC), or photosensitive organic insulating materials such as photoacrylic. When the second sealing layer 422 is formed by an inkjet method, a dam (DAM) may be placed to prevent the liquid form of the second sealing layer 422 from diffusing to the edge of the substrate 411. The dam (DAM) may be placed even closer to the edge of the substrate 411 than the second sealing layer 422. Such a dam (DAM) can prevent the second sealing layer 422 from diffusing into the pad area where conductive pads, which are located on the outermost edge of the substrate 411, are placed.

[0109] The dam (DAM) is designed to prevent the diffusion of the second sealing layer 422. However, if the second sealing layer 422 is formed to exceed the height of the dam during the process, the organic layer of the second sealing layer 422 may be exposed to the outside, making it easier for moisture and other substances to penetrate into the interior of the light-emitting element. Therefore, to prevent this, at least 10 or more dams (DAMs) may be formed in overlapping layers.

[0110] The dam (DAM) may be placed on the second interlayer insulating layer 417 of the non-display area (NA).

[0111] Furthermore, the dam (DAM) can be formed simultaneously with the first flattening layer 418 and the second flattening layer 419. The lower layer of the dam (DAM) may be formed at the same time as the first flattening layer 418, and the upper layer of the dam (DAM) may be formed at the same time as the second flattening layer 419, thus forming a double-layered structure.

[0112] Therefore, the dam (DAM) may, but is not limited to, be composed of the same material as the first flattening layer 418 and the second flattening layer 419.

[0113] Dams (DAMs) can be formed overlapping with low-voltage power lines (LVLs). For example, low-voltage power lines (LVLs) may be formed in the lower layer of the region where a dam (DAM) is located in the non-display area (NA).

[0114] The gate drive circuit 120, consisting of a low-voltage power supply line LVL and a GIP (Gate In Panel) configuration, is formed to surround the outer casing of the display panel, and the low-voltage power supply line LVL can be located further out from the gate drive circuit 120. Furthermore, the low-voltage power supply line LVL can be connected to the cathode electrode CAT to apply a common voltage. Although the gate drive circuit 120 is simply represented in the plan and cross-sectional drawings, it can be constructed using thin-film transistors with the same structure as the thin-film transistors in display area AA.

[0115] The low-voltage power line LVL is located outside the gate drive circuit 120. The low-voltage power line LVL is located outside the gate drive circuit 120 and surrounds the display area AA. For example, the low-voltage power line LVL may, but is not limited to, be made of the same material as the first gate electrode GE1, and may, but is not limited to, the same material as the second electrode CST2 or the first source and drain electrodes SD1, SD2.

[0116] Furthermore, the low-voltage power line LVL can be electrically connected to the cathode electrode CAT. The low-voltage power line LVL can supply low-voltage power ELVSS to the pixels of the display area AA.

[0117] A touch layer may be placed on the sealing layer 420. In the touch layer, the touch buffer film 451 can be positioned between the touch sensor metal, which includes touch electrode connecting lines 452, 454 and touch electrodes 455, 456, and the cathode electrode CAT of the light-emitting element EL.

[0118] The touch buffer film 451 can block chemicals (developer or etching solution, etc.) used during the manufacturing process of the touch sensor metal placed on the touch buffer film 451, or moisture from the outside, from penetrating the light-emitting layer LEL which contains organic matter. Accordingly, the touch buffer film 451 can prevent damage to the light-emitting layer LEL, which is vulnerable to chemicals or moisture.

[0119] The touch buffer film 451 can be formed at a low temperature (e.g., below 100°C) to prevent damage to the light-emitting layer LEL containing organic materials that are vulnerable to high temperatures, and is formed from an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer film 451 can be formed from acrylic, epoxy, or siloxane series materials. A touch buffer film 451 made of an organic insulating material with planar properties can prevent damage to the sealing layer 420 due to bending of the organic light-emitting display device and prevent the breakage of the touch sensor metal formed on the touch buffer film 451.

[0120] According to the mutual capacitance substrate touch sensor structure, touch electrodes 455 and 456 are arranged on a touch buffer film 451, and the touch electrodes 455 and 456 may be arranged to intersect each other.

[0121] The touch electrode connecting lines 452 and 454 can electrically connect the touch electrodes 455 and 456. The touch electrode connecting lines 452 and 454 and the touch electrodes 455 and 456 can be located in different layers separated by the touch insulating film 453.

[0122] The touch electrode connecting lines 452 and 454 are positioned to overlap with the bank layer BNK, which helps prevent a decrease in aperture ratio.

[0123] On the other hand, touch electrodes 455 and 456 can be electrically connected to a touch drive circuit (not shown) via a touch pad through a portion of the touch electrode connecting line 452, passing over the top and sides of the sealing layer 420 and the top and sides of the dam DAM.

[0124] A portion of the touch electrode connecting line 452 can receive a touch drive signal from the touch drive circuit and transmit it to the touch electrodes 455 and 456, and may also transmit touch sensing signals from the touch electrodes 455 and 456 to the touch drive circuit.

[0125] A touch protective film 457 may be placed on the touch electrodes 455 and 456. Although the drawings show the touch protective film 457 placed only on the touch electrodes 455 and 456, it is not limited to this, and the touch protective film 457 may be extended to the front or back of the dam and also placed on the touch electrode connecting line 452.

[0126] Furthermore, a color filter (not shown) may be placed on the sealing layer 420, and the color filter may be located on the touch layer or between the sealing layer 420 and the touch layer.

[0127] On the other hand, oxide thin-film transistors are subjected to more stress from temperature, light, etc., compared to polycrystalline thin-film transistors. As the usage time of the display device accumulates, the electrical characteristics of oxide thin-film transistors, such as the threshold voltage, will change.

[0128] When the electrical characteristics of an oxide thin-film transistor change, the global current, which is the total current flowing through the pixel array of display area AA, decreases, which can cause the overall brightness of the display device to decrease. Here, the stress can be one or more of the following: positive bias temperature stress (PBTS), negative bias temperature stress (NBTS), or negative bias temperature and illumination stress (NBTiS).

[0129] In this invention, multiple sensing current generation circuits CG for sensing the global current of the pixel array, i.e., the global current of the display area AA, are arranged on one side of the display area AA, thereby enabling sensing of the global current of the display area AA. Here, the global current of the display area AA may gradually decrease as the usage time of the display device accumulates. Therefore, by repeatedly sensing the global current with a time difference, fluctuations in the global current of the display area AA can be confirmed, and these fluctuations in the global current can also be compensated for.

[0130] Specifically, a display device according to one embodiment of the present invention may include a global sensing current generation circuit capable of sensing the global current of display area AA.

[0131] Referring to Figure 1, the global sensing current generation circuit can include multiple sensing current generation circuits CG, a single current sensing line GCL_S, a switch circuit SW_sel, a data line DL_S for current sensing, and a current summing circuit 112.

[0132] In one embodiment of the present invention, the sensing region SA, which is the region in which a plurality of sensing current generation circuits CG are arranged, may be located on one side of the display region AA as shown in Figures 1 and 5, or it may be located on the other side of the display region AA as shown in Figures 2 and 6.

[0133] When the sensing area SA is located on one side and the other side of the display area AA, multiple sensing current generation circuits CG, a single current sensing line GCL_S, a switch circuit SW_sel, and a data line DL_S for current sensing can be arranged on both sides of the display area AA, as shown in Figure 2.

[0134] Multiple sensing current generation circuits CG are arranged adjacent to one side of the display area AA and may receive a data voltage for current sensing during the current sensing period.

[0135] Multiple sensing current generation circuits CG are arranged adjacent to each other on both sides of the display area AA and may receive a data voltage for current sensing during the current sensing period. Here, the multiple sensing current generation circuits CG may be arranged in a second direction Y on one side or both sides of the display area AA. In other words, the multiple sensing current generation circuits CG may be arranged in a pixel column configuration. In Figures 1 and 2, the multiple sensing current generation circuits CG are shown as being arranged in a single pixel column configuration on one side or both sides of the display area AA, but the present invention is not limited thereto, and the multiple sensing current generation circuits CG may be arranged in two or more pixel column configurations.

[0136] In this invention, if the display area AA includes m pixel lines, one or more sensing current generation circuits CG can be placed on one or both sides of each pixel line, so the number of sensing current generation circuits CG can be an integer multiple of m.

[0137] Here, multiple pixel circuits P are arranged in the display area AA. The pixel circuit P can include a light-emitting element EL, a capacitor Cst, a drive transistor DT, multiple switch transistors (e.g., ST1, ST2), and the remaining switch transistors ST3 to ST7, as shown in Figure 7.

[0138] The sensing current generation circuit CG, as shown in Figure 8, includes a sensing drive transistor DT_S that generates a sensing current based on the gate-source voltage, a sensing capacitor Cst_S that charges the gate-source voltage of the sensing drive transistor DT_S, and a number of sensing switch transistors (e.g., ST1_S, ST2_S) that are electrically connected to the sensing drive transistor DT_S and the sensing capacitor Cst_S to sample the threshold voltage of the sensing drive transistor, as well as the remaining sensing switch transistors ST3_S to ST7_S. The sensing current generation circuit CG does not include any light-emitting elements.

[0139] The sensing drive transistor DT_S is the same type of transistor as the drive transistor DT, and the multiple sensing switch transistors ST1_S and ST2_S are the same type of transistors as the multiple switch transistors ST1 and ST2. The remaining sensing switch transistors ST3_S to ST7_S are also the same type of transistors as the remaining switch transistors ST3 to ST7.

[0140] The number of multiple sensing switch transistors ST1_S and ST2_S is the same as the number of multiple switch transistors ST1 and ST2, and the number of the remaining sensing switch transistors ST3_S to ST7_S is the same as the number of the remaining switch transistors ST3 to ST7.

[0141] Furthermore, multiple switch transistors ST1, ST2 and one or more sensing switch transistors ST1_S, ST2_S may be oxide thin-film transistors, while the remaining switch transistors ST3~ST7 and the remaining sensing switch transistors ST3_S~ST7_S may be polycrystalline thin-film transistors.

[0142] In other words, the sensing current generation circuit CG is identical to the pixel circuit P in all its components except for the light-emitting element.

[0143] In Figure 1, the single current sensing line GCL_S is connected in common to multiple sensing current generation circuits CG.

[0144] A switch circuit SW_sel is then placed at one end of the single current sensing line GCL_S.

[0145] The switch circuit SW_sel electrically connects the single current sensing line GCL_S and the current summing circuit 112 during the current sensing period, and electrically connects the low-voltage power supply line LVL, which is commonly connected to multiple pixel circuits, and the single current sensing line GCL_S during periods other than the current sensing period. Here, the low-voltage power supply line LVL is the line that supplies the low-voltage power supply ELVSS. The low-voltage power supply ELVSS may be set to -5[V], but is not limited to this.

[0146] Although not shown in Figure 1, the gate line GL that supplies the scan signal, the high-voltage power supply line (not shown) that supplies the high-voltage power supply ELVDD, etc., are connected to the same pixel circuit P and sensing current generation circuit CG.

[0147] Therefore, when multiple pixel circuits P are driven with the switch circuit SW_sel electrically connecting the low-voltage power supply line LVL and the single-current sensing line GCL_S, the transistors of the multiple sensing current generation circuits CG located adjacent to the display area AA and the transistors of the multiple pixel circuits P can operate identically.

[0148] Consequently, the oxide thin-film transistors in the sensing current generation circuit CG will experience the same level of stress as the oxide thin-film transistors in the pixel circuit P.

[0149] In other words, when multiple pixel circuits P are driven with the low-voltage power supply line LVL and the single-current sensing line GCL_S electrically connected by the switch circuit SW_sel, one or more stresses, including positive bias stress and negative bias stress, can accumulate in multiple switch transistors ST1, ST2 and multiple sensing switch transistors ST1_S, ST2_S. Here, positive bias stress may be positive bias temperature stress PBTS, positive bias temperature and light stress PBTiS, etc., and negative bias stress may be negative bias temperature stress NBTS, negative bias temperature and light stress NBTiS, etc.

[0150] On the other hand, the current sensing data line DL_S is connected in common to multiple sensing current generation circuits CG, and supplies current sensing data voltages to multiple sensing current generation circuits CG during the current sensing period. Here, the current sensing data voltages can be output by the data drive circuit 110.

[0151] The current summing circuit 112 receives the sensing currents generated by each of the multiple sensing current generation circuits CG through the single current sensing line GCL_S during the current sensing period, and outputs a global current sensing value obtained by summing the current values ​​of the sensing currents.

[0152] Here, multiple sensing current generation circuits CG are arranged in a pixel column configuration and connected to the corresponding gate line GL, so that sensing current can be sequentially generated and output from the top to the bottom or from the bottom to the top of the display panel 100. The current summing circuit 112 can then sequentially receive sensing current through a single current sensing line GCL_S.

[0153] Such a current summing circuit 112 may include an ADC (Analog-to-Digital Converter) circuit that sums the current values ​​of the sensing currents, which are analog values, during the current sensing period and outputs them as a global current sensing value, which is a digital value. Here, the ADC circuit may be an integrating ADC circuit, which is a single-slope ADC (Single-Slope Analog-to-Digital Converter) circuit. The sensing current may be the drive current of a sensing current generation circuit CG that reflects the accumulated stress in one or more sensing switch transistors, i.e., one or more oxide thin-film transistors.

[0154] In the global sensing current generation circuit described above, multiple sensing current generation circuits CG, a single current sensing line GCL_S, and a data line DL_S for current sensing are arranged on a display panel 100 including a display area AA, and a switch circuit SW_sel and a current summing circuit 112 may be arranged on a data driving circuit 110 that supplies data voltages to multiple pixel circuits P.

[0155] On the other hand, the global current sensing value output by the current summing circuit 112 can be received by the timing controller 130.

[0156] The timing controller 130, upon receiving the global current sensing value, can use the global current sensing value to check the global current fluctuation amount in display area AA. The timing controller 130 can then compensate for the global current fluctuation amount. A detailed explanation of this will be provided in the explanations of Figures 12 and 13.

[0157] The following section will explain the driving method of the global sensing current generation circuit.

[0158] Figure 9 is a diagram illustrating the driving method of a global sensing current generation circuit according to one embodiment of the present invention.

[0159] Referring to Figure 9, during the normal timing period, which is a period other than the current sensing period (GC Sensing Timing), a switching signal of the first voltage level Lv1 can be input to the switch circuit SW_sel of the global sensing current generation circuit. Upon receiving the switching signal of the first voltage level Lv1, the switch circuit SW_sel can electrically connect the single current sensing line GCL_S and the low voltage power supply line LVL.

[0160] Furthermore, during the normal timing period, the current sensing data voltage Vdata_S is not supplied to the multiple sensing current generation circuits CG.

[0161] However, when multiple pixel circuits P are driven, the scan signals and high-voltage power supply ELVDD supplied to the multiple pixel circuits P are also supplied to multiple sensing current generation circuits CG. Therefore, when multiple pixel circuits P are driven during the normal timing, the transistors of the multiple sensing current generation circuits CG, which are located adjacent to the display area AA, and the transistors of the multiple pixel circuits P can operate in the same manner.

[0162] Consequently, the same level of stress as the positive or negative bias stress accumulated in the oxide thin-film transistors of the pixel circuit P is also accumulated in the oxide thin-film transistors of the sensing current generation circuit CG. Here, during the normal timing, a data voltage Vdata is supplied to multiple pixel circuits P, while a current sensing data voltage Vdata_S is not supplied to multiple sensing current generation circuits CG. However, the presence or absence of data voltage supply may not have much effect on the stress on the oxide thin-film transistors.

[0163] The reason for this is that oxide thin-film transistors are sensitive to negative bias stress when the transistor is turned off, and therefore, changes in electrical characteristics mainly occur due to negative bias stress.

[0164] As described above, during the normal timing, the switch circuit SW_sel electrically connects the single current sensing line GCL_S and the low-voltage power supply line LVL, which can cause the same level of stress as that of multiple pixel circuits P to accumulate in multiple sensing current generation circuits CG.

[0165] On the other hand, during the current sensing period (GC Sensing Timing), a switching signal at a second voltage level Lv2 may be input to the switch circuit SW_sel. Upon receiving the switching signal at the second voltage level Lv2, the switch circuit SW_sel can electrically connect the single current sensing line GCL_S and the current summing circuit 112.

[0166] During the current sensing period (GC Sensing Timing), a current sensing data voltage Vdata_S can be supplied to multiple sensing current generation circuits CG. Here, the current sensing data voltage Vdata_S supplied to each of the multiple sensing current generation circuits CG can have the same voltage value. For example, the current sensing data voltage Vdata_S can have a voltage value corresponding to a brightness of 600 nits (Nit).

[0167] Then, the scan signals output sequentially by the gate drive circuit 120 can sequentially supply current sensing data voltage Vdata_S to multiple sensing current generation circuits CG.

[0168] Multiple sensing current generation circuits CG, upon receiving the current sensing data voltage Vdata_S, can each generate a sensing current.

[0169] The sensing currents generated by each of the multiple sensing current generation circuits CG are input to the current summing circuit 112 through a single current sensing line GCL_S. Here, the multiple sensing current generation circuits CG can sequentially generate and output sensing currents, and the current summing circuit 112 can sequentially receive sensing currents through the single current sensing line GCL_S. Here, the sensing current may be the drive current of the sensing current generation circuit CG, which reflects the accumulated stress in one or more sensing switch transistors, i.e., one or more oxide thin-film transistors, included in the sensing current generation circuit CG.

[0170] The current summing circuit 112, upon receiving the sensing current input, sums the current values ​​of the sensing currents and outputs a global current sensing value GC Sen. Here, since the sensing currents are input sequentially, the global current sensing value GC Sen can increase linearly during the current sensing period (GC Sensing Timing).

[0171] Then, at the end of the current sensing period (GC Sensing Timing) in which all sensing currents are input to the current summing circuit 112, the global current sensing value GC Sen output by the current summing circuit 112 can be used as the global current sensing value for display area AA.

[0172] In other words, since the pixel circuit P and sensing current generation circuit CG included in each pixel line have the same transistor configuration and accumulate stress at the same level, the drive current generated by multiple pixel circuits P and the sensing current generated by multiple sensing current generation circuits CG can be the same or very similar. Therefore, the global current value of the display area AA can be replaced by the sum of all sensing currents generated by multiple sensing current generation circuits CG.

[0173] The global sensing current generation circuit can sense the global current value of display area AA through the method described above. The global sensing current generation circuit can then proceed by repeating the current sensing period (GC Sensing Timing) with a time difference. Here, the time difference may be a constant period or a non-constant period, such as the turn-on or turn-off time of the display device.

[0174] On the other hand, since the multiple sensing current generation circuits CG do not include light-emitting elements EL, they do not emit light in response to the data voltage for current sensing. Therefore, the current sensing period (GC Sensing Timing) can proceed independently of the driving of the multiple pixel circuits P.

[0175] In other words, as shown in Figure 9, the current sensing period (GC Sensing Timing) can proceed while multiple pixel circuits P are driven by the data voltage Vdata, or it can proceed while multiple pixel circuits P are not driven.

[0176] Figures 10 and 11 are diagrams illustrating the fluctuations in global current due to the cumulative use of the display device.

[0177] Referring to Figure 10, the global current value is generally best at T1, which is the initial point of use for the display device. The global current may then decrease as the usage time of the display device accumulates.

[0178] Therefore, the global current value at T2, which is the point in time when the cumulative usage time of the display device has exceeded a certain period, may be smaller than the global current value at T1.

[0179] The global sensing current generation circuit of the display device proceeds by repeating the current sensing period with a time difference, so as shown in Figure 11, it can output the global current sensing value GC Sen at time T1 and also output the global current sensing value GC Sen at time T2. Here, the global current sensing value at time T2 may be smaller than the global current sensing value at time T1.

[0180] In other words, the global current sensing value may gradually decrease as the usage time of the display device accumulates.

[0181] The timing controller 130 of the display device receives a global current sensing value based on the cumulative usage time from the global sensing current generation circuit, checks the amount of global current fluctuation in the display area AA as described below, and can compensate for the amount of global current fluctuation.

[0182] Figure 12 is a diagram illustrating a method for compensating for fluctuations in global current in a display device according to one embodiment of the present invention.

[0183] The timing controller 130 can store the best global current value of the display device as a reference value.

[0184] The timing controller 130 can then compare the global current sensing value received by the global sensing current generation circuit with a reference value to confirm the amount of global current fluctuation in display area AA.

[0185] Thereafter, the timing controller 130 can compensate for the global current fluctuation in display area AA using a compensation cane (Gain) corresponding to the global current fluctuation. Therefore, the global current in display area AA can be maintained as a reference value regardless of the cumulative usage time of the display device.

[0186] Here, the timing controller 130 can store a lookup table as shown in Figure 13, and can use the lookup table to compensate for global current fluctuations.

[0187] Specifically, the timing controller 130 can calculate the global current reduction ratio, which is the global current fluctuation amount, using the reference value and the global current sensing value.

[0188] The timing controller 130 can then use a compensation cane (Gain) corresponding to the calculated global current reduction ratio to increase the overall brightness value of the video data.

[0189] Subsequently, the timing controller 130 can transmit video data with an overall increased brightness value, i.e., compensated video data, to the data drive circuit 110.

[0190] The data drive circuit 110 can increase the data voltage according to the compensated video data, so that the global current of display area AA can be maintained as a reference value.

[0191] For example, if the global current reduction ratio is 40%, the timing controller 130 can increase the overall brightness value of the video data by using a compensation cane (Gain) of 1.67, which corresponds to a global current reduction ratio of 40%, in a lookup table as shown in Figure 13.

[0192] This allows the global current for display area AA to be maintained at 100%.

[0193] The following section will explain the driving method of the sensing current generation circuit CG.

[0194] Figure 14 is a diagram showing the waveforms of the scan signal and EM signal generated to drive the sensing current generation circuit. Figures 15 to 19 are circuit diagrams that show the stepwise operation of the sensing current generation circuit during its operation period.

[0195] Referring to Figure 14, the driving period of the sensing current generation circuit CG can be divided into the initialization period INI, the sampling period SAM, the on-bias period OBS, the holding period HOLD, and the emission period EMI.

[0196] During the initialization period INI, the voltages of the scan signals SC1, SC2, SC3(n), SC3(n+1), SC4 and the EM signal EM are the gate high voltage VGH. Therefore, during the initialization period INI, as shown in Figure 15, the first sensing switch transistor ST1_S and the second sensing switch transistor ST2_S are turned on and the initialization voltage Vinit is applied to the second node n2 and the third node n3. The initialization voltage Vinit can also be applied to the first node n1 through the sensing drive transistor DT_S, which remains in the ON state.

[0197] During the initialization period INI, the voltages at the second node n2, the third node n3, and the first node n1 are the initialization voltage Vinit. During the initialization period INI, the fifth sensing switch transistor ST5_S and the sixth sensing switch transistor ST6_S are in the off state, so the fourth node n4 is floating and maintains its previous state. Here, the first sensing switch transistor ST1_S and the second sensing switch transistor ST2_S may be N-channel transistors turned on at the gate high voltage VGH. The initialization voltage Vinit may be set to -5[V], but is not limited to this.

[0198] During the sampling period SAM, the voltage of the second scan signal SC2 is inverted from the gate high voltage VGH to the gate low voltage VGL.

[0199] During the sampling period SAM, the voltages of the first scan signal SC1 and the EM signal EM are the gate high voltage VGH, and the voltage of the fourth scan signal SC4 is the gate low voltage VGL. When the third sensing switch transistor ST3_S is turned on during the sampling period SAM in response to the gate low voltage VGL of the second scan signal SC2, as shown in Figure 16, the current sensing data voltage Vdata_S is applied to the first node n1, and the current sensing data voltage Vdata_S is also applied to the third node n3 and the second node n2 through the ON sensing drive transistor DT_S. At this time, the voltage at the first node n1 is the current sensing data voltage Vdata_S, and the voltages at the third node n3 and the second node n2 are Vdata_S + Vth + α, which is the current sensing data voltage Vdata_S plus the threshold voltage Vth of the drive element DT and the threshold voltage change value α of the oxide thin film transistor. Here, the threshold voltage change α of the oxide thin-film transistor can be the decrease in the threshold voltage of the oxide thin-film transistor due to the accumulated stress on the oxide thin-film transistor. The threshold voltage change α can be a negative number.

[0200] Meanwhile, during the sampling period SAM, the fourth node n4 is in a floating state. Here, the third sensing switch transistor ST3_S may be a P-channel transistor that is turned on at the gate low voltage VGL. The current sensing data voltage Vdata_S may be set to a voltage between 0[V] and 4[V], but is not limited to this range.

[0201] During the on-bias period OBS, the voltages of the third(n) scan signal SC3(n) and the third(n+1) scan signal SC3(n+1) are inverted from the gate high voltage VGH to the gate low voltage VGL.

[0202] The fourth sensing switch transistor ST4_S is turned on during the on-bias period OBS in response to the gate low voltage VGL of the third (n) scan signal SC3(n).

[0203] Then, the fifth sensing switch transistor ST5_S is turned on during the on-bias period OBS in response to the gate low voltage VGL of the third (n+1) scan signal SC3(n+1). As a result, the first compensation voltage VOBS is applied to the first node n1 and the third node n3, and the second compensation voltage VAR is applied to the fourth node n4, as shown in Figure 17.

[0204] At this time, the voltages at the first node n1 and the third node n3 are the first compensation voltage VOBS, and the voltage at the fourth node n4 is the second compensation voltage VAR. The voltage at the second node n2 can be Vdata_S + Vth + α, maintaining its previous state. Here, the fourth sensing switch transistor ST4_S and the fifth sensing switch transistor ST5_S can be P-channel transistors turned on at the gate low voltage VGL. The first compensation voltage VOBS and the second compensation voltage VAR can be set to -4.5[V], respectively, but are not limited to this.

[0205] During the holding period, the voltages of the first scan signal SC1 and the fourth scan signal SC4 are the gate low voltage VGL, and the voltages of the second scan signal SC2, the third (n) scan signal SC3(n), and the third (n+1) scan signal SC3(n+1) are the gate high voltage VGH. The voltage of the EM signal EM is the gate high voltage VGH during the holding period. Therefore, as shown in Figure 18, since the first sensing switch transistor ST1_S to the seventh sensing switch transistor ST7_S are all in the off state, the first node n1 to the fourth node n4 are floating and maintain their previous state.

[0206] During the light emission period EMI, the voltages of the first scan signal SC1, the fourth scan signal SC4, and the EM signal EM are the gate low voltage VGL, while the voltages of the second scan signal SC2, the third (n) scan signal SC3(n), and the third (n+1) scan signal SC3(n+1) are the gate high voltage VGH. As shown in Figure 19, the sixth sensing switch transistor ST6_S and the seventh sensing switch transistor ST7_S are turned on in response to the gate low voltage VGL of the EM signal EM. Therefore, during the light emission period EMI, a current path is formed between the high-voltage power supply ELVDD and the fourth node n4.

[0207] During the EMI emission period, the sensing current generated by the gate-source voltage Vdata_S + Vth + α of the sensing drive transistor DT_S may be output through a single current sensing line GCL_S. Here, the sixth sensing switch transistor ST6_S and the seventh sensing switch transistor ST7_S may be P-channel transistors turned on at the gate low voltage VGL. The high-voltage power supply ELVDD may, but is not limited to, 6[V].

[0208] Through the operation of the sensing current generation circuit CG described above, a sensing current that reflects the accumulated stress in multiple sensing switch transistors, which are oxide thin-film transistors, can be generated in the sensing current generation circuit CG.

[0209] As described above, in one embodiment of the present invention, multiple sensing current generation circuits CG are arranged to be subjected to the same level of stress as multiple pixel circuits P, and the global current value of the display area AA can be derived by summing the sensing currents output by the multiple sensing current generation circuits CG.

[0210] In one embodiment of the present invention, the sensing current generation circuit was described as performing only the function of generating a sensing current. However, the present invention is not limited thereto, and the sensing current generation circuit may further perform other functions. In other words, the sensing current generation circuit may be used for other purposes as well.

[0211] Figure 20 is a block diagram showing a global sensing current generation circuit according to another embodiment of the present invention. Figures 21 and 22 are illustrative diagrams showing sensing current generation circuits according to another embodiment of the present invention.

[0212] Referring to Figure 20, in other embodiments of the present invention, the global sensing current generation circuit may include multiple repair / current generation circuits R / CG that also serve as repair pixel circuits for repairing defective pixel circuits DP included in multiple pixel circuits P. In Figure 20, the multiple repair / current generation circuits R / CG are shown arranged in a single pixel column configuration on one side of the display area AA, but the present invention is not limited thereto, and the multiple repair / current generation circuits R / CG may be arranged in two or more pixel column configurations. Furthermore, the multiple repair / current generation circuits R / CG may be arranged on both sides of the display area AA.

[0213] A repair / current generation circuit R / CG, which is a sensing current generation circuit according to another embodiment of the present invention, is composed of the same transistors as the pixel circuit, as shown in Figures 21 and 22. In other words, the repair / current generation circuit R / CG may include one or more oxide thin-film transistors (e.g., ST1, ST2).

[0214] Furthermore, the light-emitting element EL is not connected to the fourth node n4 side, and the single current sensing line GCL_S is connected to the fourth node n4 side.

[0215] On the current sensing data line DL_S, either the current sensing data voltage Vdata_S can be supplied as shown in Figure 21, or the repair data voltage Vdata_re can be supplied as shown in Figure 22.

[0216] Repair wiring may be placed between one or more pixel circuits P that form a single pixel line and repair / current generating circuits R / CG.

[0217] As shown in Figure 21, the normal pixel circuit and the repair / current generation circuit R / CG are not electrically connected by the repair wire.

[0218] Furthermore, during the current sensing period of the global sensing current generation circuit, a current sensing data voltage Vdata_S may be supplied to the repair / current generation circuit R / CG.

[0219] On the other hand, as shown in Figure 22, the defective pixel circuit and the repair / current generation circuit R / CG are electrically connected by a repair wire. Here, the fourth node n4 of the repair / current generation circuit R / CG and the repair wire are electrically connected by welding or the like, and the fourth node n4 of the defective pixel circuit and the repair wire are electrically connected by welding or the like.

[0220] Then, the repair / current generation circuit R / CG and the single current sensing line GCL_S are disconnected. Additionally, the power line supplied with high voltage power supply ELVDD in the defective pixel circuit, the line connecting the fourth node n4 and the fifth switch transistor ST5, and the line connecting the fourth node n4 and the sixth switch transistor ST6 are also disconnected.

[0221] As shown in Figure 22, when the repair / current generation circuit R / CG is electrically connected to the defective pixel circuit, the repair data voltage Vdata_re is supplied to the current sensing data line DL_S. Here, the repair data voltage Vdata_re is the data voltage supplied to the defective pixel circuit.

[0222] For example, if a faulty pixel circuit DP is located on the third line (3rd Line) as shown in Figure 20, the data voltage Vdata_3rd of the third line may be supplied to the repair data voltage Vdata_re.

[0223] Through this process, the drive current corresponding to the video data data_3rd of the third line flows through the repair wire to the light-emitting element (EL) of the defective pixel circuit.

[0224] As described above, the repair / current generation circuit R / CG, which is electrically connected to the defective pixel circuit, is not supplied with the current sensing data voltage Vdata_S.

[0225] For example, if the repair / current generation circuit R / CG of the third line is connected to the defective pixel circuit DP of the third line, as shown in Figure 20, the current sensing data voltage Vdata_S is not supplied to the repair / current generation circuit R / CG of the third line during the GC sensing timing as shown in Figure 23. Therefore, the light-emitting element EL of the defective pixel circuit electrically connected to the repair / current generation circuit R / CG of the third line does not emit light due to the current sensing data voltage Vdata_S.

[0226] Here, the global current sensing value GC Sen is the sum of the sensing currents output by multiple repair / current generation circuits R / CG. Therefore, even if a small number of repair / current generation circuits R / CG are used as repair pixel circuits, the reliability of the global current sensing value GC Sen does not decrease significantly.

[0227] Figure 24 is a block diagram showing a global sensing current generation circuit according to yet another embodiment of the present invention. And Figure 25 is a diagram illustrating a sensing current generation circuit according to yet another embodiment of the present invention.

[0228] Referring to Figure 24, in yet another embodiment of the present invention, the global sensing current generation circuit may include a dummy / current generation circuit D / CG that also serves as a dummy pixel circuit driven during orbit driving of the display device. Here, orbit driving means a driving method that mitigates degradation and afterimages of multiple pixel circuits P by moving the entire display image in accordance with a predetermined period.

[0229] In Figure 24, multiple dummy / current generating circuits D / CG are shown arranged in two pixel column configurations on one side of the display area AA. However, the present invention is not limited to this, and multiple dummy / current generating circuits D / CG may be arranged in one or three or more pixel column configurations. Furthermore, multiple dummy / current generating circuits D / CG may be arranged on both sides of the display area AA.

[0230] A dummy / current generation circuit D / CG, which is a sensing current generation circuit according to yet another embodiment of the present invention, is composed of the same transistors as the pixel circuit, as shown in Figure 25. In other words, the dummy / current generation circuit D / CG may include one or more oxide thin-film transistors (e.g., ST1, ST2).

[0231] Then, the light-emitting element EL is connected to the fourth node n4 side, and the single current sensing line GCL_S is connected to the cathode side of the light-emitting element EL.

[0232] The current sensing data line DL_S may be supplied with either a current sensing data voltage Vdata_S or an orbit drive data voltage Vdata_O. Here, the current sensing data voltage Vdata_S is supplied during the current sensing period, and the orbit drive data voltage Vdata_O is supplied when the orbit is driven.

[0233] In yet another embodiment of the present invention, the dummy / current generation circuit D / CG includes a light-emitting element EL, so that when a current sensing data voltage Vdata_S is supplied to the dummy / current generation circuit D / CG during the current sensing period, the light-emitting element EL of the dummy / current generation circuit D / CG can emit light.

[0234] Therefore, in yet another embodiment of the present invention, the current sensing period may be the turn-on time of the display device, the turn-off time, the operation time of the screen saver, etc. During the current sensing period, the display area AA may display an image that matches the light emission patterns of multiple dummy / current generating circuits D / CG.

[0235] Since the issues to be addressed, the means of solving those issues, and the effects described in the specification above do not specify the essential features of the claims, the scope of rights of the claims is not limited by the matters described in the specification.

[0236] Although embodiments of the present invention have been described in more detail above with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and can be modified and implemented in various ways without departing from the technical concept of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and not limiting in all respects. The scope of protection of the present invention should be interpreted by the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of the rights of the present invention. [Explanation of Symbols]

[0237] 100: Display Panel 110: Data-driven circuit 112: Current summing circuit 120: Gate drive circuit 130: Timing Controller 200: Host System

Claims

1. Multiple sensing current generation circuits, A single current sensing line connected to the plurality of sensing current generation circuits, through which sensing currents generated from each of the plurality of sensing current generation circuits during the current sensing period flows, and The system includes a switch circuit that electrically connects the single current sensing line and the current summing circuit during the current sensing period, and electrically connects the single current sensing line to a low-voltage power supply line that is commonly connected to multiple pixel circuits during periods other than the current sensing period. Each of the sensing current generation circuits is: A drive transistor that generates the sensing current based on the gate-source voltage, A capacitor for charging the gate-source voltage of the drive transistor, and An integrated circuit including a plurality of switch transistors electrically connected to the drive transistor and the capacitor, which sample the threshold voltage of the drive transistor.

2. The integrated circuit according to claim 1, further comprising a current summing circuit that receives sensing currents generated by the plurality of sensing current generation circuits through the single current sensing line during the current sensing period and outputs a global current sensing value obtained by summing the current values ​​of the sensing currents.

3. The integrated circuit according to claim 2, further comprising a current sensing data line connected to the plurality of sensing current generation circuits, which supplies current sensing data voltages to the plurality of sensing current generation circuits during the current sensing period.

4. The integrated circuit according to claim 3, wherein the drive transistor is the same type of transistor as the drive transistor included in the pixel circuit, and the plurality of switch transistors are the same type of transistor as the plurality of switch transistors included in the pixel circuit.

5. The integrated circuit according to claim 4, wherein the plurality of switch transistors in the sensing current generation circuit and the plurality of switch transistors in the pixel circuit are oxide transistors.

6. The integrated circuit according to claim 5, wherein the plurality of switch transistors in the sensing current generation circuit and the plurality of switch transistors in the pixel circuit are the same number.

7. The integrated circuit according to claim 5, wherein when the pixel circuit is driven with the low-voltage power supply line and the single-current sensing line electrically connected by the switch circuit, one or more stresses, including positive bias stress and negative bias stress, are accumulated in the plurality of switch transistors of the sensing current generation circuit and the plurality of switch transistors included in the pixel circuit.

8. The integrated circuit according to claim 1, wherein the integrated circuit does not include a light-emitting element.

9. The integrated circuit according to claim 8, wherein the sensing current generation circuit is also used as a repair pixel circuit for repairing defective pixel circuits included in the display area.

10. The aforementioned integrated circuit is The system further includes a current sensing data line connected to the plurality of sensing current generation circuits, which supplies current sensing data voltages to the plurality of sensing current generation circuits during the current sensing period. The integrated circuit according to claim 9, wherein when the Nth (where N is a natural number of 1 or more) sensing current generation circuit among the plurality of sensing current generation circuits is used as the repair pixel circuit, the Nth sensing current generation circuit is not supplied with the current sensing data voltage during the current sensing period.

11. The integrated circuit according to claim 2, wherein the current summing circuit includes an analog-to-digital converter (ADC) circuit that sums the current values ​​of the sensing current, which are analog values, during the current sensing period and outputs the summed value as the global current sensing value, which is a digital value.

12. It further includes a dummy / current generating circuit containing an electroluminescent (EL) element, The integrated circuit according to claim 1, wherein the dummy / current generating circuit is also used as a dummy pixel circuit.

13. An integrated circuit including: a plurality of sensing current generation circuits arranged adjacent to one side of a display area; a single current sensing line connected to the plurality of sensing current generation circuits, through which sensing currents generated from each of the plurality of sensing current generation circuits during the current sensing period flow; and a current summing circuit that receives the sensing currents generated by the plurality of sensing current generation circuits through the single current sensing line during the current sensing period and outputs a global current sensing value obtained by summing the current values ​​of the sensing currents; and A display device including a timing controller that receives the global current sensing value output by the current summing circuit, uses the global current sensing value to check the amount of global current fluctuation in the display area, and compensates for the amount of global current fluctuation.

14. The display device according to claim 13, wherein the timing controller compensates for the global current fluctuation by increasing the brightness value of the video data to be displayed in the display area.

15. The display device according to claim 14, wherein the timing controller increases the brightness value of the video data overall by using a gain value corresponding to the global current sensing value in a pre-stored lookup table.

16. The display device according to claim 13, wherein the current summing circuit includes an analog-to-digital converter (ADC) circuit that sums the current values ​​of the sensing current, which are analog values, during the current sensing period and outputs the summed value as the global current sensing value, which is a digital value.

17. The display device according to claim 16, wherein the ADC circuit is a single-slope ADC circuit.

18. The display device according to claim 13, further comprising a plurality of pixel circuits included in the display area that are in a driving state during the current sensing period.

19. The sensing current generation circuit is, A drive transistor that generates the sensing current based on the gate-source voltage, A capacitor for charging the gate-source voltage of the drive transistor, and The display device according to claim 13, further comprising a plurality of switch transistors electrically connected to the drive transistor and the capacitor for sampling the threshold voltage of the drive transistor.

20. The display device according to claim 19, wherein the drive transistor is a transistor of the same type as the drive transistor included in the pixel circuit, and the plurality of switch transistors are transistors of the same type as the plurality of switch transistors included in the pixel circuit.

21. The display device according to claim 20, wherein the plurality of switch transistors in the sensing current generation circuit and the plurality of switch transistors in the pixel circuit are oxide transistors.

22. The display device according to claim 21, wherein the plurality of switch transistors in the sensing current generation circuit and the plurality of switch transistors in the pixel circuit are the same number.

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